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-rw-r--r--drivers/char/drm/ati_pcigart.c91
-rw-r--r--drivers/char/drm/drmP.h3
-rw-r--r--drivers/char/drm/drm_fops.c7
-rw-r--r--drivers/char/drm/drm_lock.c35
-rw-r--r--drivers/char/drm/drm_pciids.h7
-rw-r--r--drivers/char/drm/r128_cce.c1
-rw-r--r--drivers/char/drm/radeon_cp.c1
-rw-r--r--drivers/char/drm/via_dma.c59
-rw-r--r--drivers/char/drm/via_dmablit.c2
-rw-r--r--drivers/char/hw_random/Kconfig9
-rw-r--r--drivers/char/riscom8.c2
-rw-r--r--drivers/char/rocket.c37
-rw-r--r--drivers/char/rocket_int.h83
13 files changed, 175 insertions, 162 deletions
diff --git a/drivers/char/drm/ati_pcigart.c b/drivers/char/drm/ati_pcigart.c
index d352dbb4ccf7..e5a0e97cfdda 100644
--- a/drivers/char/drm/ati_pcigart.c
+++ b/drivers/char/drm/ati_pcigart.c
@@ -35,42 +35,23 @@
35 35
36# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 36# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
37 37
38static void *drm_ati_alloc_pcigart_table(int order) 38static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
39 struct drm_ati_pcigart_info *gart_info)
39{ 40{
40 unsigned long address; 41 gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
41 struct page *page; 42 PAGE_SIZE,
42 int i; 43 gart_info->table_mask);
43 44 if (gart_info->table_handle == NULL)
44 DRM_DEBUG("%d order\n", order); 45 return -ENOMEM;
45
46 address = __get_free_pages(GFP_KERNEL | __GFP_COMP,
47 order);
48 if (address == 0UL) {
49 return NULL;
50 }
51
52 page = virt_to_page(address);
53 46
54 for (i = 0; i < order; i++, page++) 47 return 0;
55 SetPageReserved(page);
56
57 DRM_DEBUG("returning 0x%08lx\n", address);
58 return (void *)address;
59} 48}
60 49
61static void drm_ati_free_pcigart_table(void *address, int order) 50static void drm_ati_free_pcigart_table(struct drm_device *dev,
51 struct drm_ati_pcigart_info *gart_info)
62{ 52{
63 struct page *page; 53 drm_pci_free(dev, gart_info->table_handle);
64 int i; 54 gart_info->table_handle = NULL;
65 int num_pages = 1 << order;
66 DRM_DEBUG("\n");
67
68 page = virt_to_page((unsigned long)address);
69
70 for (i = 0; i < num_pages; i++, page++)
71 ClearPageReserved(page);
72
73 free_pages((unsigned long)address, order);
74} 55}
75 56
76int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) 57int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
@@ -78,8 +59,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info
78 struct drm_sg_mem *entry = dev->sg; 59 struct drm_sg_mem *entry = dev->sg;
79 unsigned long pages; 60 unsigned long pages;
80 int i; 61 int i;
81 int order; 62 int max_pages;
82 int num_pages, max_pages;
83 63
84 /* we need to support large memory configurations */ 64 /* we need to support large memory configurations */
85 if (!entry) { 65 if (!entry) {
@@ -87,15 +67,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info
87 return 0; 67 return 0;
88 } 68 }
89 69
90 order = drm_order((gart_info->table_size + (PAGE_SIZE-1)) / PAGE_SIZE);
91 num_pages = 1 << order;
92
93 if (gart_info->bus_addr) { 70 if (gart_info->bus_addr) {
94 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
95 pci_unmap_single(dev->pdev, gart_info->bus_addr,
96 num_pages * PAGE_SIZE,
97 PCI_DMA_TODEVICE);
98 }
99 71
100 max_pages = (gart_info->table_size / sizeof(u32)); 72 max_pages = (gart_info->table_size / sizeof(u32));
101 pages = (entry->pages <= max_pages) 73 pages = (entry->pages <= max_pages)
@@ -112,10 +84,9 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info
112 gart_info->bus_addr = 0; 84 gart_info->bus_addr = 0;
113 } 85 }
114 86
115 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN 87 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN &&
116 && gart_info->addr) { 88 gart_info->table_handle) {
117 drm_ati_free_pcigart_table(gart_info->addr, order); 89 drm_ati_free_pcigart_table(dev, gart_info);
118 gart_info->addr = NULL;
119 } 90 }
120 91
121 return 1; 92 return 1;
@@ -127,11 +98,10 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
127 struct drm_sg_mem *entry = dev->sg; 98 struct drm_sg_mem *entry = dev->sg;
128 void *address = NULL; 99 void *address = NULL;
129 unsigned long pages; 100 unsigned long pages;
130 u32 *pci_gart, page_base, bus_address = 0; 101 u32 *pci_gart, page_base;
102 dma_addr_t bus_address = 0;
131 int i, j, ret = 0; 103 int i, j, ret = 0;
132 int order;
133 int max_pages; 104 int max_pages;
134 int num_pages;
135 105
136 if (!entry) { 106 if (!entry) {
137 DRM_ERROR("no scatter/gather memory!\n"); 107 DRM_ERROR("no scatter/gather memory!\n");
@@ -141,31 +111,14 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
141 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { 111 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
142 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n"); 112 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
143 113
144 order = drm_order((gart_info->table_size + 114 ret = drm_ati_alloc_pcigart_table(dev, gart_info);
145 (PAGE_SIZE-1)) / PAGE_SIZE); 115 if (ret) {
146 num_pages = 1 << order;
147 address = drm_ati_alloc_pcigart_table(order);
148 if (!address) {
149 DRM_ERROR("cannot allocate PCI GART page!\n"); 116 DRM_ERROR("cannot allocate PCI GART page!\n");
150 goto done; 117 goto done;
151 } 118 }
152 119
153 if (!dev->pdev) { 120 address = gart_info->table_handle->vaddr;
154 DRM_ERROR("PCI device unknown!\n"); 121 bus_address = gart_info->table_handle->busaddr;
155 goto done;
156 }
157
158 bus_address = pci_map_single(dev->pdev, address,
159 num_pages * PAGE_SIZE,
160 PCI_DMA_TODEVICE);
161 if (bus_address == 0) {
162 DRM_ERROR("unable to map PCIGART pages!\n");
163 order = drm_order((gart_info->table_size +
164 (PAGE_SIZE-1)) / PAGE_SIZE);
165 drm_ati_free_pcigart_table(address, order);
166 address = NULL;
167 goto done;
168 }
169 } else { 122 } else {
170 address = gart_info->addr; 123 address = gart_info->addr;
171 bus_address = gart_info->bus_addr; 124 bus_address = gart_info->bus_addr;
diff --git a/drivers/char/drm/drmP.h b/drivers/char/drm/drmP.h
index a6789f25009b..8ea9dd1717a9 100644
--- a/drivers/char/drm/drmP.h
+++ b/drivers/char/drm/drmP.h
@@ -54,6 +54,7 @@
54#include <linux/pci.h> 54#include <linux/pci.h>
55#include <linux/jiffies.h> 55#include <linux/jiffies.h>
56#include <linux/smp_lock.h> /* For (un)lock_kernel */ 56#include <linux/smp_lock.h> /* For (un)lock_kernel */
57#include <linux/dma-mapping.h>
57#include <linux/mm.h> 58#include <linux/mm.h>
58#include <linux/cdev.h> 59#include <linux/cdev.h>
59#include <linux/mutex.h> 60#include <linux/mutex.h>
@@ -551,6 +552,8 @@ struct drm_ati_pcigart_info {
551 int gart_reg_if; 552 int gart_reg_if;
552 void *addr; 553 void *addr;
553 dma_addr_t bus_addr; 554 dma_addr_t bus_addr;
555 dma_addr_t table_mask;
556 struct drm_dma_handle *table_handle;
554 drm_local_map_t mapping; 557 drm_local_map_t mapping;
555 int table_size; 558 int table_size;
556}; 559};
diff --git a/drivers/char/drm/drm_fops.c b/drivers/char/drm/drm_fops.c
index 3992f73299cc..f09d4b5002b0 100644
--- a/drivers/char/drm/drm_fops.c
+++ b/drivers/char/drm/drm_fops.c
@@ -326,6 +326,7 @@ int drm_release(struct inode *inode, struct file *filp)
326 struct drm_file *file_priv = filp->private_data; 326 struct drm_file *file_priv = filp->private_data;
327 struct drm_device *dev = file_priv->head->dev; 327 struct drm_device *dev = file_priv->head->dev;
328 int retcode = 0; 328 int retcode = 0;
329 unsigned long irqflags;
329 330
330 lock_kernel(); 331 lock_kernel();
331 332
@@ -357,9 +358,11 @@ int drm_release(struct inode *inode, struct file *filp)
357 */ 358 */
358 359
359 do{ 360 do{
360 spin_lock(&dev->lock.spinlock); 361 spin_lock_irqsave(&dev->lock.spinlock,
362 irqflags);
361 locked = dev->lock.idle_has_lock; 363 locked = dev->lock.idle_has_lock;
362 spin_unlock(&dev->lock.spinlock); 364 spin_unlock_irqrestore(&dev->lock.spinlock,
365 irqflags);
363 if (locked) 366 if (locked)
364 break; 367 break;
365 schedule(); 368 schedule();
diff --git a/drivers/char/drm/drm_lock.c b/drivers/char/drm/drm_lock.c
index bea2a7d5b2b2..12dcdd1832f0 100644
--- a/drivers/char/drm/drm_lock.c
+++ b/drivers/char/drm/drm_lock.c
@@ -53,6 +53,7 @@ int drm_lock(struct drm_device *dev, void *data, struct drm_file *file_priv)
53 DECLARE_WAITQUEUE(entry, current); 53 DECLARE_WAITQUEUE(entry, current);
54 struct drm_lock *lock = data; 54 struct drm_lock *lock = data;
55 int ret = 0; 55 int ret = 0;
56 unsigned long irqflags;
56 57
57 ++file_priv->lock_count; 58 ++file_priv->lock_count;
58 59
@@ -71,9 +72,9 @@ int drm_lock(struct drm_device *dev, void *data, struct drm_file *file_priv)
71 return -EINVAL; 72 return -EINVAL;
72 73
73 add_wait_queue(&dev->lock.lock_queue, &entry); 74 add_wait_queue(&dev->lock.lock_queue, &entry);
74 spin_lock(&dev->lock.spinlock); 75 spin_lock_irqsave(&dev->lock.spinlock, irqflags);
75 dev->lock.user_waiters++; 76 dev->lock.user_waiters++;
76 spin_unlock(&dev->lock.spinlock); 77 spin_unlock_irqrestore(&dev->lock.spinlock, irqflags);
77 for (;;) { 78 for (;;) {
78 __set_current_state(TASK_INTERRUPTIBLE); 79 __set_current_state(TASK_INTERRUPTIBLE);
79 if (!dev->lock.hw_lock) { 80 if (!dev->lock.hw_lock) {
@@ -95,9 +96,9 @@ int drm_lock(struct drm_device *dev, void *data, struct drm_file *file_priv)
95 break; 96 break;
96 } 97 }
97 } 98 }
98 spin_lock(&dev->lock.spinlock); 99 spin_lock_irqsave(&dev->lock.spinlock, irqflags);
99 dev->lock.user_waiters--; 100 dev->lock.user_waiters--;
100 spin_unlock(&dev->lock.spinlock); 101 spin_unlock_irqrestore(&dev->lock.spinlock, irqflags);
101 __set_current_state(TASK_RUNNING); 102 __set_current_state(TASK_RUNNING);
102 remove_wait_queue(&dev->lock.lock_queue, &entry); 103 remove_wait_queue(&dev->lock.lock_queue, &entry);
103 104
@@ -198,8 +199,9 @@ int drm_lock_take(struct drm_lock_data *lock_data,
198{ 199{
199 unsigned int old, new, prev; 200 unsigned int old, new, prev;
200 volatile unsigned int *lock = &lock_data->hw_lock->lock; 201 volatile unsigned int *lock = &lock_data->hw_lock->lock;
202 unsigned long irqflags;
201 203
202 spin_lock(&lock_data->spinlock); 204 spin_lock_irqsave(&lock_data->spinlock, irqflags);
203 do { 205 do {
204 old = *lock; 206 old = *lock;
205 if (old & _DRM_LOCK_HELD) 207 if (old & _DRM_LOCK_HELD)
@@ -211,7 +213,7 @@ int drm_lock_take(struct drm_lock_data *lock_data,
211 } 213 }
212 prev = cmpxchg(lock, old, new); 214 prev = cmpxchg(lock, old, new);
213 } while (prev != old); 215 } while (prev != old);
214 spin_unlock(&lock_data->spinlock); 216 spin_unlock_irqrestore(&lock_data->spinlock, irqflags);
215 217
216 if (_DRM_LOCKING_CONTEXT(old) == context) { 218 if (_DRM_LOCKING_CONTEXT(old) == context) {
217 if (old & _DRM_LOCK_HELD) { 219 if (old & _DRM_LOCK_HELD) {
@@ -272,15 +274,16 @@ int drm_lock_free(struct drm_lock_data *lock_data, unsigned int context)
272{ 274{
273 unsigned int old, new, prev; 275 unsigned int old, new, prev;
274 volatile unsigned int *lock = &lock_data->hw_lock->lock; 276 volatile unsigned int *lock = &lock_data->hw_lock->lock;
277 unsigned long irqflags;
275 278
276 spin_lock(&lock_data->spinlock); 279 spin_lock_irqsave(&lock_data->spinlock, irqflags);
277 if (lock_data->kernel_waiters != 0) { 280 if (lock_data->kernel_waiters != 0) {
278 drm_lock_transfer(lock_data, 0); 281 drm_lock_transfer(lock_data, 0);
279 lock_data->idle_has_lock = 1; 282 lock_data->idle_has_lock = 1;
280 spin_unlock(&lock_data->spinlock); 283 spin_unlock_irqrestore(&lock_data->spinlock, irqflags);
281 return 1; 284 return 1;
282 } 285 }
283 spin_unlock(&lock_data->spinlock); 286 spin_unlock_irqrestore(&lock_data->spinlock, irqflags);
284 287
285 do { 288 do {
286 old = *lock; 289 old = *lock;
@@ -344,19 +347,20 @@ static int drm_notifier(void *priv)
344void drm_idlelock_take(struct drm_lock_data *lock_data) 347void drm_idlelock_take(struct drm_lock_data *lock_data)
345{ 348{
346 int ret = 0; 349 int ret = 0;
350 unsigned long irqflags;
347 351
348 spin_lock(&lock_data->spinlock); 352 spin_lock_irqsave(&lock_data->spinlock, irqflags);
349 lock_data->kernel_waiters++; 353 lock_data->kernel_waiters++;
350 if (!lock_data->idle_has_lock) { 354 if (!lock_data->idle_has_lock) {
351 355
352 spin_unlock(&lock_data->spinlock); 356 spin_unlock_irqrestore(&lock_data->spinlock, irqflags);
353 ret = drm_lock_take(lock_data, DRM_KERNEL_CONTEXT); 357 ret = drm_lock_take(lock_data, DRM_KERNEL_CONTEXT);
354 spin_lock(&lock_data->spinlock); 358 spin_lock_irqsave(&lock_data->spinlock, irqflags);
355 359
356 if (ret == 1) 360 if (ret == 1)
357 lock_data->idle_has_lock = 1; 361 lock_data->idle_has_lock = 1;
358 } 362 }
359 spin_unlock(&lock_data->spinlock); 363 spin_unlock_irqrestore(&lock_data->spinlock, irqflags);
360} 364}
361EXPORT_SYMBOL(drm_idlelock_take); 365EXPORT_SYMBOL(drm_idlelock_take);
362 366
@@ -364,8 +368,9 @@ void drm_idlelock_release(struct drm_lock_data *lock_data)
364{ 368{
365 unsigned int old, prev; 369 unsigned int old, prev;
366 volatile unsigned int *lock = &lock_data->hw_lock->lock; 370 volatile unsigned int *lock = &lock_data->hw_lock->lock;
371 unsigned long irqflags;
367 372
368 spin_lock(&lock_data->spinlock); 373 spin_lock_irqsave(&lock_data->spinlock, irqflags);
369 if (--lock_data->kernel_waiters == 0) { 374 if (--lock_data->kernel_waiters == 0) {
370 if (lock_data->idle_has_lock) { 375 if (lock_data->idle_has_lock) {
371 do { 376 do {
@@ -376,7 +381,7 @@ void drm_idlelock_release(struct drm_lock_data *lock_data)
376 lock_data->idle_has_lock = 0; 381 lock_data->idle_has_lock = 0;
377 } 382 }
378 } 383 }
379 spin_unlock(&lock_data->spinlock); 384 spin_unlock_irqrestore(&lock_data->spinlock, irqflags);
380} 385}
381EXPORT_SYMBOL(drm_idlelock_release); 386EXPORT_SYMBOL(drm_idlelock_release);
382 387
diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h
index 715b361f0c2b..a6a499f97e22 100644
--- a/drivers/char/drm/drm_pciids.h
+++ b/drivers/char/drm/drm_pciids.h
@@ -205,9 +205,9 @@
205 {0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 205 {0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
206 {0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ 206 {0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
207 {0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 207 {0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
208 {0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ 208 {0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
209 {0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 209 {0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
210 {0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 210 {0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
211 {0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ 211 {0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
212 {0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ 212 {0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
213 {0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ 213 {0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
@@ -238,6 +238,7 @@
238 {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ 238 {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
239 {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 239 {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
240 {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ 240 {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
241 {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
241 {0, 0, 0} 242 {0, 0, 0}
242 243
243#define r128_PCI_IDS \ 244#define r128_PCI_IDS \
diff --git a/drivers/char/drm/r128_cce.c b/drivers/char/drm/r128_cce.c
index 892e0a589846..f36adbd3aaf5 100644
--- a/drivers/char/drm/r128_cce.c
+++ b/drivers/char/drm/r128_cce.c
@@ -558,6 +558,7 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
558#if __OS_HAS_AGP 558#if __OS_HAS_AGP
559 if (dev_priv->is_pci) { 559 if (dev_priv->is_pci) {
560#endif 560#endif
561 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
561 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; 562 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
562 dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE; 563 dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
563 dev_priv->gart_info.addr = NULL; 564 dev_priv->gart_info.addr = NULL;
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index 833abc7e55fb..9072e4a1894e 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -1807,6 +1807,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
1807 } else 1807 } else
1808#endif 1808#endif
1809 { 1809 {
1810 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1810 /* if we have an offset set from userspace */ 1811 /* if we have an offset set from userspace */
1811 if (dev_priv->pcigart_offset_set) { 1812 if (dev_priv->pcigart_offset_set) {
1812 dev_priv->gart_info.bus_addr = 1813 dev_priv->gart_info.bus_addr =
diff --git a/drivers/char/drm/via_dma.c b/drivers/char/drm/via_dma.c
index 94baec692b57..7a339dba6a69 100644
--- a/drivers/char/drm/via_dma.c
+++ b/drivers/char/drm/via_dma.c
@@ -126,6 +126,8 @@ via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
126 hw_addr, cur_addr, next_addr); 126 hw_addr, cur_addr, next_addr);
127 return -1; 127 return -1;
128 } 128 }
129 if ((cur_addr < hw_addr) && (next_addr >= hw_addr))
130 msleep(1);
129 } while ((cur_addr < hw_addr) && (next_addr >= hw_addr)); 131 } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
130 return 0; 132 return 0;
131} 133}
@@ -416,27 +418,50 @@ static int via_hook_segment(drm_via_private_t * dev_priv,
416 int paused, count; 418 int paused, count;
417 volatile uint32_t *paused_at = dev_priv->last_pause_ptr; 419 volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
418 uint32_t reader,ptr; 420 uint32_t reader,ptr;
421 uint32_t diff;
419 422
420 paused = 0; 423 paused = 0;
421 via_flush_write_combine(); 424 via_flush_write_combine();
422 (void) *(volatile uint32_t *)(via_get_dma(dev_priv) -1); 425 (void) *(volatile uint32_t *)(via_get_dma(dev_priv) -1);
426
423 *paused_at = pause_addr_lo; 427 *paused_at = pause_addr_lo;
424 via_flush_write_combine(); 428 via_flush_write_combine();
425 (void) *paused_at; 429 (void) *paused_at;
430
426 reader = *(dev_priv->hw_addr_ptr); 431 reader = *(dev_priv->hw_addr_ptr);
427 ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) + 432 ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
428 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; 433 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
434
429 dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1; 435 dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
430 436
431 if ((ptr - reader) <= dev_priv->dma_diff ) { 437 /*
432 count = 10000000; 438 * If there is a possibility that the command reader will
433 while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--); 439 * miss the new pause address and pause on the old one,
440 * In that case we need to program the new start address
441 * using PCI.
442 */
443
444 diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;
445 count = 10000000;
446 while(diff == 0 && count--) {
447 paused = (VIA_READ(0x41c) & 0x80000000);
448 if (paused)
449 break;
450 reader = *(dev_priv->hw_addr_ptr);
451 diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;
434 } 452 }
435 453
454 paused = VIA_READ(0x41c) & 0x80000000;
455
436 if (paused && !no_pci_fire) { 456 if (paused && !no_pci_fire) {
437 reader = *(dev_priv->hw_addr_ptr); 457 reader = *(dev_priv->hw_addr_ptr);
438 if ((ptr - reader) == dev_priv->dma_diff) { 458 diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;
439 459 diff &= (dev_priv->dma_high - 1);
460 if (diff != 0 && diff < (dev_priv->dma_high >> 1)) {
461 DRM_ERROR("Paused at incorrect address. "
462 "0x%08x, 0x%08x 0x%08x\n",
463 ptr, reader, dev_priv->dma_diff);
464 } else if (diff == 0) {
440 /* 465 /*
441 * There is a concern that these writes may stall the PCI bus 466 * There is a concern that these writes may stall the PCI bus
442 * if the GPU is not idle. However, idling the GPU first 467 * if the GPU is not idle. However, idling the GPU first
@@ -577,6 +602,7 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
577 uint32_t pause_addr_lo, pause_addr_hi; 602 uint32_t pause_addr_lo, pause_addr_hi;
578 uint32_t jump_addr_lo, jump_addr_hi; 603 uint32_t jump_addr_lo, jump_addr_hi;
579 volatile uint32_t *last_pause_ptr; 604 volatile uint32_t *last_pause_ptr;
605 uint32_t dma_low_save1, dma_low_save2;
580 606
581 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; 607 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
582 via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi, 608 via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
@@ -603,8 +629,29 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
603 &pause_addr_lo, 0); 629 &pause_addr_lo, 0);
604 630
605 *last_pause_ptr = pause_addr_lo; 631 *last_pause_ptr = pause_addr_lo;
632 dma_low_save1 = dev_priv->dma_low;
606 633
607 via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0); 634 /*
635 * Now, set a trap that will pause the regulator if it tries to rerun the old
636 * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause
637 * and reissues the jump command over PCI, while the regulator has already taken the jump
638 * and actually paused at the current buffer end).
639 * There appears to be no other way to detect this condition, since the hw_addr_pointer
640 * does not seem to get updated immediately when a jump occurs.
641 */
642
643 last_pause_ptr =
644 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
645 &pause_addr_lo, 0) - 1;
646 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
647 &pause_addr_lo, 0);
648 *last_pause_ptr = pause_addr_lo;
649
650 dma_low_save2 = dev_priv->dma_low;
651 dev_priv->dma_low = dma_low_save1;
652 via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0);
653 dev_priv->dma_low = dma_low_save2;
654 via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
608} 655}
609 656
610 657
diff --git a/drivers/char/drm/via_dmablit.c b/drivers/char/drm/via_dmablit.c
index 33c5197b73c4..409e00afdd07 100644
--- a/drivers/char/drm/via_dmablit.c
+++ b/drivers/char/drm/via_dmablit.c
@@ -603,7 +603,7 @@ via_build_sg_info(struct drm_device *dev, drm_via_sg_info_t *vsg, drm_via_dmabli
603 * (Not a big limitation anyway.) 603 * (Not a big limitation anyway.)
604 */ 604 */
605 605
606 if ((xfer->mem_stride - xfer->line_length) >= PAGE_SIZE) { 606 if ((xfer->mem_stride - xfer->line_length) > 2*PAGE_SIZE) {
607 DRM_ERROR("Too large system memory stride. Stride: %d, " 607 DRM_ERROR("Too large system memory stride. Stride: %d, "
608 "Length: %d\n", xfer->mem_stride, xfer->line_length); 608 "Length: %d\n", xfer->mem_stride, xfer->line_length);
609 return -EINVAL; 609 return -EINVAL;
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index 6bbd4fa50f3b..8d6c2089d2a8 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -9,7 +9,14 @@ config HW_RANDOM
9 Hardware Random Number Generator Core infrastructure. 9 Hardware Random Number Generator Core infrastructure.
10 10
11 To compile this driver as a module, choose M here: the 11 To compile this driver as a module, choose M here: the
12 module will be called rng-core. 12 module will be called rng-core. This provides a device
13 that's usually called /dev/hw_random, and which exposes one
14 of possibly several hardware random number generators.
15
16 These hardware random number generators do not feed directly
17 into the kernel's random number generator. That is usually
18 handled by the "rngd" daemon. Documentation/hw_random.txt
19 has more information.
13 20
14 If unsure, say Y. 21 If unsure, say Y.
15 22
diff --git a/drivers/char/riscom8.c b/drivers/char/riscom8.c
index 589ac6f65b9a..3f9d0a9ac36d 100644
--- a/drivers/char/riscom8.c
+++ b/drivers/char/riscom8.c
@@ -1709,7 +1709,7 @@ static int __init riscom8_init_module (void)
1709 1709
1710 if (iobase || iobase1 || iobase2 || iobase3) { 1710 if (iobase || iobase1 || iobase2 || iobase3) {
1711 for(i = 0; i < RC_NBOARD; i++) 1711 for(i = 0; i < RC_NBOARD; i++)
1712 rc_board[0].base = 0; 1712 rc_board[i].base = 0;
1713 } 1713 }
1714 1714
1715 if (iobase) 1715 if (iobase)
diff --git a/drivers/char/rocket.c b/drivers/char/rocket.c
index 72f289279d8f..f585bc8579e9 100644
--- a/drivers/char/rocket.c
+++ b/drivers/char/rocket.c
@@ -83,6 +83,7 @@
83#include <linux/pci.h> 83#include <linux/pci.h>
84#include <asm/uaccess.h> 84#include <asm/uaccess.h>
85#include <asm/atomic.h> 85#include <asm/atomic.h>
86#include <asm/unaligned.h>
86#include <linux/bitops.h> 87#include <linux/bitops.h>
87#include <linux/spinlock.h> 88#include <linux/spinlock.h>
88#include <linux/init.h> 89#include <linux/init.h>
@@ -1312,7 +1313,7 @@ static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1312 if (clear & TIOCM_DTR) 1313 if (clear & TIOCM_DTR)
1313 info->channel.TxControl[3] &= ~SET_DTR; 1314 info->channel.TxControl[3] &= ~SET_DTR;
1314 1315
1315 sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0])); 1316 out32(info->channel.IndexAddr, info->channel.TxControl);
1316 return 0; 1317 return 0;
1317} 1318}
1318 1319
@@ -1748,7 +1749,7 @@ static int rp_write(struct tty_struct *tty,
1748 1749
1749 /* Write remaining data into the port's xmit_buf */ 1750 /* Write remaining data into the port's xmit_buf */
1750 while (1) { 1751 while (1) {
1751 if (info->tty == 0) /* Seemingly obligatory check... */ 1752 if (!info->tty) /* Seemingly obligatory check... */
1752 goto end; 1753 goto end;
1753 1754
1754 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head)); 1755 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
@@ -2798,7 +2799,7 @@ static int sReadAiopNumChan(WordIO_t io)
2798 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 }; 2799 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2799 2800
2800 /* write to chan 0 SRAM */ 2801 /* write to chan 0 SRAM */
2801 sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0])); 2802 out32((DWordIO_t) io + _INDX_ADDR, R);
2802 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */ 2803 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2803 x = sInW(io + _INDX_DATA); 2804 x = sInW(io + _INDX_DATA);
2804 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */ 2805 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
@@ -2864,7 +2865,7 @@ static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2864 R[1] = RData[i + 1] + 0x10 * ChanNum; 2865 R[1] = RData[i + 1] + 0x10 * ChanNum;
2865 R[2] = RData[i + 2]; 2866 R[2] = RData[i + 2];
2866 R[3] = RData[i + 3]; 2867 R[3] = RData[i + 3];
2867 sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0])); 2868 out32(ChP->IndexAddr, R);
2868 } 2869 }
2869 2870
2870 ChR = ChP->R; 2871 ChR = ChP->R;
@@ -2887,43 +2888,43 @@ static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2887 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8); 2888 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2888 ChP->BaudDiv[2] = (Byte_t) brd9600; 2889 ChP->BaudDiv[2] = (Byte_t) brd9600;
2889 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8); 2890 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2890 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]); 2891 out32(ChP->IndexAddr, ChP->BaudDiv);
2891 2892
2892 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL); 2893 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2893 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8); 2894 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2894 ChP->TxControl[2] = 0; 2895 ChP->TxControl[2] = 0;
2895 ChP->TxControl[3] = 0; 2896 ChP->TxControl[3] = 0;
2896 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); 2897 out32(ChP->IndexAddr, ChP->TxControl);
2897 2898
2898 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL); 2899 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2899 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8); 2900 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2900 ChP->RxControl[2] = 0; 2901 ChP->RxControl[2] = 0;
2901 ChP->RxControl[3] = 0; 2902 ChP->RxControl[3] = 0;
2902 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); 2903 out32(ChP->IndexAddr, ChP->RxControl);
2903 2904
2904 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS); 2905 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2905 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8); 2906 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2906 ChP->TxEnables[2] = 0; 2907 ChP->TxEnables[2] = 0;
2907 ChP->TxEnables[3] = 0; 2908 ChP->TxEnables[3] = 0;
2908 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]); 2909 out32(ChP->IndexAddr, ChP->TxEnables);
2909 2910
2910 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1); 2911 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2911 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8); 2912 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2912 ChP->TxCompare[2] = 0; 2913 ChP->TxCompare[2] = 0;
2913 ChP->TxCompare[3] = 0; 2914 ChP->TxCompare[3] = 0;
2914 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]); 2915 out32(ChP->IndexAddr, ChP->TxCompare);
2915 2916
2916 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1); 2917 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2917 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8); 2918 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2918 ChP->TxReplace1[2] = 0; 2919 ChP->TxReplace1[2] = 0;
2919 ChP->TxReplace1[3] = 0; 2920 ChP->TxReplace1[3] = 0;
2920 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]); 2921 out32(ChP->IndexAddr, ChP->TxReplace1);
2921 2922
2922 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2); 2923 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2923 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8); 2924 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2924 ChP->TxReplace2[2] = 0; 2925 ChP->TxReplace2[2] = 0;
2925 ChP->TxReplace2[3] = 0; 2926 ChP->TxReplace2[3] = 0;
2926 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]); 2927 out32(ChP->IndexAddr, ChP->TxReplace2);
2927 2928
2928 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP; 2929 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2929 ChP->TxFIFO = ChOff + _TX_FIFO; 2930 ChP->TxFIFO = ChOff + _TX_FIFO;
@@ -2979,7 +2980,7 @@ static void sStopRxProcessor(CHANNEL_T * ChP)
2979 R[1] = ChP->R[1]; 2980 R[1] = ChP->R[1];
2980 R[2] = 0x0a; 2981 R[2] = 0x0a;
2981 R[3] = ChP->R[3]; 2982 R[3] = ChP->R[3];
2982 sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]); 2983 out32(ChP->IndexAddr, R);
2983} 2984}
2984 2985
2985/*************************************************************************** 2986/***************************************************************************
@@ -3094,13 +3095,13 @@ static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3094 *WordPtr = ChP->TxPrioBuf; /* data byte address */ 3095 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3095 3096
3096 DWBuf[2] = Data; /* data byte value */ 3097 DWBuf[2] = Data; /* data byte value */
3097 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */ 3098 out32(IndexAddr, DWBuf); /* write it out */
3098 3099
3099 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */ 3100 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3100 3101
3101 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */ 3102 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3102 DWBuf[3] = 0; /* priority buffer pointer */ 3103 DWBuf[3] = 0; /* priority buffer pointer */
3103 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */ 3104 out32(IndexAddr, DWBuf); /* write it out */
3104 } else { /* write it to Tx FIFO */ 3105 } else { /* write it to Tx FIFO */
3105 3106
3106 sWriteTxByte(sGetTxRxDataIO(ChP), Data); 3107 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
@@ -3147,11 +3148,11 @@ static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3147 ChP->RxControl[2] |= 3148 ChP->RxControl[2] |=
3148 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN)); 3149 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3149 3150
3150 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); 3151 out32(ChP->IndexAddr, ChP->RxControl);
3151 3152
3152 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN); 3153 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3153 3154
3154 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); 3155 out32(ChP->IndexAddr, ChP->TxControl);
3155 3156
3156 if (Flags & CHANINT_EN) { 3157 if (Flags & CHANINT_EN) {
3157 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum]; 3158 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
@@ -3190,9 +3191,9 @@ static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3190 3191
3191 ChP->RxControl[2] &= 3192 ChP->RxControl[2] &=
3192 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN)); 3193 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3193 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); 3194 out32(ChP->IndexAddr, ChP->RxControl);
3194 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN); 3195 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3195 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); 3196 out32(ChP->IndexAddr, ChP->TxControl);
3196 3197
3197 if (Flags & CHANINT_EN) { 3198 if (Flags & CHANINT_EN) {
3198 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum]; 3199 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
diff --git a/drivers/char/rocket_int.h b/drivers/char/rocket_int.h
index f3a75791b811..b01d38125a8f 100644
--- a/drivers/char/rocket_int.h
+++ b/drivers/char/rocket_int.h
@@ -26,7 +26,6 @@ typedef unsigned int ByteIO_t;
26typedef unsigned int Word_t; 26typedef unsigned int Word_t;
27typedef unsigned int WordIO_t; 27typedef unsigned int WordIO_t;
28 28
29typedef unsigned long DWord_t;
30typedef unsigned int DWordIO_t; 29typedef unsigned int DWordIO_t;
31 30
32/* 31/*
@@ -38,7 +37,6 @@ typedef unsigned int DWordIO_t;
38 * instruction. 37 * instruction.
39 */ 38 */
40 39
41#ifdef ROCKET_DEBUG_IO
42static inline void sOutB(unsigned short port, unsigned char value) 40static inline void sOutB(unsigned short port, unsigned char value)
43{ 41{
44#ifdef ROCKET_DEBUG_IO 42#ifdef ROCKET_DEBUG_IO
@@ -55,12 +53,13 @@ static inline void sOutW(unsigned short port, unsigned short value)
55 outw_p(value, port); 53 outw_p(value, port);
56} 54}
57 55
58static inline void sOutDW(unsigned short port, unsigned long value) 56static inline void out32(unsigned short port, Byte_t *p)
59{ 57{
58 u32 value = le32_to_cpu(get_unaligned((__le32 *)p));
60#ifdef ROCKET_DEBUG_IO 59#ifdef ROCKET_DEBUG_IO
61 printk(KERN_DEBUG "sOutDW(%x, %lx)...\n", port, value); 60 printk(KERN_DEBUG "out32(%x, %lx)...\n", port, value);
62#endif 61#endif
63 outl_p(cpu_to_le32(value), port); 62 outl_p(value, port);
64} 63}
65 64
66static inline unsigned char sInB(unsigned short port) 65static inline unsigned char sInB(unsigned short port)
@@ -73,14 +72,6 @@ static inline unsigned short sInW(unsigned short port)
73 return inw_p(port); 72 return inw_p(port);
74} 73}
75 74
76#else /* !ROCKET_DEBUG_IO */
77#define sOutB(a, b) outb_p(b, a)
78#define sOutW(a, b) outw_p(b, a)
79#define sOutDW(port, value) outl_p(cpu_to_le32(value), port)
80#define sInB(a) (inb_p(a))
81#define sInW(a) (inw_p(a))
82#endif /* ROCKET_DEBUG_IO */
83
84/* This is used to move arrays of bytes so byte swapping isn't appropriate. */ 75/* This is used to move arrays of bytes so byte swapping isn't appropriate. */
85#define sOutStrW(port, addr, count) if (count) outsw(port, addr, count) 76#define sOutStrW(port, addr, count) if (count) outsw(port, addr, count)
86#define sInStrW(port, addr, count) if (count) insw(port, addr, count) 77#define sInStrW(port, addr, count) if (count) insw(port, addr, count)
@@ -390,7 +381,7 @@ Call: sClrBreak(ChP)
390#define sClrBreak(ChP) \ 381#define sClrBreak(ChP) \
391do { \ 382do { \
392 (ChP)->TxControl[3] &= ~SETBREAK; \ 383 (ChP)->TxControl[3] &= ~SETBREAK; \
393 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 384 out32((ChP)->IndexAddr,(ChP)->TxControl); \
394} while (0) 385} while (0)
395 386
396/*************************************************************************** 387/***************************************************************************
@@ -402,7 +393,7 @@ Call: sClrDTR(ChP)
402#define sClrDTR(ChP) \ 393#define sClrDTR(ChP) \
403do { \ 394do { \
404 (ChP)->TxControl[3] &= ~SET_DTR; \ 395 (ChP)->TxControl[3] &= ~SET_DTR; \
405 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 396 out32((ChP)->IndexAddr,(ChP)->TxControl); \
406} while (0) 397} while (0)
407 398
408/*************************************************************************** 399/***************************************************************************
@@ -415,7 +406,7 @@ Call: sClrRTS(ChP)
415do { \ 406do { \
416 if ((ChP)->rtsToggle) break; \ 407 if ((ChP)->rtsToggle) break; \
417 (ChP)->TxControl[3] &= ~SET_RTS; \ 408 (ChP)->TxControl[3] &= ~SET_RTS; \
418 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 409 out32((ChP)->IndexAddr,(ChP)->TxControl); \
419} while (0) 410} while (0)
420 411
421/*************************************************************************** 412/***************************************************************************
@@ -489,7 +480,7 @@ Call: sDisCTSFlowCtl(ChP)
489#define sDisCTSFlowCtl(ChP) \ 480#define sDisCTSFlowCtl(ChP) \
490do { \ 481do { \
491 (ChP)->TxControl[2] &= ~CTSFC_EN; \ 482 (ChP)->TxControl[2] &= ~CTSFC_EN; \
492 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 483 out32((ChP)->IndexAddr,(ChP)->TxControl); \
493} while (0) 484} while (0)
494 485
495/*************************************************************************** 486/***************************************************************************
@@ -501,7 +492,7 @@ Call: sDisIXANY(ChP)
501#define sDisIXANY(ChP) \ 492#define sDisIXANY(ChP) \
502do { \ 493do { \
503 (ChP)->R[0x0e] = 0x86; \ 494 (ChP)->R[0x0e] = 0x86; \
504 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \ 495 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
505} while (0) 496} while (0)
506 497
507/*************************************************************************** 498/***************************************************************************
@@ -515,7 +506,7 @@ Comments: Function sSetParity() can be used in place of functions sEnParity(),
515#define sDisParity(ChP) \ 506#define sDisParity(ChP) \
516do { \ 507do { \
517 (ChP)->TxControl[2] &= ~PARITY_EN; \ 508 (ChP)->TxControl[2] &= ~PARITY_EN; \
518 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 509 out32((ChP)->IndexAddr,(ChP)->TxControl); \
519} while (0) 510} while (0)
520 511
521/*************************************************************************** 512/***************************************************************************
@@ -527,7 +518,7 @@ Call: sDisRTSToggle(ChP)
527#define sDisRTSToggle(ChP) \ 518#define sDisRTSToggle(ChP) \
528do { \ 519do { \
529 (ChP)->TxControl[2] &= ~RTSTOG_EN; \ 520 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
530 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 521 out32((ChP)->IndexAddr,(ChP)->TxControl); \
531 (ChP)->rtsToggle = 0; \ 522 (ChP)->rtsToggle = 0; \
532} while (0) 523} while (0)
533 524
@@ -540,7 +531,7 @@ Call: sDisRxFIFO(ChP)
540#define sDisRxFIFO(ChP) \ 531#define sDisRxFIFO(ChP) \
541do { \ 532do { \
542 (ChP)->R[0x32] = 0x0a; \ 533 (ChP)->R[0x32] = 0x0a; \
543 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ 534 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
544} while (0) 535} while (0)
545 536
546/*************************************************************************** 537/***************************************************************************
@@ -567,7 +558,7 @@ Call: sDisTransmit(ChP)
567#define sDisTransmit(ChP) \ 558#define sDisTransmit(ChP) \
568do { \ 559do { \
569 (ChP)->TxControl[3] &= ~TX_ENABLE; \ 560 (ChP)->TxControl[3] &= ~TX_ENABLE; \
570 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 561 out32((ChP)->IndexAddr,(ChP)->TxControl); \
571} while (0) 562} while (0)
572 563
573/*************************************************************************** 564/***************************************************************************
@@ -579,7 +570,7 @@ Call: sDisTxSoftFlowCtl(ChP)
579#define sDisTxSoftFlowCtl(ChP) \ 570#define sDisTxSoftFlowCtl(ChP) \
580do { \ 571do { \
581 (ChP)->R[0x06] = 0x8a; \ 572 (ChP)->R[0x06] = 0x8a; \
582 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ 573 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
583} while (0) 574} while (0)
584 575
585/*************************************************************************** 576/***************************************************************************
@@ -604,7 +595,7 @@ Call: sEnCTSFlowCtl(ChP)
604#define sEnCTSFlowCtl(ChP) \ 595#define sEnCTSFlowCtl(ChP) \
605do { \ 596do { \
606 (ChP)->TxControl[2] |= CTSFC_EN; \ 597 (ChP)->TxControl[2] |= CTSFC_EN; \
607 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 598 out32((ChP)->IndexAddr,(ChP)->TxControl); \
608} while (0) 599} while (0)
609 600
610/*************************************************************************** 601/***************************************************************************
@@ -616,7 +607,7 @@ Call: sEnIXANY(ChP)
616#define sEnIXANY(ChP) \ 607#define sEnIXANY(ChP) \
617do { \ 608do { \
618 (ChP)->R[0x0e] = 0x21; \ 609 (ChP)->R[0x0e] = 0x21; \
619 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \ 610 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
620} while (0) 611} while (0)
621 612
622/*************************************************************************** 613/***************************************************************************
@@ -633,7 +624,7 @@ Warnings: Before enabling parity odd or even parity should be chosen using
633#define sEnParity(ChP) \ 624#define sEnParity(ChP) \
634do { \ 625do { \
635 (ChP)->TxControl[2] |= PARITY_EN; \ 626 (ChP)->TxControl[2] |= PARITY_EN; \
636 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 627 out32((ChP)->IndexAddr,(ChP)->TxControl); \
637} while (0) 628} while (0)
638 629
639/*************************************************************************** 630/***************************************************************************
@@ -647,10 +638,10 @@ Comments: This function will disable RTS flow control and clear the RTS
647#define sEnRTSToggle(ChP) \ 638#define sEnRTSToggle(ChP) \
648do { \ 639do { \
649 (ChP)->RxControl[2] &= ~RTSFC_EN; \ 640 (ChP)->RxControl[2] &= ~RTSFC_EN; \
650 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 641 out32((ChP)->IndexAddr,(ChP)->RxControl); \
651 (ChP)->TxControl[2] |= RTSTOG_EN; \ 642 (ChP)->TxControl[2] |= RTSTOG_EN; \
652 (ChP)->TxControl[3] &= ~SET_RTS; \ 643 (ChP)->TxControl[3] &= ~SET_RTS; \
653 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 644 out32((ChP)->IndexAddr,(ChP)->TxControl); \
654 (ChP)->rtsToggle = 1; \ 645 (ChP)->rtsToggle = 1; \
655} while (0) 646} while (0)
656 647
@@ -663,7 +654,7 @@ Call: sEnRxFIFO(ChP)
663#define sEnRxFIFO(ChP) \ 654#define sEnRxFIFO(ChP) \
664do { \ 655do { \
665 (ChP)->R[0x32] = 0x08; \ 656 (ChP)->R[0x32] = 0x08; \
666 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ 657 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
667} while (0) 658} while (0)
668 659
669/*************************************************************************** 660/***************************************************************************
@@ -684,7 +675,7 @@ Warnings: This function must be called after valid microcode has been
684#define sEnRxProcessor(ChP) \ 675#define sEnRxProcessor(ChP) \
685do { \ 676do { \
686 (ChP)->RxControl[2] |= RXPROC_EN; \ 677 (ChP)->RxControl[2] |= RXPROC_EN; \
687 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 678 out32((ChP)->IndexAddr,(ChP)->RxControl); \
688} while (0) 679} while (0)
689 680
690/*************************************************************************** 681/***************************************************************************
@@ -708,7 +699,7 @@ Call: sEnTransmit(ChP)
708#define sEnTransmit(ChP) \ 699#define sEnTransmit(ChP) \
709do { \ 700do { \
710 (ChP)->TxControl[3] |= TX_ENABLE; \ 701 (ChP)->TxControl[3] |= TX_ENABLE; \
711 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 702 out32((ChP)->IndexAddr,(ChP)->TxControl); \
712} while (0) 703} while (0)
713 704
714/*************************************************************************** 705/***************************************************************************
@@ -720,7 +711,7 @@ Call: sEnTxSoftFlowCtl(ChP)
720#define sEnTxSoftFlowCtl(ChP) \ 711#define sEnTxSoftFlowCtl(ChP) \
721do { \ 712do { \
722 (ChP)->R[0x06] = 0xc5; \ 713 (ChP)->R[0x06] = 0xc5; \
723 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ 714 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
724} while (0) 715} while (0)
725 716
726/*************************************************************************** 717/***************************************************************************
@@ -927,7 +918,7 @@ Call: sSendBreak(ChP)
927#define sSendBreak(ChP) \ 918#define sSendBreak(ChP) \
928do { \ 919do { \
929 (ChP)->TxControl[3] |= SETBREAK; \ 920 (ChP)->TxControl[3] |= SETBREAK; \
930 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 921 out32((ChP)->IndexAddr,(ChP)->TxControl); \
931} while (0) 922} while (0)
932 923
933/*************************************************************************** 924/***************************************************************************
@@ -941,7 +932,7 @@ Call: sSetBaud(ChP,Divisor)
941do { \ 932do { \
942 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ 933 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
943 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ 934 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
944 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \ 935 out32((ChP)->IndexAddr,(ChP)->BaudDiv); \
945} while (0) 936} while (0)
946 937
947/*************************************************************************** 938/***************************************************************************
@@ -953,7 +944,7 @@ Call: sSetData7(ChP)
953#define sSetData7(ChP) \ 944#define sSetData7(ChP) \
954do { \ 945do { \
955 (ChP)->TxControl[2] &= ~DATA8BIT; \ 946 (ChP)->TxControl[2] &= ~DATA8BIT; \
956 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 947 out32((ChP)->IndexAddr,(ChP)->TxControl); \
957} while (0) 948} while (0)
958 949
959/*************************************************************************** 950/***************************************************************************
@@ -965,7 +956,7 @@ Call: sSetData8(ChP)
965#define sSetData8(ChP) \ 956#define sSetData8(ChP) \
966do { \ 957do { \
967 (ChP)->TxControl[2] |= DATA8BIT; \ 958 (ChP)->TxControl[2] |= DATA8BIT; \
968 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 959 out32((ChP)->IndexAddr,(ChP)->TxControl); \
969} while (0) 960} while (0)
970 961
971/*************************************************************************** 962/***************************************************************************
@@ -977,7 +968,7 @@ Call: sSetDTR(ChP)
977#define sSetDTR(ChP) \ 968#define sSetDTR(ChP) \
978do { \ 969do { \
979 (ChP)->TxControl[3] |= SET_DTR; \ 970 (ChP)->TxControl[3] |= SET_DTR; \
980 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 971 out32((ChP)->IndexAddr,(ChP)->TxControl); \
981} while (0) 972} while (0)
982 973
983/*************************************************************************** 974/***************************************************************************
@@ -994,7 +985,7 @@ Warnings: This function has no effect unless parity is enabled with function
994#define sSetEvenParity(ChP) \ 985#define sSetEvenParity(ChP) \
995do { \ 986do { \
996 (ChP)->TxControl[2] |= EVEN_PAR; \ 987 (ChP)->TxControl[2] |= EVEN_PAR; \
997 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 988 out32((ChP)->IndexAddr,(ChP)->TxControl); \
998} while (0) 989} while (0)
999 990
1000/*************************************************************************** 991/***************************************************************************
@@ -1011,7 +1002,7 @@ Warnings: This function has no effect unless parity is enabled with function
1011#define sSetOddParity(ChP) \ 1002#define sSetOddParity(ChP) \
1012do { \ 1003do { \
1013 (ChP)->TxControl[2] &= ~EVEN_PAR; \ 1004 (ChP)->TxControl[2] &= ~EVEN_PAR; \
1014 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 1005 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1015} while (0) 1006} while (0)
1016 1007
1017/*************************************************************************** 1008/***************************************************************************
@@ -1024,7 +1015,7 @@ Call: sSetRTS(ChP)
1024do { \ 1015do { \
1025 if ((ChP)->rtsToggle) break; \ 1016 if ((ChP)->rtsToggle) break; \
1026 (ChP)->TxControl[3] |= SET_RTS; \ 1017 (ChP)->TxControl[3] |= SET_RTS; \
1027 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 1018 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1028} while (0) 1019} while (0)
1029 1020
1030/*************************************************************************** 1021/***************************************************************************
@@ -1050,7 +1041,7 @@ Comments: An interrupt will be generated when the trigger level is reached
1050do { \ 1041do { \
1051 (ChP)->RxControl[2] &= ~TRIG_MASK; \ 1042 (ChP)->RxControl[2] &= ~TRIG_MASK; \
1052 (ChP)->RxControl[2] |= LEVEL; \ 1043 (ChP)->RxControl[2] |= LEVEL; \
1053 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 1044 out32((ChP)->IndexAddr,(ChP)->RxControl); \
1054} while (0) 1045} while (0)
1055 1046
1056/*************************************************************************** 1047/***************************************************************************
@@ -1062,7 +1053,7 @@ Call: sSetStop1(ChP)
1062#define sSetStop1(ChP) \ 1053#define sSetStop1(ChP) \
1063do { \ 1054do { \
1064 (ChP)->TxControl[2] &= ~STOP2; \ 1055 (ChP)->TxControl[2] &= ~STOP2; \
1065 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 1056 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1066} while (0) 1057} while (0)
1067 1058
1068/*************************************************************************** 1059/***************************************************************************
@@ -1074,7 +1065,7 @@ Call: sSetStop2(ChP)
1074#define sSetStop2(ChP) \ 1065#define sSetStop2(ChP) \
1075do { \ 1066do { \
1076 (ChP)->TxControl[2] |= STOP2; \ 1067 (ChP)->TxControl[2] |= STOP2; \
1077 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 1068 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1078} while (0) 1069} while (0)
1079 1070
1080/*************************************************************************** 1071/***************************************************************************
@@ -1087,7 +1078,7 @@ Call: sSetTxXOFFChar(ChP,Ch)
1087#define sSetTxXOFFChar(ChP,CH) \ 1078#define sSetTxXOFFChar(ChP,CH) \
1088do { \ 1079do { \
1089 (ChP)->R[0x07] = (CH); \ 1080 (ChP)->R[0x07] = (CH); \
1090 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ 1081 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
1091} while (0) 1082} while (0)
1092 1083
1093/*************************************************************************** 1084/***************************************************************************
@@ -1100,7 +1091,7 @@ Call: sSetTxXONChar(ChP,Ch)
1100#define sSetTxXONChar(ChP,CH) \ 1091#define sSetTxXONChar(ChP,CH) \
1101do { \ 1092do { \
1102 (ChP)->R[0x0b] = (CH); \ 1093 (ChP)->R[0x0b] = (CH); \
1103 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x08]); \ 1094 out32((ChP)->IndexAddr,&(ChP)->R[0x08]); \
1104} while (0) 1095} while (0)
1105 1096
1106/*************************************************************************** 1097/***************************************************************************
@@ -1113,7 +1104,7 @@ Comments: This function is used to start a Rx processor after it was
1113 will restart both the Rx processor and software input flow control. 1104 will restart both the Rx processor and software input flow control.
1114 1105
1115*/ 1106*/
1116#define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0]) 1107#define sStartRxProcessor(ChP) out32((ChP)->IndexAddr,&(ChP)->R[0])
1117 1108
1118/*************************************************************************** 1109/***************************************************************************
1119Function: sWriteTxByte 1110Function: sWriteTxByte
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-02 05:39:56 -0500