diff options
Diffstat (limited to 'drivers/char')
-rw-r--r-- | drivers/char/agp/intel-agp.c | 5 | ||||
-rw-r--r-- | drivers/char/agp/intel-agp.h | 3 | ||||
-rw-r--r-- | drivers/char/agp/intel-gtt.c | 91 |
3 files changed, 66 insertions, 33 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index 0a4185279417..92622d44e12d 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c | |||
@@ -12,6 +12,7 @@ | |||
12 | #include <asm/smp.h> | 12 | #include <asm/smp.h> |
13 | #include "agp.h" | 13 | #include "agp.h" |
14 | #include "intel-agp.h" | 14 | #include "intel-agp.h" |
15 | #include <drm/intel-gtt.h> | ||
15 | 16 | ||
16 | int intel_agp_enabled; | 17 | int intel_agp_enabled; |
17 | EXPORT_SYMBOL(intel_agp_enabled); | 18 | EXPORT_SYMBOL(intel_agp_enabled); |
@@ -747,7 +748,7 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev, | |||
747 | 748 | ||
748 | bridge->capndx = cap_ptr; | 749 | bridge->capndx = cap_ptr; |
749 | 750 | ||
750 | if (intel_gmch_probe(pdev, bridge)) | 751 | if (intel_gmch_probe(pdev, NULL, bridge)) |
751 | goto found_gmch; | 752 | goto found_gmch; |
752 | 753 | ||
753 | for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { | 754 | for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { |
@@ -824,7 +825,7 @@ static void __devexit agp_intel_remove(struct pci_dev *pdev) | |||
824 | 825 | ||
825 | agp_remove_bridge(bridge); | 826 | agp_remove_bridge(bridge); |
826 | 827 | ||
827 | intel_gmch_remove(pdev); | 828 | intel_gmch_remove(); |
828 | 829 | ||
829 | agp_put_bridge(bridge); | 830 | agp_put_bridge(bridge); |
830 | } | 831 | } |
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h index 8e2d9140f300..57226424690c 100644 --- a/drivers/char/agp/intel-agp.h +++ b/drivers/char/agp/intel-agp.h | |||
@@ -251,7 +251,4 @@ | |||
251 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV 0x0c16 /* SDV */ | 251 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV 0x0c16 /* SDV */ |
252 | #define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04 | 252 | #define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04 |
253 | 253 | ||
254 | int intel_gmch_probe(struct pci_dev *pdev, | ||
255 | struct agp_bridge_data *bridge); | ||
256 | void intel_gmch_remove(struct pci_dev *pdev); | ||
257 | #endif | 254 | #endif |
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index 1237e7575c3f..9ed92ef5829b 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c | |||
@@ -66,7 +66,6 @@ static struct _intel_private { | |||
66 | struct pci_dev *bridge_dev; | 66 | struct pci_dev *bridge_dev; |
67 | u8 __iomem *registers; | 67 | u8 __iomem *registers; |
68 | phys_addr_t gtt_bus_addr; | 68 | phys_addr_t gtt_bus_addr; |
69 | phys_addr_t gma_bus_addr; | ||
70 | u32 PGETBL_save; | 69 | u32 PGETBL_save; |
71 | u32 __iomem *gtt; /* I915G */ | 70 | u32 __iomem *gtt; /* I915G */ |
72 | bool clear_fake_agp; /* on first access via agp, fill with scratch */ | 71 | bool clear_fake_agp; /* on first access via agp, fill with scratch */ |
@@ -76,6 +75,7 @@ static struct _intel_private { | |||
76 | struct resource ifp_resource; | 75 | struct resource ifp_resource; |
77 | int resource_valid; | 76 | int resource_valid; |
78 | struct page *scratch_page; | 77 | struct page *scratch_page; |
78 | int refcount; | ||
79 | } intel_private; | 79 | } intel_private; |
80 | 80 | ||
81 | #define INTEL_GTT_GEN intel_private.driver->gen | 81 | #define INTEL_GTT_GEN intel_private.driver->gen |
@@ -648,6 +648,7 @@ static void intel_gtt_cleanup(void) | |||
648 | 648 | ||
649 | static int intel_gtt_init(void) | 649 | static int intel_gtt_init(void) |
650 | { | 650 | { |
651 | u32 gma_addr; | ||
651 | u32 gtt_map_size; | 652 | u32 gtt_map_size; |
652 | int ret; | 653 | int ret; |
653 | 654 | ||
@@ -694,6 +695,15 @@ static int intel_gtt_init(void) | |||
694 | return ret; | 695 | return ret; |
695 | } | 696 | } |
696 | 697 | ||
698 | if (INTEL_GTT_GEN <= 2) | ||
699 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, | ||
700 | &gma_addr); | ||
701 | else | ||
702 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, | ||
703 | &gma_addr); | ||
704 | |||
705 | intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); | ||
706 | |||
697 | return 0; | 707 | return 0; |
698 | } | 708 | } |
699 | 709 | ||
@@ -767,20 +777,10 @@ static void i830_write_entry(dma_addr_t addr, unsigned int entry, | |||
767 | writel(addr | pte_flags, intel_private.gtt + entry); | 777 | writel(addr | pte_flags, intel_private.gtt + entry); |
768 | } | 778 | } |
769 | 779 | ||
770 | static bool intel_enable_gtt(void) | 780 | bool intel_enable_gtt(void) |
771 | { | 781 | { |
772 | u32 gma_addr; | ||
773 | u8 __iomem *reg; | 782 | u8 __iomem *reg; |
774 | 783 | ||
775 | if (INTEL_GTT_GEN <= 2) | ||
776 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, | ||
777 | &gma_addr); | ||
778 | else | ||
779 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, | ||
780 | &gma_addr); | ||
781 | |||
782 | intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); | ||
783 | |||
784 | if (INTEL_GTT_GEN >= 6) | 784 | if (INTEL_GTT_GEN >= 6) |
785 | return true; | 785 | return true; |
786 | 786 | ||
@@ -823,6 +823,7 @@ static bool intel_enable_gtt(void) | |||
823 | 823 | ||
824 | return true; | 824 | return true; |
825 | } | 825 | } |
826 | EXPORT_SYMBOL(intel_enable_gtt); | ||
826 | 827 | ||
827 | static int i830_setup(void) | 828 | static int i830_setup(void) |
828 | { | 829 | { |
@@ -860,7 +861,7 @@ static int intel_fake_agp_configure(void) | |||
860 | return -EIO; | 861 | return -EIO; |
861 | 862 | ||
862 | intel_private.clear_fake_agp = true; | 863 | intel_private.clear_fake_agp = true; |
863 | agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; | 864 | agp_bridge->gart_bus_addr = intel_private.base.gma_bus_addr; |
864 | 865 | ||
865 | return 0; | 866 | return 0; |
866 | } | 867 | } |
@@ -1182,9 +1183,17 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry, | |||
1182 | static void valleyview_write_entry(dma_addr_t addr, unsigned int entry, | 1183 | static void valleyview_write_entry(dma_addr_t addr, unsigned int entry, |
1183 | unsigned int flags) | 1184 | unsigned int flags) |
1184 | { | 1185 | { |
1186 | unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; | ||
1187 | unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; | ||
1185 | u32 pte_flags; | 1188 | u32 pte_flags; |
1186 | 1189 | ||
1187 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; | 1190 | if (type_mask == AGP_USER_MEMORY) |
1191 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; | ||
1192 | else { | ||
1193 | pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; | ||
1194 | if (gfdt) | ||
1195 | pte_flags |= GEN6_PTE_GFDT; | ||
1196 | } | ||
1188 | 1197 | ||
1189 | /* gen6 has bit11-4 for physical addr bit39-32 */ | 1198 | /* gen6 has bit11-4 for physical addr bit39-32 */ |
1190 | addr |= (addr >> 28) & 0xff0; | 1199 | addr |= (addr >> 28) & 0xff0; |
@@ -1244,6 +1253,7 @@ static int i9xx_setup(void) | |||
1244 | switch (INTEL_GTT_GEN) { | 1253 | switch (INTEL_GTT_GEN) { |
1245 | case 5: | 1254 | case 5: |
1246 | case 6: | 1255 | case 6: |
1256 | case 7: | ||
1247 | gtt_offset = MB(2); | 1257 | gtt_offset = MB(2); |
1248 | break; | 1258 | break; |
1249 | case 4: | 1259 | case 4: |
@@ -1379,7 +1389,6 @@ static const struct intel_gtt_driver valleyview_gtt_driver = { | |||
1379 | .write_entry = valleyview_write_entry, | 1389 | .write_entry = valleyview_write_entry, |
1380 | .dma_mask_size = 40, | 1390 | .dma_mask_size = 40, |
1381 | .check_flags = gen6_check_flags, | 1391 | .check_flags = gen6_check_flags, |
1382 | .chipset_flush = i9xx_chipset_flush, | ||
1383 | }; | 1392 | }; |
1384 | 1393 | ||
1385 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of | 1394 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
@@ -1523,14 +1532,32 @@ static int find_gmch(u16 device) | |||
1523 | return 1; | 1532 | return 1; |
1524 | } | 1533 | } |
1525 | 1534 | ||
1526 | int intel_gmch_probe(struct pci_dev *pdev, | 1535 | int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, |
1527 | struct agp_bridge_data *bridge) | 1536 | struct agp_bridge_data *bridge) |
1528 | { | 1537 | { |
1529 | int i, mask; | 1538 | int i, mask; |
1530 | intel_private.driver = NULL; | 1539 | |
1540 | /* | ||
1541 | * Can be called from the fake agp driver but also directly from | ||
1542 | * drm/i915.ko. Hence we need to check whether everything is set up | ||
1543 | * already. | ||
1544 | */ | ||
1545 | if (intel_private.driver) { | ||
1546 | intel_private.refcount++; | ||
1547 | return 1; | ||
1548 | } | ||
1531 | 1549 | ||
1532 | for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { | 1550 | for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { |
1533 | if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { | 1551 | if (gpu_pdev) { |
1552 | if (gpu_pdev->device == | ||
1553 | intel_gtt_chipsets[i].gmch_chip_id) { | ||
1554 | intel_private.pcidev = pci_dev_get(gpu_pdev); | ||
1555 | intel_private.driver = | ||
1556 | intel_gtt_chipsets[i].gtt_driver; | ||
1557 | |||
1558 | break; | ||
1559 | } | ||
1560 | } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { | ||
1534 | intel_private.driver = | 1561 | intel_private.driver = |
1535 | intel_gtt_chipsets[i].gtt_driver; | 1562 | intel_gtt_chipsets[i].gtt_driver; |
1536 | break; | 1563 | break; |
@@ -1540,13 +1567,17 @@ int intel_gmch_probe(struct pci_dev *pdev, | |||
1540 | if (!intel_private.driver) | 1567 | if (!intel_private.driver) |
1541 | return 0; | 1568 | return 0; |
1542 | 1569 | ||
1543 | bridge->driver = &intel_fake_agp_driver; | 1570 | intel_private.refcount++; |
1544 | bridge->dev_private_data = &intel_private; | 1571 | |
1545 | bridge->dev = pdev; | 1572 | if (bridge) { |
1573 | bridge->driver = &intel_fake_agp_driver; | ||
1574 | bridge->dev_private_data = &intel_private; | ||
1575 | bridge->dev = bridge_pdev; | ||
1576 | } | ||
1546 | 1577 | ||
1547 | intel_private.bridge_dev = pci_dev_get(pdev); | 1578 | intel_private.bridge_dev = pci_dev_get(bridge_pdev); |
1548 | 1579 | ||
1549 | dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); | 1580 | dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
1550 | 1581 | ||
1551 | mask = intel_private.driver->dma_mask_size; | 1582 | mask = intel_private.driver->dma_mask_size; |
1552 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) | 1583 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) |
@@ -1556,11 +1587,11 @@ int intel_gmch_probe(struct pci_dev *pdev, | |||
1556 | pci_set_consistent_dma_mask(intel_private.pcidev, | 1587 | pci_set_consistent_dma_mask(intel_private.pcidev, |
1557 | DMA_BIT_MASK(mask)); | 1588 | DMA_BIT_MASK(mask)); |
1558 | 1589 | ||
1559 | /*if (bridge->driver == &intel_810_driver) | 1590 | if (intel_gtt_init() != 0) { |
1560 | return 1;*/ | 1591 | intel_gmch_remove(); |
1561 | 1592 | ||
1562 | if (intel_gtt_init() != 0) | ||
1563 | return 0; | 1593 | return 0; |
1594 | } | ||
1564 | 1595 | ||
1565 | return 1; | 1596 | return 1; |
1566 | } | 1597 | } |
@@ -1579,12 +1610,16 @@ void intel_gtt_chipset_flush(void) | |||
1579 | } | 1610 | } |
1580 | EXPORT_SYMBOL(intel_gtt_chipset_flush); | 1611 | EXPORT_SYMBOL(intel_gtt_chipset_flush); |
1581 | 1612 | ||
1582 | void intel_gmch_remove(struct pci_dev *pdev) | 1613 | void intel_gmch_remove(void) |
1583 | { | 1614 | { |
1615 | if (--intel_private.refcount) | ||
1616 | return; | ||
1617 | |||
1584 | if (intel_private.pcidev) | 1618 | if (intel_private.pcidev) |
1585 | pci_dev_put(intel_private.pcidev); | 1619 | pci_dev_put(intel_private.pcidev); |
1586 | if (intel_private.bridge_dev) | 1620 | if (intel_private.bridge_dev) |
1587 | pci_dev_put(intel_private.bridge_dev); | 1621 | pci_dev_put(intel_private.bridge_dev); |
1622 | intel_private.driver = NULL; | ||
1588 | } | 1623 | } |
1589 | EXPORT_SYMBOL(intel_gmch_remove); | 1624 | EXPORT_SYMBOL(intel_gmch_remove); |
1590 | 1625 | ||