11 files changed, 133 insertions, 71 deletions

diff --git a/drivers/char/agp/Kconfig b/drivers/char/agp/Kconfig
index 486ed8a11b59..a4d425d2dce2 100644
--- a/drivers/char/agp/Kconfig
+++ b/drivers/char/agp/Kconfig
@@ -15,22 +15,23 @@ config AGP
           due to kernel allocation issues), you could use PCI accesses
           and have up to a couple gigs of texture space.
 
-          Note that this is the only means to have XFree4/GLX use
+          Note that this is the only means to have X/GLX use
           write-combining with MTRR support on the AGP bus. Without it, OpenGL
           direct rendering will be a lot slower but still faster than PIO.
 
-          You should say Y here if you use XFree86 3.3.6 or 4.x and want to
-          use GLX or DRI.  If unsure, say N.
-
           To compile this driver as a module, choose M here: the
           module will be called agpgart.
 
+          You should say Y here if you want to use GLX or DRI.
+
+          If unsure, say N.
+
 config AGP_ALI
         tristate "ALI chipset support"
         depends on AGP && X86_32
         ---help---
           This option gives you AGP support for the GLX component of
-          XFree86 4.x on the following ALi chipsets.  The supported chipsets
+          X on the following ALi chipsets.  The supported chipsets
           include M1541, M1621, M1631, M1632, M1641,M1647,and M1651.
           For the ALi-chipset question, ALi suggests you refer to
           <http://www.ali.com.tw/eng/support/index.shtml>.
@@ -40,28 +41,19 @@ config AGP_ALI
           timing issues, this chipset cannot do AGP 2x with the G200.
           This is a hardware limitation. AGP 1x seems to be fine, though.
 
-          You should say Y here if you use XFree86 3.3.6 or 4.x and want to
-          use GLX or DRI.  If unsure, say N.
-
 config AGP_ATI
         tristate "ATI chipset support"
         depends on AGP && X86_32
         ---help---
-      This option gives you AGP support for the GLX component of
-      XFree86 4.x on the ATI RadeonIGP family of chipsets.
-
-      You should say Y here if you use XFree86 3.3.6 or 4.x and want to
-      use GLX or DRI.  If unsure, say N.
+          This option gives you AGP support for the GLX component of
+          X on the ATI RadeonIGP family of chipsets.
 
 config AGP_AMD
         tristate "AMD Irongate, 761, and 762 chipset support"
         depends on AGP && X86_32
         help
           This option gives you AGP support for the GLX component of
-          XFree86 4.x on AMD Irongate, 761, and 762 chipsets.
-
-          You should say Y here if you use XFree86 3.3.6 or 4.x and want to
-          use GLX or DRI.  If unsure, say N.
+          X on AMD Irongate, 761, and 762 chipsets.
 
 config AGP_AMD64
         tristate "AMD Opteron/Athlon64 on-CPU GART support" if !GART_IOMMU
@@ -69,45 +61,38 @@ config AGP_AMD64
         default y if GART_IOMMU
         help
           This option gives you AGP support for the GLX component of
-          XFree86 4.x using the on-CPU northbridge of the AMD Athlon64/Opteron CPUs.
+          X using the on-CPU northbridge of the AMD Athlon64/Opteron CPUs.
           You still need an external AGP bridge like the AMD 8151, VIA
           K8T400M, SiS755. It may also support other AGP bridges when loaded
           with agp_try_unsupported=1.
-          You should say Y here if you use XFree86 3.3.6 or 4.x and want to
-          use GLX or DRI.  If unsure, say Y
 
 config AGP_INTEL
         tristate "Intel 440LX/BX/GX, I8xx and E7x05 chipset support"
         depends on AGP && X86
         help
-          This option gives you AGP support for the GLX component of XFree86 4.x
+          This option gives you AGP support for the GLX component of X
           on Intel 440LX/BX/GX, 815, 820, 830, 840, 845, 850, 860, 875,
-          E7205 and E7505 chipsets and full support for the 810, 815, 830M, 845G,
-          852GM, 855GM, 865G and I915 integrated graphics chipsets.
+          E7205 and E7505 chipsets and full support for the 810, 815, 830M,
+          845G, 852GM, 855GM, 865G and I915 integrated graphics chipsets.
+
 
-          You should say Y here if you use XFree86 3.3.6 or 4.x and want to
-          use GLX or DRI, or if you have any Intel integrated graphics
-          chipsets.  If unsure, say Y.
 
 config AGP_NVIDIA
         tristate "NVIDIA nForce/nForce2 chipset support"
         depends on AGP && X86_32
         help
           This option gives you AGP support for the GLX component of
-          XFree86 4.x on the following NVIDIA chipsets.  The supported chipsets
-          include nForce and nForce2
+          X on NVIDIA chipsets including nForce and nForce2
 
 config AGP_SIS
         tristate "SiS chipset support"
         depends on AGP && X86_32
         help
           This option gives you AGP support for the GLX component of
-          XFree86 4.x on Silicon Integrated Systems [SiS] chipsets.
+          X on Silicon Integrated Systems [SiS] chipsets.
 
           Note that 5591/5592 AGP chipsets are NOT supported.
 
-          You should say Y here if you use XFree86 3.3.6 or 4.x and want to
-          use GLX or DRI.  If unsure, say N.
 
 config AGP_SWORKS
         tristate "Serverworks LE/HE chipset support"
@@ -121,10 +106,7 @@ config AGP_VIA
         depends on AGP && X86_32
         help
           This option gives you AGP support for the GLX component of
-          XFree86 4.x on VIA MVP3/Apollo Pro chipsets.
-
-          You should say Y here if you use XFree86 3.3.6 or 4.x and want to
-          use GLX or DRI.  If unsure, say N.
+          X on VIA MVP3/Apollo Pro chipsets.
 
 config AGP_I460
         tristate "Intel 460GX chipset support"
@@ -159,9 +141,6 @@ config AGP_EFFICEON
           This option gives you AGP support for the Transmeta Efficeon
           series processors with integrated northbridges.
 
-          You should say Y here if you use XFree86 3.3.6 or 4.x and want to
-          use GLX or DRI.  If unsure, say Y.
-
 config AGP_SGI_TIOCA
         tristate "SGI TIO chipset AGP support"
         depends on AGP && (IA64_SGI_SN2 || IA64_GENERIC)
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index 9964c508c111..1251b2515bbe 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -516,8 +516,10 @@ static int __devinit nforce3_agp_init(struct pci_dev *pdev)
         pci_read_config_dword (hammers[0], AMD64_GARTAPERTUREBASE, &apbase);
 
         /* if x86-64 aperture base is beyond 4G, exit here */
-        if ( (apbase & 0x7fff) >> (32 - 25) )
-                 return -ENODEV;
+        if ( (apbase & 0x7fff) >> (32 - 25) ) {
+                printk(KERN_INFO PFX "aperture base > 4G\n");
+                return -ENODEV;
+        }
 
         apbase = (apbase & 0x7fff) << 25;
 
diff --git a/drivers/char/agp/sworks-agp.c b/drivers/char/agp/sworks-agp.c
index 268f78d926d3..efef9999f1cf 100644
--- a/drivers/char/agp/sworks-agp.c
+++ b/drivers/char/agp/sworks-agp.c
@@ -468,9 +468,7 @@ static int __devinit agp_serverworks_probe(struct pci_dev *pdev,
 
         switch (pdev->device) {
         case 0x0006:
-                /* ServerWorks CNB20HE
-                Fail silently.*/
-                printk (KERN_ERR PFX "Detected ServerWorks CNB20HE chipset: No AGP present.\n");
+                printk (KERN_ERR PFX "ServerWorks CNB20HE is unsupported due to lack of documentation.\n");
                 return -ENODEV;
 
         case PCI_DEVICE_ID_SERVERWORKS_HE:
diff --git a/drivers/char/drm/i915_irq.c b/drivers/char/drm/i915_irq.c
index a1381c61aa63..d3879ac9970f 100644
--- a/drivers/char/drm/i915_irq.c
+++ b/drivers/char/drm/i915_irq.c
@@ -202,10 +202,15 @@ void i915_driver_irq_postinstall(drm_device_t * dev)
 void i915_driver_irq_uninstall(drm_device_t * dev)
 {
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+        u16 temp;
+
         if (!dev_priv)
                 return;
 
         I915_WRITE16(I915REG_HWSTAM, 0xffff);
         I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
         I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
+
+        temp = I915_READ16(I915REG_INT_IDENTITY_R);
+        I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
 }
diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c
index 291dbf4c8186..c08fa5076f05 100644
--- a/drivers/char/drm/r300_cmdbuf.c
+++ b/drivers/char/drm/r300_cmdbuf.c
@@ -161,6 +161,7 @@ void r300_init_reg_flags(void)
         ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
         ADD_RANGE(R300_GB_ENABLE, 1);
         ADD_RANGE(R300_GB_MSPOS0, 5);
+        ADD_RANGE(R300_TX_CNTL, 1);
         ADD_RANGE(R300_TX_ENABLE, 1);
         ADD_RANGE(0x4200, 4);
         ADD_RANGE(0x4214, 1);
@@ -489,6 +490,50 @@ static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv,
 
         return 0;
 }
+static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
+                                             drm_radeon_kcmd_buffer_t *cmdbuf)
+{
+        u32 *cmd = (u32 *) cmdbuf->buf;
+        int count, ret;
+        RING_LOCALS;
+
+        count=(cmd[0]>>16) & 0x3fff;
+
+        if (cmd[0] & 0x8000) {
+                u32 offset;
+
+                if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL 
+                              | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
+                        offset = cmd[2] << 10;
+                        ret = r300_check_offset(dev_priv, offset);
+                        if (ret) {
+                                DRM_ERROR("Invalid bitblt first offset is %08X\n", offset);
+                                return DRM_ERR(EINVAL);
+                        }
+                }
+
+                if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
+                    (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
+                        offset = cmd[3] << 10;
+                        ret = r300_check_offset(dev_priv, offset);
+                        if (ret) {
+                                DRM_ERROR("Invalid bitblt second offset is %08X\n", offset);
+                                return DRM_ERR(EINVAL);
+                        }
+                        
+                }
+        }
+
+        BEGIN_RING(count+2);
+        OUT_RING(cmd[0]);
+        OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
+        ADVANCE_RING();
+
+        cmdbuf->buf += (count+2)*4;
+        cmdbuf->bufsz -= (count+2)*4;
+
+        return 0;
+}
 
 static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
                                             drm_radeon_kcmd_buffer_t *cmdbuf)
@@ -527,6 +572,9 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
         case RADEON_3D_LOAD_VBPNTR:     /* load vertex array pointers */
                 return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header);
 
+        case RADEON_CNTL_BITBLT_MULTI:
+                return r300_emit_bitblt_multi(dev_priv, cmdbuf);
+
         case RADEON_CP_3D_DRAW_IMMD_2:  /* triggers drawing using in-packet vertex data */
         case RADEON_CP_3D_DRAW_VBUF_2:  /* triggers drawing of vertex buffers setup elsewhere */
         case RADEON_CP_3D_DRAW_INDX_2:  /* triggers drawing using indices to vertex buffer */
diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h
index a0ed20e25221..d1e19954406b 100644
--- a/drivers/char/drm/r300_reg.h
+++ b/drivers/char/drm/r300_reg.h
@@ -451,6 +451,9 @@ I am fairly certain that they are correct unless stated otherwise in comments.
 /* END */
 
 /* gap */
+/* Zero to flush caches. */
+#define R300_TX_CNTL                        0x4100
+
 /* The upper enable bits are guessed, based on fglrx reported limits. */
 #define R300_TX_ENABLE                      0x4104
 #       define R300_TX_ENABLE_0                  (1 << 0)
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 498b19b1d641..1f7d2ab8c4fc 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -90,9 +90,10 @@
  * 1.19- Add support for gart table in FB memory and PCIE r300
  * 1.20- Add support for r300 texrect
  * 1.21- Add support for card type getparam
+ * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
  */
 #define DRIVER_MAJOR            1
-#define DRIVER_MINOR            21
+#define DRIVER_MINOR            22
 #define DRIVER_PATCHLEVEL       0
 
 /*
diff --git a/drivers/char/hvc_console.c b/drivers/char/hvc_console.c
index 1994a92d4733..f65b2e14a485 100644
--- a/drivers/char/hvc_console.c
+++ b/drivers/char/hvc_console.c
@@ -335,6 +335,8 @@ static int hvc_open(struct tty_struct *tty, struct file * filp)
         } /* else count == 0 */
 
         tty->driver_data = hp;
+        tty->low_latency = 1; /* Makes flushes to ldisc synchronous. */
+
         hp->tty = tty;
         /* Save for request_irq outside of spin_lock. */
         irq = hp->irq;
@@ -633,9 +635,6 @@ static int hvc_poll(struct hvc_struct *hp)
                         tty_insert_flip_char(tty, buf[i], 0);
                 }
 
-                if (count)
-                        tty_schedule_flip(tty);
-
                 /*
                  * Account for the total amount read in one loop, and if above
                  * 64 bytes, we do a quick schedule loop to let the tty grok
@@ -656,6 +655,9 @@ static int hvc_poll(struct hvc_struct *hp)
  bail:
         spin_unlock_irqrestore(&hp->lock, flags);
 
+        if (read_total)
+                tty_flip_buffer_push(tty);
+        
         return poll_mask;
 }
 
diff --git a/drivers/char/sx.c b/drivers/char/sx.c
index c2490e270f1f..a6b4f02bdceb 100644
--- a/drivers/char/sx.c
+++ b/drivers/char/sx.c
@@ -1095,17 +1095,17 @@ static inline void sx_receive_chars (struct sx_port *port)
 
                 sx_dprintk (SX_DEBUG_RECEIVE, "rxop=%d, c = %d.\n", rx_op, c); 
 
+                /* Don't copy past the end of the hardware receive buffer */
+                if (rx_op + c > 0x100) c = 0x100 - rx_op;
+
+                sx_dprintk (SX_DEBUG_RECEIVE, "c = %d.\n", c);
+
                 /* Don't copy more bytes than there is room for in the buffer */
 
                 c = tty_prepare_flip_string(tty, &rp, c);
 
                 sx_dprintk (SX_DEBUG_RECEIVE, "c = %d.\n", c); 
 
-                /* Don't copy past the end of the hardware receive buffer */
-                if (rx_op + c > 0x100) c = 0x100 - rx_op;
-
-                sx_dprintk (SX_DEBUG_RECEIVE, "c = %d.\n", c);
-
                 /* If for one reason or another, we can't copy more data, we're done! */
                 if (c == 0) break;
 
@@ -2173,15 +2173,17 @@ static int probe_si (struct sx_board *board)
         if ( IS_SI1_BOARD(board)) {
                 /* This should be an SI1 board, which has this
                    location writable... */
-                if (read_sx_byte (board, SI2_ISA_ID_BASE) != 0x10)
+                if (read_sx_byte (board, SI2_ISA_ID_BASE) != 0x10) {
                         func_exit ();
                         return 0; 
+                }
         } else {
                 /* This should be an SI2 board, which has the bottom
                    3 bits non-writable... */
-                if (read_sx_byte (board, SI2_ISA_ID_BASE) == 0x10)
+                if (read_sx_byte (board, SI2_ISA_ID_BASE) == 0x10) {
                         func_exit ();
                         return 0; 
+                }
         }
 
         /* Now we're pretty much convinced that there is an SI board here, 
@@ -2192,15 +2194,17 @@ static int probe_si (struct sx_board *board)
         if ( IS_SI1_BOARD(board)) {
                 /* This should be an SI1 board, which has this
                    location writable... */
-                if (read_sx_byte (board, SI2_ISA_ID_BASE) != 0x10)
+                if (read_sx_byte (board, SI2_ISA_ID_BASE) != 0x10) {
                         func_exit();
                         return 0; 
+                }
         } else {
                 /* This should be an SI2 board, which has the bottom
                    3 bits non-writable... */
-                if (read_sx_byte (board, SI2_ISA_ID_BASE) == 0x10)
+                if (read_sx_byte (board, SI2_ISA_ID_BASE) == 0x10) {
                         func_exit ();
                         return 0; 
+                }
         }
 
         printheader ();
diff --git a/drivers/char/sysrq.c b/drivers/char/sysrq.c
index 5765f672e853..d58f82318853 100644
--- a/drivers/char/sysrq.c
+++ b/drivers/char/sysrq.c
@@ -243,7 +243,7 @@ static struct sysrq_key_op sysrq_term_op = {
 
 static void moom_callback(void *ignored)
 {
-        out_of_memory(GFP_KERNEL, 0);
+        out_of_memory(&NODE_DATA(0)->node_zonelists[ZONE_NORMAL], GFP_KERNEL, 0);
 }
 
 static DECLARE_WORK(moom_work, moom_callback, NULL);
diff --git a/drivers/char/tpm/tpm_infineon.c b/drivers/char/tpm/tpm_infineon.c
index ec7590951af5..24095f6ee6da 100644
--- a/drivers/char/tpm/tpm_infineon.c
+++ b/drivers/char/tpm/tpm_infineon.c
@@ -33,6 +33,7 @@
 static int TPM_INF_DATA;
 static int TPM_INF_ADDR;
 static int TPM_INF_BASE;
+static int TPM_INF_ADDR_LEN;
 static int TPM_INF_PORT_LEN;
 
 /* TPM header definitions */
@@ -195,6 +196,7 @@ static int tpm_inf_recv(struct tpm_chip *chip, u8 * buf, size_t count)
         int i;
         int ret;
         u32 size = 0;
+        number_of_wtx = 0;
 
 recv_begin:
         /* start receiving header */
@@ -378,24 +380,35 @@ static int __devinit tpm_inf_pnp_probe(struct pnp_dev *dev,
         if (pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
             !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
                 TPM_INF_ADDR = pnp_port_start(dev, 0);
+                TPM_INF_ADDR_LEN = pnp_port_len(dev, 0);
                 TPM_INF_DATA = (TPM_INF_ADDR + 1);
                 TPM_INF_BASE = pnp_port_start(dev, 1);
                 TPM_INF_PORT_LEN = pnp_port_len(dev, 1);
-                if (!TPM_INF_PORT_LEN)
-                        return -EINVAL;
+                if ((TPM_INF_PORT_LEN < 4) || (TPM_INF_ADDR_LEN < 2)) {
+                        rc = -EINVAL;
+                        goto err_last;
+                }
                 dev_info(&dev->dev, "Found %s with ID %s\n",
                          dev->name, dev_id->id);
-                if (!((TPM_INF_BASE >> 8) & 0xff))
-                        return -EINVAL;
+                if (!((TPM_INF_BASE >> 8) & 0xff)) {
+                        rc = -EINVAL;
+                        goto err_last;
+                }
                 /* publish my base address and request region */
                 tpm_inf.base = TPM_INF_BASE;
                 if (request_region
                     (tpm_inf.base, TPM_INF_PORT_LEN, "tpm_infineon0") == NULL) {
-                        release_region(tpm_inf.base, TPM_INF_PORT_LEN);
-                        return -EINVAL;
+                        rc = -EINVAL;
+                        goto err_last;
+                }
+                if (request_region(TPM_INF_ADDR, TPM_INF_ADDR_LEN,
+                                "tpm_infineon0") == NULL) {
+                        rc = -EINVAL;
+                        goto err_last;
                 }
         } else {
-                return -EINVAL;
+                rc = -EINVAL;
+                goto err_last;
         }
 
         /* query chip for its vendor, its version number a.s.o. */
@@ -443,8 +456,8 @@ static int __devinit tpm_inf_pnp_probe(struct pnp_dev *dev,
                         dev_err(&dev->dev,
                                 "Could not set IO-ports to 0x%lx\n",
                                 tpm_inf.base);
-                        release_region(tpm_inf.base, TPM_INF_PORT_LEN);
-                        return -EIO;
+                        rc = -EIO;
+                        goto err_release_region;
                 }
 
                 /* activate register */
@@ -471,14 +484,21 @@ static int __devinit tpm_inf_pnp_probe(struct pnp_dev *dev,
 
                 rc = tpm_register_hardware(&dev->dev, &tpm_inf);
                 if (rc < 0) {
-                        release_region(tpm_inf.base, TPM_INF_PORT_LEN);
-                        return -ENODEV;
+                        rc = -ENODEV;
+                        goto err_release_region;
                 }
                 return 0;
         } else {
-                dev_info(&dev->dev, "No Infineon TPM found!\n");
-                return -ENODEV;
+                rc = -ENODEV;
+                goto err_release_region;
         }
+
+err_release_region:
+        release_region(tpm_inf.base, TPM_INF_PORT_LEN);
+        release_region(TPM_INF_ADDR, TPM_INF_ADDR_LEN);
+
+err_last:
+        return rc;
 }
 
 static __devexit void tpm_inf_pnp_remove(struct pnp_dev *dev)
@@ -518,5 +538,5 @@ module_exit(cleanup_inf);
 
 MODULE_AUTHOR("Marcel Selhorst <selhorst@crypto.rub.de>");
 MODULE_DESCRIPTION("Driver for Infineon TPM SLD 9630 TT 1.1 / SLB 9635 TT 1.2");
-MODULE_VERSION("1.6");
+MODULE_VERSION("1.7");
 MODULE_LICENSE("GPL");