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-rw-r--r--drivers/char/Kconfig12
-rw-r--r--drivers/char/agp/agp.h6
-rw-r--r--drivers/char/agp/alpha-agp.c4
-rw-r--r--drivers/char/agp/amd-k7-agp.c4
-rw-r--r--drivers/char/agp/amd64-agp.c89
-rw-r--r--drivers/char/agp/ati-agp.c8
-rw-r--r--drivers/char/agp/backend.c16
-rw-r--r--drivers/char/agp/compat_ioctl.c2
-rw-r--r--drivers/char/agp/efficeon-agp.c6
-rw-r--r--drivers/char/agp/frontend.c12
-rw-r--r--drivers/char/agp/generic.c35
-rw-r--r--drivers/char/agp/hp-agp.c6
-rw-r--r--drivers/char/agp/i460-agp.c2
-rw-r--r--drivers/char/agp/intel-agp.c239
-rw-r--r--drivers/char/agp/nvidia-agp.c4
-rw-r--r--drivers/char/agp/parisc-agp.c6
-rw-r--r--drivers/char/agp/sgi-agp.c8
-rw-r--r--drivers/char/agp/sworks-agp.c6
-rw-r--r--drivers/char/agp/uninorth-agp.c10
-rw-r--r--drivers/char/agp/via-agp.c13
-rw-r--r--drivers/char/drm/ati_pcigart.c8
-rw-r--r--drivers/char/drm/drm.h2
-rw-r--r--drivers/char/drm/drm_drv.c7
-rw-r--r--drivers/char/drm/drm_pciids.h17
-rw-r--r--drivers/char/drm/drm_sysfs.c2
-rw-r--r--drivers/char/drm/i915_drv.c1
-rw-r--r--drivers/char/drm/i915_drv.h11
-rw-r--r--drivers/char/drm/i915_irq.c4
-rw-r--r--drivers/char/drm/r300_cmdbuf.c117
-rw-r--r--drivers/char/drm/r300_reg.h242
-rw-r--r--drivers/char/drm/radeon_cp.c1148
-rw-r--r--drivers/char/drm/radeon_drm.h8
-rw-r--r--drivers/char/drm/radeon_drv.h251
-rw-r--r--drivers/char/drm/radeon_irq.c2
-rw-r--r--drivers/char/drm/radeon_microcode.h1844
-rw-r--r--drivers/char/drm/radeon_state.c17
-rw-r--r--drivers/char/generic_nvram.c2
-rw-r--r--drivers/char/hvc_xen.c61
-rw-r--r--drivers/char/hw_random/Kconfig9
-rw-r--r--drivers/char/hw_random/Makefile1
-rw-r--r--drivers/char/hw_random/intel-rng.c2
-rw-r--r--drivers/char/hw_random/virtio-rng.c155
-rw-r--r--drivers/char/ip2/Makefile4
-rw-r--r--drivers/char/ip2/ip2main.c23
-rw-r--r--drivers/char/keyboard.c7
-rw-r--r--drivers/char/pcmcia/ipwireless/hardware.c20
-rw-r--r--drivers/char/sysrq.c1
-rw-r--r--drivers/char/tty_io.c2
-rw-r--r--drivers/char/tty_ioctl.c7
-rw-r--r--drivers/char/viocons.c2
-rw-r--r--drivers/char/viotape.c2
-rw-r--r--drivers/char/vt.c15
52 files changed, 3126 insertions, 1356 deletions
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 595a925c62a9..2d854bb9373e 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -118,8 +118,8 @@ config COMPUTONE
118 order to become a dial-in server. If you have a card like that, say 118 order to become a dial-in server. If you have a card like that, say
119 Y here and read <file:Documentation/computone.txt>. 119 Y here and read <file:Documentation/computone.txt>.
120 120
121 To compile this driver as modules, choose M here: the 121 To compile this driver as module, choose M here: the
122 modules will be called ip2 and ip2main. 122 module will be called ip2.
123 123
124config ROCKETPORT 124config ROCKETPORT
125 tristate "Comtrol RocketPort support" 125 tristate "Comtrol RocketPort support"
@@ -749,7 +749,7 @@ config NVRAM
749if RTC_LIB=n 749if RTC_LIB=n
750 750
751config RTC 751config RTC
752 tristate "Enhanced Real Time Clock Support" 752 tristate "Enhanced Real Time Clock Support (legacy PC RTC driver)"
753 depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV \ 753 depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV \
754 && !ARM && !SUPERH && !S390 && !AVR32 754 && !ARM && !SUPERH && !S390 && !AVR32
755 ---help--- 755 ---help---
@@ -1036,9 +1036,9 @@ config HPET
1036 non-periodic and/or periodic. 1036 non-periodic and/or periodic.
1037 1037
1038config HPET_RTC_IRQ 1038config HPET_RTC_IRQ
1039 bool "HPET Control RTC IRQ" if !HPET_EMULATE_RTC 1039 bool
1040 default n 1040 default HPET_EMULATE_RTC
1041 depends on HPET 1041 depends on RTC && HPET
1042 help 1042 help
1043 If you say Y here, you will disable RTC_IRQ in drivers/char/rtc.c. It 1043 If you say Y here, you will disable RTC_IRQ in drivers/char/rtc.c. It
1044 is assumed the platform called hpet_alloc with the RTC IRQ values for 1044 is assumed the platform called hpet_alloc with the RTC IRQ values for
diff --git a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h
index 99e6a406efb4..81e14bea54bd 100644
--- a/drivers/char/agp/agp.h
+++ b/drivers/char/agp/agp.h
@@ -99,8 +99,8 @@ struct agp_bridge_driver {
99 const void *aperture_sizes; 99 const void *aperture_sizes;
100 int num_aperture_sizes; 100 int num_aperture_sizes;
101 enum aper_size_type size_type; 101 enum aper_size_type size_type;
102 int cant_use_aperture; 102 bool cant_use_aperture;
103 int needs_scratch_page; 103 bool needs_scratch_page;
104 const struct gatt_mask *masks; 104 const struct gatt_mask *masks;
105 int (*fetch_size)(void); 105 int (*fetch_size)(void);
106 int (*configure)(void); 106 int (*configure)(void);
@@ -278,7 +278,7 @@ void agp_generic_destroy_page(void *addr, int flags);
278void agp_free_key(int key); 278void agp_free_key(int key);
279int agp_num_entries(void); 279int agp_num_entries(void);
280u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command); 280u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command);
281void agp_device_command(u32 command, int agp_v3); 281void agp_device_command(u32 command, bool agp_v3);
282int agp_3_5_enable(struct agp_bridge_data *bridge); 282int agp_3_5_enable(struct agp_bridge_data *bridge);
283void global_cache_flush(void); 283void global_cache_flush(void);
284void get_agp_version(struct agp_bridge_data *bridge); 284void get_agp_version(struct agp_bridge_data *bridge);
diff --git a/drivers/char/agp/alpha-agp.c b/drivers/char/agp/alpha-agp.c
index e77c17838c8a..5da89f6c6c25 100644
--- a/drivers/char/agp/alpha-agp.c
+++ b/drivers/char/agp/alpha-agp.c
@@ -80,7 +80,7 @@ static void alpha_core_agp_enable(struct agp_bridge_data *bridge, u32 mode)
80 agp->mode.bits.enable = 1; 80 agp->mode.bits.enable = 1;
81 agp->ops->configure(agp); 81 agp->ops->configure(agp);
82 82
83 agp_device_command(agp->mode.lw, 0); 83 agp_device_command(agp->mode.lw, false);
84} 84}
85 85
86static int alpha_core_agp_insert_memory(struct agp_memory *mem, off_t pg_start, 86static int alpha_core_agp_insert_memory(struct agp_memory *mem, off_t pg_start,
@@ -126,7 +126,7 @@ struct agp_bridge_driver alpha_core_agp_driver = {
126 .aperture_sizes = alpha_core_agp_sizes, 126 .aperture_sizes = alpha_core_agp_sizes,
127 .num_aperture_sizes = 1, 127 .num_aperture_sizes = 1,
128 .size_type = FIXED_APER_SIZE, 128 .size_type = FIXED_APER_SIZE,
129 .cant_use_aperture = 1, 129 .cant_use_aperture = true,
130 .masks = NULL, 130 .masks = NULL,
131 131
132 .fetch_size = alpha_core_agp_fetch_size, 132 .fetch_size = alpha_core_agp_fetch_size,
diff --git a/drivers/char/agp/amd-k7-agp.c b/drivers/char/agp/amd-k7-agp.c
index 96bdb9296b07..39a0718bc616 100644
--- a/drivers/char/agp/amd-k7-agp.c
+++ b/drivers/char/agp/amd-k7-agp.c
@@ -314,9 +314,9 @@ static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
314 j++; 314 j++;
315 } 315 }
316 316
317 if (mem->is_flushed == FALSE) { 317 if (!mem->is_flushed) {
318 global_cache_flush(); 318 global_cache_flush();
319 mem->is_flushed = TRUE; 319 mem->is_flushed = true;
320 } 320 }
321 321
322 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 322 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index d8200ac8f8cb..481ffe87c716 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -16,28 +16,9 @@
16#include <asm/page.h> /* PAGE_SIZE */ 16#include <asm/page.h> /* PAGE_SIZE */
17#include <asm/e820.h> 17#include <asm/e820.h>
18#include <asm/k8.h> 18#include <asm/k8.h>
19#include <asm/gart.h>
19#include "agp.h" 20#include "agp.h"
20 21
21/* PTE bits. */
22#define GPTE_VALID 1
23#define GPTE_COHERENT 2
24
25/* Aperture control register bits. */
26#define GARTEN (1<<0)
27#define DISGARTCPU (1<<4)
28#define DISGARTIO (1<<5)
29
30/* GART cache control register bits. */
31#define INVGART (1<<0)
32#define GARTPTEERR (1<<1)
33
34/* K8 On-cpu GART registers */
35#define AMD64_GARTAPERTURECTL 0x90
36#define AMD64_GARTAPERTUREBASE 0x94
37#define AMD64_GARTTABLEBASE 0x98
38#define AMD64_GARTCACHECTL 0x9c
39#define AMD64_GARTEN (1<<0)
40
41/* NVIDIA K8 registers */ 22/* NVIDIA K8 registers */
42#define NVIDIA_X86_64_0_APBASE 0x10 23#define NVIDIA_X86_64_0_APBASE 0x10
43#define NVIDIA_X86_64_1_APBASE1 0x50 24#define NVIDIA_X86_64_1_APBASE1 0x50
@@ -90,9 +71,9 @@ static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
90 j++; 71 j++;
91 } 72 }
92 73
93 if (mem->is_flushed == FALSE) { 74 if (!mem->is_flushed) {
94 global_cache_flush(); 75 global_cache_flush();
95 mem->is_flushed = TRUE; 76 mem->is_flushed = true;
96 } 77 }
97 78
98 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 79 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
@@ -165,29 +146,18 @@ static int amd64_fetch_size(void)
165 * In a multiprocessor x86-64 system, this function gets 146 * In a multiprocessor x86-64 system, this function gets
166 * called once for each CPU. 147 * called once for each CPU.
167 */ 148 */
168static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table) 149static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
169{ 150{
170 u64 aperturebase; 151 u64 aperturebase;
171 u32 tmp; 152 u32 tmp;
172 u64 addr, aper_base; 153 u64 aper_base;
173 154
174 /* Address to map to */ 155 /* Address to map to */
175 pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp); 156 pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
176 aperturebase = tmp << 25; 157 aperturebase = tmp << 25;
177 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); 158 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
178 159
179 /* address of the mappings table */ 160 enable_gart_translation(hammer, gatt_table);
180 addr = (u64) gatt_table;
181 addr >>= 12;
182 tmp = (u32) addr<<4;
183 tmp &= ~0xf;
184 pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp);
185
186 /* Enable GART translation for this hammer. */
187 pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
188 tmp |= GARTEN;
189 tmp &= ~(DISGARTCPU | DISGARTIO);
190 pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
191 161
192 return aper_base; 162 return aper_base;
193} 163}
@@ -226,9 +196,9 @@ static void amd64_cleanup(void)
226 for (i = 0; i < num_k8_northbridges; i++) { 196 for (i = 0; i < num_k8_northbridges; i++) {
227 struct pci_dev *dev = k8_northbridges[i]; 197 struct pci_dev *dev = k8_northbridges[i];
228 /* disable gart translation */ 198 /* disable gart translation */
229 pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp); 199 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
230 tmp &= ~AMD64_GARTEN; 200 tmp &= ~AMD64_GARTEN;
231 pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp); 201 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
232 } 202 }
233} 203}
234 204
@@ -258,24 +228,10 @@ static const struct agp_bridge_driver amd_8151_driver = {
258}; 228};
259 229
260/* Some basic sanity checks for the aperture. */ 230/* Some basic sanity checks for the aperture. */
261static int __devinit aperture_valid(u64 aper, u32 size) 231static int __devinit agp_aperture_valid(u64 aper, u32 size)
262{ 232{
263 if (aper == 0) { 233 if (!aperture_valid(aper, size, 32*1024*1024))
264 printk(KERN_ERR PFX "No aperture\n");
265 return 0;
266 }
267 if (size < 32*1024*1024) {
268 printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20);
269 return 0;
270 }
271 if ((u64)aper + size > 0x100000000ULL) {
272 printk(KERN_ERR PFX "Aperture out of bounds\n");
273 return 0; 234 return 0;
274 }
275 if (e820_any_mapped(aper, aper + size, E820_RAM)) {
276 printk(KERN_ERR PFX "Aperture pointing to RAM\n");
277 return 0;
278 }
279 235
280 /* Request the Aperture. This catches cases when someone else 236 /* Request the Aperture. This catches cases when someone else
281 already put a mapping in there - happens with some very broken BIOS 237 already put a mapping in there - happens with some very broken BIOS
@@ -308,11 +264,11 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
308 u32 nb_order, nb_base; 264 u32 nb_order, nb_base;
309 u16 apsize; 265 u16 apsize;
310 266
311 pci_read_config_dword(nb, 0x90, &nb_order); 267 pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
312 nb_order = (nb_order >> 1) & 7; 268 nb_order = (nb_order >> 1) & 7;
313 pci_read_config_dword(nb, 0x94, &nb_base); 269 pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
314 nb_aper = nb_base << 25; 270 nb_aper = nb_base << 25;
315 if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) { 271 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
316 return 0; 272 return 0;
317 } 273 }
318 274
@@ -331,12 +287,23 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
331 pci_read_config_dword(agp, 0x10, &aper_low); 287 pci_read_config_dword(agp, 0x10, &aper_low);
332 pci_read_config_dword(agp, 0x14, &aper_hi); 288 pci_read_config_dword(agp, 0x14, &aper_hi);
333 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); 289 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
290
291 /*
292 * On some sick chips APSIZE is 0. This means it wants 4G
293 * so let double check that order, and lets trust the AMD NB settings
294 */
295 if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
296 printk(KERN_INFO "Aperture size %u MB is not right, using settings from NB\n",
297 32 << order);
298 order = nb_order;
299 }
300
334 printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order); 301 printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order);
335 if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order)) 302 if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
336 return -1; 303 return -1;
337 304
338 pci_write_config_dword(nb, 0x90, order << 1); 305 pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1);
339 pci_write_config_dword(nb, 0x94, aper >> 25); 306 pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
340 307
341 return 0; 308 return 0;
342} 309}
diff --git a/drivers/char/agp/ati-agp.c b/drivers/char/agp/ati-agp.c
index 55c97f623242..3a4566c0d84f 100644
--- a/drivers/char/agp/ati-agp.c
+++ b/drivers/char/agp/ati-agp.c
@@ -287,10 +287,10 @@ static int ati_insert_memory(struct agp_memory * mem,
287 j++; 287 j++;
288 } 288 }
289 289
290 if (mem->is_flushed == FALSE) { 290 if (!mem->is_flushed) {
291 /*CACHE_FLUSH(); */ 291 /*CACHE_FLUSH(); */
292 global_cache_flush(); 292 global_cache_flush();
293 mem->is_flushed = TRUE; 293 mem->is_flushed = true;
294 } 294 }
295 295
296 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 296 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
@@ -458,6 +458,10 @@ static struct agp_device_ids ati_agp_device_ids[] __devinitdata =
458 .chipset_name = "IGP9100/M", 458 .chipset_name = "IGP9100/M",
459 }, 459 },
460 { 460 {
461 .device_id = PCI_DEVICE_ID_ATI_RS350_133,
462 .chipset_name = "IGP9000/M",
463 },
464 {
461 .device_id = PCI_DEVICE_ID_ATI_RS350_200, 465 .device_id = PCI_DEVICE_ID_ATI_RS350_200,
462 .chipset_name = "IGP9100/M", 466 .chipset_name = "IGP9100/M",
463 }, 467 },
diff --git a/drivers/char/agp/backend.c b/drivers/char/agp/backend.c
index b1bdd015165c..1ec87104e68c 100644
--- a/drivers/char/agp/backend.c
+++ b/drivers/char/agp/backend.c
@@ -188,10 +188,10 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge)
188 188
189err_out: 189err_out:
190 if (bridge->driver->needs_scratch_page) { 190 if (bridge->driver->needs_scratch_page) {
191 bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real), 191 void *va = gart_to_virt(bridge->scratch_page_real);
192 AGP_PAGE_DESTROY_UNMAP); 192
193 bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real), 193 bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_UNMAP);
194 AGP_PAGE_DESTROY_FREE); 194 bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_FREE);
195 } 195 }
196 if (got_gatt) 196 if (got_gatt)
197 bridge->driver->free_gatt_table(bridge); 197 bridge->driver->free_gatt_table(bridge);
@@ -215,10 +215,10 @@ static void agp_backend_cleanup(struct agp_bridge_data *bridge)
215 215
216 if (bridge->driver->agp_destroy_page && 216 if (bridge->driver->agp_destroy_page &&
217 bridge->driver->needs_scratch_page) { 217 bridge->driver->needs_scratch_page) {
218 bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real), 218 void *va = gart_to_virt(bridge->scratch_page_real);
219 AGP_PAGE_DESTROY_UNMAP); 219
220 bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real), 220 bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_UNMAP);
221 AGP_PAGE_DESTROY_FREE); 221 bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_FREE);
222 } 222 }
223} 223}
224 224
diff --git a/drivers/char/agp/compat_ioctl.c b/drivers/char/agp/compat_ioctl.c
index 39275794fe63..58c57cb2518c 100644
--- a/drivers/char/agp/compat_ioctl.c
+++ b/drivers/char/agp/compat_ioctl.c
@@ -214,7 +214,7 @@ long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
214 ret_val = -EINVAL; 214 ret_val = -EINVAL;
215 goto ioctl_out; 215 goto ioctl_out;
216 } 216 }
217 if ((agp_fe.backend_acquired != TRUE) && 217 if ((agp_fe.backend_acquired != true) &&
218 (cmd != AGPIOC_ACQUIRE32)) { 218 (cmd != AGPIOC_ACQUIRE32)) {
219 ret_val = -EBUSY; 219 ret_val = -EBUSY;
220 goto ioctl_out; 220 goto ioctl_out;
diff --git a/drivers/char/agp/efficeon-agp.c b/drivers/char/agp/efficeon-agp.c
index cac0009cebc1..8ca6f262ef85 100644
--- a/drivers/char/agp/efficeon-agp.c
+++ b/drivers/char/agp/efficeon-agp.c
@@ -249,9 +249,9 @@ static int efficeon_insert_memory(struct agp_memory * mem, off_t pg_start, int t
249 if (type != 0 || mem->type != 0) 249 if (type != 0 || mem->type != 0)
250 return -EINVAL; 250 return -EINVAL;
251 251
252 if (mem->is_flushed == FALSE) { 252 if (!mem->is_flushed) {
253 global_cache_flush(); 253 global_cache_flush();
254 mem->is_flushed = TRUE; 254 mem->is_flushed = true;
255 } 255 }
256 256
257 last_page = NULL; 257 last_page = NULL;
@@ -329,7 +329,7 @@ static const struct agp_bridge_driver efficeon_driver = {
329 .free_gatt_table = efficeon_free_gatt_table, 329 .free_gatt_table = efficeon_free_gatt_table,
330 .insert_memory = efficeon_insert_memory, 330 .insert_memory = efficeon_insert_memory,
331 .remove_memory = efficeon_remove_memory, 331 .remove_memory = efficeon_remove_memory,
332 .cant_use_aperture = 0, // 1 might be faster? 332 .cant_use_aperture = false, // true might be faster?
333 333
334 // Generic 334 // Generic
335 .alloc_by_type = agp_generic_alloc_by_type, 335 .alloc_by_type = agp_generic_alloc_by_type,
diff --git a/drivers/char/agp/frontend.c b/drivers/char/agp/frontend.c
index 857b26227d87..e6cb1ab03e06 100644
--- a/drivers/char/agp/frontend.c
+++ b/drivers/char/agp/frontend.c
@@ -395,7 +395,7 @@ static int agp_remove_controller(struct agp_controller *controller)
395 395
396 if (agp_fe.current_controller == controller) { 396 if (agp_fe.current_controller == controller) {
397 agp_fe.current_controller = NULL; 397 agp_fe.current_controller = NULL;
398 agp_fe.backend_acquired = FALSE; 398 agp_fe.backend_acquired = false;
399 agp_backend_release(agp_bridge); 399 agp_backend_release(agp_bridge);
400 } 400 }
401 kfree(controller); 401 kfree(controller);
@@ -443,7 +443,7 @@ static void agp_controller_release_current(struct agp_controller *controller,
443 } 443 }
444 444
445 agp_fe.current_controller = NULL; 445 agp_fe.current_controller = NULL;
446 agp_fe.used_by_controller = FALSE; 446 agp_fe.used_by_controller = false;
447 agp_backend_release(agp_bridge); 447 agp_backend_release(agp_bridge);
448} 448}
449 449
@@ -573,7 +573,7 @@ static int agp_mmap(struct file *file, struct vm_area_struct *vma)
573 573
574 mutex_lock(&(agp_fe.agp_mutex)); 574 mutex_lock(&(agp_fe.agp_mutex));
575 575
576 if (agp_fe.backend_acquired != TRUE) 576 if (agp_fe.backend_acquired != true)
577 goto out_eperm; 577 goto out_eperm;
578 578
579 if (!(test_bit(AGP_FF_IS_VALID, &priv->access_flags))) 579 if (!(test_bit(AGP_FF_IS_VALID, &priv->access_flags)))
@@ -768,7 +768,7 @@ int agpioc_acquire_wrap(struct agp_file_private *priv)
768 768
769 atomic_inc(&agp_bridge->agp_in_use); 769 atomic_inc(&agp_bridge->agp_in_use);
770 770
771 agp_fe.backend_acquired = TRUE; 771 agp_fe.backend_acquired = true;
772 772
773 controller = agp_find_controller_by_pid(priv->my_pid); 773 controller = agp_find_controller_by_pid(priv->my_pid);
774 774
@@ -778,7 +778,7 @@ int agpioc_acquire_wrap(struct agp_file_private *priv)
778 controller = agp_create_controller(priv->my_pid); 778 controller = agp_create_controller(priv->my_pid);
779 779
780 if (controller == NULL) { 780 if (controller == NULL) {
781 agp_fe.backend_acquired = FALSE; 781 agp_fe.backend_acquired = false;
782 agp_backend_release(agp_bridge); 782 agp_backend_release(agp_bridge);
783 return -ENOMEM; 783 return -ENOMEM;
784 } 784 }
@@ -981,7 +981,7 @@ static long agp_ioctl(struct file *file,
981 ret_val = -EINVAL; 981 ret_val = -EINVAL;
982 goto ioctl_out; 982 goto ioctl_out;
983 } 983 }
984 if ((agp_fe.backend_acquired != TRUE) && 984 if ((agp_fe.backend_acquired != true) &&
985 (cmd != AGPIOC_ACQUIRE)) { 985 (cmd != AGPIOC_ACQUIRE)) {
986 ret_val = -EBUSY; 986 ret_val = -EBUSY;
987 goto ioctl_out; 987 goto ioctl_out;
diff --git a/drivers/char/agp/generic.c b/drivers/char/agp/generic.c
index 7fc0c99a3a58..564daaa6c7d0 100644
--- a/drivers/char/agp/generic.c
+++ b/drivers/char/agp/generic.c
@@ -96,13 +96,13 @@ EXPORT_SYMBOL(agp_flush_chipset);
96void agp_alloc_page_array(size_t size, struct agp_memory *mem) 96void agp_alloc_page_array(size_t size, struct agp_memory *mem)
97{ 97{
98 mem->memory = NULL; 98 mem->memory = NULL;
99 mem->vmalloc_flag = 0; 99 mem->vmalloc_flag = false;
100 100
101 if (size <= 2*PAGE_SIZE) 101 if (size <= 2*PAGE_SIZE)
102 mem->memory = kmalloc(size, GFP_KERNEL | __GFP_NORETRY); 102 mem->memory = kmalloc(size, GFP_KERNEL | __GFP_NORETRY);
103 if (mem->memory == NULL) { 103 if (mem->memory == NULL) {
104 mem->memory = vmalloc(size); 104 mem->memory = vmalloc(size);
105 mem->vmalloc_flag = 1; 105 mem->vmalloc_flag = true;
106 } 106 }
107} 107}
108EXPORT_SYMBOL(agp_alloc_page_array); 108EXPORT_SYMBOL(agp_alloc_page_array);
@@ -188,7 +188,7 @@ void agp_free_memory(struct agp_memory *curr)
188 if (curr == NULL) 188 if (curr == NULL)
189 return; 189 return;
190 190
191 if (curr->is_bound == TRUE) 191 if (curr->is_bound)
192 agp_unbind_memory(curr); 192 agp_unbind_memory(curr);
193 193
194 if (curr->type >= AGP_USER_TYPES) { 194 if (curr->type >= AGP_USER_TYPES) {
@@ -202,10 +202,13 @@ void agp_free_memory(struct agp_memory *curr)
202 } 202 }
203 if (curr->page_count != 0) { 203 if (curr->page_count != 0) {
204 for (i = 0; i < curr->page_count; i++) { 204 for (i = 0; i < curr->page_count; i++) {
205 curr->bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[i]), AGP_PAGE_DESTROY_UNMAP); 205 curr->memory[i] = (unsigned long)gart_to_virt(curr->memory[i]);
206 curr->bridge->driver->agp_destroy_page((void *)curr->memory[i],
207 AGP_PAGE_DESTROY_UNMAP);
206 } 208 }
207 for (i = 0; i < curr->page_count; i++) { 209 for (i = 0; i < curr->page_count; i++) {
208 curr->bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[i]), AGP_PAGE_DESTROY_FREE); 210 curr->bridge->driver->agp_destroy_page((void *)curr->memory[i],
211 AGP_PAGE_DESTROY_FREE);
209 } 212 }
210 } 213 }
211 agp_free_key(curr->key); 214 agp_free_key(curr->key);
@@ -411,20 +414,20 @@ int agp_bind_memory(struct agp_memory *curr, off_t pg_start)
411 if (curr == NULL) 414 if (curr == NULL)
412 return -EINVAL; 415 return -EINVAL;
413 416
414 if (curr->is_bound == TRUE) { 417 if (curr->is_bound) {
415 printk(KERN_INFO PFX "memory %p is already bound!\n", curr); 418 printk(KERN_INFO PFX "memory %p is already bound!\n", curr);
416 return -EINVAL; 419 return -EINVAL;
417 } 420 }
418 if (curr->is_flushed == FALSE) { 421 if (!curr->is_flushed) {
419 curr->bridge->driver->cache_flush(); 422 curr->bridge->driver->cache_flush();
420 curr->is_flushed = TRUE; 423 curr->is_flushed = true;
421 } 424 }
422 ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type); 425 ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type);
423 426
424 if (ret_val != 0) 427 if (ret_val != 0)
425 return ret_val; 428 return ret_val;
426 429
427 curr->is_bound = TRUE; 430 curr->is_bound = true;
428 curr->pg_start = pg_start; 431 curr->pg_start = pg_start;
429 return 0; 432 return 0;
430} 433}
@@ -446,7 +449,7 @@ int agp_unbind_memory(struct agp_memory *curr)
446 if (curr == NULL) 449 if (curr == NULL)
447 return -EINVAL; 450 return -EINVAL;
448 451
449 if (curr->is_bound != TRUE) { 452 if (!curr->is_bound) {
450 printk(KERN_INFO PFX "memory %p was not bound!\n", curr); 453 printk(KERN_INFO PFX "memory %p was not bound!\n", curr);
451 return -EINVAL; 454 return -EINVAL;
452 } 455 }
@@ -456,7 +459,7 @@ int agp_unbind_memory(struct agp_memory *curr)
456 if (ret_val != 0) 459 if (ret_val != 0)
457 return ret_val; 460 return ret_val;
458 461
459 curr->is_bound = FALSE; 462 curr->is_bound = false;
460 curr->pg_start = 0; 463 curr->pg_start = 0;
461 return 0; 464 return 0;
462} 465}
@@ -754,7 +757,7 @@ u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 requested_mode
754EXPORT_SYMBOL(agp_collect_device_status); 757EXPORT_SYMBOL(agp_collect_device_status);
755 758
756 759
757void agp_device_command(u32 bridge_agpstat, int agp_v3) 760void agp_device_command(u32 bridge_agpstat, bool agp_v3)
758{ 761{
759 struct pci_dev *device = NULL; 762 struct pci_dev *device = NULL;
760 int mode; 763 int mode;
@@ -818,7 +821,7 @@ void agp_generic_enable(struct agp_bridge_data *bridge, u32 requested_mode)
818 /* If we have 3.5, we can do the isoch stuff. */ 821 /* If we have 3.5, we can do the isoch stuff. */
819 if (bridge->minor_version >= 5) 822 if (bridge->minor_version >= 5)
820 agp_3_5_enable(bridge); 823 agp_3_5_enable(bridge);
821 agp_device_command(bridge_agpstat, TRUE); 824 agp_device_command(bridge_agpstat, true);
822 return; 825 return;
823 } else { 826 } else {
824 /* Disable calibration cycle in RX91<1> when not in AGP3.0 mode of operation.*/ 827 /* Disable calibration cycle in RX91<1> when not in AGP3.0 mode of operation.*/
@@ -835,7 +838,7 @@ void agp_generic_enable(struct agp_bridge_data *bridge, u32 requested_mode)
835 } 838 }
836 839
837 /* AGP v<3 */ 840 /* AGP v<3 */
838 agp_device_command(bridge_agpstat, FALSE); 841 agp_device_command(bridge_agpstat, false);
839} 842}
840EXPORT_SYMBOL(agp_generic_enable); 843EXPORT_SYMBOL(agp_generic_enable);
841 844
@@ -1083,9 +1086,9 @@ int agp_generic_insert_memory(struct agp_memory * mem, off_t pg_start, int type)
1083 j++; 1086 j++;
1084 } 1087 }
1085 1088
1086 if (mem->is_flushed == FALSE) { 1089 if (!mem->is_flushed) {
1087 bridge->driver->cache_flush(); 1090 bridge->driver->cache_flush();
1088 mem->is_flushed = TRUE; 1091 mem->is_flushed = true;
1089 } 1092 }
1090 1093
1091 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 1094 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
diff --git a/drivers/char/agp/hp-agp.c b/drivers/char/agp/hp-agp.c
index cbb0444467ba..80d7317f85c9 100644
--- a/drivers/char/agp/hp-agp.c
+++ b/drivers/char/agp/hp-agp.c
@@ -353,9 +353,9 @@ hp_zx1_insert_memory (struct agp_memory *mem, off_t pg_start, int type)
353 j++; 353 j++;
354 } 354 }
355 355
356 if (mem->is_flushed == FALSE) { 356 if (!mem->is_flushed) {
357 global_cache_flush(); 357 global_cache_flush();
358 mem->is_flushed = TRUE; 358 mem->is_flushed = true;
359 } 359 }
360 360
361 for (i = 0, j = io_pg_start; i < mem->page_count; i++) { 361 for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
@@ -437,7 +437,7 @@ const struct agp_bridge_driver hp_zx1_driver = {
437 .agp_alloc_page = agp_generic_alloc_page, 437 .agp_alloc_page = agp_generic_alloc_page,
438 .agp_destroy_page = agp_generic_destroy_page, 438 .agp_destroy_page = agp_generic_destroy_page,
439 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 439 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
440 .cant_use_aperture = 1, 440 .cant_use_aperture = true,
441}; 441};
442 442
443static int __init 443static int __init
diff --git a/drivers/char/agp/i460-agp.c b/drivers/char/agp/i460-agp.c
index 76f581c85a7d..e587eebebc67 100644
--- a/drivers/char/agp/i460-agp.c
+++ b/drivers/char/agp/i460-agp.c
@@ -580,7 +580,7 @@ const struct agp_bridge_driver intel_i460_driver = {
580 .alloc_by_type = agp_generic_alloc_by_type, 580 .alloc_by_type = agp_generic_alloc_by_type,
581 .free_by_type = agp_generic_free_by_type, 581 .free_by_type = agp_generic_free_by_type,
582 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 582 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
583 .cant_use_aperture = 1, 583 .cant_use_aperture = true,
584}; 584};
585 585
586static int __devinit agp_intel_i460_probe(struct pci_dev *pdev, 586static int __devinit agp_intel_i460_probe(struct pci_dev *pdev,
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index eeea50a1d22a..df702642ab8f 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -34,6 +34,12 @@
34#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 34#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
35#define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40 35#define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40
36#define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42 36#define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42
37#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
38#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
39#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
40#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
41#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
42#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
37 43
38/* cover 915 and 945 variants */ 44/* cover 915 and 945 variants */
39#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ 45#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@ -55,6 +61,10 @@
55 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ 61 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
56 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB) 62 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
57 63
64#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
65 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
66 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB)
67
58extern int agp_memory_reserved; 68extern int agp_memory_reserved;
59 69
60 70
@@ -80,8 +90,13 @@ extern int agp_memory_reserved;
80#define I915_PTEADDR 0x1C 90#define I915_PTEADDR 0x1C
81#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 91#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
82#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 92#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
83#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 93#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
84#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 94#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
95#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
96#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
97#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
98#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
99
85#define I915_IFPADDR 0x60 100#define I915_IFPADDR 0x60
86 101
87/* Intel 965G registers */ 102/* Intel 965G registers */
@@ -325,7 +340,7 @@ static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
325out: 340out:
326 ret = 0; 341 ret = 0;
327out_err: 342out_err:
328 mem->is_flushed = 1; 343 mem->is_flushed = true;
329 return ret; 344 return ret;
330} 345}
331 346
@@ -418,9 +433,11 @@ static void intel_i810_free_by_type(struct agp_memory *curr)
418 if (curr->page_count == 4) 433 if (curr->page_count == 4)
419 i8xx_destroy_pages(gart_to_virt(curr->memory[0])); 434 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
420 else { 435 else {
421 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]), 436 void *va = gart_to_virt(curr->memory[0]);
437
438 agp_bridge->driver->agp_destroy_page(va,
422 AGP_PAGE_DESTROY_UNMAP); 439 AGP_PAGE_DESTROY_UNMAP);
423 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]), 440 agp_bridge->driver->agp_destroy_page(va,
424 AGP_PAGE_DESTROY_FREE); 441 AGP_PAGE_DESTROY_FREE);
425 } 442 }
426 agp_free_page_array(curr); 443 agp_free_page_array(curr);
@@ -504,6 +521,10 @@ static void intel_i830_init_gtt_entries(void)
504 size = 512; 521 size = 512;
505 } 522 }
506 size += 4; 523 size += 4;
524 } else if (IS_G4X) {
525 /* On 4 series hardware, GTT stolen is separate from graphics
526 * stolen, ignore it in stolen gtt entries counting */
527 size = 0;
507 } else { 528 } else {
508 /* On previous hardware, the GTT size was just what was 529 /* On previous hardware, the GTT size was just what was
509 * required to map the aperture. 530 * required to map the aperture.
@@ -552,30 +573,54 @@ static void intel_i830_init_gtt_entries(void)
552 break; 573 break;
553 case I915_GMCH_GMS_STOLEN_48M: 574 case I915_GMCH_GMS_STOLEN_48M:
554 /* Check it's really I915G */ 575 /* Check it's really I915G */
555 if (IS_I915 || IS_I965 || IS_G33) 576 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
556 gtt_entries = MB(48) - KB(size); 577 gtt_entries = MB(48) - KB(size);
557 else 578 else
558 gtt_entries = 0; 579 gtt_entries = 0;
559 break; 580 break;
560 case I915_GMCH_GMS_STOLEN_64M: 581 case I915_GMCH_GMS_STOLEN_64M:
561 /* Check it's really I915G */ 582 /* Check it's really I915G */
562 if (IS_I915 || IS_I965 || IS_G33) 583 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
563 gtt_entries = MB(64) - KB(size); 584 gtt_entries = MB(64) - KB(size);
564 else 585 else
565 gtt_entries = 0; 586 gtt_entries = 0;
566 break; 587 break;
567 case G33_GMCH_GMS_STOLEN_128M: 588 case G33_GMCH_GMS_STOLEN_128M:
568 if (IS_G33) 589 if (IS_G33 || IS_I965 || IS_G4X)
569 gtt_entries = MB(128) - KB(size); 590 gtt_entries = MB(128) - KB(size);
570 else 591 else
571 gtt_entries = 0; 592 gtt_entries = 0;
572 break; 593 break;
573 case G33_GMCH_GMS_STOLEN_256M: 594 case G33_GMCH_GMS_STOLEN_256M:
574 if (IS_G33) 595 if (IS_G33 || IS_I965 || IS_G4X)
575 gtt_entries = MB(256) - KB(size); 596 gtt_entries = MB(256) - KB(size);
576 else 597 else
577 gtt_entries = 0; 598 gtt_entries = 0;
578 break; 599 break;
600 case INTEL_GMCH_GMS_STOLEN_96M:
601 if (IS_I965 || IS_G4X)
602 gtt_entries = MB(96) - KB(size);
603 else
604 gtt_entries = 0;
605 break;
606 case INTEL_GMCH_GMS_STOLEN_160M:
607 if (IS_I965 || IS_G4X)
608 gtt_entries = MB(160) - KB(size);
609 else
610 gtt_entries = 0;
611 break;
612 case INTEL_GMCH_GMS_STOLEN_224M:
613 if (IS_I965 || IS_G4X)
614 gtt_entries = MB(224) - KB(size);
615 else
616 gtt_entries = 0;
617 break;
618 case INTEL_GMCH_GMS_STOLEN_352M:
619 if (IS_I965 || IS_G4X)
620 gtt_entries = MB(352) - KB(size);
621 else
622 gtt_entries = 0;
623 break;
579 default: 624 default:
580 gtt_entries = 0; 625 gtt_entries = 0;
581 break; 626 break;
@@ -793,7 +838,7 @@ static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
793out: 838out:
794 ret = 0; 839 ret = 0;
795out_err: 840out_err:
796 mem->is_flushed = 1; 841 mem->is_flushed = true;
797 return ret; 842 return ret;
798} 843}
799 844
@@ -903,7 +948,7 @@ static void intel_i9xx_setup_flush(void)
903 intel_private.ifp_resource.flags = IORESOURCE_MEM; 948 intel_private.ifp_resource.flags = IORESOURCE_MEM;
904 949
905 /* Setup chipset flush for 915 */ 950 /* Setup chipset flush for 915 */
906 if (IS_I965 || IS_G33) { 951 if (IS_I965 || IS_G33 || IS_G4X) {
907 intel_i965_g33_setup_chipset_flush(); 952 intel_i965_g33_setup_chipset_flush();
908 } else { 953 } else {
909 intel_i915_setup_chipset_flush(); 954 intel_i915_setup_chipset_flush();
@@ -1020,7 +1065,7 @@ static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1020 out: 1065 out:
1021 ret = 0; 1066 ret = 0;
1022 out_err: 1067 out_err:
1023 mem->is_flushed = 1; 1068 mem->is_flushed = true;
1024 return ret; 1069 return ret;
1025} 1070}
1026 1071
@@ -1134,53 +1179,64 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1134 return addr | bridge->driver->masks[type].mask; 1179 return addr | bridge->driver->masks[type].mask;
1135} 1180}
1136 1181
1182static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1183{
1184 switch (agp_bridge->dev->device) {
1185 case PCI_DEVICE_ID_INTEL_IGD_HB:
1186 case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1187 case PCI_DEVICE_ID_INTEL_Q45_HB:
1188 case PCI_DEVICE_ID_INTEL_G45_HB:
1189 *gtt_offset = *gtt_size = MB(2);
1190 break;
1191 default:
1192 *gtt_offset = *gtt_size = KB(512);
1193 }
1194}
1195
1137/* The intel i965 automatically initializes the agp aperture during POST. 1196/* The intel i965 automatically initializes the agp aperture during POST.
1138 * Use the memory already set aside for in the GTT. 1197 * Use the memory already set aside for in the GTT.
1139 */ 1198 */
1140static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) 1199static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1141{ 1200{
1142 int page_order; 1201 int page_order;
1143 struct aper_size_info_fixed *size; 1202 struct aper_size_info_fixed *size;
1144 int num_entries; 1203 int num_entries;
1145 u32 temp; 1204 u32 temp;
1146 int gtt_offset, gtt_size; 1205 int gtt_offset, gtt_size;
1147 1206
1148 size = agp_bridge->current_size; 1207 size = agp_bridge->current_size;
1149 page_order = size->page_order; 1208 page_order = size->page_order;
1150 num_entries = size->num_entries; 1209 num_entries = size->num_entries;
1151 agp_bridge->gatt_table_real = NULL; 1210 agp_bridge->gatt_table_real = NULL;
1152 1211
1153 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1212 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1154 1213
1155 temp &= 0xfff00000; 1214 temp &= 0xfff00000;
1156 1215
1157 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB) 1216 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1158 gtt_offset = gtt_size = MB(2);
1159 else
1160 gtt_offset = gtt_size = KB(512);
1161 1217
1162 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); 1218 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1163 1219
1164 if (!intel_private.gtt) 1220 if (!intel_private.gtt)
1165 return -ENOMEM; 1221 return -ENOMEM;
1166 1222
1167 intel_private.registers = ioremap(temp, 128 * 4096); 1223 intel_private.registers = ioremap(temp, 128 * 4096);
1168 if (!intel_private.registers) { 1224 if (!intel_private.registers) {
1169 iounmap(intel_private.gtt); 1225 iounmap(intel_private.gtt);
1170 return -ENOMEM; 1226 return -ENOMEM;
1171 } 1227 }
1172 1228
1173 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1229 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1174 global_cache_flush(); /* FIXME: ? */ 1230 global_cache_flush(); /* FIXME: ? */
1175 1231
1176 /* we have to call this as early as possible after the MMIO base address is known */ 1232 /* we have to call this as early as possible after the MMIO base address is known */
1177 intel_i830_init_gtt_entries(); 1233 intel_i830_init_gtt_entries();
1178 1234
1179 agp_bridge->gatt_table = NULL; 1235 agp_bridge->gatt_table = NULL;
1180 1236
1181 agp_bridge->gatt_bus_addr = temp; 1237 agp_bridge->gatt_bus_addr = temp;
1182 1238
1183 return 0; 1239 return 0;
1184} 1240}
1185 1241
1186 1242
@@ -1656,7 +1712,7 @@ static const struct agp_bridge_driver intel_810_driver = {
1656 .aperture_sizes = intel_i810_sizes, 1712 .aperture_sizes = intel_i810_sizes,
1657 .size_type = FIXED_APER_SIZE, 1713 .size_type = FIXED_APER_SIZE,
1658 .num_aperture_sizes = 2, 1714 .num_aperture_sizes = 2,
1659 .needs_scratch_page = TRUE, 1715 .needs_scratch_page = true,
1660 .configure = intel_i810_configure, 1716 .configure = intel_i810_configure,
1661 .fetch_size = intel_i810_fetch_size, 1717 .fetch_size = intel_i810_fetch_size,
1662 .cleanup = intel_i810_cleanup, 1718 .cleanup = intel_i810_cleanup,
@@ -1697,7 +1753,7 @@ static const struct agp_bridge_driver intel_815_driver = {
1697 .free_by_type = agp_generic_free_by_type, 1753 .free_by_type = agp_generic_free_by_type,
1698 .agp_alloc_page = agp_generic_alloc_page, 1754 .agp_alloc_page = agp_generic_alloc_page,
1699 .agp_destroy_page = agp_generic_destroy_page, 1755 .agp_destroy_page = agp_generic_destroy_page,
1700 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1756 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1701}; 1757};
1702 1758
1703static const struct agp_bridge_driver intel_830_driver = { 1759static const struct agp_bridge_driver intel_830_driver = {
@@ -1705,7 +1761,7 @@ static const struct agp_bridge_driver intel_830_driver = {
1705 .aperture_sizes = intel_i830_sizes, 1761 .aperture_sizes = intel_i830_sizes,
1706 .size_type = FIXED_APER_SIZE, 1762 .size_type = FIXED_APER_SIZE,
1707 .num_aperture_sizes = 4, 1763 .num_aperture_sizes = 4,
1708 .needs_scratch_page = TRUE, 1764 .needs_scratch_page = true,
1709 .configure = intel_i830_configure, 1765 .configure = intel_i830_configure,
1710 .fetch_size = intel_i830_fetch_size, 1766 .fetch_size = intel_i830_fetch_size,
1711 .cleanup = intel_i830_cleanup, 1767 .cleanup = intel_i830_cleanup,
@@ -1876,7 +1932,7 @@ static const struct agp_bridge_driver intel_915_driver = {
1876 .aperture_sizes = intel_i830_sizes, 1932 .aperture_sizes = intel_i830_sizes,
1877 .size_type = FIXED_APER_SIZE, 1933 .size_type = FIXED_APER_SIZE,
1878 .num_aperture_sizes = 4, 1934 .num_aperture_sizes = 4,
1879 .needs_scratch_page = TRUE, 1935 .needs_scratch_page = true,
1880 .configure = intel_i915_configure, 1936 .configure = intel_i915_configure,
1881 .fetch_size = intel_i9xx_fetch_size, 1937 .fetch_size = intel_i9xx_fetch_size,
1882 .cleanup = intel_i915_cleanup, 1938 .cleanup = intel_i915_cleanup,
@@ -1898,28 +1954,28 @@ static const struct agp_bridge_driver intel_915_driver = {
1898}; 1954};
1899 1955
1900static const struct agp_bridge_driver intel_i965_driver = { 1956static const struct agp_bridge_driver intel_i965_driver = {
1901 .owner = THIS_MODULE, 1957 .owner = THIS_MODULE,
1902 .aperture_sizes = intel_i830_sizes, 1958 .aperture_sizes = intel_i830_sizes,
1903 .size_type = FIXED_APER_SIZE, 1959 .size_type = FIXED_APER_SIZE,
1904 .num_aperture_sizes = 4, 1960 .num_aperture_sizes = 4,
1905 .needs_scratch_page = TRUE, 1961 .needs_scratch_page = true,
1906 .configure = intel_i915_configure, 1962 .configure = intel_i915_configure,
1907 .fetch_size = intel_i9xx_fetch_size, 1963 .fetch_size = intel_i9xx_fetch_size,
1908 .cleanup = intel_i915_cleanup, 1964 .cleanup = intel_i915_cleanup,
1909 .tlb_flush = intel_i810_tlbflush, 1965 .tlb_flush = intel_i810_tlbflush,
1910 .mask_memory = intel_i965_mask_memory, 1966 .mask_memory = intel_i965_mask_memory,
1911 .masks = intel_i810_masks, 1967 .masks = intel_i810_masks,
1912 .agp_enable = intel_i810_agp_enable, 1968 .agp_enable = intel_i810_agp_enable,
1913 .cache_flush = global_cache_flush, 1969 .cache_flush = global_cache_flush,
1914 .create_gatt_table = intel_i965_create_gatt_table, 1970 .create_gatt_table = intel_i965_create_gatt_table,
1915 .free_gatt_table = intel_i830_free_gatt_table, 1971 .free_gatt_table = intel_i830_free_gatt_table,
1916 .insert_memory = intel_i915_insert_entries, 1972 .insert_memory = intel_i915_insert_entries,
1917 .remove_memory = intel_i915_remove_entries, 1973 .remove_memory = intel_i915_remove_entries,
1918 .alloc_by_type = intel_i830_alloc_by_type, 1974 .alloc_by_type = intel_i830_alloc_by_type,
1919 .free_by_type = intel_i810_free_by_type, 1975 .free_by_type = intel_i810_free_by_type,
1920 .agp_alloc_page = agp_generic_alloc_page, 1976 .agp_alloc_page = agp_generic_alloc_page,
1921 .agp_destroy_page = agp_generic_destroy_page, 1977 .agp_destroy_page = agp_generic_destroy_page,
1922 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1978 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1923 .chipset_flush = intel_i915_chipset_flush, 1979 .chipset_flush = intel_i915_chipset_flush,
1924}; 1980};
1925 1981
@@ -1948,28 +2004,28 @@ static const struct agp_bridge_driver intel_7505_driver = {
1948}; 2004};
1949 2005
1950static const struct agp_bridge_driver intel_g33_driver = { 2006static const struct agp_bridge_driver intel_g33_driver = {
1951 .owner = THIS_MODULE, 2007 .owner = THIS_MODULE,
1952 .aperture_sizes = intel_i830_sizes, 2008 .aperture_sizes = intel_i830_sizes,
1953 .size_type = FIXED_APER_SIZE, 2009 .size_type = FIXED_APER_SIZE,
1954 .num_aperture_sizes = 4, 2010 .num_aperture_sizes = 4,
1955 .needs_scratch_page = TRUE, 2011 .needs_scratch_page = true,
1956 .configure = intel_i915_configure, 2012 .configure = intel_i915_configure,
1957 .fetch_size = intel_i9xx_fetch_size, 2013 .fetch_size = intel_i9xx_fetch_size,
1958 .cleanup = intel_i915_cleanup, 2014 .cleanup = intel_i915_cleanup,
1959 .tlb_flush = intel_i810_tlbflush, 2015 .tlb_flush = intel_i810_tlbflush,
1960 .mask_memory = intel_i965_mask_memory, 2016 .mask_memory = intel_i965_mask_memory,
1961 .masks = intel_i810_masks, 2017 .masks = intel_i810_masks,
1962 .agp_enable = intel_i810_agp_enable, 2018 .agp_enable = intel_i810_agp_enable,
1963 .cache_flush = global_cache_flush, 2019 .cache_flush = global_cache_flush,
1964 .create_gatt_table = intel_i915_create_gatt_table, 2020 .create_gatt_table = intel_i915_create_gatt_table,
1965 .free_gatt_table = intel_i830_free_gatt_table, 2021 .free_gatt_table = intel_i830_free_gatt_table,
1966 .insert_memory = intel_i915_insert_entries, 2022 .insert_memory = intel_i915_insert_entries,
1967 .remove_memory = intel_i915_remove_entries, 2023 .remove_memory = intel_i915_remove_entries,
1968 .alloc_by_type = intel_i830_alloc_by_type, 2024 .alloc_by_type = intel_i830_alloc_by_type,
1969 .free_by_type = intel_i810_free_by_type, 2025 .free_by_type = intel_i810_free_by_type,
1970 .agp_alloc_page = agp_generic_alloc_page, 2026 .agp_alloc_page = agp_generic_alloc_page,
1971 .agp_destroy_page = agp_generic_destroy_page, 2027 .agp_destroy_page = agp_generic_destroy_page,
1972 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2028 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1973 .chipset_flush = intel_i915_chipset_flush, 2029 .chipset_flush = intel_i915_chipset_flush,
1974}; 2030};
1975 2031
@@ -2063,6 +2119,12 @@ static const struct intel_driver_description {
2063 NULL, &intel_g33_driver }, 2119 NULL, &intel_g33_driver },
2064 { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0, 2120 { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
2065 "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, 2121 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2122 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2123 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2124 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2125 "Q45/Q43", NULL, &intel_i965_driver },
2126 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2127 "G45/G43", NULL, &intel_i965_driver },
2066 { 0, 0, 0, NULL, NULL, NULL } 2128 { 0, 0, 0, NULL, NULL, NULL }
2067}; 2129};
2068 2130
@@ -2254,6 +2316,9 @@ static struct pci_device_id agp_intel_pci_table[] = {
2254 ID(PCI_DEVICE_ID_INTEL_Q35_HB), 2316 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2255 ID(PCI_DEVICE_ID_INTEL_Q33_HB), 2317 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2256 ID(PCI_DEVICE_ID_INTEL_IGD_HB), 2318 ID(PCI_DEVICE_ID_INTEL_IGD_HB),
2319 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2320 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2321 ID(PCI_DEVICE_ID_INTEL_G45_HB),
2257 { } 2322 { }
2258}; 2323};
2259 2324
diff --git a/drivers/char/agp/nvidia-agp.c b/drivers/char/agp/nvidia-agp.c
index 225ed2a53d45..eaceb61ba2dc 100644
--- a/drivers/char/agp/nvidia-agp.c
+++ b/drivers/char/agp/nvidia-agp.c
@@ -214,9 +214,9 @@ static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type
214 return -EBUSY; 214 return -EBUSY;
215 } 215 }
216 216
217 if (mem->is_flushed == FALSE) { 217 if (!mem->is_flushed) {
218 global_cache_flush(); 218 global_cache_flush();
219 mem->is_flushed = TRUE; 219 mem->is_flushed = true;
220 } 220 }
221 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 221 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
222 writel(agp_bridge->driver->mask_memory(agp_bridge, 222 writel(agp_bridge->driver->mask_memory(agp_bridge,
diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c
index 2939e3570f9d..8c42dcc5958c 100644
--- a/drivers/char/agp/parisc-agp.c
+++ b/drivers/char/agp/parisc-agp.c
@@ -141,9 +141,9 @@ parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
141 j++; 141 j++;
142 } 142 }
143 143
144 if (mem->is_flushed == FALSE) { 144 if (!mem->is_flushed) {
145 global_cache_flush(); 145 global_cache_flush();
146 mem->is_flushed = TRUE; 146 mem->is_flushed = true;
147 } 147 }
148 148
149 for (i = 0, j = io_pg_start; i < mem->page_count; i++) { 149 for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
@@ -226,7 +226,7 @@ static const struct agp_bridge_driver parisc_agp_driver = {
226 .agp_alloc_page = agp_generic_alloc_page, 226 .agp_alloc_page = agp_generic_alloc_page,
227 .agp_destroy_page = agp_generic_destroy_page, 227 .agp_destroy_page = agp_generic_destroy_page,
228 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 228 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
229 .cant_use_aperture = 1, 229 .cant_use_aperture = true,
230}; 230};
231 231
232static int __init 232static int __init
diff --git a/drivers/char/agp/sgi-agp.c b/drivers/char/agp/sgi-agp.c
index 98cf8abb3e57..b972d83bb1b2 100644
--- a/drivers/char/agp/sgi-agp.c
+++ b/drivers/char/agp/sgi-agp.c
@@ -182,9 +182,9 @@ static int sgi_tioca_insert_memory(struct agp_memory *mem, off_t pg_start,
182 j++; 182 j++;
183 } 183 }
184 184
185 if (mem->is_flushed == FALSE) { 185 if (!mem->is_flushed) {
186 bridge->driver->cache_flush(); 186 bridge->driver->cache_flush();
187 mem->is_flushed = TRUE; 187 mem->is_flushed = true;
188 } 188 }
189 189
190 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 190 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
@@ -264,8 +264,8 @@ const struct agp_bridge_driver sgi_tioca_driver = {
264 .agp_alloc_page = sgi_tioca_alloc_page, 264 .agp_alloc_page = sgi_tioca_alloc_page,
265 .agp_destroy_page = agp_generic_destroy_page, 265 .agp_destroy_page = agp_generic_destroy_page,
266 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 266 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
267 .cant_use_aperture = 1, 267 .cant_use_aperture = true,
268 .needs_scratch_page = 0, 268 .needs_scratch_page = false,
269 .num_aperture_sizes = 1, 269 .num_aperture_sizes = 1,
270}; 270};
271 271
diff --git a/drivers/char/agp/sworks-agp.c b/drivers/char/agp/sworks-agp.c
index e08934e58f32..0e054c134490 100644
--- a/drivers/char/agp/sworks-agp.c
+++ b/drivers/char/agp/sworks-agp.c
@@ -339,9 +339,9 @@ static int serverworks_insert_memory(struct agp_memory *mem,
339 j++; 339 j++;
340 } 340 }
341 341
342 if (mem->is_flushed == FALSE) { 342 if (!mem->is_flushed) {
343 global_cache_flush(); 343 global_cache_flush();
344 mem->is_flushed = TRUE; 344 mem->is_flushed = true;
345 } 345 }
346 346
347 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 347 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
@@ -412,7 +412,7 @@ static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
412 bridge->capndx + PCI_AGP_COMMAND, 412 bridge->capndx + PCI_AGP_COMMAND,
413 command); 413 command);
414 414
415 agp_device_command(command, 0); 415 agp_device_command(command, false);
416} 416}
417 417
418static const struct agp_bridge_driver sworks_driver = { 418static const struct agp_bridge_driver sworks_driver = {
diff --git a/drivers/char/agp/uninorth-agp.c b/drivers/char/agp/uninorth-agp.c
index 42c0a600b1ac..d2fa3cfca02a 100644
--- a/drivers/char/agp/uninorth-agp.c
+++ b/drivers/char/agp/uninorth-agp.c
@@ -281,10 +281,10 @@ static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode)
281 281
282 if (uninorth_rev >= 0x30) { 282 if (uninorth_rev >= 0x30) {
283 /* This is an AGP V3 */ 283 /* This is an AGP V3 */
284 agp_device_command(command, (status & AGPSTAT_MODE_3_0)); 284 agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0);
285 } else { 285 } else {
286 /* AGP V2 */ 286 /* AGP V2 */
287 agp_device_command(command, 0); 287 agp_device_command(command, false);
288 } 288 }
289 289
290 uninorth_tlbflush(NULL); 290 uninorth_tlbflush(NULL);
@@ -511,7 +511,7 @@ const struct agp_bridge_driver uninorth_agp_driver = {
511 .agp_alloc_page = agp_generic_alloc_page, 511 .agp_alloc_page = agp_generic_alloc_page,
512 .agp_destroy_page = agp_generic_destroy_page, 512 .agp_destroy_page = agp_generic_destroy_page,
513 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 513 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
514 .cant_use_aperture = 1, 514 .cant_use_aperture = true,
515}; 515};
516 516
517const struct agp_bridge_driver u3_agp_driver = { 517const struct agp_bridge_driver u3_agp_driver = {
@@ -536,8 +536,8 @@ const struct agp_bridge_driver u3_agp_driver = {
536 .agp_alloc_page = agp_generic_alloc_page, 536 .agp_alloc_page = agp_generic_alloc_page,
537 .agp_destroy_page = agp_generic_destroy_page, 537 .agp_destroy_page = agp_generic_destroy_page,
538 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 538 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
539 .cant_use_aperture = 1, 539 .cant_use_aperture = true,
540 .needs_scratch_page = 1, 540 .needs_scratch_page = true,
541}; 541};
542 542
543static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = { 543static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = {
diff --git a/drivers/char/agp/via-agp.c b/drivers/char/agp/via-agp.c
index 0ecc54d327bc..7b36476dff41 100644
--- a/drivers/char/agp/via-agp.c
+++ b/drivers/char/agp/via-agp.c
@@ -389,11 +389,20 @@ static struct agp_device_ids via_agp_device_ids[] __devinitdata =
389 .device_id = PCI_DEVICE_ID_VIA_VT3324, 389 .device_id = PCI_DEVICE_ID_VIA_VT3324,
390 .chipset_name = "CX700", 390 .chipset_name = "CX700",
391 }, 391 },
392 /* VT3336 */ 392 /* VT3336 - this is a chipset for AMD Athlon/K8 CPU. Due to K8's unique
393 * architecture, the AGP resource and behavior are different from
394 * the traditional AGP which resides only in chipset. AGP is used
395 * by 3D driver which wasn't available for the VT3336 and VT3364
396 * generation until now. Unfortunately, by testing, VT3364 works
397 * but VT3336 doesn't. - explaination from via, just leave this as
398 * as a placeholder to avoid future patches adding it back in.
399 */
400#if 0
393 { 401 {
394 .device_id = PCI_DEVICE_ID_VIA_VT3336, 402 .device_id = PCI_DEVICE_ID_VIA_VT3336,
395 .chipset_name = "VT3336", 403 .chipset_name = "VT3336",
396 }, 404 },
405#endif
397 /* P4M890 */ 406 /* P4M890 */
398 { 407 {
399 .device_id = PCI_DEVICE_ID_VIA_P4M890, 408 .device_id = PCI_DEVICE_ID_VIA_P4M890,
@@ -546,8 +555,8 @@ static const struct pci_device_id agp_via_pci_table[] = {
546 ID(PCI_DEVICE_ID_VIA_3296_0), 555 ID(PCI_DEVICE_ID_VIA_3296_0),
547 ID(PCI_DEVICE_ID_VIA_P4M800CE), 556 ID(PCI_DEVICE_ID_VIA_P4M800CE),
548 ID(PCI_DEVICE_ID_VIA_VT3324), 557 ID(PCI_DEVICE_ID_VIA_VT3324),
549 ID(PCI_DEVICE_ID_VIA_VT3336),
550 ID(PCI_DEVICE_ID_VIA_P4M890), 558 ID(PCI_DEVICE_ID_VIA_P4M890),
559 ID(PCI_DEVICE_ID_VIA_VT3364),
551 { } 560 { }
552}; 561};
553 562
diff --git a/drivers/char/drm/ati_pcigart.c b/drivers/char/drm/ati_pcigart.c
index b710426bab3e..c533d0c9ec61 100644
--- a/drivers/char/drm/ati_pcigart.c
+++ b/drivers/char/drm/ati_pcigart.c
@@ -76,7 +76,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info
76 for (i = 0; i < pages; i++) { 76 for (i = 0; i < pages; i++) {
77 if (!entry->busaddr[i]) 77 if (!entry->busaddr[i])
78 break; 78 break;
79 pci_unmap_single(dev->pdev, entry->busaddr[i], 79 pci_unmap_page(dev->pdev, entry->busaddr[i],
80 PAGE_SIZE, PCI_DMA_TODEVICE); 80 PAGE_SIZE, PCI_DMA_TODEVICE);
81 } 81 }
82 82
@@ -137,10 +137,8 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
137 137
138 for (i = 0; i < pages; i++) { 138 for (i = 0; i < pages; i++) {
139 /* we need to support large memory configurations */ 139 /* we need to support large memory configurations */
140 entry->busaddr[i] = pci_map_single(dev->pdev, 140 entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
141 page_address(entry-> 141 0, PAGE_SIZE, PCI_DMA_TODEVICE);
142 pagelist[i]),
143 PAGE_SIZE, PCI_DMA_TODEVICE);
144 if (entry->busaddr[i] == 0) { 142 if (entry->busaddr[i] == 0) {
145 DRM_ERROR("unable to map PCIGART pages!\n"); 143 DRM_ERROR("unable to map PCIGART pages!\n");
146 drm_ati_pcigart_cleanup(dev, gart_info); 144 drm_ati_pcigart_cleanup(dev, gart_info);
diff --git a/drivers/char/drm/drm.h b/drivers/char/drm/drm.h
index 3a05c6d5ebe1..38d3c6b8276a 100644
--- a/drivers/char/drm/drm.h
+++ b/drivers/char/drm/drm.h
@@ -628,7 +628,7 @@ struct drm_set_version {
628#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 628#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
629#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 629#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
630 630
631#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather) 631#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
632#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 632#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
633 633
634#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 634#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
diff --git a/drivers/char/drm/drm_drv.c b/drivers/char/drm/drm_drv.c
index fc54140551a7..564138714bb5 100644
--- a/drivers/char/drm/drm_drv.c
+++ b/drivers/char/drm/drm_drv.c
@@ -470,17 +470,18 @@ int drm_ioctl(struct inode *inode, struct file *filp,
470 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) && 470 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) &&
471 (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) 471 (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls))
472 ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE]; 472 ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];
473 else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) 473 else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) {
474 ioctl = &drm_ioctls[nr]; 474 ioctl = &drm_ioctls[nr];
475 else 475 cmd = ioctl->cmd;
476 } else
476 goto err_i1; 477 goto err_i1;
477 478
479 /* Do not trust userspace, use our own definition */
478 func = ioctl->func; 480 func = ioctl->func;
479 /* is there a local override? */ 481 /* is there a local override? */
480 if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl) 482 if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl)
481 func = dev->driver->dma_ioctl; 483 func = dev->driver->dma_ioctl;
482 484
483
484 if (!func) { 485 if (!func) {
485 DRM_DEBUG("no function\n"); 486 DRM_DEBUG("no function\n");
486 retcode = -EINVAL; 487 retcode = -EINVAL;
diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h
index a6a499f97e22..135bd19499fc 100644
--- a/drivers/char/drm/drm_pciids.h
+++ b/drivers/char/drm/drm_pciids.h
@@ -103,20 +103,18 @@
103 {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 103 {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
104 {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \ 104 {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \
105 {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ 105 {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
106 {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 106 {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
107 {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 107 {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
108 {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 108 {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
109 {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 109 {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
110 {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 110 {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
111 {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 111 {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
112 {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 112 {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
113 {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 113 {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
114 {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 114 {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
115 {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ 115 {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
116 {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 116 {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
117 {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 117 {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
118 {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
119 {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
120 {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 118 {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
121 {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 119 {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
122 {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 120 {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
@@ -411,4 +409,7 @@
411 {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 409 {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
412 {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 410 {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
413 {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 411 {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
412 {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
413 {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
414 {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
414 {0, 0, 0} 415 {0, 0, 0}
diff --git a/drivers/char/drm/drm_sysfs.c b/drivers/char/drm/drm_sysfs.c
index 9a32169e88fb..af211a0ef179 100644
--- a/drivers/char/drm/drm_sysfs.c
+++ b/drivers/char/drm/drm_sysfs.c
@@ -34,8 +34,6 @@ static int drm_sysfs_suspend(struct device *dev, pm_message_t state)
34 struct drm_minor *drm_minor = to_drm_minor(dev); 34 struct drm_minor *drm_minor = to_drm_minor(dev);
35 struct drm_device *drm_dev = drm_minor->dev; 35 struct drm_device *drm_dev = drm_minor->dev;
36 36
37 printk(KERN_ERR "%s\n", __func__);
38
39 if (drm_dev->driver->suspend) 37 if (drm_dev->driver->suspend)
40 return drm_dev->driver->suspend(drm_dev, state); 38 return drm_dev->driver->suspend(drm_dev, state);
41 39
diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c
index e8f3d682e3b1..93aed1c38bd2 100644
--- a/drivers/char/drm/i915_drv.c
+++ b/drivers/char/drm/i915_drv.c
@@ -389,6 +389,7 @@ static int i915_resume(struct drm_device *dev)
389 pci_restore_state(dev->pdev); 389 pci_restore_state(dev->pdev);
390 if (pci_enable_device(dev->pdev)) 390 if (pci_enable_device(dev->pdev))
391 return -1; 391 return -1;
392 pci_set_master(dev->pdev);
392 393
393 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 394 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
394 395
diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h
index 1b20f7c0639c..d7326d92a237 100644
--- a/drivers/char/drm/i915_drv.h
+++ b/drivers/char/drm/i915_drv.h
@@ -1112,12 +1112,19 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1112 (dev)->pci_device == 0x29A2 || \ 1112 (dev)->pci_device == 0x29A2 || \
1113 (dev)->pci_device == 0x2A02 || \ 1113 (dev)->pci_device == 0x2A02 || \
1114 (dev)->pci_device == 0x2A12 || \ 1114 (dev)->pci_device == 0x2A12 || \
1115 (dev)->pci_device == 0x2A42) 1115 (dev)->pci_device == 0x2A42 || \
1116 (dev)->pci_device == 0x2E02 || \
1117 (dev)->pci_device == 0x2E12 || \
1118 (dev)->pci_device == 0x2E22)
1116 1119
1117#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 1120#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
1118 1121
1119#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42) 1122#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
1120 1123
1124#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
1125 (dev)->pci_device == 0x2E12 || \
1126 (dev)->pci_device == 0x2E22)
1127
1121#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 1128#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1122 (dev)->pci_device == 0x29B2 || \ 1129 (dev)->pci_device == 0x29B2 || \
1123 (dev)->pci_device == 0x29D2) 1130 (dev)->pci_device == 0x29D2)
@@ -1128,7 +1135,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1128#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 1135#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1129 IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev)) 1136 IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
1130 1137
1131#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev)) 1138#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))
1132 1139
1133#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1140#define PRIMARY_RINGBUFFER_SIZE (128*1024)
1134 1141
diff --git a/drivers/char/drm/i915_irq.c b/drivers/char/drm/i915_irq.c
index f7f16e7a8bf3..df036118b8b1 100644
--- a/drivers/char/drm/i915_irq.c
+++ b/drivers/char/drm/i915_irq.c
@@ -62,11 +62,11 @@ static void i915_vblank_tasklet(struct drm_device *dev)
62 u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24); 62 u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
63 RING_LOCALS; 63 RING_LOCALS;
64 64
65 if (sarea_priv->front_tiled) { 65 if (IS_I965G(dev) && sarea_priv->front_tiled) {
66 cmd |= XY_SRC_COPY_BLT_DST_TILED; 66 cmd |= XY_SRC_COPY_BLT_DST_TILED;
67 dst_pitch >>= 2; 67 dst_pitch >>= 2;
68 } 68 }
69 if (sarea_priv->back_tiled) { 69 if (IS_I965G(dev) && sarea_priv->back_tiled) {
70 cmd |= XY_SRC_COPY_BLT_SRC_TILED; 70 cmd |= XY_SRC_COPY_BLT_SRC_TILED;
71 src_pitch >>= 2; 71 src_pitch >>= 2;
72 } 72 }
diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c
index f535812e4057..702df45320f7 100644
--- a/drivers/char/drm/r300_cmdbuf.c
+++ b/drivers/char/drm/r300_cmdbuf.c
@@ -189,18 +189,12 @@ void r300_init_reg_flags(struct drm_device *dev)
189 ADD_RANGE(R300_RE_CULL_CNTL, 1); 189 ADD_RANGE(R300_RE_CULL_CNTL, 1);
190 ADD_RANGE(0x42C0, 2); 190 ADD_RANGE(0x42C0, 2);
191 ADD_RANGE(R300_RS_CNTL_0, 2); 191 ADD_RANGE(R300_RS_CNTL_0, 2);
192 ADD_RANGE(R300_RS_INTERP_0, 8); 192
193 ADD_RANGE(R300_RS_ROUTE_0, 8); 193 ADD_RANGE(R300_SC_HYPERZ, 2);
194 ADD_RANGE(0x43A4, 2);
195 ADD_RANGE(0x43E8, 1); 194 ADD_RANGE(0x43E8, 1);
196 ADD_RANGE(R300_PFS_CNTL_0, 3); 195
197 ADD_RANGE(R300_PFS_NODE_0, 4);
198 ADD_RANGE(R300_PFS_TEXI_0, 64);
199 ADD_RANGE(0x46A4, 5); 196 ADD_RANGE(0x46A4, 5);
200 ADD_RANGE(R300_PFS_INSTR0_0, 64); 197
201 ADD_RANGE(R300_PFS_INSTR1_0, 64);
202 ADD_RANGE(R300_PFS_INSTR2_0, 64);
203 ADD_RANGE(R300_PFS_INSTR3_0, 64);
204 ADD_RANGE(R300_RE_FOG_STATE, 1); 198 ADD_RANGE(R300_RE_FOG_STATE, 1);
205 ADD_RANGE(R300_FOG_COLOR_R, 3); 199 ADD_RANGE(R300_FOG_COLOR_R, 3);
206 ADD_RANGE(R300_PP_ALPHA_TEST, 2); 200 ADD_RANGE(R300_PP_ALPHA_TEST, 2);
@@ -215,14 +209,12 @@ void r300_init_reg_flags(struct drm_device *dev)
215 ADD_RANGE(0x4E50, 9); 209 ADD_RANGE(0x4E50, 9);
216 ADD_RANGE(0x4E88, 1); 210 ADD_RANGE(0x4E88, 1);
217 ADD_RANGE(0x4EA0, 2); 211 ADD_RANGE(0x4EA0, 2);
218 ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3); 212 ADD_RANGE(R300_ZB_CNTL, 3);
219 ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4); 213 ADD_RANGE(R300_ZB_FORMAT, 4);
220 ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ 214 ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
221 ADD_RANGE(R300_RB3D_DEPTHPITCH, 1); 215 ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
222 ADD_RANGE(0x4F28, 1); 216 ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
223 ADD_RANGE(0x4F30, 2); 217 ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
224 ADD_RANGE(0x4F44, 1);
225 ADD_RANGE(0x4F54, 1);
226 218
227 ADD_RANGE(R300_TX_FILTER_0, 16); 219 ADD_RANGE(R300_TX_FILTER_0, 16);
228 ADD_RANGE(R300_TX_FILTER1_0, 16); 220 ADD_RANGE(R300_TX_FILTER1_0, 16);
@@ -235,13 +227,32 @@ void r300_init_reg_flags(struct drm_device *dev)
235 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); 227 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
236 228
237 /* Sporadic registers used as primitives are emitted */ 229 /* Sporadic registers used as primitives are emitted */
238 ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1); 230 ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
239 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1); 231 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
240 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8); 232 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
241 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8); 233 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
242 234
243 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { 235 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
244 ADD_RANGE(0x4074, 16); 236 ADD_RANGE(R500_VAP_INDEX_OFFSET, 1);
237 ADD_RANGE(R500_US_CONFIG, 2);
238 ADD_RANGE(R500_US_CODE_ADDR, 3);
239 ADD_RANGE(R500_US_FC_CTRL, 1);
240 ADD_RANGE(R500_RS_IP_0, 16);
241 ADD_RANGE(R500_RS_INST_0, 16);
242 ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
243 ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
244 ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
245 } else {
246 ADD_RANGE(R300_PFS_CNTL_0, 3);
247 ADD_RANGE(R300_PFS_NODE_0, 4);
248 ADD_RANGE(R300_PFS_TEXI_0, 64);
249 ADD_RANGE(R300_PFS_INSTR0_0, 64);
250 ADD_RANGE(R300_PFS_INSTR1_0, 64);
251 ADD_RANGE(R300_PFS_INSTR2_0, 64);
252 ADD_RANGE(R300_PFS_INSTR3_0, 64);
253 ADD_RANGE(R300_RS_INTERP_0, 8);
254 ADD_RANGE(R300_RS_ROUTE_0, 8);
255
245 } 256 }
246} 257}
247 258
@@ -707,8 +718,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
707 BEGIN_RING(6); 718 BEGIN_RING(6);
708 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 719 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
709 OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A); 720 OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
710 OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 721 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
711 OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03); 722 OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE|
723 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
712 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0)); 724 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
713 OUT_RING(0x0); 725 OUT_RING(0x0);
714 ADVANCE_RING(); 726 ADVANCE_RING();
@@ -829,6 +841,54 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
829} 841}
830 842
831/** 843/**
844 * Uploads user-supplied vertex program instructions or parameters onto
845 * the graphics card.
846 * Called by r300_do_cp_cmdbuf.
847 */
848static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
849 drm_radeon_kcmd_buffer_t *cmdbuf,
850 drm_r300_cmd_header_t header)
851{
852 int sz;
853 int addr;
854 int type;
855 int clamp;
856 int stride;
857 RING_LOCALS;
858
859 sz = header.r500fp.count;
860 /* address is 9 bits 0 - 8, bit 1 of flags is part of address */
861 addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo;
862
863 type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
864 clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
865
866 addr |= (type << 16);
867 addr |= (clamp << 17);
868
869 stride = type ? 4 : 6;
870
871 DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type);
872 if (!sz)
873 return 0;
874 if (sz * stride * 4 > cmdbuf->bufsz)
875 return -EINVAL;
876
877 BEGIN_RING(3 + sz * stride);
878 OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr);
879 OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1));
880 OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride);
881
882 ADVANCE_RING();
883
884 cmdbuf->buf += sz * stride * 4;
885 cmdbuf->bufsz -= sz * stride * 4;
886
887 return 0;
888}
889
890
891/**
832 * Parses and validates a user-supplied command buffer and emits appropriate 892 * Parses and validates a user-supplied command buffer and emits appropriate
833 * commands on the DMA ring buffer. 893 * commands on the DMA ring buffer.
834 * Called by the ioctl handler function radeon_cp_cmdbuf. 894 * Called by the ioctl handler function radeon_cp_cmdbuf.
@@ -963,6 +1023,19 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
963 } 1023 }
964 break; 1024 break;
965 1025
1026 case R300_CMD_R500FP:
1027 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
1028 DRM_ERROR("Calling r500 command on r300 card\n");
1029 ret = -EINVAL;
1030 goto cleanup;
1031 }
1032 DRM_DEBUG("R300_CMD_R500FP\n");
1033 ret = r300_emit_r500fp(dev_priv, cmdbuf, header);
1034 if (ret) {
1035 DRM_ERROR("r300_emit_r500fp failed\n");
1036 goto cleanup;
1037 }
1038 break;
966 default: 1039 default:
967 DRM_ERROR("bad cmd_type %i at %p\n", 1040 DRM_ERROR("bad cmd_type %i at %p\n",
968 header.header.cmd_type, 1041 header.header.cmd_type,
diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h
index 8f664af9c4a4..a6802f26afc4 100644
--- a/drivers/char/drm/r300_reg.h
+++ b/drivers/char/drm/r300_reg.h
@@ -702,6 +702,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
702# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) 702# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11)
703/* END: Rasterization / Interpolators - many guesses */ 703/* END: Rasterization / Interpolators - many guesses */
704 704
705/* Hierarchical Z Enable */
706#define R300_SC_HYPERZ 0x43a4
707# define R300_SC_HYPERZ_DISABLE (0 << 0)
708# define R300_SC_HYPERZ_ENABLE (1 << 0)
709# define R300_SC_HYPERZ_MIN (0 << 1)
710# define R300_SC_HYPERZ_MAX (1 << 1)
711# define R300_SC_HYPERZ_ADJ_256 (0 << 2)
712# define R300_SC_HYPERZ_ADJ_128 (1 << 2)
713# define R300_SC_HYPERZ_ADJ_64 (2 << 2)
714# define R300_SC_HYPERZ_ADJ_32 (3 << 2)
715# define R300_SC_HYPERZ_ADJ_16 (4 << 2)
716# define R300_SC_HYPERZ_ADJ_8 (5 << 2)
717# define R300_SC_HYPERZ_ADJ_4 (6 << 2)
718# define R300_SC_HYPERZ_ADJ_2 (7 << 2)
719# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
720# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)
721# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
722# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)
723
724#define R300_SC_EDGERULE 0x43a8
725
705/* BEGIN: Scissors and cliprects */ 726/* BEGIN: Scissors and cliprects */
706 727
707/* There are four clipping rectangles. Their corner coordinates are inclusive. 728/* There are four clipping rectangles. Their corner coordinates are inclusive.
@@ -1346,7 +1367,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1346/* Guess by Vladimir. 1367/* Guess by Vladimir.
1347 * Set to 0A before 3D operations, set to 02 afterwards. 1368 * Set to 0A before 3D operations, set to 02 afterwards.
1348 */ 1369 */
1349#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C 1370/*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/
1350# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002 1371# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002
1351# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A 1372# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A
1352 1373
@@ -1355,19 +1376,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1355 * for this. 1376 * for this.
1356 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd 1377 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
1357 */ 1378 */
1358#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00 1379#define R300_ZB_CNTL 0x4F00
1359# define R300_RB3D_Z_DISABLED_1 0x00000010 1380# define R300_STENCIL_ENABLE (1 << 0)
1360# define R300_RB3D_Z_DISABLED_2 0x00000014 1381# define R300_Z_ENABLE (1 << 1)
1361# define R300_RB3D_Z_TEST 0x00000012 1382# define R300_Z_WRITE_ENABLE (1 << 2)
1362# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 1383# define R300_Z_SIGNED_COMPARE (1 << 3)
1363# define R300_RB3D_Z_WRITE_ONLY 0x00000006 1384# define R300_STENCIL_FRONT_BACK (1 << 4)
1364 1385
1365# define R300_RB3D_Z_TEST 0x00000012 1386#define R300_ZB_ZSTENCILCNTL 0x4f04
1366# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
1367# define R300_RB3D_Z_WRITE_ONLY 0x00000006
1368# define R300_RB3D_STENCIL_ENABLE 0x00000001
1369
1370#define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04
1371 /* functions */ 1387 /* functions */
1372# define R300_ZS_NEVER 0 1388# define R300_ZS_NEVER 0
1373# define R300_ZS_LESS 1 1389# define R300_ZS_LESS 1
@@ -1387,52 +1403,166 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1387# define R300_ZS_INVERT 5 1403# define R300_ZS_INVERT 5
1388# define R300_ZS_INCR_WRAP 6 1404# define R300_ZS_INCR_WRAP 6
1389# define R300_ZS_DECR_WRAP 7 1405# define R300_ZS_DECR_WRAP 7
1406# define R300_Z_FUNC_SHIFT 0
1390 /* front and back refer to operations done for front 1407 /* front and back refer to operations done for front
1391 and back faces, i.e. separate stencil function support */ 1408 and back faces, i.e. separate stencil function support */
1392# define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0 1409# define R300_S_FRONT_FUNC_SHIFT 3
1393# define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3 1410# define R300_S_FRONT_SFAIL_OP_SHIFT 6
1394# define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6 1411# define R300_S_FRONT_ZPASS_OP_SHIFT 9
1395# define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9 1412# define R300_S_FRONT_ZFAIL_OP_SHIFT 12
1396# define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12 1413# define R300_S_BACK_FUNC_SHIFT 15
1397# define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15 1414# define R300_S_BACK_SFAIL_OP_SHIFT 18
1398# define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18 1415# define R300_S_BACK_ZPASS_OP_SHIFT 21
1399# define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21 1416# define R300_S_BACK_ZFAIL_OP_SHIFT 24
1400# define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24 1417
1401 1418#define R300_ZB_STENCILREFMASK 0x4f08
1402#define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08 1419# define R300_STENCILREF_SHIFT 0
1403# define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0 1420# define R300_STENCILREF_MASK 0x000000ff
1404# define R300_RB3D_ZS2_STENCIL_MASK 0xFF 1421# define R300_STENCILMASK_SHIFT 8
1405# define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8 1422# define R300_STENCILMASK_MASK 0x0000ff00
1406# define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16 1423# define R300_STENCILWRITEMASK_SHIFT 16
1424# define R300_STENCILWRITEMASK_MASK 0x00ff0000
1407 1425
1408/* gap */ 1426/* gap */
1409 1427
1410#define R300_RB3D_ZSTENCIL_FORMAT 0x4F10 1428#define R300_ZB_FORMAT 0x4f10
1411# define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1429# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
1412# define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1430# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
1413 /* 16 bit format or some aditional bit ? */ 1431# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
1414# define R300_DEPTH_FORMAT_UNK32 (32 << 0) 1432/* reserved up to (15 << 0) */
1433# define R300_INVERT_13E3_LEADING_ONES (0 << 4)
1434# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
1415 1435
1416#define R300_RB3D_EARLY_Z 0x4F14 1436#define R300_ZB_ZTOP 0x4F14
1417# define R300_EARLY_Z_DISABLE (0 << 0) 1437# define R300_ZTOP_DISABLE (0 << 0)
1418# define R300_EARLY_Z_ENABLE (1 << 0) 1438# define R300_ZTOP_ENABLE (1 << 0)
1419 1439
1420/* gap */ 1440/* gap */
1421 1441
1422#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */ 1442#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
1423# define R300_RB3D_ZCACHE_UNKNOWN_01 0x1 1443# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
1424# define R300_RB3D_ZCACHE_UNKNOWN_03 0x3 1444# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
1445# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
1446# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
1447# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
1448# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
1449
1450#define R300_ZB_BW_CNTL 0x4f1c
1451# define R300_HIZ_DISABLE (0 << 0)
1452# define R300_HIZ_ENABLE (1 << 0)
1453# define R300_HIZ_MIN (0 << 1)
1454# define R300_HIZ_MAX (1 << 1)
1455# define R300_FAST_FILL_DISABLE (0 << 2)
1456# define R300_FAST_FILL_ENABLE (1 << 2)
1457# define R300_RD_COMP_DISABLE (0 << 3)
1458# define R300_RD_COMP_ENABLE (1 << 3)
1459# define R300_WR_COMP_DISABLE (0 << 4)
1460# define R300_WR_COMP_ENABLE (1 << 4)
1461# define R300_ZB_CB_CLEAR_RMW (0 << 5)
1462# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
1463# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
1464# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
1465
1466# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
1467# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
1468# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
1469# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
1470
1471# define R500_BMASK_ENABLE (0 << 10)
1472# define R500_BMASK_DISABLE (1 << 10)
1473# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
1474# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
1475# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
1476# define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
1477# define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
1478# define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
1479# define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
1480# define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
1481# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
1482# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
1483# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
1484# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
1485# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
1486# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
1487# define R500_PEQ_PACKING_DISABLE (0 << 18)
1488# define R500_PEQ_PACKING_ENABLE (1 << 18)
1489# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
1490# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
1491
1425 1492
1426/* gap */ 1493/* gap */
1427 1494
1428#define R300_RB3D_DEPTHOFFSET 0x4F20 1495/* Z Buffer Address Offset.
1429#define R300_RB3D_DEPTHPITCH 0x4F24 1496 * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
1430# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ 1497 */
1431# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ 1498#define R300_ZB_DEPTHOFFSET 0x4f20
1432# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */ 1499
1433# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ 1500/* Z Buffer Pitch and Endian Control */
1434# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ 1501#define R300_ZB_DEPTHPITCH 0x4f24
1435# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ 1502# define R300_DEPTHPITCH_MASK 0x00003FFC
1503# define R300_DEPTHMACROTILE_DISABLE (0 << 16)
1504# define R300_DEPTHMACROTILE_ENABLE (1 << 16)
1505# define R300_DEPTHMICROTILE_LINEAR (0 << 17)
1506# define R300_DEPTHMICROTILE_TILED (1 << 17)
1507# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
1508# define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
1509# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
1510# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
1511# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
1512
1513/* Z Buffer Clear Value */
1514#define R300_ZB_DEPTHCLEARVALUE 0x4f28
1515
1516#define R300_ZB_ZMASK_OFFSET 0x4f30
1517#define R300_ZB_ZMASK_PITCH 0x4f34
1518#define R300_ZB_ZMASK_WRINDEX 0x4f38
1519#define R300_ZB_ZMASK_DWORD 0x4f3c
1520#define R300_ZB_ZMASK_RDINDEX 0x4f40
1521
1522/* Hierarchical Z Memory Offset */
1523#define R300_ZB_HIZ_OFFSET 0x4f44
1524
1525/* Hierarchical Z Write Index */
1526#define R300_ZB_HIZ_WRINDEX 0x4f48
1527
1528/* Hierarchical Z Data */
1529#define R300_ZB_HIZ_DWORD 0x4f4c
1530
1531/* Hierarchical Z Read Index */
1532#define R300_ZB_HIZ_RDINDEX 0x4f50
1533
1534/* Hierarchical Z Pitch */
1535#define R300_ZB_HIZ_PITCH 0x4f54
1536
1537/* Z Buffer Z Pass Counter Data */
1538#define R300_ZB_ZPASS_DATA 0x4f58
1539
1540/* Z Buffer Z Pass Counter Address */
1541#define R300_ZB_ZPASS_ADDR 0x4f5c
1542
1543/* Depth buffer X and Y coordinate offset */
1544#define R300_ZB_DEPTHXY_OFFSET 0x4f60
1545# define R300_DEPTHX_OFFSET_SHIFT 1
1546# define R300_DEPTHX_OFFSET_MASK 0x000007FE
1547# define R300_DEPTHY_OFFSET_SHIFT 17
1548# define R300_DEPTHY_OFFSET_MASK 0x07FE0000
1549
1550/* Sets the fifo sizes */
1551#define R500_ZB_FIFO_SIZE 0x4fd0
1552# define R500_OP_FIFO_SIZE_FULL (0 << 0)
1553# define R500_OP_FIFO_SIZE_HALF (1 << 0)
1554# define R500_OP_FIFO_SIZE_QUATER (2 << 0)
1555# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
1556
1557/* Stencil Reference Value and Mask for backfacing quads */
1558/* R300_ZB_STENCILREFMASK handles front face */
1559#define R500_ZB_STENCILREFMASK_BF 0x4fd4
1560# define R500_STENCILREF_SHIFT 0
1561# define R500_STENCILREF_MASK 0x000000ff
1562# define R500_STENCILMASK_SHIFT 8
1563# define R500_STENCILMASK_MASK 0x0000ff00
1564# define R500_STENCILWRITEMASK_SHIFT 16
1565# define R500_STENCILWRITEMASK_MASK 0x00ff0000
1436 1566
1437/* BEGIN: Vertex program instruction set */ 1567/* BEGIN: Vertex program instruction set */
1438 1568
@@ -1623,4 +1753,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1623 */ 1753 */
1624#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 1754#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
1625 1755
1756#define R500_VAP_INDEX_OFFSET 0x208c
1757
1758#define R500_GA_US_VECTOR_INDEX 0x4250
1759#define R500_GA_US_VECTOR_DATA 0x4254
1760
1761#define R500_RS_IP_0 0x4074
1762#define R500_RS_INST_0 0x4320
1763
1764#define R500_US_CONFIG 0x4600
1765
1766#define R500_US_FC_CTRL 0x4624
1767#define R500_US_CODE_ADDR 0x4630
1768
1769#define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0
1770#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8
1771
1626#endif /* _R300_REG_H */ 1772#endif /* _R300_REG_H */
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index f6f6c92bf771..e53158f0ecb5 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -2,6 +2,7 @@
2/* 2/*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
5 * All Rights Reserved. 6 * All Rights Reserved.
6 * 7 *
7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,789 +35,13 @@
34#include "radeon_drv.h" 35#include "radeon_drv.h"
35#include "r300_reg.h" 36#include "r300_reg.h"
36 37
38#include "radeon_microcode.h"
39
37#define RADEON_FIFO_DEBUG 0 40#define RADEON_FIFO_DEBUG 0
38 41
39static int radeon_do_cleanup_cp(struct drm_device * dev); 42static int radeon_do_cleanup_cp(struct drm_device * dev);
40 43
41/* CP microcode (from ATI) */ 44static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
42static const u32 R200_cp_microcode[][2] = {
43 {0x21007000, 0000000000},
44 {0x20007000, 0000000000},
45 {0x000000ab, 0x00000004},
46 {0x000000af, 0x00000004},
47 {0x66544a49, 0000000000},
48 {0x49494174, 0000000000},
49 {0x54517d83, 0000000000},
50 {0x498d8b64, 0000000000},
51 {0x49494949, 0000000000},
52 {0x49da493c, 0000000000},
53 {0x49989898, 0000000000},
54 {0xd34949d5, 0000000000},
55 {0x9dc90e11, 0000000000},
56 {0xce9b9b9b, 0000000000},
57 {0x000f0000, 0x00000016},
58 {0x352e232c, 0000000000},
59 {0x00000013, 0x00000004},
60 {0x000f0000, 0x00000016},
61 {0x352e272c, 0000000000},
62 {0x000f0001, 0x00000016},
63 {0x3239362f, 0000000000},
64 {0x000077ef, 0x00000002},
65 {0x00061000, 0x00000002},
66 {0x00000020, 0x0000001a},
67 {0x00004000, 0x0000001e},
68 {0x00061000, 0x00000002},
69 {0x00000020, 0x0000001a},
70 {0x00004000, 0x0000001e},
71 {0x00061000, 0x00000002},
72 {0x00000020, 0x0000001a},
73 {0x00004000, 0x0000001e},
74 {0x00000016, 0x00000004},
75 {0x0003802a, 0x00000002},
76 {0x040067e0, 0x00000002},
77 {0x00000016, 0x00000004},
78 {0x000077e0, 0x00000002},
79 {0x00065000, 0x00000002},
80 {0x000037e1, 0x00000002},
81 {0x040067e1, 0x00000006},
82 {0x000077e0, 0x00000002},
83 {0x000077e1, 0x00000002},
84 {0x000077e1, 0x00000006},
85 {0xffffffff, 0000000000},
86 {0x10000000, 0000000000},
87 {0x0003802a, 0x00000002},
88 {0x040067e0, 0x00000006},
89 {0x00007675, 0x00000002},
90 {0x00007676, 0x00000002},
91 {0x00007677, 0x00000002},
92 {0x00007678, 0x00000006},
93 {0x0003802b, 0x00000002},
94 {0x04002676, 0x00000002},
95 {0x00007677, 0x00000002},
96 {0x00007678, 0x00000006},
97 {0x0000002e, 0x00000018},
98 {0x0000002e, 0x00000018},
99 {0000000000, 0x00000006},
100 {0x0000002f, 0x00000018},
101 {0x0000002f, 0x00000018},
102 {0000000000, 0x00000006},
103 {0x01605000, 0x00000002},
104 {0x00065000, 0x00000002},
105 {0x00098000, 0x00000002},
106 {0x00061000, 0x00000002},
107 {0x64c0603d, 0x00000004},
108 {0x00080000, 0x00000016},
109 {0000000000, 0000000000},
110 {0x0400251d, 0x00000002},
111 {0x00007580, 0x00000002},
112 {0x00067581, 0x00000002},
113 {0x04002580, 0x00000002},
114 {0x00067581, 0x00000002},
115 {0x00000046, 0x00000004},
116 {0x00005000, 0000000000},
117 {0x00061000, 0x00000002},
118 {0x0000750e, 0x00000002},
119 {0x00019000, 0x00000002},
120 {0x00011055, 0x00000014},
121 {0x00000055, 0x00000012},
122 {0x0400250f, 0x00000002},
123 {0x0000504a, 0x00000004},
124 {0x00007565, 0x00000002},
125 {0x00007566, 0x00000002},
126 {0x00000051, 0x00000004},
127 {0x01e655b4, 0x00000002},
128 {0x4401b0dc, 0x00000002},
129 {0x01c110dc, 0x00000002},
130 {0x2666705d, 0x00000018},
131 {0x040c2565, 0x00000002},
132 {0x0000005d, 0x00000018},
133 {0x04002564, 0x00000002},
134 {0x00007566, 0x00000002},
135 {0x00000054, 0x00000004},
136 {0x00401060, 0x00000008},
137 {0x00101000, 0x00000002},
138 {0x000d80ff, 0x00000002},
139 {0x00800063, 0x00000008},
140 {0x000f9000, 0x00000002},
141 {0x000e00ff, 0x00000002},
142 {0000000000, 0x00000006},
143 {0x00000080, 0x00000018},
144 {0x00000054, 0x00000004},
145 {0x00007576, 0x00000002},
146 {0x00065000, 0x00000002},
147 {0x00009000, 0x00000002},
148 {0x00041000, 0x00000002},
149 {0x0c00350e, 0x00000002},
150 {0x00049000, 0x00000002},
151 {0x00051000, 0x00000002},
152 {0x01e785f8, 0x00000002},
153 {0x00200000, 0x00000002},
154 {0x00600073, 0x0000000c},
155 {0x00007563, 0x00000002},
156 {0x006075f0, 0x00000021},
157 {0x20007068, 0x00000004},
158 {0x00005068, 0x00000004},
159 {0x00007576, 0x00000002},
160 {0x00007577, 0x00000002},
161 {0x0000750e, 0x00000002},
162 {0x0000750f, 0x00000002},
163 {0x00a05000, 0x00000002},
164 {0x00600076, 0x0000000c},
165 {0x006075f0, 0x00000021},
166 {0x000075f8, 0x00000002},
167 {0x00000076, 0x00000004},
168 {0x000a750e, 0x00000002},
169 {0x0020750f, 0x00000002},
170 {0x00600079, 0x00000004},
171 {0x00007570, 0x00000002},
172 {0x00007571, 0x00000002},
173 {0x00007572, 0x00000006},
174 {0x00005000, 0x00000002},
175 {0x00a05000, 0x00000002},
176 {0x00007568, 0x00000002},
177 {0x00061000, 0x00000002},
178 {0x00000084, 0x0000000c},
179 {0x00058000, 0x00000002},
180 {0x0c607562, 0x00000002},
181 {0x00000086, 0x00000004},
182 {0x00600085, 0x00000004},
183 {0x400070dd, 0000000000},
184 {0x000380dd, 0x00000002},
185 {0x00000093, 0x0000001c},
186 {0x00065095, 0x00000018},
187 {0x040025bb, 0x00000002},
188 {0x00061096, 0x00000018},
189 {0x040075bc, 0000000000},
190 {0x000075bb, 0x00000002},
191 {0x000075bc, 0000000000},
192 {0x00090000, 0x00000006},
193 {0x00090000, 0x00000002},
194 {0x000d8002, 0x00000006},
195 {0x00005000, 0x00000002},
196 {0x00007821, 0x00000002},
197 {0x00007800, 0000000000},
198 {0x00007821, 0x00000002},
199 {0x00007800, 0000000000},
200 {0x01665000, 0x00000002},
201 {0x000a0000, 0x00000002},
202 {0x000671cc, 0x00000002},
203 {0x0286f1cd, 0x00000002},
204 {0x000000a3, 0x00000010},
205 {0x21007000, 0000000000},
206 {0x000000aa, 0x0000001c},
207 {0x00065000, 0x00000002},
208 {0x000a0000, 0x00000002},
209 {0x00061000, 0x00000002},
210 {0x000b0000, 0x00000002},
211 {0x38067000, 0x00000002},
212 {0x000a00a6, 0x00000004},
213 {0x20007000, 0000000000},
214 {0x01200000, 0x00000002},
215 {0x20077000, 0x00000002},
216 {0x01200000, 0x00000002},
217 {0x20007000, 0000000000},
218 {0x00061000, 0x00000002},
219 {0x0120751b, 0x00000002},
220 {0x8040750a, 0x00000002},
221 {0x8040750b, 0x00000002},
222 {0x00110000, 0x00000002},
223 {0x000380dd, 0x00000002},
224 {0x000000bd, 0x0000001c},
225 {0x00061096, 0x00000018},
226 {0x844075bd, 0x00000002},
227 {0x00061095, 0x00000018},
228 {0x840075bb, 0x00000002},
229 {0x00061096, 0x00000018},
230 {0x844075bc, 0x00000002},
231 {0x000000c0, 0x00000004},
232 {0x804075bd, 0x00000002},
233 {0x800075bb, 0x00000002},
234 {0x804075bc, 0x00000002},
235 {0x00108000, 0x00000002},
236 {0x01400000, 0x00000002},
237 {0x006000c4, 0x0000000c},
238 {0x20c07000, 0x00000020},
239 {0x000000c6, 0x00000012},
240 {0x00800000, 0x00000006},
241 {0x0080751d, 0x00000006},
242 {0x000025bb, 0x00000002},
243 {0x000040c0, 0x00000004},
244 {0x0000775c, 0x00000002},
245 {0x00a05000, 0x00000002},
246 {0x00661000, 0x00000002},
247 {0x0460275d, 0x00000020},
248 {0x00004000, 0000000000},
249 {0x00007999, 0x00000002},
250 {0x00a05000, 0x00000002},
251 {0x00661000, 0x00000002},
252 {0x0460299b, 0x00000020},
253 {0x00004000, 0000000000},
254 {0x01e00830, 0x00000002},
255 {0x21007000, 0000000000},
256 {0x00005000, 0x00000002},
257 {0x00038042, 0x00000002},
258 {0x040025e0, 0x00000002},
259 {0x000075e1, 0000000000},
260 {0x00000001, 0000000000},
261 {0x000380d9, 0x00000002},
262 {0x04007394, 0000000000},
263 {0000000000, 0000000000},
264 {0000000000, 0000000000},
265 {0000000000, 0000000000},
266 {0000000000, 0000000000},
267 {0000000000, 0000000000},
268 {0000000000, 0000000000},
269 {0000000000, 0000000000},
270 {0000000000, 0000000000},
271 {0000000000, 0000000000},
272 {0000000000, 0000000000},
273 {0000000000, 0000000000},
274 {0000000000, 0000000000},
275 {0000000000, 0000000000},
276 {0000000000, 0000000000},
277 {0000000000, 0000000000},
278 {0000000000, 0000000000},
279 {0000000000, 0000000000},
280 {0000000000, 0000000000},
281 {0000000000, 0000000000},
282 {0000000000, 0000000000},
283 {0000000000, 0000000000},
284 {0000000000, 0000000000},
285 {0000000000, 0000000000},
286 {0000000000, 0000000000},
287 {0000000000, 0000000000},
288 {0000000000, 0000000000},
289 {0000000000, 0000000000},
290 {0000000000, 0000000000},
291 {0000000000, 0000000000},
292 {0000000000, 0000000000},
293 {0000000000, 0000000000},
294 {0000000000, 0000000000},
295 {0000000000, 0000000000},
296 {0000000000, 0000000000},
297 {0000000000, 0000000000},
298 {0000000000, 0000000000},
299};
300
301static const u32 radeon_cp_microcode[][2] = {
302 {0x21007000, 0000000000},
303 {0x20007000, 0000000000},
304 {0x000000b4, 0x00000004},
305 {0x000000b8, 0x00000004},
306 {0x6f5b4d4c, 0000000000},
307 {0x4c4c427f, 0000000000},
308 {0x5b568a92, 0000000000},
309 {0x4ca09c6d, 0000000000},
310 {0xad4c4c4c, 0000000000},
311 {0x4ce1af3d, 0000000000},
312 {0xd8afafaf, 0000000000},
313 {0xd64c4cdc, 0000000000},
314 {0x4cd10d10, 0000000000},
315 {0x000f0000, 0x00000016},
316 {0x362f242d, 0000000000},
317 {0x00000012, 0x00000004},
318 {0x000f0000, 0x00000016},
319 {0x362f282d, 0000000000},
320 {0x000380e7, 0x00000002},
321 {0x04002c97, 0x00000002},
322 {0x000f0001, 0x00000016},
323 {0x333a3730, 0000000000},
324 {0x000077ef, 0x00000002},
325 {0x00061000, 0x00000002},
326 {0x00000021, 0x0000001a},
327 {0x00004000, 0x0000001e},
328 {0x00061000, 0x00000002},
329 {0x00000021, 0x0000001a},
330 {0x00004000, 0x0000001e},
331 {0x00061000, 0x00000002},
332 {0x00000021, 0x0000001a},
333 {0x00004000, 0x0000001e},
334 {0x00000017, 0x00000004},
335 {0x0003802b, 0x00000002},
336 {0x040067e0, 0x00000002},
337 {0x00000017, 0x00000004},
338 {0x000077e0, 0x00000002},
339 {0x00065000, 0x00000002},
340 {0x000037e1, 0x00000002},
341 {0x040067e1, 0x00000006},
342 {0x000077e0, 0x00000002},
343 {0x000077e1, 0x00000002},
344 {0x000077e1, 0x00000006},
345 {0xffffffff, 0000000000},
346 {0x10000000, 0000000000},
347 {0x0003802b, 0x00000002},
348 {0x040067e0, 0x00000006},
349 {0x00007675, 0x00000002},
350 {0x00007676, 0x00000002},
351 {0x00007677, 0x00000002},
352 {0x00007678, 0x00000006},
353 {0x0003802c, 0x00000002},
354 {0x04002676, 0x00000002},
355 {0x00007677, 0x00000002},
356 {0x00007678, 0x00000006},
357 {0x0000002f, 0x00000018},
358 {0x0000002f, 0x00000018},
359 {0000000000, 0x00000006},
360 {0x00000030, 0x00000018},
361 {0x00000030, 0x00000018},
362 {0000000000, 0x00000006},
363 {0x01605000, 0x00000002},
364 {0x00065000, 0x00000002},
365 {0x00098000, 0x00000002},
366 {0x00061000, 0x00000002},
367 {0x64c0603e, 0x00000004},
368 {0x000380e6, 0x00000002},
369 {0x040025c5, 0x00000002},
370 {0x00080000, 0x00000016},
371 {0000000000, 0000000000},
372 {0x0400251d, 0x00000002},
373 {0x00007580, 0x00000002},
374 {0x00067581, 0x00000002},
375 {0x04002580, 0x00000002},
376 {0x00067581, 0x00000002},
377 {0x00000049, 0x00000004},
378 {0x00005000, 0000000000},
379 {0x000380e6, 0x00000002},
380 {0x040025c5, 0x00000002},
381 {0x00061000, 0x00000002},
382 {0x0000750e, 0x00000002},
383 {0x00019000, 0x00000002},
384 {0x00011055, 0x00000014},
385 {0x00000055, 0x00000012},
386 {0x0400250f, 0x00000002},
387 {0x0000504f, 0x00000004},
388 {0x000380e6, 0x00000002},
389 {0x040025c5, 0x00000002},
390 {0x00007565, 0x00000002},
391 {0x00007566, 0x00000002},
392 {0x00000058, 0x00000004},
393 {0x000380e6, 0x00000002},
394 {0x040025c5, 0x00000002},
395 {0x01e655b4, 0x00000002},
396 {0x4401b0e4, 0x00000002},
397 {0x01c110e4, 0x00000002},
398 {0x26667066, 0x00000018},
399 {0x040c2565, 0x00000002},
400 {0x00000066, 0x00000018},
401 {0x04002564, 0x00000002},
402 {0x00007566, 0x00000002},
403 {0x0000005d, 0x00000004},
404 {0x00401069, 0x00000008},
405 {0x00101000, 0x00000002},
406 {0x000d80ff, 0x00000002},
407 {0x0080006c, 0x00000008},
408 {0x000f9000, 0x00000002},
409 {0x000e00ff, 0x00000002},
410 {0000000000, 0x00000006},
411 {0x0000008f, 0x00000018},
412 {0x0000005b, 0x00000004},
413 {0x000380e6, 0x00000002},
414 {0x040025c5, 0x00000002},
415 {0x00007576, 0x00000002},
416 {0x00065000, 0x00000002},
417 {0x00009000, 0x00000002},
418 {0x00041000, 0x00000002},
419 {0x0c00350e, 0x00000002},
420 {0x00049000, 0x00000002},
421 {0x00051000, 0x00000002},
422 {0x01e785f8, 0x00000002},
423 {0x00200000, 0x00000002},
424 {0x0060007e, 0x0000000c},
425 {0x00007563, 0x00000002},
426 {0x006075f0, 0x00000021},
427 {0x20007073, 0x00000004},
428 {0x00005073, 0x00000004},
429 {0x000380e6, 0x00000002},
430 {0x040025c5, 0x00000002},
431 {0x00007576, 0x00000002},
432 {0x00007577, 0x00000002},
433 {0x0000750e, 0x00000002},
434 {0x0000750f, 0x00000002},
435 {0x00a05000, 0x00000002},
436 {0x00600083, 0x0000000c},
437 {0x006075f0, 0x00000021},
438 {0x000075f8, 0x00000002},
439 {0x00000083, 0x00000004},
440 {0x000a750e, 0x00000002},
441 {0x000380e6, 0x00000002},
442 {0x040025c5, 0x00000002},
443 {0x0020750f, 0x00000002},
444 {0x00600086, 0x00000004},
445 {0x00007570, 0x00000002},
446 {0x00007571, 0x00000002},
447 {0x00007572, 0x00000006},
448 {0x000380e6, 0x00000002},
449 {0x040025c5, 0x00000002},
450 {0x00005000, 0x00000002},
451 {0x00a05000, 0x00000002},
452 {0x00007568, 0x00000002},
453 {0x00061000, 0x00000002},
454 {0x00000095, 0x0000000c},
455 {0x00058000, 0x00000002},
456 {0x0c607562, 0x00000002},
457 {0x00000097, 0x00000004},
458 {0x000380e6, 0x00000002},
459 {0x040025c5, 0x00000002},
460 {0x00600096, 0x00000004},
461 {0x400070e5, 0000000000},
462 {0x000380e6, 0x00000002},
463 {0x040025c5, 0x00000002},
464 {0x000380e5, 0x00000002},
465 {0x000000a8, 0x0000001c},
466 {0x000650aa, 0x00000018},
467 {0x040025bb, 0x00000002},
468 {0x000610ab, 0x00000018},
469 {0x040075bc, 0000000000},
470 {0x000075bb, 0x00000002},
471 {0x000075bc, 0000000000},
472 {0x00090000, 0x00000006},
473 {0x00090000, 0x00000002},
474 {0x000d8002, 0x00000006},
475 {0x00007832, 0x00000002},
476 {0x00005000, 0x00000002},
477 {0x000380e7, 0x00000002},
478 {0x04002c97, 0x00000002},
479 {0x00007820, 0x00000002},
480 {0x00007821, 0x00000002},
481 {0x00007800, 0000000000},
482 {0x01200000, 0x00000002},
483 {0x20077000, 0x00000002},
484 {0x01200000, 0x00000002},
485 {0x20007000, 0x00000002},
486 {0x00061000, 0x00000002},
487 {0x0120751b, 0x00000002},
488 {0x8040750a, 0x00000002},
489 {0x8040750b, 0x00000002},
490 {0x00110000, 0x00000002},
491 {0x000380e5, 0x00000002},
492 {0x000000c6, 0x0000001c},
493 {0x000610ab, 0x00000018},
494 {0x844075bd, 0x00000002},
495 {0x000610aa, 0x00000018},
496 {0x840075bb, 0x00000002},
497 {0x000610ab, 0x00000018},
498 {0x844075bc, 0x00000002},
499 {0x000000c9, 0x00000004},
500 {0x804075bd, 0x00000002},
501 {0x800075bb, 0x00000002},
502 {0x804075bc, 0x00000002},
503 {0x00108000, 0x00000002},
504 {0x01400000, 0x00000002},
505 {0x006000cd, 0x0000000c},
506 {0x20c07000, 0x00000020},
507 {0x000000cf, 0x00000012},
508 {0x00800000, 0x00000006},
509 {0x0080751d, 0x00000006},
510 {0000000000, 0000000000},
511 {0x0000775c, 0x00000002},
512 {0x00a05000, 0x00000002},
513 {0x00661000, 0x00000002},
514 {0x0460275d, 0x00000020},
515 {0x00004000, 0000000000},
516 {0x01e00830, 0x00000002},
517 {0x21007000, 0000000000},
518 {0x6464614d, 0000000000},
519 {0x69687420, 0000000000},
520 {0x00000073, 0000000000},
521 {0000000000, 0000000000},
522 {0x00005000, 0x00000002},
523 {0x000380d0, 0x00000002},
524 {0x040025e0, 0x00000002},
525 {0x000075e1, 0000000000},
526 {0x00000001, 0000000000},
527 {0x000380e0, 0x00000002},
528 {0x04002394, 0x00000002},
529 {0x00005000, 0000000000},
530 {0000000000, 0000000000},
531 {0000000000, 0000000000},
532 {0x00000008, 0000000000},
533 {0x00000004, 0000000000},
534 {0000000000, 0000000000},
535 {0000000000, 0000000000},
536 {0000000000, 0000000000},
537 {0000000000, 0000000000},
538 {0000000000, 0000000000},
539 {0000000000, 0000000000},
540 {0000000000, 0000000000},
541 {0000000000, 0000000000},
542 {0000000000, 0000000000},
543 {0000000000, 0000000000},
544 {0000000000, 0000000000},
545 {0000000000, 0000000000},
546 {0000000000, 0000000000},
547 {0000000000, 0000000000},
548 {0000000000, 0000000000},
549 {0000000000, 0000000000},
550 {0000000000, 0000000000},
551 {0000000000, 0000000000},
552 {0000000000, 0000000000},
553 {0000000000, 0000000000},
554 {0000000000, 0000000000},
555 {0000000000, 0000000000},
556 {0000000000, 0000000000},
557 {0000000000, 0000000000},
558};
559
560static const u32 R300_cp_microcode[][2] = {
561 {0x4200e000, 0000000000},
562 {0x4000e000, 0000000000},
563 {0x000000af, 0x00000008},
564 {0x000000b3, 0x00000008},
565 {0x6c5a504f, 0000000000},
566 {0x4f4f497a, 0000000000},
567 {0x5a578288, 0000000000},
568 {0x4f91906a, 0000000000},
569 {0x4f4f4f4f, 0000000000},
570 {0x4fe24f44, 0000000000},
571 {0x4f9c9c9c, 0000000000},
572 {0xdc4f4fde, 0000000000},
573 {0xa1cd4f4f, 0000000000},
574 {0xd29d9d9d, 0000000000},
575 {0x4f0f9fd7, 0000000000},
576 {0x000ca000, 0x00000004},
577 {0x000d0012, 0x00000038},
578 {0x0000e8b4, 0x00000004},
579 {0x000d0014, 0x00000038},
580 {0x0000e8b6, 0x00000004},
581 {0x000d0016, 0x00000038},
582 {0x0000e854, 0x00000004},
583 {0x000d0018, 0x00000038},
584 {0x0000e855, 0x00000004},
585 {0x000d001a, 0x00000038},
586 {0x0000e856, 0x00000004},
587 {0x000d001c, 0x00000038},
588 {0x0000e857, 0x00000004},
589 {0x000d001e, 0x00000038},
590 {0x0000e824, 0x00000004},
591 {0x000d0020, 0x00000038},
592 {0x0000e825, 0x00000004},
593 {0x000d0022, 0x00000038},
594 {0x0000e830, 0x00000004},
595 {0x000d0024, 0x00000038},
596 {0x0000f0c0, 0x00000004},
597 {0x000d0026, 0x00000038},
598 {0x0000f0c1, 0x00000004},
599 {0x000d0028, 0x00000038},
600 {0x0000f041, 0x00000004},
601 {0x000d002a, 0x00000038},
602 {0x0000f184, 0x00000004},
603 {0x000d002c, 0x00000038},
604 {0x0000f185, 0x00000004},
605 {0x000d002e, 0x00000038},
606 {0x0000f186, 0x00000004},
607 {0x000d0030, 0x00000038},
608 {0x0000f187, 0x00000004},
609 {0x000d0032, 0x00000038},
610 {0x0000f180, 0x00000004},
611 {0x000d0034, 0x00000038},
612 {0x0000f393, 0x00000004},
613 {0x000d0036, 0x00000038},
614 {0x0000f38a, 0x00000004},
615 {0x000d0038, 0x00000038},
616 {0x0000f38e, 0x00000004},
617 {0x0000e821, 0x00000004},
618 {0x0140a000, 0x00000004},
619 {0x00000043, 0x00000018},
620 {0x00cce800, 0x00000004},
621 {0x001b0001, 0x00000004},
622 {0x08004800, 0x00000004},
623 {0x001b0001, 0x00000004},
624 {0x08004800, 0x00000004},
625 {0x001b0001, 0x00000004},
626 {0x08004800, 0x00000004},
627 {0x0000003a, 0x00000008},
628 {0x0000a000, 0000000000},
629 {0x02c0a000, 0x00000004},
630 {0x000ca000, 0x00000004},
631 {0x00130000, 0x00000004},
632 {0x000c2000, 0x00000004},
633 {0xc980c045, 0x00000008},
634 {0x2000451d, 0x00000004},
635 {0x0000e580, 0x00000004},
636 {0x000ce581, 0x00000004},
637 {0x08004580, 0x00000004},
638 {0x000ce581, 0x00000004},
639 {0x0000004c, 0x00000008},
640 {0x0000a000, 0000000000},
641 {0x000c2000, 0x00000004},
642 {0x0000e50e, 0x00000004},
643 {0x00032000, 0x00000004},
644 {0x00022056, 0x00000028},
645 {0x00000056, 0x00000024},
646 {0x0800450f, 0x00000004},
647 {0x0000a050, 0x00000008},
648 {0x0000e565, 0x00000004},
649 {0x0000e566, 0x00000004},
650 {0x00000057, 0x00000008},
651 {0x03cca5b4, 0x00000004},
652 {0x05432000, 0x00000004},
653 {0x00022000, 0x00000004},
654 {0x4ccce063, 0x00000030},
655 {0x08274565, 0x00000004},
656 {0x00000063, 0x00000030},
657 {0x08004564, 0x00000004},
658 {0x0000e566, 0x00000004},
659 {0x0000005a, 0x00000008},
660 {0x00802066, 0x00000010},
661 {0x00202000, 0x00000004},
662 {0x001b00ff, 0x00000004},
663 {0x01000069, 0x00000010},
664 {0x001f2000, 0x00000004},
665 {0x001c00ff, 0x00000004},
666 {0000000000, 0x0000000c},
667 {0x00000085, 0x00000030},
668 {0x0000005a, 0x00000008},
669 {0x0000e576, 0x00000004},
670 {0x000ca000, 0x00000004},
671 {0x00012000, 0x00000004},
672 {0x00082000, 0x00000004},
673 {0x1800650e, 0x00000004},
674 {0x00092000, 0x00000004},
675 {0x000a2000, 0x00000004},
676 {0x000f0000, 0x00000004},
677 {0x00400000, 0x00000004},
678 {0x00000079, 0x00000018},
679 {0x0000e563, 0x00000004},
680 {0x00c0e5f9, 0x000000c2},
681 {0x0000006e, 0x00000008},
682 {0x0000a06e, 0x00000008},
683 {0x0000e576, 0x00000004},
684 {0x0000e577, 0x00000004},
685 {0x0000e50e, 0x00000004},
686 {0x0000e50f, 0x00000004},
687 {0x0140a000, 0x00000004},
688 {0x0000007c, 0x00000018},
689 {0x00c0e5f9, 0x000000c2},
690 {0x0000007c, 0x00000008},
691 {0x0014e50e, 0x00000004},
692 {0x0040e50f, 0x00000004},
693 {0x00c0007f, 0x00000008},
694 {0x0000e570, 0x00000004},
695 {0x0000e571, 0x00000004},
696 {0x0000e572, 0x0000000c},
697 {0x0000a000, 0x00000004},
698 {0x0140a000, 0x00000004},
699 {0x0000e568, 0x00000004},
700 {0x000c2000, 0x00000004},
701 {0x00000089, 0x00000018},
702 {0x000b0000, 0x00000004},
703 {0x18c0e562, 0x00000004},
704 {0x0000008b, 0x00000008},
705 {0x00c0008a, 0x00000008},
706 {0x000700e4, 0x00000004},
707 {0x00000097, 0x00000038},
708 {0x000ca099, 0x00000030},
709 {0x080045bb, 0x00000004},
710 {0x000c209a, 0x00000030},
711 {0x0800e5bc, 0000000000},
712 {0x0000e5bb, 0x00000004},
713 {0x0000e5bc, 0000000000},
714 {0x00120000, 0x0000000c},
715 {0x00120000, 0x00000004},
716 {0x001b0002, 0x0000000c},
717 {0x0000a000, 0x00000004},
718 {0x0000e821, 0x00000004},
719 {0x0000e800, 0000000000},
720 {0x0000e821, 0x00000004},
721 {0x0000e82e, 0000000000},
722 {0x02cca000, 0x00000004},
723 {0x00140000, 0x00000004},
724 {0x000ce1cc, 0x00000004},
725 {0x050de1cd, 0x00000004},
726 {0x000000a7, 0x00000020},
727 {0x4200e000, 0000000000},
728 {0x000000ae, 0x00000038},
729 {0x000ca000, 0x00000004},
730 {0x00140000, 0x00000004},
731 {0x000c2000, 0x00000004},
732 {0x00160000, 0x00000004},
733 {0x700ce000, 0x00000004},
734 {0x001400aa, 0x00000008},
735 {0x4000e000, 0000000000},
736 {0x02400000, 0x00000004},
737 {0x400ee000, 0x00000004},
738 {0x02400000, 0x00000004},
739 {0x4000e000, 0000000000},
740 {0x000c2000, 0x00000004},
741 {0x0240e51b, 0x00000004},
742 {0x0080e50a, 0x00000005},
743 {0x0080e50b, 0x00000005},
744 {0x00220000, 0x00000004},
745 {0x000700e4, 0x00000004},
746 {0x000000c1, 0x00000038},
747 {0x000c209a, 0x00000030},
748 {0x0880e5bd, 0x00000005},
749 {0x000c2099, 0x00000030},
750 {0x0800e5bb, 0x00000005},
751 {0x000c209a, 0x00000030},
752 {0x0880e5bc, 0x00000005},
753 {0x000000c4, 0x00000008},
754 {0x0080e5bd, 0x00000005},
755 {0x0000e5bb, 0x00000005},
756 {0x0080e5bc, 0x00000005},
757 {0x00210000, 0x00000004},
758 {0x02800000, 0x00000004},
759 {0x00c000c8, 0x00000018},
760 {0x4180e000, 0x00000040},
761 {0x000000ca, 0x00000024},
762 {0x01000000, 0x0000000c},
763 {0x0100e51d, 0x0000000c},
764 {0x000045bb, 0x00000004},
765 {0x000080c4, 0x00000008},
766 {0x0000f3ce, 0x00000004},
767 {0x0140a000, 0x00000004},
768 {0x00cc2000, 0x00000004},
769 {0x08c053cf, 0x00000040},
770 {0x00008000, 0000000000},
771 {0x0000f3d2, 0x00000004},
772 {0x0140a000, 0x00000004},
773 {0x00cc2000, 0x00000004},
774 {0x08c053d3, 0x00000040},
775 {0x00008000, 0000000000},
776 {0x0000f39d, 0x00000004},
777 {0x0140a000, 0x00000004},
778 {0x00cc2000, 0x00000004},
779 {0x08c0539e, 0x00000040},
780 {0x00008000, 0000000000},
781 {0x03c00830, 0x00000004},
782 {0x4200e000, 0000000000},
783 {0x0000a000, 0x00000004},
784 {0x200045e0, 0x00000004},
785 {0x0000e5e1, 0000000000},
786 {0x00000001, 0000000000},
787 {0x000700e1, 0x00000004},
788 {0x0800e394, 0000000000},
789 {0000000000, 0000000000},
790 {0000000000, 0000000000},
791 {0000000000, 0000000000},
792 {0000000000, 0000000000},
793 {0000000000, 0000000000},
794 {0000000000, 0000000000},
795 {0000000000, 0000000000},
796 {0000000000, 0000000000},
797 {0000000000, 0000000000},
798 {0000000000, 0000000000},
799 {0000000000, 0000000000},
800 {0000000000, 0000000000},
801 {0000000000, 0000000000},
802 {0000000000, 0000000000},
803 {0000000000, 0000000000},
804 {0000000000, 0000000000},
805 {0000000000, 0000000000},
806 {0000000000, 0000000000},
807 {0000000000, 0000000000},
808 {0000000000, 0000000000},
809 {0000000000, 0000000000},
810 {0000000000, 0000000000},
811 {0000000000, 0000000000},
812 {0000000000, 0000000000},
813 {0000000000, 0000000000},
814 {0000000000, 0000000000},
815 {0000000000, 0000000000},
816 {0000000000, 0000000000},
817};
818
819static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
820{ 45{
821 u32 ret; 46 u32 ret;
822 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); 47 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
@@ -825,21 +50,41 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
825 return ret; 50 return ret;
826} 51}
827 52
53static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
54{
55 u32 ret;
56 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
57 ret = RADEON_READ(RS480_NB_MC_DATA);
58 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
59 return ret;
60}
61
828static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 62static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
829{ 63{
64 u32 ret;
830 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 65 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
831 return RADEON_READ(RS690_MC_DATA); 66 ret = RADEON_READ(RS690_MC_DATA);
67 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
68 return ret;
69}
70
71static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
72{
73 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
74 return RS690_READ_MCIND(dev_priv, addr);
75 else
76 return RS480_READ_MCIND(dev_priv, addr);
832} 77}
833 78
834u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) 79u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
835{ 80{
836 81
837 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 82 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
838 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); 83 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
839 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 84 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
840 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); 85 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
841 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 86 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
842 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); 87 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
843 else 88 else
844 return RADEON_READ(RADEON_MC_FB_LOCATION); 89 return RADEON_READ(RADEON_MC_FB_LOCATION);
845} 90}
@@ -847,11 +92,11 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
847static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) 92static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
848{ 93{
849 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 94 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
850 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); 95 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
851 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 96 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
852 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); 97 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
853 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 98 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
854 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); 99 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
855 else 100 else
856 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); 101 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
857} 102}
@@ -859,15 +104,39 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
859static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) 104static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
860{ 105{
861 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 106 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
862 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); 107 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
863 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 108 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
864 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); 109 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
865 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 110 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
866 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); 111 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
867 else 112 else
868 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); 113 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
869} 114}
870 115
116static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
117{
118 u32 agp_base_hi = upper_32_bits(agp_base);
119 u32 agp_base_lo = agp_base & 0xffffffff;
120
121 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
122 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
123 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
124 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
125 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
126 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
127 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
128 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
129 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
130 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {
131 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
132 RADEON_WRITE(RS480_AGP_BASE_2, 0);
133 } else {
134 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
135 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
136 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
137 }
138}
139
871static int RADEON_READ_PLL(struct drm_device * dev, int addr) 140static int RADEON_READ_PLL(struct drm_device * dev, int addr)
872{ 141{
873 drm_radeon_private_t *dev_priv = dev->dev_private; 142 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -882,15 +151,6 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
882 return RADEON_READ(RADEON_PCIE_DATA); 151 return RADEON_READ(RADEON_PCIE_DATA);
883} 152}
884 153
885static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
886{
887 u32 ret;
888 RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
889 ret = RADEON_READ(RADEON_IGPGART_DATA);
890 RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
891 return ret;
892}
893
894#if RADEON_FIFO_DEBUG 154#if RADEON_FIFO_DEBUG
895static void radeon_status(drm_radeon_private_t * dev_priv) 155static void radeon_status(drm_radeon_private_t * dev_priv)
896{ 156{
@@ -925,16 +185,36 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
925 185
926 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 186 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
927 187
928 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); 188 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
929 tmp |= RADEON_RB3D_DC_FLUSH_ALL; 189 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
930 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); 190 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
191 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
931 192
932 for (i = 0; i < dev_priv->usec_timeout; i++) { 193 for (i = 0; i < dev_priv->usec_timeout; i++) {
933 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) 194 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
934 & RADEON_RB3D_DC_BUSY)) { 195 & RADEON_RB3D_DC_BUSY)) {
935 return 0; 196 return 0;
197 }
198 DRM_UDELAY(1);
199 }
200 } else {
201 /* 3D */
202 tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
203 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
204 RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
205
206 /* 2D */
207 tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT);
208 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
209 RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp);
210
211 for (i = 0; i < dev_priv->usec_timeout; i++) {
212 if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT)
213 & RADEON_RB3D_DC_BUSY)) {
214 return 0;
215 }
216 DRM_UDELAY(1);
936 } 217 }
937 DRM_UDELAY(1);
938 } 218 }
939 219
940#if RADEON_FIFO_DEBUG 220#if RADEON_FIFO_DEBUG
@@ -991,6 +271,50 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
991 return -EBUSY; 271 return -EBUSY;
992} 272}
993 273
274static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
275{
276 uint32_t gb_tile_config, gb_pipe_sel = 0;
277
278 /* RS4xx/RS6xx/R4xx/R5xx */
279 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
280 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
281 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
282 } else {
283 /* R3xx */
284 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
285 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
286 dev_priv->num_gb_pipes = 2;
287 } else {
288 /* R3Vxx */
289 dev_priv->num_gb_pipes = 1;
290 }
291 }
292 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
293
294 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
295
296 switch (dev_priv->num_gb_pipes) {
297 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
298 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
299 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
300 default:
301 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
302 }
303
304 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
305 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
306 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
307 }
308 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
309 radeon_do_wait_for_idle(dev_priv);
310 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
311 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
312 R300_DC_AUTOFLUSH_ENABLE |
313 R300_DC_DC_DISABLE_IGNORE_PE));
314
315
316}
317
994/* ================================================================ 318/* ================================================================
995 * CP control, initialization 319 * CP control, initialization
996 */ 320 */
@@ -1004,8 +328,22 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1004 radeon_do_wait_for_idle(dev_priv); 328 radeon_do_wait_for_idle(dev_priv);
1005 329
1006 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); 330 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
1007 331 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
1008 if (dev_priv->microcode_version == UCODE_R200) { 332 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
333 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
334 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
335 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
336 DRM_INFO("Loading R100 Microcode\n");
337 for (i = 0; i < 256; i++) {
338 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
339 R100_cp_microcode[i][1]);
340 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
341 R100_cp_microcode[i][0]);
342 }
343 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
344 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
345 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
346 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
1009 DRM_INFO("Loading R200 Microcode\n"); 347 DRM_INFO("Loading R200 Microcode\n");
1010 for (i = 0; i < 256; i++) { 348 for (i = 0; i < 256; i++) {
1011 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 349 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -1013,7 +351,11 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1013 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 351 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1014 R200_cp_microcode[i][0]); 352 R200_cp_microcode[i][0]);
1015 } 353 }
1016 } else if (dev_priv->microcode_version == UCODE_R300) { 354 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
355 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
356 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
357 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
358 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
1017 DRM_INFO("Loading R300 Microcode\n"); 359 DRM_INFO("Loading R300 Microcode\n");
1018 for (i = 0; i < 256; i++) { 360 for (i = 0; i < 256; i++) {
1019 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 361 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -1021,12 +363,35 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1021 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 363 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1022 R300_cp_microcode[i][0]); 364 R300_cp_microcode[i][0]);
1023 } 365 }
1024 } else { 366 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
367 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
368 DRM_INFO("Loading R400 Microcode\n");
1025 for (i = 0; i < 256; i++) { 369 for (i = 0; i < 256; i++) {
1026 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 370 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1027 radeon_cp_microcode[i][1]); 371 R420_cp_microcode[i][1]);
1028 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 372 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1029 radeon_cp_microcode[i][0]); 373 R420_cp_microcode[i][0]);
374 }
375 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
376 DRM_INFO("Loading RS690 Microcode\n");
377 for (i = 0; i < 256; i++) {
378 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
379 RS690_cp_microcode[i][1]);
380 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
381 RS690_cp_microcode[i][0]);
382 }
383 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
384 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
385 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
386 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
387 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
388 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
389 DRM_INFO("Loading R500 Microcode\n");
390 for (i = 0; i < 256; i++) {
391 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
392 R520_cp_microcode[i][1]);
393 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
394 R520_cp_microcode[i][0]);
1030 } 395 }
1031 } 396 }
1032} 397}
@@ -1121,12 +486,13 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1121static int radeon_do_engine_reset(struct drm_device * dev) 486static int radeon_do_engine_reset(struct drm_device * dev)
1122{ 487{
1123 drm_radeon_private_t *dev_priv = dev->dev_private; 488 drm_radeon_private_t *dev_priv = dev->dev_private;
1124 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; 489 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
1125 DRM_DEBUG("\n"); 490 DRM_DEBUG("\n");
1126 491
1127 radeon_do_pixcache_flush(dev_priv); 492 radeon_do_pixcache_flush(dev_priv);
1128 493
1129 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { 494 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
495 /* may need something similar for newer chips */
1130 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); 496 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1131 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); 497 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1132 498
@@ -1137,33 +503,39 @@ static int radeon_do_engine_reset(struct drm_device * dev)
1137 RADEON_FORCEON_YCLKB | 503 RADEON_FORCEON_YCLKB |
1138 RADEON_FORCEON_MC | 504 RADEON_FORCEON_MC |
1139 RADEON_FORCEON_AIC)); 505 RADEON_FORCEON_AIC));
506 }
1140 507
1141 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); 508 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1142 509
1143 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | 510 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1144 RADEON_SOFT_RESET_CP | 511 RADEON_SOFT_RESET_CP |
1145 RADEON_SOFT_RESET_HI | 512 RADEON_SOFT_RESET_HI |
1146 RADEON_SOFT_RESET_SE | 513 RADEON_SOFT_RESET_SE |
1147 RADEON_SOFT_RESET_RE | 514 RADEON_SOFT_RESET_RE |
1148 RADEON_SOFT_RESET_PP | 515 RADEON_SOFT_RESET_PP |
1149 RADEON_SOFT_RESET_E2 | 516 RADEON_SOFT_RESET_E2 |
1150 RADEON_SOFT_RESET_RB)); 517 RADEON_SOFT_RESET_RB));
1151 RADEON_READ(RADEON_RBBM_SOFT_RESET); 518 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1152 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 519 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1153 ~(RADEON_SOFT_RESET_CP | 520 ~(RADEON_SOFT_RESET_CP |
1154 RADEON_SOFT_RESET_HI | 521 RADEON_SOFT_RESET_HI |
1155 RADEON_SOFT_RESET_SE | 522 RADEON_SOFT_RESET_SE |
1156 RADEON_SOFT_RESET_RE | 523 RADEON_SOFT_RESET_RE |
1157 RADEON_SOFT_RESET_PP | 524 RADEON_SOFT_RESET_PP |
1158 RADEON_SOFT_RESET_E2 | 525 RADEON_SOFT_RESET_E2 |
1159 RADEON_SOFT_RESET_RB))); 526 RADEON_SOFT_RESET_RB)));
1160 RADEON_READ(RADEON_RBBM_SOFT_RESET); 527 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1161 528
529 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
1162 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); 530 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1163 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); 531 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1164 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); 532 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1165 } 533 }
1166 534
535 /* setup the raster pipes */
536 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
537 radeon_init_pipes(dev_priv);
538
1167 /* Reset the CP ring */ 539 /* Reset the CP ring */
1168 radeon_do_cp_reset(dev_priv); 540 radeon_do_cp_reset(dev_priv);
1169 541
@@ -1194,7 +566,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
1194 566
1195#if __OS_HAS_AGP 567#if __OS_HAS_AGP
1196 if (dev_priv->flags & RADEON_IS_AGP) { 568 if (dev_priv->flags & RADEON_IS_AGP) {
1197 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); 569 radeon_write_agp_base(dev_priv, dev->agp->base);
570
1198 radeon_write_agp_location(dev_priv, 571 radeon_write_agp_location(dev_priv,
1199 (((dev_priv->gart_vm_start - 1 + 572 (((dev_priv->gart_vm_start - 1 +
1200 dev_priv->gart_size) & 0xffff0000) | 573 dev_priv->gart_size) & 0xffff0000) |
@@ -1339,102 +712,70 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1339/* Enable or disable IGP GART on the chip */ 712/* Enable or disable IGP GART on the chip */
1340static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) 713static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
1341{ 714{
1342 u32 temp, tmp;
1343
1344 tmp = RADEON_READ(RADEON_AIC_CNTL);
1345 if (on) {
1346 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
1347 dev_priv->gart_vm_start,
1348 (long)dev_priv->gart_info.bus_addr,
1349 dev_priv->gart_size);
1350
1351 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
1352 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
1353 RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
1354 RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
1355 dev_priv->gart_info.bus_addr);
1356
1357 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
1358 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
1359
1360 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
1361 dev_priv->gart_size = 32*1024*1024;
1362 radeon_write_agp_location(dev_priv,
1363 (((dev_priv->gart_vm_start - 1 +
1364 dev_priv->gart_size) & 0xffff0000) |
1365 (dev_priv->gart_vm_start >> 16)));
1366
1367 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
1368 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
1369
1370 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1371 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
1372 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1373 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
1374 }
1375}
1376
1377/* Enable or disable RS690 GART on the chip */
1378static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
1379{
1380 u32 temp; 715 u32 temp;
1381 716
1382 if (on) { 717 if (on) {
1383 DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n", 718 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
1384 dev_priv->gart_vm_start, 719 dev_priv->gart_vm_start,
1385 (long)dev_priv->gart_info.bus_addr, 720 (long)dev_priv->gart_info.bus_addr,
1386 dev_priv->gart_size); 721 dev_priv->gart_size);
1387 722
1388 temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL); 723 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
1389 RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000); 724 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
725 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
726 RS690_BLOCK_GFX_D3_EN));
727 else
728 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
1390 729
1391 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, 730 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
1392 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); 731 RS480_VA_SIZE_32MB));
1393 732
1394 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID); 733 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
1395 RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800); 734 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
735 RS480_TLB_ENABLE |
736 RS480_GTW_LAC_EN |
737 RS480_1LEVEL_GART));
1396 738
1397 RS690_WRITE_MCIND(RS690_MC_GART_BASE, 739 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
1398 dev_priv->gart_info.bus_addr); 740 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
741 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
1399 742
1400 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL); 743 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
1401 RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000); 744 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
745 RS480_REQ_TYPE_SNOOP_DIS));
1402 746
1403 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, 747 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
1404 (unsigned int)dev_priv->gart_vm_start);
1405 748
1406 dev_priv->gart_size = 32*1024*1024; 749 dev_priv->gart_size = 32*1024*1024;
1407 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & 750 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
1408 0xffff0000) | (dev_priv->gart_vm_start >> 16)); 751 0xffff0000) | (dev_priv->gart_vm_start >> 16));
1409 752
1410 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp); 753 radeon_write_agp_location(dev_priv, temp);
1411 754
1412 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE); 755 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
1413 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, 756 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
1414 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); 757 RS480_VA_SIZE_32MB));
1415 758
1416 do { 759 do {
1417 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); 760 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
1418 if ((temp & RS690_MC_GART_CLEAR_STATUS) == 761 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
1419 RS690_MC_GART_CLEAR_DONE)
1420 break; 762 break;
1421 DRM_UDELAY(1); 763 DRM_UDELAY(1);
1422 } while (1); 764 } while (1);
1423 765
1424 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, 766 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
1425 RS690_MC_GART_CC_CLEAR); 767 RS480_GART_CACHE_INVALIDATE);
768
1426 do { 769 do {
1427 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); 770 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
1428 if ((temp & RS690_MC_GART_CLEAR_STATUS) == 771 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
1429 RS690_MC_GART_CLEAR_DONE)
1430 break; 772 break;
1431 DRM_UDELAY(1); 773 DRM_UDELAY(1);
1432 } while (1); 774 } while (1);
1433 775
1434 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, 776 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
1435 RS690_MC_GART_CC_NO_CHANGE);
1436 } else { 777 } else {
1437 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS); 778 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
1438 } 779 }
1439} 780}
1440 781
@@ -1472,12 +813,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1472{ 813{
1473 u32 tmp; 814 u32 tmp;
1474 815
1475 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { 816 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1476 radeon_set_rs690gart(dev_priv, on); 817 (dev_priv->flags & RADEON_IS_IGPGART)) {
1477 return;
1478 }
1479
1480 if (dev_priv->flags & RADEON_IS_IGPGART) {
1481 radeon_set_igpgart(dev_priv, on); 818 radeon_set_igpgart(dev_priv, on);
1482 return; 819 return;
1483 } 820 }
@@ -1951,6 +1288,7 @@ static int radeon_do_resume_cp(struct drm_device * dev)
1951 radeon_cp_init_ring_buffer(dev, dev_priv); 1288 radeon_cp_init_ring_buffer(dev, dev_priv);
1952 1289
1953 radeon_do_engine_reset(dev); 1290 radeon_do_engine_reset(dev);
1291 radeon_enable_interrupt(dev);
1954 1292
1955 DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1293 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1956 1294
diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h
index aab82e121e07..73ff51f12311 100644
--- a/drivers/char/drm/radeon_drm.h
+++ b/drivers/char/drm/radeon_drm.h
@@ -240,6 +240,7 @@ typedef union {
240# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 240# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
241 241
242#define R300_CMD_SCRATCH 8 242#define R300_CMD_SCRATCH 8
243#define R300_CMD_R500FP 9
243 244
244typedef union { 245typedef union {
245 unsigned int u; 246 unsigned int u;
@@ -268,6 +269,9 @@ typedef union {
268 struct { 269 struct {
269 unsigned char cmd_type, reg, n_bufs, flags; 270 unsigned char cmd_type, reg, n_bufs, flags;
270 } scratch; 271 } scratch;
272 struct {
273 unsigned char cmd_type, count, adrlo, adrhi_flags;
274 } r500fp;
271} drm_r300_cmd_header_t; 275} drm_r300_cmd_header_t;
272 276
273#define RADEON_FRONT 0x1 277#define RADEON_FRONT 0x1
@@ -278,6 +282,9 @@ typedef union {
278#define RADEON_USE_HIERZ 0x40000000 282#define RADEON_USE_HIERZ 0x40000000
279#define RADEON_USE_COMP_ZBUF 0x20000000 283#define RADEON_USE_COMP_ZBUF 0x20000000
280 284
285#define R500FP_CONSTANT_TYPE (1 << 1)
286#define R500FP_CONSTANT_CLAMP (1 << 2)
287
281/* Primitive types 288/* Primitive types
282 */ 289 */
283#define RADEON_POINTS 0x1 290#define RADEON_POINTS 0x1
@@ -669,6 +676,7 @@ typedef struct drm_radeon_indirect {
669#define RADEON_PARAM_CARD_TYPE 12 676#define RADEON_PARAM_CARD_TYPE 12
670#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ 677#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
671#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ 678#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
679#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
672 680
673typedef struct drm_radeon_getparam { 681typedef struct drm_radeon_getparam {
674 int param; 682 int param;
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 173ae620223a..3f0eca957aa7 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -38,7 +38,7 @@
38 38
39#define DRIVER_NAME "radeon" 39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon" 40#define DRIVER_DESC "ATI Radeon"
41#define DRIVER_DATE "20060524" 41#define DRIVER_DATE "20080528"
42 42
43/* Interface history: 43/* Interface history:
44 * 44 *
@@ -98,9 +98,10 @@
98 * 1.26- Add support for variable size PCI(E) gart aperture 98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART 99 * 1.27- Add support for IGP GART
100 * 1.28- Add support for VBL on CRTC2 100 * 1.28- Add support for VBL on CRTC2
101 * 1.29- R500 3D cmd buffer support
101 */ 102 */
102#define DRIVER_MAJOR 1 103#define DRIVER_MAJOR 1
103#define DRIVER_MINOR 28 104#define DRIVER_MINOR 29
104#define DRIVER_PATCHLEVEL 0 105#define DRIVER_PATCHLEVEL 0
105 106
106/* 107/*
@@ -122,7 +123,7 @@ enum radeon_family {
122 CHIP_RV380, 123 CHIP_RV380,
123 CHIP_R420, 124 CHIP_R420,
124 CHIP_RV410, 125 CHIP_RV410,
125 CHIP_RS400, 126 CHIP_RS480,
126 CHIP_RS690, 127 CHIP_RS690,
127 CHIP_RV515, 128 CHIP_RV515,
128 CHIP_R520, 129 CHIP_R520,
@@ -294,6 +295,7 @@ typedef struct drm_radeon_private {
294 int vblank_crtc; 295 int vblank_crtc;
295 uint32_t irq_enable_reg; 296 uint32_t irq_enable_reg;
296 int irq_enabled; 297 int irq_enabled;
298 uint32_t r500_disp_irq_reg;
297 299
298 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 300 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
299 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 301 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
@@ -307,6 +309,8 @@ typedef struct drm_radeon_private {
307 /* starting from here on, data is preserved accross an open */ 309 /* starting from here on, data is preserved accross an open */
308 uint32_t flags; /* see radeon_chip_flags */ 310 uint32_t flags; /* see radeon_chip_flags */
309 unsigned long fb_aper_offset; 311 unsigned long fb_aper_offset;
312
313 int num_gb_pipes;
310} drm_radeon_private_t; 314} drm_radeon_private_t;
311 315
312typedef struct drm_radeon_buf_priv { 316typedef struct drm_radeon_buf_priv {
@@ -382,6 +386,7 @@ extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
382extern void radeon_driver_irq_preinstall(struct drm_device * dev); 386extern void radeon_driver_irq_preinstall(struct drm_device * dev);
383extern void radeon_driver_irq_postinstall(struct drm_device * dev); 387extern void radeon_driver_irq_postinstall(struct drm_device * dev);
384extern void radeon_driver_irq_uninstall(struct drm_device * dev); 388extern void radeon_driver_irq_uninstall(struct drm_device * dev);
389extern void radeon_enable_interrupt(struct drm_device *dev);
385extern int radeon_vblank_crtc_get(struct drm_device *dev); 390extern int radeon_vblank_crtc_get(struct drm_device *dev);
386extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 391extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
387 392
@@ -444,13 +449,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
444#define RADEON_PCIE_DATA 0x0034 449#define RADEON_PCIE_DATA 0x0034
445#define RADEON_PCIE_TX_GART_CNTL 0x10 450#define RADEON_PCIE_TX_GART_CNTL 0x10
446# define RADEON_PCIE_TX_GART_EN (1 << 0) 451# define RADEON_PCIE_TX_GART_EN (1 << 0)
447# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) 452# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
448# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) 453# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
449# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) 454# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
450# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3) 455# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
451# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3) 456# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
452# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5) 457# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
453# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) 458# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
454#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 459#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
455#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 460#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
456#define RADEON_PCIE_TX_GART_BASE 0x13 461#define RADEON_PCIE_TX_GART_BASE 0x13
@@ -459,14 +464,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
459#define RADEON_PCIE_TX_GART_END_LO 0x16 464#define RADEON_PCIE_TX_GART_END_LO 0x16
460#define RADEON_PCIE_TX_GART_END_HI 0x17 465#define RADEON_PCIE_TX_GART_END_HI 0x17
461 466
462#define RADEON_IGPGART_INDEX 0x168 467#define RS480_NB_MC_INDEX 0x168
463#define RADEON_IGPGART_DATA 0x16c 468# define RS480_NB_MC_IND_WR_EN (1 << 8)
464#define RADEON_IGPGART_UNK_18 0x18 469#define RS480_NB_MC_DATA 0x16c
465#define RADEON_IGPGART_CTRL 0x2b
466#define RADEON_IGPGART_BASE_ADDR 0x2c
467#define RADEON_IGPGART_FLUSH 0x2e
468#define RADEON_IGPGART_ENABLE 0x38
469#define RADEON_IGPGART_UNK_39 0x39
470 470
471#define RS690_MC_INDEX 0x78 471#define RS690_MC_INDEX 0x78
472# define RS690_MC_INDEX_MASK 0x1ff 472# define RS690_MC_INDEX_MASK 0x1ff
@@ -474,45 +474,91 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
474# define RS690_MC_INDEX_WR_ACK 0x7f 474# define RS690_MC_INDEX_WR_ACK 0x7f
475#define RS690_MC_DATA 0x7c 475#define RS690_MC_DATA 0x7c
476 476
477#define RS690_MC_MISC_CNTL 0x18 477/* MC indirect registers */
478#define RS690_MC_GART_FEATURE_ID 0x2b 478#define RS480_MC_MISC_CNTL 0x18
479#define RS690_MC_GART_BASE 0x2c 479# define RS480_DISABLE_GTW (1 << 1)
480#define RS690_MC_GART_CACHE_CNTL 0x2e 480/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
481# define RS690_MC_GART_CC_NO_CHANGE 0x0 481# define RS480_GART_INDEX_REG_EN (1 << 12)
482# define RS690_MC_GART_CC_CLEAR 0x1 482# define RS690_BLOCK_GFX_D3_EN (1 << 14)
483# define RS690_MC_GART_CLEAR_STATUS (1 << 1) 483#define RS480_K8_FB_LOCATION 0x1e
484# define RS690_MC_GART_CLEAR_DONE (0 << 1) 484#define RS480_GART_FEATURE_ID 0x2b
485# define RS690_MC_GART_CLEAR_PENDING (1 << 1) 485# define RS480_HANG_EN (1 << 11)
486#define RS690_MC_AGP_SIZE 0x38 486# define RS480_TLB_ENABLE (1 << 18)
487# define RS690_MC_GART_DIS 0x0 487# define RS480_P2P_ENABLE (1 << 19)
488# define RS690_MC_GART_EN 0x1 488# define RS480_GTW_LAC_EN (1 << 25)
489# define RS690_MC_AGP_SIZE_32MB (0 << 1) 489# define RS480_2LEVEL_GART (0 << 30)
490# define RS690_MC_AGP_SIZE_64MB (1 << 1) 490# define RS480_1LEVEL_GART (1 << 30)
491# define RS690_MC_AGP_SIZE_128MB (2 << 1) 491# define RS480_PDC_EN (1 << 31)
492# define RS690_MC_AGP_SIZE_256MB (3 << 1) 492#define RS480_GART_BASE 0x2c
493# define RS690_MC_AGP_SIZE_512MB (4 << 1) 493#define RS480_GART_CACHE_CNTRL 0x2e
494# define RS690_MC_AGP_SIZE_1GB (5 << 1) 494# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
495# define RS690_MC_AGP_SIZE_2GB (6 << 1) 495#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
496#define RS690_MC_AGP_MODE_CONTROL 0x39 496# define RS480_GART_EN (1 << 0)
497# define RS480_VA_SIZE_32MB (0 << 1)
498# define RS480_VA_SIZE_64MB (1 << 1)
499# define RS480_VA_SIZE_128MB (2 << 1)
500# define RS480_VA_SIZE_256MB (3 << 1)
501# define RS480_VA_SIZE_512MB (4 << 1)
502# define RS480_VA_SIZE_1GB (5 << 1)
503# define RS480_VA_SIZE_2GB (6 << 1)
504#define RS480_AGP_MODE_CNTL 0x39
505# define RS480_POST_GART_Q_SIZE (1 << 18)
506# define RS480_NONGART_SNOOP (1 << 19)
507# define RS480_AGP_RD_BUF_SIZE (1 << 20)
508# define RS480_REQ_TYPE_SNOOP_SHIFT 22
509# define RS480_REQ_TYPE_SNOOP_MASK 0x3
510# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
511#define RS480_MC_MISC_UMA_CNTL 0x5f
512#define RS480_MC_MCLK_CNTL 0x7a
513#define RS480_MC_UMA_DUALCH_CNTL 0x86
514
497#define RS690_MC_FB_LOCATION 0x100 515#define RS690_MC_FB_LOCATION 0x100
498#define RS690_MC_AGP_LOCATION 0x101 516#define RS690_MC_AGP_LOCATION 0x101
499#define RS690_MC_AGP_BASE 0x102 517#define RS690_MC_AGP_BASE 0x102
518#define RS690_MC_AGP_BASE_2 0x103
500 519
501#define R520_MC_IND_INDEX 0x70 520#define R520_MC_IND_INDEX 0x70
502#define R520_MC_IND_WR_EN (1<<24) 521#define R520_MC_IND_WR_EN (1 << 24)
503#define R520_MC_IND_DATA 0x74 522#define R520_MC_IND_DATA 0x74
504 523
505#define RV515_MC_FB_LOCATION 0x01 524#define RV515_MC_FB_LOCATION 0x01
506#define RV515_MC_AGP_LOCATION 0x02 525#define RV515_MC_AGP_LOCATION 0x02
526#define RV515_MC_AGP_BASE 0x03
527#define RV515_MC_AGP_BASE_2 0x04
507 528
508#define R520_MC_FB_LOCATION 0x04 529#define R520_MC_FB_LOCATION 0x04
509#define R520_MC_AGP_LOCATION 0x05 530#define R520_MC_AGP_LOCATION 0x05
531#define R520_MC_AGP_BASE 0x06
532#define R520_MC_AGP_BASE_2 0x07
510 533
511#define RADEON_MPP_TB_CONFIG 0x01c0 534#define RADEON_MPP_TB_CONFIG 0x01c0
512#define RADEON_MEM_CNTL 0x0140 535#define RADEON_MEM_CNTL 0x0140
513#define RADEON_MEM_SDRAM_MODE_REG 0x0158 536#define RADEON_MEM_SDRAM_MODE_REG 0x0158
537#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
538#define RS480_AGP_BASE_2 0x0164
514#define RADEON_AGP_BASE 0x0170 539#define RADEON_AGP_BASE 0x0170
515 540
541/* pipe config regs */
542#define R400_GB_PIPE_SELECT 0x402c
543#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
544#define R500_SU_REG_DEST 0x42c8
545#define R300_GB_TILE_CONFIG 0x4018
546# define R300_ENABLE_TILING (1 << 0)
547# define R300_PIPE_COUNT_RV350 (0 << 1)
548# define R300_PIPE_COUNT_R300 (3 << 1)
549# define R300_PIPE_COUNT_R420_3P (6 << 1)
550# define R300_PIPE_COUNT_R420 (7 << 1)
551# define R300_TILE_SIZE_8 (0 << 4)
552# define R300_TILE_SIZE_16 (1 << 4)
553# define R300_TILE_SIZE_32 (2 << 4)
554# define R300_SUBPIXEL_1_12 (0 << 16)
555# define R300_SUBPIXEL_1_16 (1 << 16)
556#define R300_DST_PIPE_CONFIG 0x170c
557# define R300_PIPE_AUTO_CONFIG (1 << 31)
558#define R300_RB2D_DSTCACHE_MODE 0x3428
559# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
560# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
561
516#define RADEON_RB3D_COLOROFFSET 0x1c40 562#define RADEON_RB3D_COLOROFFSET 0x1c40
517#define RADEON_RB3D_COLORPITCH 0x1c48 563#define RADEON_RB3D_COLORPITCH 0x1c48
518 564
@@ -616,11 +662,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
616#define RADEON_PP_TXFILTER_1 0x1c6c 662#define RADEON_PP_TXFILTER_1 0x1c6c
617#define RADEON_PP_TXFILTER_2 0x1c84 663#define RADEON_PP_TXFILTER_2 0x1c84
618 664
619#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 665#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
620# define RADEON_RB2D_DC_FLUSH (3 << 0) 666#define R300_DSTCACHE_CTLSTAT 0x1714
621# define RADEON_RB2D_DC_FREE (3 << 2) 667# define R300_RB2D_DC_FLUSH (3 << 0)
622# define RADEON_RB2D_DC_FLUSH_ALL 0xf 668# define R300_RB2D_DC_FREE (3 << 2)
623# define RADEON_RB2D_DC_BUSY (1 << 31) 669# define R300_RB2D_DC_FLUSH_ALL 0xf
670# define R300_RB2D_DC_BUSY (1 << 31)
624#define RADEON_RB3D_CNTL 0x1c3c 671#define RADEON_RB3D_CNTL 0x1c3c
625# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 672# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
626# define RADEON_PLANE_MASK_ENABLE (1 << 1) 673# define RADEON_PLANE_MASK_ENABLE (1 << 1)
@@ -643,11 +690,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
643# define RADEON_RB3D_ZC_FREE (1 << 2) 690# define RADEON_RB3D_ZC_FREE (1 << 2)
644# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 691# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
645# define RADEON_RB3D_ZC_BUSY (1 << 31) 692# define RADEON_RB3D_ZC_BUSY (1 << 31)
693#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
694# define R300_ZC_FLUSH (1 << 0)
695# define R300_ZC_FREE (1 << 1)
696# define R300_ZC_FLUSH_ALL 0x3
697# define R300_ZC_BUSY (1 << 31)
646#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 698#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
647# define RADEON_RB3D_DC_FLUSH (3 << 0) 699# define RADEON_RB3D_DC_FLUSH (3 << 0)
648# define RADEON_RB3D_DC_FREE (3 << 2) 700# define RADEON_RB3D_DC_FREE (3 << 2)
649# define RADEON_RB3D_DC_FLUSH_ALL 0xf 701# define RADEON_RB3D_DC_FLUSH_ALL 0xf
650# define RADEON_RB3D_DC_BUSY (1 << 31) 702# define RADEON_RB3D_DC_BUSY (1 << 31)
703#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
704# define R300_RB3D_DC_FINISH (1 << 4)
651#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 705#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
652# define RADEON_Z_TEST_MASK (7 << 4) 706# define RADEON_Z_TEST_MASK (7 << 4)
653# define RADEON_Z_TEST_ALWAYS (7 << 4) 707# define RADEON_Z_TEST_ALWAYS (7 << 4)
@@ -1057,6 +1111,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
1057 1111
1058#define R200_VAP_PVS_CNTL_1 0x22D0 1112#define R200_VAP_PVS_CNTL_1 0x22D0
1059 1113
1114#define R500_D1CRTC_STATUS 0x609c
1115#define R500_D2CRTC_STATUS 0x689c
1116#define R500_CRTC_V_BLANK (1<<0)
1117
1118#define R500_D1CRTC_FRAME_COUNT 0x60a4
1119#define R500_D2CRTC_FRAME_COUNT 0x68a4
1120
1121#define R500_D1MODE_V_COUNTER 0x6530
1122#define R500_D2MODE_V_COUNTER 0x6d30
1123
1124#define R500_D1MODE_VBLANK_STATUS 0x6534
1125#define R500_D2MODE_VBLANK_STATUS 0x6d34
1126#define R500_VBLANK_OCCURED (1<<0)
1127#define R500_VBLANK_ACK (1<<4)
1128#define R500_VBLANK_STAT (1<<12)
1129#define R500_VBLANK_INT (1<<16)
1130
1131#define R500_DxMODE_INT_MASK 0x6540
1132#define R500_D1MODE_INT_MASK (1<<0)
1133#define R500_D2MODE_INT_MASK (1<<8)
1134
1135#define R500_DISP_INTERRUPT_STATUS 0x7edc
1136#define R500_D1_VBLANK_INTERRUPT (1 << 4)
1137#define R500_D2_VBLANK_INTERRUPT (1 << 5)
1138
1060/* Constants */ 1139/* Constants */
1061#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1140#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1062 1141
@@ -1078,42 +1157,50 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
1078#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1157#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1079#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1158#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1080 1159
1081#define RADEON_WRITE_PLL( addr, val ) \ 1160#define RADEON_WRITE_PLL(addr, val) \
1082do { \ 1161do { \
1083 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 1162 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1084 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1163 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1085 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 1164 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1086} while (0) 1165} while (0)
1087 1166
1088#define RADEON_WRITE_IGPGART( addr, val ) \ 1167#define RADEON_WRITE_PCIE(addr, val) \
1089do { \ 1168do { \
1090 RADEON_WRITE( RADEON_IGPGART_INDEX, \ 1169 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1091 ((addr) & 0x7f) | (1 << 8)); \ 1170 ((addr) & 0xff)); \
1092 RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \ 1171 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1093 RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
1094} while (0) 1172} while (0)
1095 1173
1096#define RADEON_WRITE_PCIE( addr, val ) \ 1174#define R500_WRITE_MCIND(addr, val) \
1097do { \ 1175do { \
1098 RADEON_WRITE8( RADEON_PCIE_INDEX, \ 1176 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1099 ((addr) & 0xff)); \ 1177 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1100 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 1178 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1101} while (0) 1179} while (0)
1102 1180
1103#define RADEON_WRITE_MCIND( addr, val ) \ 1181#define RS480_WRITE_MCIND(addr, val) \
1104 do { \ 1182do { \
1105 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1183 RADEON_WRITE(RS480_NB_MC_INDEX, \
1106 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1184 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1107 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1185 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1108 } while (0) 1186 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1187} while (0)
1109 1188
1110#define RS690_WRITE_MCIND( addr, val ) \ 1189#define RS690_WRITE_MCIND(addr, val) \
1111do { \ 1190do { \
1112 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1191 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1113 RADEON_WRITE(RS690_MC_DATA, val); \ 1192 RADEON_WRITE(RS690_MC_DATA, val); \
1114 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1193 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1115} while (0) 1194} while (0)
1116 1195
1196#define IGP_WRITE_MCIND(addr, val) \
1197do { \
1198 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
1199 RS690_WRITE_MCIND(addr, val); \
1200 else \
1201 RS480_WRITE_MCIND(addr, val); \
1202} while (0)
1203
1117#define CP_PACKET0( reg, n ) \ 1204#define CP_PACKET0( reg, n ) \
1118 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1205 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1119#define CP_PACKET0_TABLE( reg, n ) \ 1206#define CP_PACKET0_TABLE( reg, n ) \
@@ -1154,23 +1241,43 @@ do { \
1154} while (0) 1241} while (0)
1155 1242
1156#define RADEON_FLUSH_CACHE() do { \ 1243#define RADEON_FLUSH_CACHE() do { \
1157 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ 1244 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1158 OUT_RING( RADEON_RB3D_DC_FLUSH ); \ 1245 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1246 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1247 } else { \
1248 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1249 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1250 } \
1159} while (0) 1251} while (0)
1160 1252
1161#define RADEON_PURGE_CACHE() do { \ 1253#define RADEON_PURGE_CACHE() do { \
1162 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ 1254 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1163 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \ 1255 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1256 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1257 } else { \
1258 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1259 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1260 } \
1164} while (0) 1261} while (0)
1165 1262
1166#define RADEON_FLUSH_ZCACHE() do { \ 1263#define RADEON_FLUSH_ZCACHE() do { \
1167 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1264 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1168 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 1265 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1266 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1267 } else { \
1268 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1269 OUT_RING(R300_ZC_FLUSH); \
1270 } \
1169} while (0) 1271} while (0)
1170 1272
1171#define RADEON_PURGE_ZCACHE() do { \ 1273#define RADEON_PURGE_ZCACHE() do { \
1172 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1274 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1173 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 1275 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1276 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
1277 } else { \
1278 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1279 OUT_RING(R300_ZC_FLUSH_ALL); \
1280 } \
1174} while (0) 1281} while (0)
1175 1282
1176/* ================================================================ 1283/* ================================================================
diff --git a/drivers/char/drm/radeon_irq.c b/drivers/char/drm/radeon_irq.c
index 009af3814b6f..ee40d197deb7 100644
--- a/drivers/char/drm/radeon_irq.c
+++ b/drivers/char/drm/radeon_irq.c
@@ -234,7 +234,7 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr
234 return radeon_wait_irq(dev, irqwait->irq_seq); 234 return radeon_wait_irq(dev, irqwait->irq_seq);
235} 235}
236 236
237static void radeon_enable_interrupt(struct drm_device *dev) 237void radeon_enable_interrupt(struct drm_device *dev)
238{ 238{
239 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; 239 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
240 240
diff --git a/drivers/char/drm/radeon_microcode.h b/drivers/char/drm/radeon_microcode.h
new file mode 100644
index 000000000000..a348c9e7db1c
--- /dev/null
+++ b/drivers/char/drm/radeon_microcode.h
@@ -0,0 +1,1844 @@
1/*
2 * Copyright 2007 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
20 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#ifndef RADEON_MICROCODE_H
27#define RADEON_MICROCODE_H
28
29/* production radeon ucode r1xx-r6xx */
30static const u32 R100_cp_microcode[][2] = {
31 { 0x21007000, 0000000000 },
32 { 0x20007000, 0000000000 },
33 { 0x000000b4, 0x00000004 },
34 { 0x000000b8, 0x00000004 },
35 { 0x6f5b4d4c, 0000000000 },
36 { 0x4c4c427f, 0000000000 },
37 { 0x5b568a92, 0000000000 },
38 { 0x4ca09c6d, 0000000000 },
39 { 0xad4c4c4c, 0000000000 },
40 { 0x4ce1af3d, 0000000000 },
41 { 0xd8afafaf, 0000000000 },
42 { 0xd64c4cdc, 0000000000 },
43 { 0x4cd10d10, 0000000000 },
44 { 0x000f0000, 0x00000016 },
45 { 0x362f242d, 0000000000 },
46 { 0x00000012, 0x00000004 },
47 { 0x000f0000, 0x00000016 },
48 { 0x362f282d, 0000000000 },
49 { 0x000380e7, 0x00000002 },
50 { 0x04002c97, 0x00000002 },
51 { 0x000f0001, 0x00000016 },
52 { 0x333a3730, 0000000000 },
53 { 0x000077ef, 0x00000002 },
54 { 0x00061000, 0x00000002 },
55 { 0x00000021, 0x0000001a },
56 { 0x00004000, 0x0000001e },
57 { 0x00061000, 0x00000002 },
58 { 0x00000021, 0x0000001a },
59 { 0x00004000, 0x0000001e },
60 { 0x00061000, 0x00000002 },
61 { 0x00000021, 0x0000001a },
62 { 0x00004000, 0x0000001e },
63 { 0x00000017, 0x00000004 },
64 { 0x0003802b, 0x00000002 },
65 { 0x040067e0, 0x00000002 },
66 { 0x00000017, 0x00000004 },
67 { 0x000077e0, 0x00000002 },
68 { 0x00065000, 0x00000002 },
69 { 0x000037e1, 0x00000002 },
70 { 0x040067e1, 0x00000006 },
71 { 0x000077e0, 0x00000002 },
72 { 0x000077e1, 0x00000002 },
73 { 0x000077e1, 0x00000006 },
74 { 0xffffffff, 0000000000 },
75 { 0x10000000, 0000000000 },
76 { 0x0003802b, 0x00000002 },
77 { 0x040067e0, 0x00000006 },
78 { 0x00007675, 0x00000002 },
79 { 0x00007676, 0x00000002 },
80 { 0x00007677, 0x00000002 },
81 { 0x00007678, 0x00000006 },
82 { 0x0003802c, 0x00000002 },
83 { 0x04002676, 0x00000002 },
84 { 0x00007677, 0x00000002 },
85 { 0x00007678, 0x00000006 },
86 { 0x0000002f, 0x00000018 },
87 { 0x0000002f, 0x00000018 },
88 { 0000000000, 0x00000006 },
89 { 0x00000030, 0x00000018 },
90 { 0x00000030, 0x00000018 },
91 { 0000000000, 0x00000006 },
92 { 0x01605000, 0x00000002 },
93 { 0x00065000, 0x00000002 },
94 { 0x00098000, 0x00000002 },
95 { 0x00061000, 0x00000002 },
96 { 0x64c0603e, 0x00000004 },
97 { 0x000380e6, 0x00000002 },
98 { 0x040025c5, 0x00000002 },
99 { 0x00080000, 0x00000016 },
100 { 0000000000, 0000000000 },
101 { 0x0400251d, 0x00000002 },
102 { 0x00007580, 0x00000002 },
103 { 0x00067581, 0x00000002 },
104 { 0x04002580, 0x00000002 },
105 { 0x00067581, 0x00000002 },
106 { 0x00000049, 0x00000004 },
107 { 0x00005000, 0000000000 },
108 { 0x000380e6, 0x00000002 },
109 { 0x040025c5, 0x00000002 },
110 { 0x00061000, 0x00000002 },
111 { 0x0000750e, 0x00000002 },
112 { 0x00019000, 0x00000002 },
113 { 0x00011055, 0x00000014 },
114 { 0x00000055, 0x00000012 },
115 { 0x0400250f, 0x00000002 },
116 { 0x0000504f, 0x00000004 },
117 { 0x000380e6, 0x00000002 },
118 { 0x040025c5, 0x00000002 },
119 { 0x00007565, 0x00000002 },
120 { 0x00007566, 0x00000002 },
121 { 0x00000058, 0x00000004 },
122 { 0x000380e6, 0x00000002 },
123 { 0x040025c5, 0x00000002 },
124 { 0x01e655b4, 0x00000002 },
125 { 0x4401b0e4, 0x00000002 },
126 { 0x01c110e4, 0x00000002 },
127 { 0x26667066, 0x00000018 },
128 { 0x040c2565, 0x00000002 },
129 { 0x00000066, 0x00000018 },
130 { 0x04002564, 0x00000002 },
131 { 0x00007566, 0x00000002 },
132 { 0x0000005d, 0x00000004 },
133 { 0x00401069, 0x00000008 },
134 { 0x00101000, 0x00000002 },
135 { 0x000d80ff, 0x00000002 },
136 { 0x0080006c, 0x00000008 },
137 { 0x000f9000, 0x00000002 },
138 { 0x000e00ff, 0x00000002 },
139 { 0000000000, 0x00000006 },
140 { 0x0000008f, 0x00000018 },
141 { 0x0000005b, 0x00000004 },
142 { 0x000380e6, 0x00000002 },
143 { 0x040025c5, 0x00000002 },
144 { 0x00007576, 0x00000002 },
145 { 0x00065000, 0x00000002 },
146 { 0x00009000, 0x00000002 },
147 { 0x00041000, 0x00000002 },
148 { 0x0c00350e, 0x00000002 },
149 { 0x00049000, 0x00000002 },
150 { 0x00051000, 0x00000002 },
151 { 0x01e785f8, 0x00000002 },
152 { 0x00200000, 0x00000002 },
153 { 0x0060007e, 0x0000000c },
154 { 0x00007563, 0x00000002 },
155 { 0x006075f0, 0x00000021 },
156 { 0x20007073, 0x00000004 },
157 { 0x00005073, 0x00000004 },
158 { 0x000380e6, 0x00000002 },
159 { 0x040025c5, 0x00000002 },
160 { 0x00007576, 0x00000002 },
161 { 0x00007577, 0x00000002 },
162 { 0x0000750e, 0x00000002 },
163 { 0x0000750f, 0x00000002 },
164 { 0x00a05000, 0x00000002 },
165 { 0x00600083, 0x0000000c },
166 { 0x006075f0, 0x00000021 },
167 { 0x000075f8, 0x00000002 },
168 { 0x00000083, 0x00000004 },
169 { 0x000a750e, 0x00000002 },
170 { 0x000380e6, 0x00000002 },
171 { 0x040025c5, 0x00000002 },
172 { 0x0020750f, 0x00000002 },
173 { 0x00600086, 0x00000004 },
174 { 0x00007570, 0x00000002 },
175 { 0x00007571, 0x00000002 },
176 { 0x00007572, 0x00000006 },
177 { 0x000380e6, 0x00000002 },
178 { 0x040025c5, 0x00000002 },
179 { 0x00005000, 0x00000002 },
180 { 0x00a05000, 0x00000002 },
181 { 0x00007568, 0x00000002 },
182 { 0x00061000, 0x00000002 },
183 { 0x00000095, 0x0000000c },
184 { 0x00058000, 0x00000002 },
185 { 0x0c607562, 0x00000002 },
186 { 0x00000097, 0x00000004 },
187 { 0x000380e6, 0x00000002 },
188 { 0x040025c5, 0x00000002 },
189 { 0x00600096, 0x00000004 },
190 { 0x400070e5, 0000000000 },
191 { 0x000380e6, 0x00000002 },
192 { 0x040025c5, 0x00000002 },
193 { 0x000380e5, 0x00000002 },
194 { 0x000000a8, 0x0000001c },
195 { 0x000650aa, 0x00000018 },
196 { 0x040025bb, 0x00000002 },
197 { 0x000610ab, 0x00000018 },
198 { 0x040075bc, 0000000000 },
199 { 0x000075bb, 0x00000002 },
200 { 0x000075bc, 0000000000 },
201 { 0x00090000, 0x00000006 },
202 { 0x00090000, 0x00000002 },
203 { 0x000d8002, 0x00000006 },
204 { 0x00007832, 0x00000002 },
205 { 0x00005000, 0x00000002 },
206 { 0x000380e7, 0x00000002 },
207 { 0x04002c97, 0x00000002 },
208 { 0x00007820, 0x00000002 },
209 { 0x00007821, 0x00000002 },
210 { 0x00007800, 0000000000 },
211 { 0x01200000, 0x00000002 },
212 { 0x20077000, 0x00000002 },
213 { 0x01200000, 0x00000002 },
214 { 0x20007000, 0x00000002 },
215 { 0x00061000, 0x00000002 },
216 { 0x0120751b, 0x00000002 },
217 { 0x8040750a, 0x00000002 },
218 { 0x8040750b, 0x00000002 },
219 { 0x00110000, 0x00000002 },
220 { 0x000380e5, 0x00000002 },
221 { 0x000000c6, 0x0000001c },
222 { 0x000610ab, 0x00000018 },
223 { 0x844075bd, 0x00000002 },
224 { 0x000610aa, 0x00000018 },
225 { 0x840075bb, 0x00000002 },
226 { 0x000610ab, 0x00000018 },
227 { 0x844075bc, 0x00000002 },
228 { 0x000000c9, 0x00000004 },
229 { 0x804075bd, 0x00000002 },
230 { 0x800075bb, 0x00000002 },
231 { 0x804075bc, 0x00000002 },
232 { 0x00108000, 0x00000002 },
233 { 0x01400000, 0x00000002 },
234 { 0x006000cd, 0x0000000c },
235 { 0x20c07000, 0x00000020 },
236 { 0x000000cf, 0x00000012 },
237 { 0x00800000, 0x00000006 },
238 { 0x0080751d, 0x00000006 },
239 { 0000000000, 0000000000 },
240 { 0x0000775c, 0x00000002 },
241 { 0x00a05000, 0x00000002 },
242 { 0x00661000, 0x00000002 },
243 { 0x0460275d, 0x00000020 },
244 { 0x00004000, 0000000000 },
245 { 0x01e00830, 0x00000002 },
246 { 0x21007000, 0000000000 },
247 { 0x6464614d, 0000000000 },
248 { 0x69687420, 0000000000 },
249 { 0x00000073, 0000000000 },
250 { 0000000000, 0000000000 },
251 { 0x00005000, 0x00000002 },
252 { 0x000380d0, 0x00000002 },
253 { 0x040025e0, 0x00000002 },
254 { 0x000075e1, 0000000000 },
255 { 0x00000001, 0000000000 },
256 { 0x000380e0, 0x00000002 },
257 { 0x04002394, 0x00000002 },
258 { 0x00005000, 0000000000 },
259 { 0000000000, 0000000000 },
260 { 0000000000, 0000000000 },
261 { 0x00000008, 0000000000 },
262 { 0x00000004, 0000000000 },
263 { 0000000000, 0000000000 },
264 { 0000000000, 0000000000 },
265 { 0000000000, 0000000000 },
266 { 0000000000, 0000000000 },
267 { 0000000000, 0000000000 },
268 { 0000000000, 0000000000 },
269 { 0000000000, 0000000000 },
270 { 0000000000, 0000000000 },
271 { 0000000000, 0000000000 },
272 { 0000000000, 0000000000 },
273 { 0000000000, 0000000000 },
274 { 0000000000, 0000000000 },
275 { 0000000000, 0000000000 },
276 { 0000000000, 0000000000 },
277 { 0000000000, 0000000000 },
278 { 0000000000, 0000000000 },
279 { 0000000000, 0000000000 },
280 { 0000000000, 0000000000 },
281 { 0000000000, 0000000000 },
282 { 0000000000, 0000000000 },
283 { 0000000000, 0000000000 },
284 { 0000000000, 0000000000 },
285 { 0000000000, 0000000000 },
286 { 0000000000, 0000000000 },
287};
288
289static const u32 R200_cp_microcode[][2] = {
290 { 0x21007000, 0000000000 },
291 { 0x20007000, 0000000000 },
292 { 0x000000bf, 0x00000004 },
293 { 0x000000c3, 0x00000004 },
294 { 0x7a685e5d, 0000000000 },
295 { 0x5d5d5588, 0000000000 },
296 { 0x68659197, 0000000000 },
297 { 0x5da19f78, 0000000000 },
298 { 0x5d5d5d5d, 0000000000 },
299 { 0x5dee5d50, 0000000000 },
300 { 0xf2acacac, 0000000000 },
301 { 0xe75df9e9, 0000000000 },
302 { 0xb1dd0e11, 0000000000 },
303 { 0xe2afafaf, 0000000000 },
304 { 0x000f0000, 0x00000016 },
305 { 0x452f232d, 0000000000 },
306 { 0x00000013, 0x00000004 },
307 { 0x000f0000, 0x00000016 },
308 { 0x452f272d, 0000000000 },
309 { 0x000f0001, 0x00000016 },
310 { 0x3e4d4a37, 0000000000 },
311 { 0x000077ef, 0x00000002 },
312 { 0x00061000, 0x00000002 },
313 { 0x00000020, 0x0000001a },
314 { 0x00004000, 0x0000001e },
315 { 0x00061000, 0x00000002 },
316 { 0x00000020, 0x0000001a },
317 { 0x00004000, 0x0000001e },
318 { 0x00061000, 0x00000002 },
319 { 0x00000020, 0x0000001a },
320 { 0x00004000, 0x0000001e },
321 { 0x00000016, 0x00000004 },
322 { 0x0003802a, 0x00000002 },
323 { 0x040067e0, 0x00000002 },
324 { 0x00000016, 0x00000004 },
325 { 0x000077e0, 0x00000002 },
326 { 0x00065000, 0x00000002 },
327 { 0x000037e1, 0x00000002 },
328 { 0x040067e1, 0x00000006 },
329 { 0x000077e0, 0x00000002 },
330 { 0x000077e1, 0x00000002 },
331 { 0x000077e1, 0x00000006 },
332 { 0xffffffff, 0000000000 },
333 { 0x10000000, 0000000000 },
334 { 0x07f007f0, 0000000000 },
335 { 0x0003802a, 0x00000002 },
336 { 0x040067e0, 0x00000006 },
337 { 0x0003802c, 0x00000002 },
338 { 0x04002741, 0x00000002 },
339 { 0x04002741, 0x00000002 },
340 { 0x04002743, 0x00000002 },
341 { 0x00007675, 0x00000002 },
342 { 0x00007676, 0x00000002 },
343 { 0x00007677, 0x00000002 },
344 { 0x00007678, 0x00000006 },
345 { 0x0003802c, 0x00000002 },
346 { 0x04002741, 0x00000002 },
347 { 0x04002741, 0x00000002 },
348 { 0x04002743, 0x00000002 },
349 { 0x00007676, 0x00000002 },
350 { 0x00007677, 0x00000002 },
351 { 0x00007678, 0x00000006 },
352 { 0x0003802b, 0x00000002 },
353 { 0x04002676, 0x00000002 },
354 { 0x00007677, 0x00000002 },
355 { 0x0003802c, 0x00000002 },
356 { 0x04002741, 0x00000002 },
357 { 0x04002743, 0x00000002 },
358 { 0x00007678, 0x00000006 },
359 { 0x0003802c, 0x00000002 },
360 { 0x04002741, 0x00000002 },
361 { 0x04002741, 0x00000002 },
362 { 0x04002743, 0x00000002 },
363 { 0x00007678, 0x00000006 },
364 { 0x0000002f, 0x00000018 },
365 { 0x0000002f, 0x00000018 },
366 { 0000000000, 0x00000006 },
367 { 0x00000037, 0x00000018 },
368 { 0x00000037, 0x00000018 },
369 { 0000000000, 0x00000006 },
370 { 0x01605000, 0x00000002 },
371 { 0x00065000, 0x00000002 },
372 { 0x00098000, 0x00000002 },
373 { 0x00061000, 0x00000002 },
374 { 0x64c06051, 0x00000004 },
375 { 0x00080000, 0x00000016 },
376 { 0000000000, 0000000000 },
377 { 0x0400251d, 0x00000002 },
378 { 0x00007580, 0x00000002 },
379 { 0x00067581, 0x00000002 },
380 { 0x04002580, 0x00000002 },
381 { 0x00067581, 0x00000002 },
382 { 0x0000005a, 0x00000004 },
383 { 0x00005000, 0000000000 },
384 { 0x00061000, 0x00000002 },
385 { 0x0000750e, 0x00000002 },
386 { 0x00019000, 0x00000002 },
387 { 0x00011064, 0x00000014 },
388 { 0x00000064, 0x00000012 },
389 { 0x0400250f, 0x00000002 },
390 { 0x0000505e, 0x00000004 },
391 { 0x00007565, 0x00000002 },
392 { 0x00007566, 0x00000002 },
393 { 0x00000065, 0x00000004 },
394 { 0x01e655b4, 0x00000002 },
395 { 0x4401b0f0, 0x00000002 },
396 { 0x01c110f0, 0x00000002 },
397 { 0x26667071, 0x00000018 },
398 { 0x040c2565, 0x00000002 },
399 { 0x00000071, 0x00000018 },
400 { 0x04002564, 0x00000002 },
401 { 0x00007566, 0x00000002 },
402 { 0x00000068, 0x00000004 },
403 { 0x00401074, 0x00000008 },
404 { 0x00101000, 0x00000002 },
405 { 0x000d80ff, 0x00000002 },
406 { 0x00800077, 0x00000008 },
407 { 0x000f9000, 0x00000002 },
408 { 0x000e00ff, 0x00000002 },
409 { 0000000000, 0x00000006 },
410 { 0x00000094, 0x00000018 },
411 { 0x00000068, 0x00000004 },
412 { 0x00007576, 0x00000002 },
413 { 0x00065000, 0x00000002 },
414 { 0x00009000, 0x00000002 },
415 { 0x00041000, 0x00000002 },
416 { 0x0c00350e, 0x00000002 },
417 { 0x00049000, 0x00000002 },
418 { 0x00051000, 0x00000002 },
419 { 0x01e785f8, 0x00000002 },
420 { 0x00200000, 0x00000002 },
421 { 0x00600087, 0x0000000c },
422 { 0x00007563, 0x00000002 },
423 { 0x006075f0, 0x00000021 },
424 { 0x2000707c, 0x00000004 },
425 { 0x0000507c, 0x00000004 },
426 { 0x00007576, 0x00000002 },
427 { 0x00007577, 0x00000002 },
428 { 0x0000750e, 0x00000002 },
429 { 0x0000750f, 0x00000002 },
430 { 0x00a05000, 0x00000002 },
431 { 0x0060008a, 0x0000000c },
432 { 0x006075f0, 0x00000021 },
433 { 0x000075f8, 0x00000002 },
434 { 0x0000008a, 0x00000004 },
435 { 0x000a750e, 0x00000002 },
436 { 0x0020750f, 0x00000002 },
437 { 0x0060008d, 0x00000004 },
438 { 0x00007570, 0x00000002 },
439 { 0x00007571, 0x00000002 },
440 { 0x00007572, 0x00000006 },
441 { 0x00005000, 0x00000002 },
442 { 0x00a05000, 0x00000002 },
443 { 0x00007568, 0x00000002 },
444 { 0x00061000, 0x00000002 },
445 { 0x00000098, 0x0000000c },
446 { 0x00058000, 0x00000002 },
447 { 0x0c607562, 0x00000002 },
448 { 0x0000009a, 0x00000004 },
449 { 0x00600099, 0x00000004 },
450 { 0x400070f1, 0000000000 },
451 { 0x000380f1, 0x00000002 },
452 { 0x000000a7, 0x0000001c },
453 { 0x000650a9, 0x00000018 },
454 { 0x040025bb, 0x00000002 },
455 { 0x000610aa, 0x00000018 },
456 { 0x040075bc, 0000000000 },
457 { 0x000075bb, 0x00000002 },
458 { 0x000075bc, 0000000000 },
459 { 0x00090000, 0x00000006 },
460 { 0x00090000, 0x00000002 },
461 { 0x000d8002, 0x00000006 },
462 { 0x00005000, 0x00000002 },
463 { 0x00007821, 0x00000002 },
464 { 0x00007800, 0000000000 },
465 { 0x00007821, 0x00000002 },
466 { 0x00007800, 0000000000 },
467 { 0x01665000, 0x00000002 },
468 { 0x000a0000, 0x00000002 },
469 { 0x000671cc, 0x00000002 },
470 { 0x0286f1cd, 0x00000002 },
471 { 0x000000b7, 0x00000010 },
472 { 0x21007000, 0000000000 },
473 { 0x000000be, 0x0000001c },
474 { 0x00065000, 0x00000002 },
475 { 0x000a0000, 0x00000002 },
476 { 0x00061000, 0x00000002 },
477 { 0x000b0000, 0x00000002 },
478 { 0x38067000, 0x00000002 },
479 { 0x000a00ba, 0x00000004 },
480 { 0x20007000, 0000000000 },
481 { 0x01200000, 0x00000002 },
482 { 0x20077000, 0x00000002 },
483 { 0x01200000, 0x00000002 },
484 { 0x20007000, 0000000000 },
485 { 0x00061000, 0x00000002 },
486 { 0x0120751b, 0x00000002 },
487 { 0x8040750a, 0x00000002 },
488 { 0x8040750b, 0x00000002 },
489 { 0x00110000, 0x00000002 },
490 { 0x000380f1, 0x00000002 },
491 { 0x000000d1, 0x0000001c },
492 { 0x000610aa, 0x00000018 },
493 { 0x844075bd, 0x00000002 },
494 { 0x000610a9, 0x00000018 },
495 { 0x840075bb, 0x00000002 },
496 { 0x000610aa, 0x00000018 },
497 { 0x844075bc, 0x00000002 },
498 { 0x000000d4, 0x00000004 },
499 { 0x804075bd, 0x00000002 },
500 { 0x800075bb, 0x00000002 },
501 { 0x804075bc, 0x00000002 },
502 { 0x00108000, 0x00000002 },
503 { 0x01400000, 0x00000002 },
504 { 0x006000d8, 0x0000000c },
505 { 0x20c07000, 0x00000020 },
506 { 0x000000da, 0x00000012 },
507 { 0x00800000, 0x00000006 },
508 { 0x0080751d, 0x00000006 },
509 { 0x000025bb, 0x00000002 },
510 { 0x000040d4, 0x00000004 },
511 { 0x0000775c, 0x00000002 },
512 { 0x00a05000, 0x00000002 },
513 { 0x00661000, 0x00000002 },
514 { 0x0460275d, 0x00000020 },
515 { 0x00004000, 0000000000 },
516 { 0x00007999, 0x00000002 },
517 { 0x00a05000, 0x00000002 },
518 { 0x00661000, 0x00000002 },
519 { 0x0460299b, 0x00000020 },
520 { 0x00004000, 0000000000 },
521 { 0x01e00830, 0x00000002 },
522 { 0x21007000, 0000000000 },
523 { 0x00005000, 0x00000002 },
524 { 0x00038056, 0x00000002 },
525 { 0x040025e0, 0x00000002 },
526 { 0x000075e1, 0000000000 },
527 { 0x00000001, 0000000000 },
528 { 0x000380ed, 0x00000002 },
529 { 0x04007394, 0000000000 },
530 { 0000000000, 0000000000 },
531 { 0000000000, 0000000000 },
532 { 0x000078c4, 0x00000002 },
533 { 0x000078c5, 0x00000002 },
534 { 0x000078c6, 0x00000002 },
535 { 0x00007924, 0x00000002 },
536 { 0x00007925, 0x00000002 },
537 { 0x00007926, 0x00000002 },
538 { 0x000000f2, 0x00000004 },
539 { 0x00007924, 0x00000002 },
540 { 0x00007925, 0x00000002 },
541 { 0x00007926, 0x00000002 },
542 { 0x000000f9, 0x00000004 },
543 { 0000000000, 0000000000 },
544 { 0000000000, 0000000000 },
545 { 0000000000, 0000000000 },
546};
547
548static const u32 R300_cp_microcode[][2] = {
549 { 0x4200e000, 0000000000 },
550 { 0x4000e000, 0000000000 },
551 { 0x000000ae, 0x00000008 },
552 { 0x000000b2, 0x00000008 },
553 { 0x67554b4a, 0000000000 },
554 { 0x4a4a4475, 0000000000 },
555 { 0x55527d83, 0000000000 },
556 { 0x4a8c8b65, 0000000000 },
557 { 0x4aef4af6, 0000000000 },
558 { 0x4ae14a4a, 0000000000 },
559 { 0xe4979797, 0000000000 },
560 { 0xdb4aebdd, 0000000000 },
561 { 0x9ccc4a4a, 0000000000 },
562 { 0xd1989898, 0000000000 },
563 { 0x4a0f9ad6, 0000000000 },
564 { 0x000ca000, 0x00000004 },
565 { 0x000d0012, 0x00000038 },
566 { 0x0000e8b4, 0x00000004 },
567 { 0x000d0014, 0x00000038 },
568 { 0x0000e8b6, 0x00000004 },
569 { 0x000d0016, 0x00000038 },
570 { 0x0000e854, 0x00000004 },
571 { 0x000d0018, 0x00000038 },
572 { 0x0000e855, 0x00000004 },
573 { 0x000d001a, 0x00000038 },
574 { 0x0000e856, 0x00000004 },
575 { 0x000d001c, 0x00000038 },
576 { 0x0000e857, 0x00000004 },
577 { 0x000d001e, 0x00000038 },
578 { 0x0000e824, 0x00000004 },
579 { 0x000d0020, 0x00000038 },
580 { 0x0000e825, 0x00000004 },
581 { 0x000d0022, 0x00000038 },
582 { 0x0000e830, 0x00000004 },
583 { 0x000d0024, 0x00000038 },
584 { 0x0000f0c0, 0x00000004 },
585 { 0x000d0026, 0x00000038 },
586 { 0x0000f0c1, 0x00000004 },
587 { 0x000d0028, 0x00000038 },
588 { 0x0000f041, 0x00000004 },
589 { 0x000d002a, 0x00000038 },
590 { 0x0000f184, 0x00000004 },
591 { 0x000d002c, 0x00000038 },
592 { 0x0000f185, 0x00000004 },
593 { 0x000d002e, 0x00000038 },
594 { 0x0000f186, 0x00000004 },
595 { 0x000d0030, 0x00000038 },
596 { 0x0000f187, 0x00000004 },
597 { 0x000d0032, 0x00000038 },
598 { 0x0000f180, 0x00000004 },
599 { 0x000d0034, 0x00000038 },
600 { 0x0000f393, 0x00000004 },
601 { 0x000d0036, 0x00000038 },
602 { 0x0000f38a, 0x00000004 },
603 { 0x000d0038, 0x00000038 },
604 { 0x0000f38e, 0x00000004 },
605 { 0x0000e821, 0x00000004 },
606 { 0x0140a000, 0x00000004 },
607 { 0x00000043, 0x00000018 },
608 { 0x00cce800, 0x00000004 },
609 { 0x001b0001, 0x00000004 },
610 { 0x08004800, 0x00000004 },
611 { 0x001b0001, 0x00000004 },
612 { 0x08004800, 0x00000004 },
613 { 0x001b0001, 0x00000004 },
614 { 0x08004800, 0x00000004 },
615 { 0x0000003a, 0x00000008 },
616 { 0x0000a000, 0000000000 },
617 { 0x2000451d, 0x00000004 },
618 { 0x0000e580, 0x00000004 },
619 { 0x000ce581, 0x00000004 },
620 { 0x08004580, 0x00000004 },
621 { 0x000ce581, 0x00000004 },
622 { 0x00000047, 0x00000008 },
623 { 0x0000a000, 0000000000 },
624 { 0x000c2000, 0x00000004 },
625 { 0x0000e50e, 0x00000004 },
626 { 0x00032000, 0x00000004 },
627 { 0x00022051, 0x00000028 },
628 { 0x00000051, 0x00000024 },
629 { 0x0800450f, 0x00000004 },
630 { 0x0000a04b, 0x00000008 },
631 { 0x0000e565, 0x00000004 },
632 { 0x0000e566, 0x00000004 },
633 { 0x00000052, 0x00000008 },
634 { 0x03cca5b4, 0x00000004 },
635 { 0x05432000, 0x00000004 },
636 { 0x00022000, 0x00000004 },
637 { 0x4ccce05e, 0x00000030 },
638 { 0x08274565, 0x00000004 },
639 { 0x0000005e, 0x00000030 },
640 { 0x08004564, 0x00000004 },
641 { 0x0000e566, 0x00000004 },
642 { 0x00000055, 0x00000008 },
643 { 0x00802061, 0x00000010 },
644 { 0x00202000, 0x00000004 },
645 { 0x001b00ff, 0x00000004 },
646 { 0x01000064, 0x00000010 },
647 { 0x001f2000, 0x00000004 },
648 { 0x001c00ff, 0x00000004 },
649 { 0000000000, 0x0000000c },
650 { 0x00000080, 0x00000030 },
651 { 0x00000055, 0x00000008 },
652 { 0x0000e576, 0x00000004 },
653 { 0x000ca000, 0x00000004 },
654 { 0x00012000, 0x00000004 },
655 { 0x00082000, 0x00000004 },
656 { 0x1800650e, 0x00000004 },
657 { 0x00092000, 0x00000004 },
658 { 0x000a2000, 0x00000004 },
659 { 0x000f0000, 0x00000004 },
660 { 0x00400000, 0x00000004 },
661 { 0x00000074, 0x00000018 },
662 { 0x0000e563, 0x00000004 },
663 { 0x00c0e5f9, 0x000000c2 },
664 { 0x00000069, 0x00000008 },
665 { 0x0000a069, 0x00000008 },
666 { 0x0000e576, 0x00000004 },
667 { 0x0000e577, 0x00000004 },
668 { 0x0000e50e, 0x00000004 },
669 { 0x0000e50f, 0x00000004 },
670 { 0x0140a000, 0x00000004 },
671 { 0x00000077, 0x00000018 },
672 { 0x00c0e5f9, 0x000000c2 },
673 { 0x00000077, 0x00000008 },
674 { 0x0014e50e, 0x00000004 },
675 { 0x0040e50f, 0x00000004 },
676 { 0x00c0007a, 0x00000008 },
677 { 0x0000e570, 0x00000004 },
678 { 0x0000e571, 0x00000004 },
679 { 0x0000e572, 0x0000000c },
680 { 0x0000a000, 0x00000004 },
681 { 0x0140a000, 0x00000004 },
682 { 0x0000e568, 0x00000004 },
683 { 0x000c2000, 0x00000004 },
684 { 0x00000084, 0x00000018 },
685 { 0x000b0000, 0x00000004 },
686 { 0x18c0e562, 0x00000004 },
687 { 0x00000086, 0x00000008 },
688 { 0x00c00085, 0x00000008 },
689 { 0x000700e3, 0x00000004 },
690 { 0x00000092, 0x00000038 },
691 { 0x000ca094, 0x00000030 },
692 { 0x080045bb, 0x00000004 },
693 { 0x000c2095, 0x00000030 },
694 { 0x0800e5bc, 0000000000 },
695 { 0x0000e5bb, 0x00000004 },
696 { 0x0000e5bc, 0000000000 },
697 { 0x00120000, 0x0000000c },
698 { 0x00120000, 0x00000004 },
699 { 0x001b0002, 0x0000000c },
700 { 0x0000a000, 0x00000004 },
701 { 0x0000e821, 0x00000004 },
702 { 0x0000e800, 0000000000 },
703 { 0x0000e821, 0x00000004 },
704 { 0x0000e82e, 0000000000 },
705 { 0x02cca000, 0x00000004 },
706 { 0x00140000, 0x00000004 },
707 { 0x000ce1cc, 0x00000004 },
708 { 0x050de1cd, 0x00000004 },
709 { 0x00400000, 0x00000004 },
710 { 0x000000a4, 0x00000018 },
711 { 0x00c0a000, 0x00000004 },
712 { 0x000000a1, 0x00000008 },
713 { 0x000000a6, 0x00000020 },
714 { 0x4200e000, 0000000000 },
715 { 0x000000ad, 0x00000038 },
716 { 0x000ca000, 0x00000004 },
717 { 0x00140000, 0x00000004 },
718 { 0x000c2000, 0x00000004 },
719 { 0x00160000, 0x00000004 },
720 { 0x700ce000, 0x00000004 },
721 { 0x001400a9, 0x00000008 },
722 { 0x4000e000, 0000000000 },
723 { 0x02400000, 0x00000004 },
724 { 0x400ee000, 0x00000004 },
725 { 0x02400000, 0x00000004 },
726 { 0x4000e000, 0000000000 },
727 { 0x000c2000, 0x00000004 },
728 { 0x0240e51b, 0x00000004 },
729 { 0x0080e50a, 0x00000005 },
730 { 0x0080e50b, 0x00000005 },
731 { 0x00220000, 0x00000004 },
732 { 0x000700e3, 0x00000004 },
733 { 0x000000c0, 0x00000038 },
734 { 0x000c2095, 0x00000030 },
735 { 0x0880e5bd, 0x00000005 },
736 { 0x000c2094, 0x00000030 },
737 { 0x0800e5bb, 0x00000005 },
738 { 0x000c2095, 0x00000030 },
739 { 0x0880e5bc, 0x00000005 },
740 { 0x000000c3, 0x00000008 },
741 { 0x0080e5bd, 0x00000005 },
742 { 0x0000e5bb, 0x00000005 },
743 { 0x0080e5bc, 0x00000005 },
744 { 0x00210000, 0x00000004 },
745 { 0x02800000, 0x00000004 },
746 { 0x00c000c7, 0x00000018 },
747 { 0x4180e000, 0x00000040 },
748 { 0x000000c9, 0x00000024 },
749 { 0x01000000, 0x0000000c },
750 { 0x0100e51d, 0x0000000c },
751 { 0x000045bb, 0x00000004 },
752 { 0x000080c3, 0x00000008 },
753 { 0x0000f3ce, 0x00000004 },
754 { 0x0140a000, 0x00000004 },
755 { 0x00cc2000, 0x00000004 },
756 { 0x08c053cf, 0x00000040 },
757 { 0x00008000, 0000000000 },
758 { 0x0000f3d2, 0x00000004 },
759 { 0x0140a000, 0x00000004 },
760 { 0x00cc2000, 0x00000004 },
761 { 0x08c053d3, 0x00000040 },
762 { 0x00008000, 0000000000 },
763 { 0x0000f39d, 0x00000004 },
764 { 0x0140a000, 0x00000004 },
765 { 0x00cc2000, 0x00000004 },
766 { 0x08c0539e, 0x00000040 },
767 { 0x00008000, 0000000000 },
768 { 0x03c00830, 0x00000004 },
769 { 0x4200e000, 0000000000 },
770 { 0x0000a000, 0x00000004 },
771 { 0x200045e0, 0x00000004 },
772 { 0x0000e5e1, 0000000000 },
773 { 0x00000001, 0000000000 },
774 { 0x000700e0, 0x00000004 },
775 { 0x0800e394, 0000000000 },
776 { 0000000000, 0000000000 },
777 { 0x0000e8c4, 0x00000004 },
778 { 0x0000e8c5, 0x00000004 },
779 { 0x0000e8c6, 0x00000004 },
780 { 0x0000e928, 0x00000004 },
781 { 0x0000e929, 0x00000004 },
782 { 0x0000e92a, 0x00000004 },
783 { 0x000000e4, 0x00000008 },
784 { 0x0000e928, 0x00000004 },
785 { 0x0000e929, 0x00000004 },
786 { 0x0000e92a, 0x00000004 },
787 { 0x000000eb, 0x00000008 },
788 { 0x02c02000, 0x00000004 },
789 { 0x00060000, 0x00000004 },
790 { 0x000000f3, 0x00000034 },
791 { 0x000000f0, 0x00000008 },
792 { 0x00008000, 0x00000004 },
793 { 0xc000e000, 0000000000 },
794 { 0000000000, 0000000000 },
795 { 0x000c2000, 0x00000004 },
796 { 0x001d0018, 0x00000004 },
797 { 0x001a0001, 0x00000004 },
798 { 0x000000fb, 0x00000034 },
799 { 0x0000004a, 0x00000008 },
800 { 0x0500a04a, 0x00000008 },
801 { 0000000000, 0000000000 },
802 { 0000000000, 0000000000 },
803 { 0000000000, 0000000000 },
804 { 0000000000, 0000000000 },
805};
806
807static const u32 R420_cp_microcode[][2] = {
808 { 0x4200e000, 0000000000 },
809 { 0x4000e000, 0000000000 },
810 { 0x00000099, 0x00000008 },
811 { 0x0000009d, 0x00000008 },
812 { 0x4a554b4a, 0000000000 },
813 { 0x4a4a4467, 0000000000 },
814 { 0x55526f75, 0000000000 },
815 { 0x4a7e7d65, 0000000000 },
816 { 0xd9d3dff6, 0000000000 },
817 { 0x4ac54a4a, 0000000000 },
818 { 0xc8828282, 0000000000 },
819 { 0xbf4acfc1, 0000000000 },
820 { 0x87b04a4a, 0000000000 },
821 { 0xb5838383, 0000000000 },
822 { 0x4a0f85ba, 0000000000 },
823 { 0x000ca000, 0x00000004 },
824 { 0x000d0012, 0x00000038 },
825 { 0x0000e8b4, 0x00000004 },
826 { 0x000d0014, 0x00000038 },
827 { 0x0000e8b6, 0x00000004 },
828 { 0x000d0016, 0x00000038 },
829 { 0x0000e854, 0x00000004 },
830 { 0x000d0018, 0x00000038 },
831 { 0x0000e855, 0x00000004 },
832 { 0x000d001a, 0x00000038 },
833 { 0x0000e856, 0x00000004 },
834 { 0x000d001c, 0x00000038 },
835 { 0x0000e857, 0x00000004 },
836 { 0x000d001e, 0x00000038 },
837 { 0x0000e824, 0x00000004 },
838 { 0x000d0020, 0x00000038 },
839 { 0x0000e825, 0x00000004 },
840 { 0x000d0022, 0x00000038 },
841 { 0x0000e830, 0x00000004 },
842 { 0x000d0024, 0x00000038 },
843 { 0x0000f0c0, 0x00000004 },
844 { 0x000d0026, 0x00000038 },
845 { 0x0000f0c1, 0x00000004 },
846 { 0x000d0028, 0x00000038 },
847 { 0x0000f041, 0x00000004 },
848 { 0x000d002a, 0x00000038 },
849 { 0x0000f184, 0x00000004 },
850 { 0x000d002c, 0x00000038 },
851 { 0x0000f185, 0x00000004 },
852 { 0x000d002e, 0x00000038 },
853 { 0x0000f186, 0x00000004 },
854 { 0x000d0030, 0x00000038 },
855 { 0x0000f187, 0x00000004 },
856 { 0x000d0032, 0x00000038 },
857 { 0x0000f180, 0x00000004 },
858 { 0x000d0034, 0x00000038 },
859 { 0x0000f393, 0x00000004 },
860 { 0x000d0036, 0x00000038 },
861 { 0x0000f38a, 0x00000004 },
862 { 0x000d0038, 0x00000038 },
863 { 0x0000f38e, 0x00000004 },
864 { 0x0000e821, 0x00000004 },
865 { 0x0140a000, 0x00000004 },
866 { 0x00000043, 0x00000018 },
867 { 0x00cce800, 0x00000004 },
868 { 0x001b0001, 0x00000004 },
869 { 0x08004800, 0x00000004 },
870 { 0x001b0001, 0x00000004 },
871 { 0x08004800, 0x00000004 },
872 { 0x001b0001, 0x00000004 },
873 { 0x08004800, 0x00000004 },
874 { 0x0000003a, 0x00000008 },
875 { 0x0000a000, 0000000000 },
876 { 0x2000451d, 0x00000004 },
877 { 0x0000e580, 0x00000004 },
878 { 0x000ce581, 0x00000004 },
879 { 0x08004580, 0x00000004 },
880 { 0x000ce581, 0x00000004 },
881 { 0x00000047, 0x00000008 },
882 { 0x0000a000, 0000000000 },
883 { 0x000c2000, 0x00000004 },
884 { 0x0000e50e, 0x00000004 },
885 { 0x00032000, 0x00000004 },
886 { 0x00022051, 0x00000028 },
887 { 0x00000051, 0x00000024 },
888 { 0x0800450f, 0x00000004 },
889 { 0x0000a04b, 0x00000008 },
890 { 0x0000e565, 0x00000004 },
891 { 0x0000e566, 0x00000004 },
892 { 0x00000052, 0x00000008 },
893 { 0x03cca5b4, 0x00000004 },
894 { 0x05432000, 0x00000004 },
895 { 0x00022000, 0x00000004 },
896 { 0x4ccce05e, 0x00000030 },
897 { 0x08274565, 0x00000004 },
898 { 0x0000005e, 0x00000030 },
899 { 0x08004564, 0x00000004 },
900 { 0x0000e566, 0x00000004 },
901 { 0x00000055, 0x00000008 },
902 { 0x00802061, 0x00000010 },
903 { 0x00202000, 0x00000004 },
904 { 0x001b00ff, 0x00000004 },
905 { 0x01000064, 0x00000010 },
906 { 0x001f2000, 0x00000004 },
907 { 0x001c00ff, 0x00000004 },
908 { 0000000000, 0x0000000c },
909 { 0x00000072, 0x00000030 },
910 { 0x00000055, 0x00000008 },
911 { 0x0000e576, 0x00000004 },
912 { 0x0000e577, 0x00000004 },
913 { 0x0000e50e, 0x00000004 },
914 { 0x0000e50f, 0x00000004 },
915 { 0x0140a000, 0x00000004 },
916 { 0x00000069, 0x00000018 },
917 { 0x00c0e5f9, 0x000000c2 },
918 { 0x00000069, 0x00000008 },
919 { 0x0014e50e, 0x00000004 },
920 { 0x0040e50f, 0x00000004 },
921 { 0x00c0006c, 0x00000008 },
922 { 0x0000e570, 0x00000004 },
923 { 0x0000e571, 0x00000004 },
924 { 0x0000e572, 0x0000000c },
925 { 0x0000a000, 0x00000004 },
926 { 0x0140a000, 0x00000004 },
927 { 0x0000e568, 0x00000004 },
928 { 0x000c2000, 0x00000004 },
929 { 0x00000076, 0x00000018 },
930 { 0x000b0000, 0x00000004 },
931 { 0x18c0e562, 0x00000004 },
932 { 0x00000078, 0x00000008 },
933 { 0x00c00077, 0x00000008 },
934 { 0x000700c7, 0x00000004 },
935 { 0x00000080, 0x00000038 },
936 { 0x0000e5bb, 0x00000004 },
937 { 0x0000e5bc, 0000000000 },
938 { 0x0000a000, 0x00000004 },
939 { 0x0000e821, 0x00000004 },
940 { 0x0000e800, 0000000000 },
941 { 0x0000e821, 0x00000004 },
942 { 0x0000e82e, 0000000000 },
943 { 0x02cca000, 0x00000004 },
944 { 0x00140000, 0x00000004 },
945 { 0x000ce1cc, 0x00000004 },
946 { 0x050de1cd, 0x00000004 },
947 { 0x00400000, 0x00000004 },
948 { 0x0000008f, 0x00000018 },
949 { 0x00c0a000, 0x00000004 },
950 { 0x0000008c, 0x00000008 },
951 { 0x00000091, 0x00000020 },
952 { 0x4200e000, 0000000000 },
953 { 0x00000098, 0x00000038 },
954 { 0x000ca000, 0x00000004 },
955 { 0x00140000, 0x00000004 },
956 { 0x000c2000, 0x00000004 },
957 { 0x00160000, 0x00000004 },
958 { 0x700ce000, 0x00000004 },
959 { 0x00140094, 0x00000008 },
960 { 0x4000e000, 0000000000 },
961 { 0x02400000, 0x00000004 },
962 { 0x400ee000, 0x00000004 },
963 { 0x02400000, 0x00000004 },
964 { 0x4000e000, 0000000000 },
965 { 0x000c2000, 0x00000004 },
966 { 0x0240e51b, 0x00000004 },
967 { 0x0080e50a, 0x00000005 },
968 { 0x0080e50b, 0x00000005 },
969 { 0x00220000, 0x00000004 },
970 { 0x000700c7, 0x00000004 },
971 { 0x000000a4, 0x00000038 },
972 { 0x0080e5bd, 0x00000005 },
973 { 0x0000e5bb, 0x00000005 },
974 { 0x0080e5bc, 0x00000005 },
975 { 0x00210000, 0x00000004 },
976 { 0x02800000, 0x00000004 },
977 { 0x00c000ab, 0x00000018 },
978 { 0x4180e000, 0x00000040 },
979 { 0x000000ad, 0x00000024 },
980 { 0x01000000, 0x0000000c },
981 { 0x0100e51d, 0x0000000c },
982 { 0x000045bb, 0x00000004 },
983 { 0x000080a7, 0x00000008 },
984 { 0x0000f3ce, 0x00000004 },
985 { 0x0140a000, 0x00000004 },
986 { 0x00cc2000, 0x00000004 },
987 { 0x08c053cf, 0x00000040 },
988 { 0x00008000, 0000000000 },
989 { 0x0000f3d2, 0x00000004 },
990 { 0x0140a000, 0x00000004 },
991 { 0x00cc2000, 0x00000004 },
992 { 0x08c053d3, 0x00000040 },
993 { 0x00008000, 0000000000 },
994 { 0x0000f39d, 0x00000004 },
995 { 0x0140a000, 0x00000004 },
996 { 0x00cc2000, 0x00000004 },
997 { 0x08c0539e, 0x00000040 },
998 { 0x00008000, 0000000000 },
999 { 0x03c00830, 0x00000004 },
1000 { 0x4200e000, 0000000000 },
1001 { 0x0000a000, 0x00000004 },
1002 { 0x200045e0, 0x00000004 },
1003 { 0x0000e5e1, 0000000000 },
1004 { 0x00000001, 0000000000 },
1005 { 0x000700c4, 0x00000004 },
1006 { 0x0800e394, 0000000000 },
1007 { 0000000000, 0000000000 },
1008 { 0x0000e8c4, 0x00000004 },
1009 { 0x0000e8c5, 0x00000004 },
1010 { 0x0000e8c6, 0x00000004 },
1011 { 0x0000e928, 0x00000004 },
1012 { 0x0000e929, 0x00000004 },
1013 { 0x0000e92a, 0x00000004 },
1014 { 0x000000c8, 0x00000008 },
1015 { 0x0000e928, 0x00000004 },
1016 { 0x0000e929, 0x00000004 },
1017 { 0x0000e92a, 0x00000004 },
1018 { 0x000000cf, 0x00000008 },
1019 { 0x02c02000, 0x00000004 },
1020 { 0x00060000, 0x00000004 },
1021 { 0x000000d7, 0x00000034 },
1022 { 0x000000d4, 0x00000008 },
1023 { 0x00008000, 0x00000004 },
1024 { 0xc000e000, 0000000000 },
1025 { 0x0000e1cc, 0x00000004 },
1026 { 0x0500e1cd, 0x00000004 },
1027 { 0x000ca000, 0x00000004 },
1028 { 0x000000de, 0x00000034 },
1029 { 0x000000da, 0x00000008 },
1030 { 0x0000a000, 0000000000 },
1031 { 0x0019e1cc, 0x00000004 },
1032 { 0x001b0001, 0x00000004 },
1033 { 0x0500a000, 0x00000004 },
1034 { 0x080041cd, 0x00000004 },
1035 { 0x000ca000, 0x00000004 },
1036 { 0x000000fb, 0x00000034 },
1037 { 0x0000004a, 0x00000008 },
1038 { 0000000000, 0000000000 },
1039 { 0000000000, 0000000000 },
1040 { 0000000000, 0000000000 },
1041 { 0000000000, 0000000000 },
1042 { 0000000000, 0000000000 },
1043 { 0000000000, 0000000000 },
1044 { 0000000000, 0000000000 },
1045 { 0000000000, 0000000000 },
1046 { 0000000000, 0000000000 },
1047 { 0000000000, 0000000000 },
1048 { 0000000000, 0000000000 },
1049 { 0000000000, 0000000000 },
1050 { 0000000000, 0000000000 },
1051 { 0000000000, 0000000000 },
1052 { 0000000000, 0000000000 },
1053 { 0000000000, 0000000000 },
1054 { 0x000c2000, 0x00000004 },
1055 { 0x001d0018, 0x00000004 },
1056 { 0x001a0001, 0x00000004 },
1057 { 0x000000fb, 0x00000034 },
1058 { 0x0000004a, 0x00000008 },
1059 { 0x0500a04a, 0x00000008 },
1060 { 0000000000, 0000000000 },
1061 { 0000000000, 0000000000 },
1062 { 0000000000, 0000000000 },
1063 { 0000000000, 0000000000 },
1064};
1065
1066static const u32 RS600_cp_microcode[][2] = {
1067 { 0x4200e000, 0000000000 },
1068 { 0x4000e000, 0000000000 },
1069 { 0x000000a0, 0x00000008 },
1070 { 0x000000a4, 0x00000008 },
1071 { 0x4a554b4a, 0000000000 },
1072 { 0x4a4a4467, 0000000000 },
1073 { 0x55526f75, 0000000000 },
1074 { 0x4a7e7d65, 0000000000 },
1075 { 0x4ae74af6, 0000000000 },
1076 { 0x4ad34a4a, 0000000000 },
1077 { 0xd6898989, 0000000000 },
1078 { 0xcd4addcf, 0000000000 },
1079 { 0x8ebe4ae2, 0000000000 },
1080 { 0xc38a8a8a, 0000000000 },
1081 { 0x4a0f8cc8, 0000000000 },
1082 { 0x000ca000, 0x00000004 },
1083 { 0x000d0012, 0x00000038 },
1084 { 0x0000e8b4, 0x00000004 },
1085 { 0x000d0014, 0x00000038 },
1086 { 0x0000e8b6, 0x00000004 },
1087 { 0x000d0016, 0x00000038 },
1088 { 0x0000e854, 0x00000004 },
1089 { 0x000d0018, 0x00000038 },
1090 { 0x0000e855, 0x00000004 },
1091 { 0x000d001a, 0x00000038 },
1092 { 0x0000e856, 0x00000004 },
1093 { 0x000d001c, 0x00000038 },
1094 { 0x0000e857, 0x00000004 },
1095 { 0x000d001e, 0x00000038 },
1096 { 0x0000e824, 0x00000004 },
1097 { 0x000d0020, 0x00000038 },
1098 { 0x0000e825, 0x00000004 },
1099 { 0x000d0022, 0x00000038 },
1100 { 0x0000e830, 0x00000004 },
1101 { 0x000d0024, 0x00000038 },
1102 { 0x0000f0c0, 0x00000004 },
1103 { 0x000d0026, 0x00000038 },
1104 { 0x0000f0c1, 0x00000004 },
1105 { 0x000d0028, 0x00000038 },
1106 { 0x0000f041, 0x00000004 },
1107 { 0x000d002a, 0x00000038 },
1108 { 0x0000f184, 0x00000004 },
1109 { 0x000d002c, 0x00000038 },
1110 { 0x0000f185, 0x00000004 },
1111 { 0x000d002e, 0x00000038 },
1112 { 0x0000f186, 0x00000004 },
1113 { 0x000d0030, 0x00000038 },
1114 { 0x0000f187, 0x00000004 },
1115 { 0x000d0032, 0x00000038 },
1116 { 0x0000f180, 0x00000004 },
1117 { 0x000d0034, 0x00000038 },
1118 { 0x0000f393, 0x00000004 },
1119 { 0x000d0036, 0x00000038 },
1120 { 0x0000f38a, 0x00000004 },
1121 { 0x000d0038, 0x00000038 },
1122 { 0x0000f38e, 0x00000004 },
1123 { 0x0000e821, 0x00000004 },
1124 { 0x0140a000, 0x00000004 },
1125 { 0x00000043, 0x00000018 },
1126 { 0x00cce800, 0x00000004 },
1127 { 0x001b0001, 0x00000004 },
1128 { 0x08004800, 0x00000004 },
1129 { 0x001b0001, 0x00000004 },
1130 { 0x08004800, 0x00000004 },
1131 { 0x001b0001, 0x00000004 },
1132 { 0x08004800, 0x00000004 },
1133 { 0x0000003a, 0x00000008 },
1134 { 0x0000a000, 0000000000 },
1135 { 0x2000451d, 0x00000004 },
1136 { 0x0000e580, 0x00000004 },
1137 { 0x000ce581, 0x00000004 },
1138 { 0x08004580, 0x00000004 },
1139 { 0x000ce581, 0x00000004 },
1140 { 0x00000047, 0x00000008 },
1141 { 0x0000a000, 0000000000 },
1142 { 0x000c2000, 0x00000004 },
1143 { 0x0000e50e, 0x00000004 },
1144 { 0x00032000, 0x00000004 },
1145 { 0x00022051, 0x00000028 },
1146 { 0x00000051, 0x00000024 },
1147 { 0x0800450f, 0x00000004 },
1148 { 0x0000a04b, 0x00000008 },
1149 { 0x0000e565, 0x00000004 },
1150 { 0x0000e566, 0x00000004 },
1151 { 0x00000052, 0x00000008 },
1152 { 0x03cca5b4, 0x00000004 },
1153 { 0x05432000, 0x00000004 },
1154 { 0x00022000, 0x00000004 },
1155 { 0x4ccce05e, 0x00000030 },
1156 { 0x08274565, 0x00000004 },
1157 { 0x0000005e, 0x00000030 },
1158 { 0x08004564, 0x00000004 },
1159 { 0x0000e566, 0x00000004 },
1160 { 0x00000055, 0x00000008 },
1161 { 0x00802061, 0x00000010 },
1162 { 0x00202000, 0x00000004 },
1163 { 0x001b00ff, 0x00000004 },
1164 { 0x01000064, 0x00000010 },
1165 { 0x001f2000, 0x00000004 },
1166 { 0x001c00ff, 0x00000004 },
1167 { 0000000000, 0x0000000c },
1168 { 0x00000072, 0x00000030 },
1169 { 0x00000055, 0x00000008 },
1170 { 0x0000e576, 0x00000004 },
1171 { 0x0000e577, 0x00000004 },
1172 { 0x0000e50e, 0x00000004 },
1173 { 0x0000e50f, 0x00000004 },
1174 { 0x0140a000, 0x00000004 },
1175 { 0x00000069, 0x00000018 },
1176 { 0x00c0e5f9, 0x000000c2 },
1177 { 0x00000069, 0x00000008 },
1178 { 0x0014e50e, 0x00000004 },
1179 { 0x0040e50f, 0x00000004 },
1180 { 0x00c0006c, 0x00000008 },
1181 { 0x0000e570, 0x00000004 },
1182 { 0x0000e571, 0x00000004 },
1183 { 0x0000e572, 0x0000000c },
1184 { 0x0000a000, 0x00000004 },
1185 { 0x0140a000, 0x00000004 },
1186 { 0x0000e568, 0x00000004 },
1187 { 0x000c2000, 0x00000004 },
1188 { 0x00000076, 0x00000018 },
1189 { 0x000b0000, 0x00000004 },
1190 { 0x18c0e562, 0x00000004 },
1191 { 0x00000078, 0x00000008 },
1192 { 0x00c00077, 0x00000008 },
1193 { 0x000700d5, 0x00000004 },
1194 { 0x00000084, 0x00000038 },
1195 { 0x000ca086, 0x00000030 },
1196 { 0x080045bb, 0x00000004 },
1197 { 0x000c2087, 0x00000030 },
1198 { 0x0800e5bc, 0000000000 },
1199 { 0x0000e5bb, 0x00000004 },
1200 { 0x0000e5bc, 0000000000 },
1201 { 0x00120000, 0x0000000c },
1202 { 0x00120000, 0x00000004 },
1203 { 0x001b0002, 0x0000000c },
1204 { 0x0000a000, 0x00000004 },
1205 { 0x0000e821, 0x00000004 },
1206 { 0x0000e800, 0000000000 },
1207 { 0x0000e821, 0x00000004 },
1208 { 0x0000e82e, 0000000000 },
1209 { 0x02cca000, 0x00000004 },
1210 { 0x00140000, 0x00000004 },
1211 { 0x000ce1cc, 0x00000004 },
1212 { 0x050de1cd, 0x00000004 },
1213 { 0x00400000, 0x00000004 },
1214 { 0x00000096, 0x00000018 },
1215 { 0x00c0a000, 0x00000004 },
1216 { 0x00000093, 0x00000008 },
1217 { 0x00000098, 0x00000020 },
1218 { 0x4200e000, 0000000000 },
1219 { 0x0000009f, 0x00000038 },
1220 { 0x000ca000, 0x00000004 },
1221 { 0x00140000, 0x00000004 },
1222 { 0x000c2000, 0x00000004 },
1223 { 0x00160000, 0x00000004 },
1224 { 0x700ce000, 0x00000004 },
1225 { 0x0014009b, 0x00000008 },
1226 { 0x4000e000, 0000000000 },
1227 { 0x02400000, 0x00000004 },
1228 { 0x400ee000, 0x00000004 },
1229 { 0x02400000, 0x00000004 },
1230 { 0x4000e000, 0000000000 },
1231 { 0x000c2000, 0x00000004 },
1232 { 0x0240e51b, 0x00000004 },
1233 { 0x0080e50a, 0x00000005 },
1234 { 0x0080e50b, 0x00000005 },
1235 { 0x00220000, 0x00000004 },
1236 { 0x000700d5, 0x00000004 },
1237 { 0x000000b2, 0x00000038 },
1238 { 0x000c2087, 0x00000030 },
1239 { 0x0880e5bd, 0x00000005 },
1240 { 0x000c2086, 0x00000030 },
1241 { 0x0800e5bb, 0x00000005 },
1242 { 0x000c2087, 0x00000030 },
1243 { 0x0880e5bc, 0x00000005 },
1244 { 0x000000b5, 0x00000008 },
1245 { 0x0080e5bd, 0x00000005 },
1246 { 0x0000e5bb, 0x00000005 },
1247 { 0x0080e5bc, 0x00000005 },
1248 { 0x00210000, 0x00000004 },
1249 { 0x02800000, 0x00000004 },
1250 { 0x00c000b9, 0x00000018 },
1251 { 0x4180e000, 0x00000040 },
1252 { 0x000000bb, 0x00000024 },
1253 { 0x01000000, 0x0000000c },
1254 { 0x0100e51d, 0x0000000c },
1255 { 0x000045bb, 0x00000004 },
1256 { 0x000080b5, 0x00000008 },
1257 { 0x0000f3ce, 0x00000004 },
1258 { 0x0140a000, 0x00000004 },
1259 { 0x00cc2000, 0x00000004 },
1260 { 0x08c053cf, 0x00000040 },
1261 { 0x00008000, 0000000000 },
1262 { 0x0000f3d2, 0x00000004 },
1263 { 0x0140a000, 0x00000004 },
1264 { 0x00cc2000, 0x00000004 },
1265 { 0x08c053d3, 0x00000040 },
1266 { 0x00008000, 0000000000 },
1267 { 0x0000f39d, 0x00000004 },
1268 { 0x0140a000, 0x00000004 },
1269 { 0x00cc2000, 0x00000004 },
1270 { 0x08c0539e, 0x00000040 },
1271 { 0x00008000, 0000000000 },
1272 { 0x03c00830, 0x00000004 },
1273 { 0x4200e000, 0000000000 },
1274 { 0x0000a000, 0x00000004 },
1275 { 0x200045e0, 0x00000004 },
1276 { 0x0000e5e1, 0000000000 },
1277 { 0x00000001, 0000000000 },
1278 { 0x000700d2, 0x00000004 },
1279 { 0x0800e394, 0000000000 },
1280 { 0000000000, 0000000000 },
1281 { 0x0000e8c4, 0x00000004 },
1282 { 0x0000e8c5, 0x00000004 },
1283 { 0x0000e8c6, 0x00000004 },
1284 { 0x0000e928, 0x00000004 },
1285 { 0x0000e929, 0x00000004 },
1286 { 0x0000e92a, 0x00000004 },
1287 { 0x000000d6, 0x00000008 },
1288 { 0x0000e928, 0x00000004 },
1289 { 0x0000e929, 0x00000004 },
1290 { 0x0000e92a, 0x00000004 },
1291 { 0x000000dd, 0x00000008 },
1292 { 0x00e00116, 0000000000 },
1293 { 0x000700e1, 0x00000004 },
1294 { 0x0800401c, 0x00000004 },
1295 { 0x200050e7, 0x00000004 },
1296 { 0x0000e01d, 0x00000004 },
1297 { 0x000000e4, 0x00000008 },
1298 { 0x02c02000, 0x00000004 },
1299 { 0x00060000, 0x00000004 },
1300 { 0x000000eb, 0x00000034 },
1301 { 0x000000e8, 0x00000008 },
1302 { 0x00008000, 0x00000004 },
1303 { 0xc000e000, 0000000000 },
1304 { 0000000000, 0000000000 },
1305 { 0000000000, 0000000000 },
1306 { 0000000000, 0000000000 },
1307 { 0000000000, 0000000000 },
1308 { 0000000000, 0000000000 },
1309 { 0000000000, 0000000000 },
1310 { 0000000000, 0000000000 },
1311 { 0000000000, 0000000000 },
1312 { 0000000000, 0000000000 },
1313 { 0x000c2000, 0x00000004 },
1314 { 0x001d0018, 0x00000004 },
1315 { 0x001a0001, 0x00000004 },
1316 { 0x000000fb, 0x00000034 },
1317 { 0x0000004a, 0x00000008 },
1318 { 0x0500a04a, 0x00000008 },
1319 { 0000000000, 0000000000 },
1320 { 0000000000, 0000000000 },
1321 { 0000000000, 0000000000 },
1322 { 0000000000, 0000000000 },
1323};
1324
1325static const u32 RS690_cp_microcode[][2] = {
1326 { 0x000000dd, 0x00000008 },
1327 { 0x000000df, 0x00000008 },
1328 { 0x000000a0, 0x00000008 },
1329 { 0x000000a4, 0x00000008 },
1330 { 0x4a554b4a, 0000000000 },
1331 { 0x4a4a4467, 0000000000 },
1332 { 0x55526f75, 0000000000 },
1333 { 0x4a7e7d65, 0000000000 },
1334 { 0x4ad74af6, 0000000000 },
1335 { 0x4ac94a4a, 0000000000 },
1336 { 0xcc898989, 0000000000 },
1337 { 0xc34ad3c5, 0000000000 },
1338 { 0x8e4a4a4a, 0000000000 },
1339 { 0x4a8a8a8a, 0000000000 },
1340 { 0x4a0f8c4a, 0000000000 },
1341 { 0x000ca000, 0x00000004 },
1342 { 0x000d0012, 0x00000038 },
1343 { 0x0000e8b4, 0x00000004 },
1344 { 0x000d0014, 0x00000038 },
1345 { 0x0000e8b6, 0x00000004 },
1346 { 0x000d0016, 0x00000038 },
1347 { 0x0000e854, 0x00000004 },
1348 { 0x000d0018, 0x00000038 },
1349 { 0x0000e855, 0x00000004 },
1350 { 0x000d001a, 0x00000038 },
1351 { 0x0000e856, 0x00000004 },
1352 { 0x000d001c, 0x00000038 },
1353 { 0x0000e857, 0x00000004 },
1354 { 0x000d001e, 0x00000038 },
1355 { 0x0000e824, 0x00000004 },
1356 { 0x000d0020, 0x00000038 },
1357 { 0x0000e825, 0x00000004 },
1358 { 0x000d0022, 0x00000038 },
1359 { 0x0000e830, 0x00000004 },
1360 { 0x000d0024, 0x00000038 },
1361 { 0x0000f0c0, 0x00000004 },
1362 { 0x000d0026, 0x00000038 },
1363 { 0x0000f0c1, 0x00000004 },
1364 { 0x000d0028, 0x00000038 },
1365 { 0x0000f041, 0x00000004 },
1366 { 0x000d002a, 0x00000038 },
1367 { 0x0000f184, 0x00000004 },
1368 { 0x000d002c, 0x00000038 },
1369 { 0x0000f185, 0x00000004 },
1370 { 0x000d002e, 0x00000038 },
1371 { 0x0000f186, 0x00000004 },
1372 { 0x000d0030, 0x00000038 },
1373 { 0x0000f187, 0x00000004 },
1374 { 0x000d0032, 0x00000038 },
1375 { 0x0000f180, 0x00000004 },
1376 { 0x000d0034, 0x00000038 },
1377 { 0x0000f393, 0x00000004 },
1378 { 0x000d0036, 0x00000038 },
1379 { 0x0000f38a, 0x00000004 },
1380 { 0x000d0038, 0x00000038 },
1381 { 0x0000f38e, 0x00000004 },
1382 { 0x0000e821, 0x00000004 },
1383 { 0x0140a000, 0x00000004 },
1384 { 0x00000043, 0x00000018 },
1385 { 0x00cce800, 0x00000004 },
1386 { 0x001b0001, 0x00000004 },
1387 { 0x08004800, 0x00000004 },
1388 { 0x001b0001, 0x00000004 },
1389 { 0x08004800, 0x00000004 },
1390 { 0x001b0001, 0x00000004 },
1391 { 0x08004800, 0x00000004 },
1392 { 0x0000003a, 0x00000008 },
1393 { 0x0000a000, 0000000000 },
1394 { 0x2000451d, 0x00000004 },
1395 { 0x0000e580, 0x00000004 },
1396 { 0x000ce581, 0x00000004 },
1397 { 0x08004580, 0x00000004 },
1398 { 0x000ce581, 0x00000004 },
1399 { 0x00000047, 0x00000008 },
1400 { 0x0000a000, 0000000000 },
1401 { 0x000c2000, 0x00000004 },
1402 { 0x0000e50e, 0x00000004 },
1403 { 0x00032000, 0x00000004 },
1404 { 0x00022051, 0x00000028 },
1405 { 0x00000051, 0x00000024 },
1406 { 0x0800450f, 0x00000004 },
1407 { 0x0000a04b, 0x00000008 },
1408 { 0x0000e565, 0x00000004 },
1409 { 0x0000e566, 0x00000004 },
1410 { 0x00000052, 0x00000008 },
1411 { 0x03cca5b4, 0x00000004 },
1412 { 0x05432000, 0x00000004 },
1413 { 0x00022000, 0x00000004 },
1414 { 0x4ccce05e, 0x00000030 },
1415 { 0x08274565, 0x00000004 },
1416 { 0x0000005e, 0x00000030 },
1417 { 0x08004564, 0x00000004 },
1418 { 0x0000e566, 0x00000004 },
1419 { 0x00000055, 0x00000008 },
1420 { 0x00802061, 0x00000010 },
1421 { 0x00202000, 0x00000004 },
1422 { 0x001b00ff, 0x00000004 },
1423 { 0x01000064, 0x00000010 },
1424 { 0x001f2000, 0x00000004 },
1425 { 0x001c00ff, 0x00000004 },
1426 { 0000000000, 0x0000000c },
1427 { 0x00000072, 0x00000030 },
1428 { 0x00000055, 0x00000008 },
1429 { 0x0000e576, 0x00000004 },
1430 { 0x0000e577, 0x00000004 },
1431 { 0x0000e50e, 0x00000004 },
1432 { 0x0000e50f, 0x00000004 },
1433 { 0x0140a000, 0x00000004 },
1434 { 0x00000069, 0x00000018 },
1435 { 0x00c0e5f9, 0x000000c2 },
1436 { 0x00000069, 0x00000008 },
1437 { 0x0014e50e, 0x00000004 },
1438 { 0x0040e50f, 0x00000004 },
1439 { 0x00c0006c, 0x00000008 },
1440 { 0x0000e570, 0x00000004 },
1441 { 0x0000e571, 0x00000004 },
1442 { 0x0000e572, 0x0000000c },
1443 { 0x0000a000, 0x00000004 },
1444 { 0x0140a000, 0x00000004 },
1445 { 0x0000e568, 0x00000004 },
1446 { 0x000c2000, 0x00000004 },
1447 { 0x00000076, 0x00000018 },
1448 { 0x000b0000, 0x00000004 },
1449 { 0x18c0e562, 0x00000004 },
1450 { 0x00000078, 0x00000008 },
1451 { 0x00c00077, 0x00000008 },
1452 { 0x000700cb, 0x00000004 },
1453 { 0x00000084, 0x00000038 },
1454 { 0x000ca086, 0x00000030 },
1455 { 0x080045bb, 0x00000004 },
1456 { 0x000c2087, 0x00000030 },
1457 { 0x0800e5bc, 0000000000 },
1458 { 0x0000e5bb, 0x00000004 },
1459 { 0x0000e5bc, 0000000000 },
1460 { 0x00120000, 0x0000000c },
1461 { 0x00120000, 0x00000004 },
1462 { 0x001b0002, 0x0000000c },
1463 { 0x0000a000, 0x00000004 },
1464 { 0x0000e821, 0x00000004 },
1465 { 0x0000e800, 0000000000 },
1466 { 0x0000e821, 0x00000004 },
1467 { 0x0000e82e, 0000000000 },
1468 { 0x02cca000, 0x00000004 },
1469 { 0x00140000, 0x00000004 },
1470 { 0x000ce1cc, 0x00000004 },
1471 { 0x050de1cd, 0x00000004 },
1472 { 0x00400000, 0x00000004 },
1473 { 0x00000096, 0x00000018 },
1474 { 0x00c0a000, 0x00000004 },
1475 { 0x00000093, 0x00000008 },
1476 { 0x00000098, 0x00000020 },
1477 { 0x4200e000, 0000000000 },
1478 { 0x0000009f, 0x00000038 },
1479 { 0x000ca000, 0x00000004 },
1480 { 0x00140000, 0x00000004 },
1481 { 0x000c2000, 0x00000004 },
1482 { 0x00160000, 0x00000004 },
1483 { 0x700ce000, 0x00000004 },
1484 { 0x0014009b, 0x00000008 },
1485 { 0x4000e000, 0000000000 },
1486 { 0x02400000, 0x00000004 },
1487 { 0x400ee000, 0x00000004 },
1488 { 0x02400000, 0x00000004 },
1489 { 0x4000e000, 0000000000 },
1490 { 0x00100000, 0x0000002c },
1491 { 0x00004000, 0000000000 },
1492 { 0x080045c8, 0x00000004 },
1493 { 0x00240005, 0x00000004 },
1494 { 0x08004d0b, 0x00000004 },
1495 { 0x000c2000, 0x00000004 },
1496 { 0x0240e51b, 0x00000004 },
1497 { 0x0080e50a, 0x00000005 },
1498 { 0x0080e50b, 0x00000005 },
1499 { 0x00220000, 0x00000004 },
1500 { 0x000700cb, 0x00000004 },
1501 { 0x000000b7, 0x00000038 },
1502 { 0x000c2087, 0x00000030 },
1503 { 0x0880e5bd, 0x00000005 },
1504 { 0x000c2086, 0x00000030 },
1505 { 0x0800e5bb, 0x00000005 },
1506 { 0x000c2087, 0x00000030 },
1507 { 0x0880e5bc, 0x00000005 },
1508 { 0x000000ba, 0x00000008 },
1509 { 0x0080e5bd, 0x00000005 },
1510 { 0x0000e5bb, 0x00000005 },
1511 { 0x0080e5bc, 0x00000005 },
1512 { 0x00210000, 0x00000004 },
1513 { 0x02800000, 0x00000004 },
1514 { 0x00c000be, 0x00000018 },
1515 { 0x4180e000, 0x00000040 },
1516 { 0x000000c0, 0x00000024 },
1517 { 0x01000000, 0x0000000c },
1518 { 0x0100e51d, 0x0000000c },
1519 { 0x000045bb, 0x00000004 },
1520 { 0x000080ba, 0x00000008 },
1521 { 0x03c00830, 0x00000004 },
1522 { 0x4200e000, 0000000000 },
1523 { 0x0000a000, 0x00000004 },
1524 { 0x200045e0, 0x00000004 },
1525 { 0x0000e5e1, 0000000000 },
1526 { 0x00000001, 0000000000 },
1527 { 0x000700c8, 0x00000004 },
1528 { 0x0800e394, 0000000000 },
1529 { 0000000000, 0000000000 },
1530 { 0x0000e8c4, 0x00000004 },
1531 { 0x0000e8c5, 0x00000004 },
1532 { 0x0000e8c6, 0x00000004 },
1533 { 0x0000e928, 0x00000004 },
1534 { 0x0000e929, 0x00000004 },
1535 { 0x0000e92a, 0x00000004 },
1536 { 0x000000cc, 0x00000008 },
1537 { 0x0000e928, 0x00000004 },
1538 { 0x0000e929, 0x00000004 },
1539 { 0x0000e92a, 0x00000004 },
1540 { 0x000000d3, 0x00000008 },
1541 { 0x02c02000, 0x00000004 },
1542 { 0x00060000, 0x00000004 },
1543 { 0x000000db, 0x00000034 },
1544 { 0x000000d8, 0x00000008 },
1545 { 0x00008000, 0x00000004 },
1546 { 0xc000e000, 0000000000 },
1547 { 0x000000e1, 0x00000030 },
1548 { 0x4200e000, 0000000000 },
1549 { 0x000000e1, 0x00000030 },
1550 { 0x4000e000, 0000000000 },
1551 { 0x0025001b, 0x00000004 },
1552 { 0x00230000, 0x00000004 },
1553 { 0x00250005, 0x00000004 },
1554 { 0x000000e6, 0x00000034 },
1555 { 0000000000, 0x0000000c },
1556 { 0x00244000, 0x00000004 },
1557 { 0x080045c8, 0x00000004 },
1558 { 0x00240005, 0x00000004 },
1559 { 0x08004d0b, 0x0000000c },
1560 { 0000000000, 0000000000 },
1561 { 0000000000, 0000000000 },
1562 { 0000000000, 0000000000 },
1563 { 0000000000, 0000000000 },
1564 { 0000000000, 0000000000 },
1565 { 0000000000, 0000000000 },
1566 { 0000000000, 0000000000 },
1567 { 0000000000, 0000000000 },
1568 { 0000000000, 0000000000 },
1569 { 0000000000, 0000000000 },
1570 { 0000000000, 0000000000 },
1571 { 0000000000, 0000000000 },
1572 { 0x000c2000, 0x00000004 },
1573 { 0x001d0018, 0x00000004 },
1574 { 0x001a0001, 0x00000004 },
1575 { 0x000000fb, 0x00000034 },
1576 { 0x0000004a, 0x00000008 },
1577 { 0x0500a04a, 0x00000008 },
1578 { 0000000000, 0000000000 },
1579 { 0000000000, 0000000000 },
1580 { 0000000000, 0000000000 },
1581 { 0000000000, 0000000000 },
1582};
1583
1584static const u32 R520_cp_microcode[][2] = {
1585 { 0x4200e000, 0000000000 },
1586 { 0x4000e000, 0000000000 },
1587 { 0x00000099, 0x00000008 },
1588 { 0x0000009d, 0x00000008 },
1589 { 0x4a554b4a, 0000000000 },
1590 { 0x4a4a4467, 0000000000 },
1591 { 0x55526f75, 0000000000 },
1592 { 0x4a7e7d65, 0000000000 },
1593 { 0xe0dae6f6, 0000000000 },
1594 { 0x4ac54a4a, 0000000000 },
1595 { 0xc8828282, 0000000000 },
1596 { 0xbf4acfc1, 0000000000 },
1597 { 0x87b04ad5, 0000000000 },
1598 { 0xb5838383, 0000000000 },
1599 { 0x4a0f85ba, 0000000000 },
1600 { 0x000ca000, 0x00000004 },
1601 { 0x000d0012, 0x00000038 },
1602 { 0x0000e8b4, 0x00000004 },
1603 { 0x000d0014, 0x00000038 },
1604 { 0x0000e8b6, 0x00000004 },
1605 { 0x000d0016, 0x00000038 },
1606 { 0x0000e854, 0x00000004 },
1607 { 0x000d0018, 0x00000038 },
1608 { 0x0000e855, 0x00000004 },
1609 { 0x000d001a, 0x00000038 },
1610 { 0x0000e856, 0x00000004 },
1611 { 0x000d001c, 0x00000038 },
1612 { 0x0000e857, 0x00000004 },
1613 { 0x000d001e, 0x00000038 },
1614 { 0x0000e824, 0x00000004 },
1615 { 0x000d0020, 0x00000038 },
1616 { 0x0000e825, 0x00000004 },
1617 { 0x000d0022, 0x00000038 },
1618 { 0x0000e830, 0x00000004 },
1619 { 0x000d0024, 0x00000038 },
1620 { 0x0000f0c0, 0x00000004 },
1621 { 0x000d0026, 0x00000038 },
1622 { 0x0000f0c1, 0x00000004 },
1623 { 0x000d0028, 0x00000038 },
1624 { 0x0000e000, 0x00000004 },
1625 { 0x000d002a, 0x00000038 },
1626 { 0x0000e000, 0x00000004 },
1627 { 0x000d002c, 0x00000038 },
1628 { 0x0000e000, 0x00000004 },
1629 { 0x000d002e, 0x00000038 },
1630 { 0x0000e000, 0x00000004 },
1631 { 0x000d0030, 0x00000038 },
1632 { 0x0000e000, 0x00000004 },
1633 { 0x000d0032, 0x00000038 },
1634 { 0x0000f180, 0x00000004 },
1635 { 0x000d0034, 0x00000038 },
1636 { 0x0000f393, 0x00000004 },
1637 { 0x000d0036, 0x00000038 },
1638 { 0x0000f38a, 0x00000004 },
1639 { 0x000d0038, 0x00000038 },
1640 { 0x0000f38e, 0x00000004 },
1641 { 0x0000e821, 0x00000004 },
1642 { 0x0140a000, 0x00000004 },
1643 { 0x00000043, 0x00000018 },
1644 { 0x00cce800, 0x00000004 },
1645 { 0x001b0001, 0x00000004 },
1646 { 0x08004800, 0x00000004 },
1647 { 0x001b0001, 0x00000004 },
1648 { 0x08004800, 0x00000004 },
1649 { 0x001b0001, 0x00000004 },
1650 { 0x08004800, 0x00000004 },
1651 { 0x0000003a, 0x00000008 },
1652 { 0x0000a000, 0000000000 },
1653 { 0x2000451d, 0x00000004 },
1654 { 0x0000e580, 0x00000004 },
1655 { 0x000ce581, 0x00000004 },
1656 { 0x08004580, 0x00000004 },
1657 { 0x000ce581, 0x00000004 },
1658 { 0x00000047, 0x00000008 },
1659 { 0x0000a000, 0000000000 },
1660 { 0x000c2000, 0x00000004 },
1661 { 0x0000e50e, 0x00000004 },
1662 { 0x00032000, 0x00000004 },
1663 { 0x00022051, 0x00000028 },
1664 { 0x00000051, 0x00000024 },
1665 { 0x0800450f, 0x00000004 },
1666 { 0x0000a04b, 0x00000008 },
1667 { 0x0000e565, 0x00000004 },
1668 { 0x0000e566, 0x00000004 },
1669 { 0x00000052, 0x00000008 },
1670 { 0x03cca5b4, 0x00000004 },
1671 { 0x05432000, 0x00000004 },
1672 { 0x00022000, 0x00000004 },
1673 { 0x4ccce05e, 0x00000030 },
1674 { 0x08274565, 0x00000004 },
1675 { 0x0000005e, 0x00000030 },
1676 { 0x08004564, 0x00000004 },
1677 { 0x0000e566, 0x00000004 },
1678 { 0x00000055, 0x00000008 },
1679 { 0x00802061, 0x00000010 },
1680 { 0x00202000, 0x00000004 },
1681 { 0x001b00ff, 0x00000004 },
1682 { 0x01000064, 0x00000010 },
1683 { 0x001f2000, 0x00000004 },
1684 { 0x001c00ff, 0x00000004 },
1685 { 0000000000, 0x0000000c },
1686 { 0x00000072, 0x00000030 },
1687 { 0x00000055, 0x00000008 },
1688 { 0x0000e576, 0x00000004 },
1689 { 0x0000e577, 0x00000004 },
1690 { 0x0000e50e, 0x00000004 },
1691 { 0x0000e50f, 0x00000004 },
1692 { 0x0140a000, 0x00000004 },
1693 { 0x00000069, 0x00000018 },
1694 { 0x00c0e5f9, 0x000000c2 },
1695 { 0x00000069, 0x00000008 },
1696 { 0x0014e50e, 0x00000004 },
1697 { 0x0040e50f, 0x00000004 },
1698 { 0x00c0006c, 0x00000008 },
1699 { 0x0000e570, 0x00000004 },
1700 { 0x0000e571, 0x00000004 },
1701 { 0x0000e572, 0x0000000c },
1702 { 0x0000a000, 0x00000004 },
1703 { 0x0140a000, 0x00000004 },
1704 { 0x0000e568, 0x00000004 },
1705 { 0x000c2000, 0x00000004 },
1706 { 0x00000076, 0x00000018 },
1707 { 0x000b0000, 0x00000004 },
1708 { 0x18c0e562, 0x00000004 },
1709 { 0x00000078, 0x00000008 },
1710 { 0x00c00077, 0x00000008 },
1711 { 0x000700c7, 0x00000004 },
1712 { 0x00000080, 0x00000038 },
1713 { 0x0000e5bb, 0x00000004 },
1714 { 0x0000e5bc, 0000000000 },
1715 { 0x0000a000, 0x00000004 },
1716 { 0x0000e821, 0x00000004 },
1717 { 0x0000e800, 0000000000 },
1718 { 0x0000e821, 0x00000004 },
1719 { 0x0000e82e, 0000000000 },
1720 { 0x02cca000, 0x00000004 },
1721 { 0x00140000, 0x00000004 },
1722 { 0x000ce1cc, 0x00000004 },
1723 { 0x050de1cd, 0x00000004 },
1724 { 0x00400000, 0x00000004 },
1725 { 0x0000008f, 0x00000018 },
1726 { 0x00c0a000, 0x00000004 },
1727 { 0x0000008c, 0x00000008 },
1728 { 0x00000091, 0x00000020 },
1729 { 0x4200e000, 0000000000 },
1730 { 0x00000098, 0x00000038 },
1731 { 0x000ca000, 0x00000004 },
1732 { 0x00140000, 0x00000004 },
1733 { 0x000c2000, 0x00000004 },
1734 { 0x00160000, 0x00000004 },
1735 { 0x700ce000, 0x00000004 },
1736 { 0x00140094, 0x00000008 },
1737 { 0x4000e000, 0000000000 },
1738 { 0x02400000, 0x00000004 },
1739 { 0x400ee000, 0x00000004 },
1740 { 0x02400000, 0x00000004 },
1741 { 0x4000e000, 0000000000 },
1742 { 0x000c2000, 0x00000004 },
1743 { 0x0240e51b, 0x00000004 },
1744 { 0x0080e50a, 0x00000005 },
1745 { 0x0080e50b, 0x00000005 },
1746 { 0x00220000, 0x00000004 },
1747 { 0x000700c7, 0x00000004 },
1748 { 0x000000a4, 0x00000038 },
1749 { 0x0080e5bd, 0x00000005 },
1750 { 0x0000e5bb, 0x00000005 },
1751 { 0x0080e5bc, 0x00000005 },
1752 { 0x00210000, 0x00000004 },
1753 { 0x02800000, 0x00000004 },
1754 { 0x00c000ab, 0x00000018 },
1755 { 0x4180e000, 0x00000040 },
1756 { 0x000000ad, 0x00000024 },
1757 { 0x01000000, 0x0000000c },
1758 { 0x0100e51d, 0x0000000c },
1759 { 0x000045bb, 0x00000004 },
1760 { 0x000080a7, 0x00000008 },
1761 { 0x0000f3ce, 0x00000004 },
1762 { 0x0140a000, 0x00000004 },
1763 { 0x00cc2000, 0x00000004 },
1764 { 0x08c053cf, 0x00000040 },
1765 { 0x00008000, 0000000000 },
1766 { 0x0000f3d2, 0x00000004 },
1767 { 0x0140a000, 0x00000004 },
1768 { 0x00cc2000, 0x00000004 },
1769 { 0x08c053d3, 0x00000040 },
1770 { 0x00008000, 0000000000 },
1771 { 0x0000f39d, 0x00000004 },
1772 { 0x0140a000, 0x00000004 },
1773 { 0x00cc2000, 0x00000004 },
1774 { 0x08c0539e, 0x00000040 },
1775 { 0x00008000, 0000000000 },
1776 { 0x03c00830, 0x00000004 },
1777 { 0x4200e000, 0000000000 },
1778 { 0x0000a000, 0x00000004 },
1779 { 0x200045e0, 0x00000004 },
1780 { 0x0000e5e1, 0000000000 },
1781 { 0x00000001, 0000000000 },
1782 { 0x000700c4, 0x00000004 },
1783 { 0x0800e394, 0000000000 },
1784 { 0000000000, 0000000000 },
1785 { 0x0000e8c4, 0x00000004 },
1786 { 0x0000e8c5, 0x00000004 },
1787 { 0x0000e8c6, 0x00000004 },
1788 { 0x0000e928, 0x00000004 },
1789 { 0x0000e929, 0x00000004 },
1790 { 0x0000e92a, 0x00000004 },
1791 { 0x000000c8, 0x00000008 },
1792 { 0x0000e928, 0x00000004 },
1793 { 0x0000e929, 0x00000004 },
1794 { 0x0000e92a, 0x00000004 },
1795 { 0x000000cf, 0x00000008 },
1796 { 0xdeadbeef, 0000000000 },
1797 { 0x00000116, 0000000000 },
1798 { 0x000700d3, 0x00000004 },
1799 { 0x080050e7, 0x00000004 },
1800 { 0x000700d4, 0x00000004 },
1801 { 0x0800401c, 0x00000004 },
1802 { 0x0000e01d, 0000000000 },
1803 { 0x02c02000, 0x00000004 },
1804 { 0x00060000, 0x00000004 },
1805 { 0x000000de, 0x00000034 },
1806 { 0x000000db, 0x00000008 },
1807 { 0x00008000, 0x00000004 },
1808 { 0xc000e000, 0000000000 },
1809 { 0x0000e1cc, 0x00000004 },
1810 { 0x0500e1cd, 0x00000004 },
1811 { 0x000ca000, 0x00000004 },
1812 { 0x000000e5, 0x00000034 },
1813 { 0x000000e1, 0x00000008 },
1814 { 0x0000a000, 0000000000 },
1815 { 0x0019e1cc, 0x00000004 },
1816 { 0x001b0001, 0x00000004 },
1817 { 0x0500a000, 0x00000004 },
1818 { 0x080041cd, 0x00000004 },
1819 { 0x000ca000, 0x00000004 },
1820 { 0x000000fb, 0x00000034 },
1821 { 0x0000004a, 0x00000008 },
1822 { 0000000000, 0000000000 },
1823 { 0000000000, 0000000000 },
1824 { 0000000000, 0000000000 },
1825 { 0000000000, 0000000000 },
1826 { 0000000000, 0000000000 },
1827 { 0000000000, 0000000000 },
1828 { 0000000000, 0000000000 },
1829 { 0000000000, 0000000000 },
1830 { 0000000000, 0000000000 },
1831 { 0x000c2000, 0x00000004 },
1832 { 0x001d0018, 0x00000004 },
1833 { 0x001a0001, 0x00000004 },
1834 { 0x000000fb, 0x00000034 },
1835 { 0x0000004a, 0x00000008 },
1836 { 0x0500a04a, 0x00000008 },
1837 { 0000000000, 0000000000 },
1838 { 0000000000, 0000000000 },
1839 { 0000000000, 0000000000 },
1840 { 0000000000, 0000000000 },
1841};
1842
1843
1844#endif
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index 6f75512f591e..11c146b49211 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -1662,7 +1662,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1662 u32 height; 1662 u32 height;
1663 int i; 1663 int i;
1664 u32 texpitch, microtile; 1664 u32 texpitch, microtile;
1665 u32 offset; 1665 u32 offset, byte_offset;
1666 RING_LOCALS; 1666 RING_LOCALS;
1667 1667
1668 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) { 1668 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
@@ -1727,6 +1727,13 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1727 } else 1727 } else
1728 microtile = 0; 1728 microtile = 0;
1729 1729
1730 /* this might fail for zero-sized uploads - are those illegal? */
1731 if (!radeon_check_offset(dev_priv, tex->offset + image->height *
1732 blit_width - 1)) {
1733 DRM_ERROR("Invalid final destination offset\n");
1734 return -EINVAL;
1735 }
1736
1730 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width); 1737 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
1731 1738
1732 do { 1739 do {
@@ -1840,6 +1847,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1840 } 1847 }
1841 1848
1842#undef RADEON_COPY_MT 1849#undef RADEON_COPY_MT
1850 byte_offset = (image->y & ~2047) * blit_width;
1843 buf->file_priv = file_priv; 1851 buf->file_priv = file_priv;
1844 buf->used = size; 1852 buf->used = size;
1845 offset = dev_priv->gart_buffers_offset + buf->offset; 1853 offset = dev_priv->gart_buffers_offset + buf->offset;
@@ -1854,9 +1862,9 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1854 RADEON_DP_SRC_SOURCE_MEMORY | 1862 RADEON_DP_SRC_SOURCE_MEMORY |
1855 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); 1863 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1856 OUT_RING((spitch << 22) | (offset >> 10)); 1864 OUT_RING((spitch << 22) | (offset >> 10));
1857 OUT_RING((texpitch << 22) | (tex->offset >> 10)); 1865 OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
1858 OUT_RING(0); 1866 OUT_RING(0);
1859 OUT_RING((image->x << 16) | image->y); 1867 OUT_RING((image->x << 16) | (image->y % 2048));
1860 OUT_RING((image->width << 16) | height); 1868 OUT_RING((image->width << 16) | height);
1861 RADEON_WAIT_UNTIL_2D_IDLE(); 1869 RADEON_WAIT_UNTIL_2D_IDLE();
1862 ADVANCE_RING(); 1870 ADVANCE_RING();
@@ -3037,6 +3045,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
3037 case RADEON_PARAM_FB_LOCATION: 3045 case RADEON_PARAM_FB_LOCATION:
3038 value = radeon_read_fb_location(dev_priv); 3046 value = radeon_read_fb_location(dev_priv);
3039 break; 3047 break;
3048 case RADEON_PARAM_NUM_GB_PIPES:
3049 value = dev_priv->num_gb_pipes;
3050 break;
3040 default: 3051 default:
3041 DRM_DEBUG("Invalid parameter %d\n", param->param); 3052 DRM_DEBUG("Invalid parameter %d\n", param->param);
3042 return -EINVAL; 3053 return -EINVAL;
diff --git a/drivers/char/generic_nvram.c b/drivers/char/generic_nvram.c
index 2398e864c28d..a00869c650d5 100644
--- a/drivers/char/generic_nvram.c
+++ b/drivers/char/generic_nvram.c
@@ -133,7 +133,7 @@ static struct miscdevice nvram_dev = {
133 133
134int __init nvram_init(void) 134int __init nvram_init(void)
135{ 135{
136 printk(KERN_INFO "Macintosh non-volatile memory driver v%s\n", 136 printk(KERN_INFO "Generic non-volatile memory driver v%s\n",
137 NVRAM_VERSION); 137 NVRAM_VERSION);
138 return misc_register(&nvram_dev); 138 return misc_register(&nvram_dev);
139} 139}
diff --git a/drivers/char/hvc_xen.c b/drivers/char/hvc_xen.c
index dd68f8541c2d..db2ae4216279 100644
--- a/drivers/char/hvc_xen.c
+++ b/drivers/char/hvc_xen.c
@@ -39,9 +39,14 @@ static int xencons_irq;
39 39
40/* ------------------------------------------------------------------ */ 40/* ------------------------------------------------------------------ */
41 41
42static unsigned long console_pfn = ~0ul;
43
42static inline struct xencons_interface *xencons_interface(void) 44static inline struct xencons_interface *xencons_interface(void)
43{ 45{
44 return mfn_to_virt(xen_start_info->console.domU.mfn); 46 if (console_pfn == ~0ul)
47 return mfn_to_virt(xen_start_info->console.domU.mfn);
48 else
49 return __va(console_pfn << PAGE_SHIFT);
45} 50}
46 51
47static inline void notify_daemon(void) 52static inline void notify_daemon(void)
@@ -101,20 +106,32 @@ static int __init xen_init(void)
101{ 106{
102 struct hvc_struct *hp; 107 struct hvc_struct *hp;
103 108
104 if (!is_running_on_xen()) 109 if (!is_running_on_xen() ||
105 return 0; 110 is_initial_xendomain() ||
111 !xen_start_info->console.domU.evtchn)
112 return -ENODEV;
106 113
107 xencons_irq = bind_evtchn_to_irq(xen_start_info->console.domU.evtchn); 114 xencons_irq = bind_evtchn_to_irq(xen_start_info->console.domU.evtchn);
108 if (xencons_irq < 0) 115 if (xencons_irq < 0)
109 xencons_irq = 0 /* NO_IRQ */; 116 xencons_irq = 0; /* NO_IRQ */
117
110 hp = hvc_alloc(HVC_COOKIE, xencons_irq, &hvc_ops, 256); 118 hp = hvc_alloc(HVC_COOKIE, xencons_irq, &hvc_ops, 256);
111 if (IS_ERR(hp)) 119 if (IS_ERR(hp))
112 return PTR_ERR(hp); 120 return PTR_ERR(hp);
113 121
114 hvc = hp; 122 hvc = hp;
123
124 console_pfn = mfn_to_pfn(xen_start_info->console.domU.mfn);
125
115 return 0; 126 return 0;
116} 127}
117 128
129void xen_console_resume(void)
130{
131 if (xencons_irq)
132 rebind_evtchn_irq(xen_start_info->console.domU.evtchn, xencons_irq);
133}
134
118static void __exit xen_fini(void) 135static void __exit xen_fini(void)
119{ 136{
120 if (hvc) 137 if (hvc)
@@ -134,12 +151,28 @@ module_init(xen_init);
134module_exit(xen_fini); 151module_exit(xen_fini);
135console_initcall(xen_cons_init); 152console_initcall(xen_cons_init);
136 153
154static void raw_console_write(const char *str, int len)
155{
156 while(len > 0) {
157 int rc = HYPERVISOR_console_io(CONSOLEIO_write, len, (char *)str);
158 if (rc <= 0)
159 break;
160
161 str += rc;
162 len -= rc;
163 }
164}
165
166#ifdef CONFIG_EARLY_PRINTK
137static void xenboot_write_console(struct console *console, const char *string, 167static void xenboot_write_console(struct console *console, const char *string,
138 unsigned len) 168 unsigned len)
139{ 169{
140 unsigned int linelen, off = 0; 170 unsigned int linelen, off = 0;
141 const char *pos; 171 const char *pos;
142 172
173 raw_console_write(string, len);
174
175 write_console(0, "(early) ", 8);
143 while (off < len && NULL != (pos = strchr(string+off, '\n'))) { 176 while (off < len && NULL != (pos = strchr(string+off, '\n'))) {
144 linelen = pos-string+off; 177 linelen = pos-string+off;
145 if (off + linelen > len) 178 if (off + linelen > len)
@@ -155,5 +188,23 @@ static void xenboot_write_console(struct console *console, const char *string,
155struct console xenboot_console = { 188struct console xenboot_console = {
156 .name = "xenboot", 189 .name = "xenboot",
157 .write = xenboot_write_console, 190 .write = xenboot_write_console,
158 .flags = CON_PRINTBUFFER | CON_BOOT, 191 .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
159}; 192};
193#endif /* CONFIG_EARLY_PRINTK */
194
195void xen_raw_console_write(const char *str)
196{
197 raw_console_write(str, strlen(str));
198}
199
200void xen_raw_printk(const char *fmt, ...)
201{
202 static char buf[512];
203 va_list ap;
204
205 va_start(ap, fmt);
206 vsnprintf(buf, sizeof(buf), fmt, ap);
207 va_end(ap);
208
209 xen_raw_console_write(buf);
210}
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index 8d6c2089d2a8..efd0b4db7c8e 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -112,3 +112,12 @@ config HW_RANDOM_PASEMI
112 112
113 If unsure, say Y. 113 If unsure, say Y.
114 114
115config HW_RANDOM_VIRTIO
116 tristate "VirtIO Random Number Generator support"
117 depends on HW_RANDOM && VIRTIO
118 ---help---
119 This driver provides kernel-side support for the virtual Random Number
120 Generator hardware.
121
122 To compile this driver as a module, choose M here: the
123 module will be called virtio-rng. If unsure, say N.
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index c8b7300e2fb1..b4940ddbb35f 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_HW_RANDOM_VIA) += via-rng.o
11obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o 11obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o
12obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o 12obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o
13obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o 13obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
14obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
diff --git a/drivers/char/hw_random/intel-rng.c b/drivers/char/hw_random/intel-rng.c
index 5cc651ef75eb..27fdc0866496 100644
--- a/drivers/char/hw_random/intel-rng.c
+++ b/drivers/char/hw_random/intel-rng.c
@@ -273,7 +273,7 @@ static int __init intel_rng_hw_init(void *_intel_rng_hw)
273 if (mfc != INTEL_FWH_MANUFACTURER_CODE || 273 if (mfc != INTEL_FWH_MANUFACTURER_CODE ||
274 (dvc != INTEL_FWH_DEVICE_CODE_8M && 274 (dvc != INTEL_FWH_DEVICE_CODE_8M &&
275 dvc != INTEL_FWH_DEVICE_CODE_4M)) { 275 dvc != INTEL_FWH_DEVICE_CODE_4M)) {
276 printk(KERN_ERR PFX "FWH not detected\n"); 276 printk(KERN_NOTICE PFX "FWH not detected\n");
277 return -ENODEV; 277 return -ENODEV;
278 } 278 }
279 279
diff --git a/drivers/char/hw_random/virtio-rng.c b/drivers/char/hw_random/virtio-rng.c
new file mode 100644
index 000000000000..d0e563e4fc39
--- /dev/null
+++ b/drivers/char/hw_random/virtio-rng.c
@@ -0,0 +1,155 @@
1/*
2 * Randomness driver for virtio
3 * Copyright (C) 2007, 2008 Rusty Russell IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/err.h>
20#include <linux/hw_random.h>
21#include <linux/scatterlist.h>
22#include <linux/spinlock.h>
23#include <linux/virtio.h>
24#include <linux/virtio_rng.h>
25
26/* The host will fill any buffer we give it with sweet, sweet randomness. We
27 * give it 64 bytes at a time, and the hwrng framework takes it 4 bytes at a
28 * time. */
29#define RANDOM_DATA_SIZE 64
30
31static struct virtqueue *vq;
32static u32 *random_data;
33static unsigned int data_left;
34static DECLARE_COMPLETION(have_data);
35
36static void random_recv_done(struct virtqueue *vq)
37{
38 int len;
39
40 /* We never get spurious callbacks. */
41 if (!vq->vq_ops->get_buf(vq, &len))
42 BUG();
43
44 data_left = len / sizeof(random_data[0]);
45 complete(&have_data);
46}
47
48static void register_buffer(void)
49{
50 struct scatterlist sg;
51
52 sg_init_one(&sg, random_data, RANDOM_DATA_SIZE);
53 /* There should always be room for one buffer. */
54 if (vq->vq_ops->add_buf(vq, &sg, 0, 1, random_data) != 0)
55 BUG();
56 vq->vq_ops->kick(vq);
57}
58
59/* At least we don't udelay() in a loop like some other drivers. */
60static int virtio_data_present(struct hwrng *rng, int wait)
61{
62 if (data_left)
63 return 1;
64
65 if (!wait)
66 return 0;
67
68 wait_for_completion(&have_data);
69 return 1;
70}
71
72/* virtio_data_present() must have succeeded before this is called. */
73static int virtio_data_read(struct hwrng *rng, u32 *data)
74{
75 BUG_ON(!data_left);
76
77 *data = random_data[--data_left];
78
79 if (!data_left) {
80 init_completion(&have_data);
81 register_buffer();
82 }
83 return sizeof(*data);
84}
85
86static struct hwrng virtio_hwrng = {
87 .name = "virtio",
88 .data_present = virtio_data_present,
89 .data_read = virtio_data_read,
90};
91
92static int virtrng_probe(struct virtio_device *vdev)
93{
94 int err;
95
96 /* We expect a single virtqueue. */
97 vq = vdev->config->find_vq(vdev, 0, random_recv_done);
98 if (IS_ERR(vq))
99 return PTR_ERR(vq);
100
101 err = hwrng_register(&virtio_hwrng);
102 if (err) {
103 vdev->config->del_vq(vq);
104 return err;
105 }
106
107 register_buffer();
108 return 0;
109}
110
111static void virtrng_remove(struct virtio_device *vdev)
112{
113 vdev->config->reset(vdev);
114 hwrng_unregister(&virtio_hwrng);
115 vdev->config->del_vq(vq);
116}
117
118static struct virtio_device_id id_table[] = {
119 { VIRTIO_ID_RNG, VIRTIO_DEV_ANY_ID },
120 { 0 },
121};
122
123static struct virtio_driver virtio_rng = {
124 .driver.name = KBUILD_MODNAME,
125 .driver.owner = THIS_MODULE,
126 .id_table = id_table,
127 .probe = virtrng_probe,
128 .remove = __devexit_p(virtrng_remove),
129};
130
131static int __init init(void)
132{
133 int err;
134
135 random_data = kmalloc(RANDOM_DATA_SIZE, GFP_KERNEL);
136 if (!random_data)
137 return -ENOMEM;
138
139 err = register_virtio_driver(&virtio_rng);
140 if (err)
141 kfree(random_data);
142 return err;
143}
144
145static void __exit fini(void)
146{
147 kfree(random_data);
148 unregister_virtio_driver(&virtio_rng);
149}
150module_init(init);
151module_exit(fini);
152
153MODULE_DEVICE_TABLE(virtio, id_table);
154MODULE_DESCRIPTION("Virtio random number driver");
155MODULE_LICENSE("GPL");
diff --git a/drivers/char/ip2/Makefile b/drivers/char/ip2/Makefile
index 6bfe2543ddc2..939618f62fe1 100644
--- a/drivers/char/ip2/Makefile
+++ b/drivers/char/ip2/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the Computone IntelliPort Plus Driver 2# Makefile for the Computone IntelliPort Plus Driver
3# 3#
4 4
5obj-$(CONFIG_COMPUTONE) += ip2.o ip2main.o 5obj-$(CONFIG_COMPUTONE) += ip2.o
6 6
7ip2-objs := ip2base.o 7ip2-objs := ip2base.o ip2main.o
8 8
diff --git a/drivers/char/ip2/ip2main.c b/drivers/char/ip2/ip2main.c
index 70957acaa960..c12cf8fc4be0 100644
--- a/drivers/char/ip2/ip2main.c
+++ b/drivers/char/ip2/ip2main.c
@@ -346,27 +346,6 @@ have_requested_irq( char irq )
346} 346}
347 347
348/******************************************************************************/ 348/******************************************************************************/
349/* Function: init_module() */
350/* Parameters: None */
351/* Returns: Success (0) */
352/* */
353/* Description: */
354/* This is a required entry point for an installable module. It simply calls */
355/* the driver initialisation function and returns what it returns. */
356/******************************************************************************/
357#ifdef MODULE
358static int __init
359ip2_init_module(void)
360{
361#ifdef IP2DEBUG_INIT
362 printk (KERN_DEBUG "Loading module ...\n" );
363#endif
364 return 0;
365}
366module_init(ip2_init_module);
367#endif /* MODULE */
368
369/******************************************************************************/
370/* Function: cleanup_module() */ 349/* Function: cleanup_module() */
371/* Parameters: None */ 350/* Parameters: None */
372/* Returns: Nothing */ 351/* Returns: Nothing */
@@ -779,8 +758,6 @@ out:
779 return err; 758 return err;
780} 759}
781 760
782EXPORT_SYMBOL(ip2_loadmain);
783
784/******************************************************************************/ 761/******************************************************************************/
785/* Function: ip2_init_board() */ 762/* Function: ip2_init_board() */
786/* Parameters: Index of board in configuration structure */ 763/* Parameters: Index of board in configuration structure */
diff --git a/drivers/char/keyboard.c b/drivers/char/keyboard.c
index 7f7e798c1384..d9a0a53c842d 100644
--- a/drivers/char/keyboard.c
+++ b/drivers/char/keyboard.c
@@ -677,12 +677,7 @@ static void k_deadunicode(struct vc_data *vc, unsigned int value, char up_flag)
677 677
678static void k_self(struct vc_data *vc, unsigned char value, char up_flag) 678static void k_self(struct vc_data *vc, unsigned char value, char up_flag)
679{ 679{
680 unsigned int uni; 680 k_unicode(vc, conv_8bit_to_uni(value), up_flag);
681 if (kbd->kbdmode == VC_UNICODE)
682 uni = value;
683 else
684 uni = conv_8bit_to_uni(value);
685 k_unicode(vc, uni, up_flag);
686} 681}
687 682
688static void k_dead2(struct vc_data *vc, unsigned char value, char up_flag) 683static void k_dead2(struct vc_data *vc, unsigned char value, char up_flag)
diff --git a/drivers/char/pcmcia/ipwireless/hardware.c b/drivers/char/pcmcia/ipwireless/hardware.c
index fa9d3c945f31..ba6340ae98af 100644
--- a/drivers/char/pcmcia/ipwireless/hardware.c
+++ b/drivers/char/pcmcia/ipwireless/hardware.c
@@ -251,10 +251,11 @@ struct ipw_hardware {
251 int init_loops; 251 int init_loops;
252 struct timer_list setup_timer; 252 struct timer_list setup_timer;
253 253
254 /* Flag if hw is ready to send next packet */
254 int tx_ready; 255 int tx_ready;
255 struct list_head tx_queue[NL_NUM_OF_PRIORITIES]; 256 /* Count of pending packets to be sent */
256 /* True if any packets are queued for transmission */
257 int tx_queued; 257 int tx_queued;
258 struct list_head tx_queue[NL_NUM_OF_PRIORITIES];
258 259
259 int rx_bytes_queued; 260 int rx_bytes_queued;
260 struct list_head rx_queue; 261 struct list_head rx_queue;
@@ -404,6 +405,8 @@ static int do_send_fragment(struct ipw_hardware *hw, const unsigned char *data,
404 405
405 spin_lock_irqsave(&hw->spinlock, flags); 406 spin_lock_irqsave(&hw->spinlock, flags);
406 407
408 hw->tx_ready = 0;
409
407 if (hw->hw_version == HW_VERSION_1) { 410 if (hw->hw_version == HW_VERSION_1) {
408 outw((unsigned short) length, hw->base_port + IODWR); 411 outw((unsigned short) length, hw->base_port + IODWR);
409 412
@@ -492,6 +495,7 @@ static int do_send_packet(struct ipw_hardware *hw, struct ipw_tx_packet *packet)
492 495
493 spin_lock_irqsave(&hw->spinlock, flags); 496 spin_lock_irqsave(&hw->spinlock, flags);
494 list_add(&packet->queue, &hw->tx_queue[0]); 497 list_add(&packet->queue, &hw->tx_queue[0]);
498 hw->tx_queued++;
495 spin_unlock_irqrestore(&hw->spinlock, flags); 499 spin_unlock_irqrestore(&hw->spinlock, flags);
496 } else { 500 } else {
497 if (packet->packet_callback) 501 if (packet->packet_callback)
@@ -949,12 +953,10 @@ static int send_pending_packet(struct ipw_hardware *hw, int priority_limit)
949 unsigned long flags; 953 unsigned long flags;
950 954
951 spin_lock_irqsave(&hw->spinlock, flags); 955 spin_lock_irqsave(&hw->spinlock, flags);
952 if (hw->tx_queued && hw->tx_ready != 0) { 956 if (hw->tx_queued && hw->tx_ready) {
953 int priority; 957 int priority;
954 struct ipw_tx_packet *packet = NULL; 958 struct ipw_tx_packet *packet = NULL;
955 959
956 hw->tx_ready--;
957
958 /* Pick a packet */ 960 /* Pick a packet */
959 for (priority = 0; priority < priority_limit; priority++) { 961 for (priority = 0; priority < priority_limit; priority++) {
960 if (!list_empty(&hw->tx_queue[priority])) { 962 if (!list_empty(&hw->tx_queue[priority])) {
@@ -963,6 +965,7 @@ static int send_pending_packet(struct ipw_hardware *hw, int priority_limit)
963 struct ipw_tx_packet, 965 struct ipw_tx_packet,
964 queue); 966 queue);
965 967
968 hw->tx_queued--;
966 list_del(&packet->queue); 969 list_del(&packet->queue);
967 970
968 break; 971 break;
@@ -973,6 +976,7 @@ static int send_pending_packet(struct ipw_hardware *hw, int priority_limit)
973 spin_unlock_irqrestore(&hw->spinlock, flags); 976 spin_unlock_irqrestore(&hw->spinlock, flags);
974 return 0; 977 return 0;
975 } 978 }
979
976 spin_unlock_irqrestore(&hw->spinlock, flags); 980 spin_unlock_irqrestore(&hw->spinlock, flags);
977 981
978 /* Send */ 982 /* Send */
@@ -1063,7 +1067,7 @@ static irqreturn_t ipwireless_handle_v1_interrupt(int irq,
1063 if (irqn & IR_TXINTR) { 1067 if (irqn & IR_TXINTR) {
1064 ack |= IR_TXINTR; 1068 ack |= IR_TXINTR;
1065 spin_lock_irqsave(&hw->spinlock, flags); 1069 spin_lock_irqsave(&hw->spinlock, flags);
1066 hw->tx_ready++; 1070 hw->tx_ready = 1;
1067 spin_unlock_irqrestore(&hw->spinlock, flags); 1071 spin_unlock_irqrestore(&hw->spinlock, flags);
1068 } 1072 }
1069 /* Received data */ 1073 /* Received data */
@@ -1170,7 +1174,7 @@ static irqreturn_t ipwireless_handle_v2_v3_interrupt(int irq,
1170 if (memrxdone & MEMRX_RX_DONE) { 1174 if (memrxdone & MEMRX_RX_DONE) {
1171 writew(0, &hw->memory_info_regs->memreg_rx_done); 1175 writew(0, &hw->memory_info_regs->memreg_rx_done);
1172 spin_lock_irqsave(&hw->spinlock, flags); 1176 spin_lock_irqsave(&hw->spinlock, flags);
1173 hw->tx_ready++; 1177 hw->tx_ready = 1;
1174 spin_unlock_irqrestore(&hw->spinlock, flags); 1178 spin_unlock_irqrestore(&hw->spinlock, flags);
1175 tx = 1; 1179 tx = 1;
1176 } 1180 }
@@ -1234,7 +1238,7 @@ static void send_packet(struct ipw_hardware *hw, int priority,
1234 1238
1235 spin_lock_irqsave(&hw->spinlock, flags); 1239 spin_lock_irqsave(&hw->spinlock, flags);
1236 list_add_tail(&packet->queue, &hw->tx_queue[priority]); 1240 list_add_tail(&packet->queue, &hw->tx_queue[priority]);
1237 hw->tx_queued = 1; 1241 hw->tx_queued++;
1238 spin_unlock_irqrestore(&hw->spinlock, flags); 1242 spin_unlock_irqrestore(&hw->spinlock, flags);
1239 1243
1240 flush_packets_to_hw(hw); 1244 flush_packets_to_hw(hw);
diff --git a/drivers/char/sysrq.c b/drivers/char/sysrq.c
index 9e9bad8bdcf4..dbce1263bdff 100644
--- a/drivers/char/sysrq.c
+++ b/drivers/char/sysrq.c
@@ -402,6 +402,7 @@ static struct sysrq_key_op *sysrq_key_table[36] = {
402 &sysrq_showstate_blocked_op, /* w */ 402 &sysrq_showstate_blocked_op, /* w */
403 /* x: May be registered on ppc/powerpc for xmon */ 403 /* x: May be registered on ppc/powerpc for xmon */
404 NULL, /* x */ 404 NULL, /* x */
405 /* y: May be registered on sparc64 for global register dump */
405 NULL, /* y */ 406 NULL, /* y */
406 NULL /* z */ 407 NULL /* z */
407}; 408};
diff --git a/drivers/char/tty_io.c b/drivers/char/tty_io.c
index e94bee032314..750131010af0 100644
--- a/drivers/char/tty_io.c
+++ b/drivers/char/tty_io.c
@@ -3322,7 +3322,7 @@ static int send_break(struct tty_struct *tty, unsigned int duration)
3322 msleep_interruptible(duration); 3322 msleep_interruptible(duration);
3323 tty->ops->break_ctl(tty, 0); 3323 tty->ops->break_ctl(tty, 0);
3324 tty_write_unlock(tty); 3324 tty_write_unlock(tty);
3325 if (!signal_pending(current)) 3325 if (signal_pending(current))
3326 return -EINTR; 3326 return -EINTR;
3327 return 0; 3327 return 0;
3328} 3328}
diff --git a/drivers/char/tty_ioctl.c b/drivers/char/tty_ioctl.c
index b1a757a5ee27..8f81139d6194 100644
--- a/drivers/char/tty_ioctl.c
+++ b/drivers/char/tty_ioctl.c
@@ -981,16 +981,9 @@ EXPORT_SYMBOL_GPL(tty_perform_flush);
981int n_tty_ioctl(struct tty_struct *tty, struct file *file, 981int n_tty_ioctl(struct tty_struct *tty, struct file *file,
982 unsigned int cmd, unsigned long arg) 982 unsigned int cmd, unsigned long arg)
983{ 983{
984 struct tty_struct *real_tty;
985 unsigned long flags; 984 unsigned long flags;
986 int retval; 985 int retval;
987 986
988 if (tty->driver->type == TTY_DRIVER_TYPE_PTY &&
989 tty->driver->subtype == PTY_TYPE_MASTER)
990 real_tty = tty->link;
991 else
992 real_tty = tty;
993
994 switch (cmd) { 987 switch (cmd) {
995 case TCXONC: 988 case TCXONC:
996 retval = tty_check_change(tty); 989 retval = tty_check_change(tty);
diff --git a/drivers/char/viocons.c b/drivers/char/viocons.c
index 3d3e1c2b310f..65fb848e1cce 100644
--- a/drivers/char/viocons.c
+++ b/drivers/char/viocons.c
@@ -7,7 +7,7 @@
7 * Authors: Dave Boutcher <boutcher@us.ibm.com> 7 * Authors: Dave Boutcher <boutcher@us.ibm.com>
8 * Ryan Arnold <ryanarn@us.ibm.com> 8 * Ryan Arnold <ryanarn@us.ibm.com>
9 * Colin Devilbiss <devilbis@us.ibm.com> 9 * Colin Devilbiss <devilbis@us.ibm.com>
10 * Stephen Rothwell <sfr@au1.ibm.com> 10 * Stephen Rothwell
11 * 11 *
12 * (C) Copyright 2000, 2001, 2002, 2003, 2004 IBM Corporation 12 * (C) Copyright 2000, 2001, 2002, 2003, 2004 IBM Corporation
13 * 13 *
diff --git a/drivers/char/viotape.c b/drivers/char/viotape.c
index 58aad63831f4..c39ddaff5e8f 100644
--- a/drivers/char/viotape.c
+++ b/drivers/char/viotape.c
@@ -6,7 +6,7 @@
6 * Authors: Dave Boutcher <boutcher@us.ibm.com> 6 * Authors: Dave Boutcher <boutcher@us.ibm.com>
7 * Ryan Arnold <ryanarn@us.ibm.com> 7 * Ryan Arnold <ryanarn@us.ibm.com>
8 * Colin Devilbiss <devilbis@us.ibm.com> 8 * Colin Devilbiss <devilbis@us.ibm.com>
9 * Stephen Rothwell <sfr@au1.ibm.com> 9 * Stephen Rothwell
10 * 10 *
11 * (C) Copyright 2000-2004 IBM Corporation 11 * (C) Copyright 2000-2004 IBM Corporation
12 * 12 *
diff --git a/drivers/char/vt.c b/drivers/char/vt.c
index fa1ffbf2c621..935f1c207a1f 100644
--- a/drivers/char/vt.c
+++ b/drivers/char/vt.c
@@ -434,7 +434,7 @@ static void update_attr(struct vc_data *vc)
434 vc->vc_blink, vc->vc_underline, 434 vc->vc_blink, vc->vc_underline,
435 vc->vc_reverse ^ vc->vc_decscnm, vc->vc_italic); 435 vc->vc_reverse ^ vc->vc_decscnm, vc->vc_italic);
436 vc->vc_video_erase_char = (build_attr(vc, vc->vc_color, 1, vc->vc_blink, 0, vc->vc_decscnm, 0) << 8) | ' '; 436 vc->vc_video_erase_char = (build_attr(vc, vc->vc_color, 1, vc->vc_blink, 0, vc->vc_decscnm, 0) << 8) | ' ';
437 vc->vc_scrl_erase_char = (build_attr(vc, vc->vc_def_color, 1, false, false, false, false) << 8) | ' '; 437 vc->vc_scrl_erase_char = (build_attr(vc, vc->vc_def_color, 1, false, false, vc->vc_decscnm, false) << 8) | ' ';
438} 438}
439 439
440/* Note: inverting the screen twice should revert to the original state */ 440/* Note: inverting the screen twice should revert to the original state */
@@ -909,7 +909,7 @@ int vc_resize(struct vc_data *vc, unsigned int cols, unsigned int lines)
909 909
910 if (vc->vc_tty) { 910 if (vc->vc_tty) {
911 struct winsize ws, *cws = &vc->vc_tty->winsize; 911 struct winsize ws, *cws = &vc->vc_tty->winsize;
912 unsigned long flags; 912 struct pid *pgrp = NULL;
913 913
914 memset(&ws, 0, sizeof(ws)); 914 memset(&ws, 0, sizeof(ws));
915 ws.ws_row = vc->vc_rows; 915 ws.ws_row = vc->vc_rows;
@@ -917,11 +917,14 @@ int vc_resize(struct vc_data *vc, unsigned int cols, unsigned int lines)
917 ws.ws_ypixel = vc->vc_scan_lines; 917 ws.ws_ypixel = vc->vc_scan_lines;
918 918
919 mutex_lock(&vc->vc_tty->termios_mutex); 919 mutex_lock(&vc->vc_tty->termios_mutex);
920 spin_lock_irqsave(&vc->vc_tty->ctrl_lock, flags); 920 spin_lock_irq(&vc->vc_tty->ctrl_lock);
921 if ((ws.ws_row != cws->ws_row || ws.ws_col != cws->ws_col) && 921 if ((ws.ws_row != cws->ws_row || ws.ws_col != cws->ws_col))
922 vc->vc_tty->pgrp) 922 pgrp = get_pid(vc->vc_tty->pgrp);
923 spin_unlock_irq(&vc->vc_tty->ctrl_lock);
924 if (pgrp) {
923 kill_pgrp(vc->vc_tty->pgrp, SIGWINCH, 1); 925 kill_pgrp(vc->vc_tty->pgrp, SIGWINCH, 1);
924 spin_unlock_irqrestore(&vc->vc_tty->ctrl_lock, flags); 926 put_pid(pgrp);
927 }
925 *cws = ws; 928 *cws = ws;
926 mutex_unlock(&vc->vc_tty->termios_mutex); 929 mutex_unlock(&vc->vc_tty->termios_mutex);
927 } 930 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 10:39:25 -0500