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path: root/drivers/char/vr41xx_rtc.c
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-rw-r--r--drivers/char/vr41xx_rtc.c717
1 files changed, 0 insertions, 717 deletions
diff --git a/drivers/char/vr41xx_rtc.c b/drivers/char/vr41xx_rtc.c
deleted file mode 100644
index b109d9a502d6..000000000000
--- a/drivers/char/vr41xx_rtc.c
+++ /dev/null
@@ -1,717 +0,0 @@
1/*
2 * Driver for NEC VR4100 series Real Time Clock unit.
3 *
4 * Copyright (C) 2003-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/platform_device.h>
21#include <linux/fs.h>
22#include <linux/init.h>
23#include <linux/ioport.h>
24#include <linux/irq.h>
25#include <linux/mc146818rtc.h>
26#include <linux/miscdevice.h>
27#include <linux/module.h>
28#include <linux/poll.h>
29#include <linux/rtc.h>
30#include <linux/spinlock.h>
31#include <linux/types.h>
32#include <linux/wait.h>
33
34#include <asm/div64.h>
35#include <asm/io.h>
36#include <asm/time.h>
37#include <asm/uaccess.h>
38#include <asm/vr41xx/vr41xx.h>
39
40MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
41MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
42MODULE_LICENSE("GPL");
43
44#define RTC1_TYPE1_START 0x0b0000c0UL
45#define RTC1_TYPE1_END 0x0b0000dfUL
46#define RTC2_TYPE1_START 0x0b0001c0UL
47#define RTC2_TYPE1_END 0x0b0001dfUL
48
49#define RTC1_TYPE2_START 0x0f000100UL
50#define RTC1_TYPE2_END 0x0f00011fUL
51#define RTC2_TYPE2_START 0x0f000120UL
52#define RTC2_TYPE2_END 0x0f00013fUL
53
54#define RTC1_SIZE 0x20
55#define RTC2_SIZE 0x20
56
57/* RTC 1 registers */
58#define ETIMELREG 0x00
59#define ETIMEMREG 0x02
60#define ETIMEHREG 0x04
61/* RFU */
62#define ECMPLREG 0x08
63#define ECMPMREG 0x0a
64#define ECMPHREG 0x0c
65/* RFU */
66#define RTCL1LREG 0x10
67#define RTCL1HREG 0x12
68#define RTCL1CNTLREG 0x14
69#define RTCL1CNTHREG 0x16
70#define RTCL2LREG 0x18
71#define RTCL2HREG 0x1a
72#define RTCL2CNTLREG 0x1c
73#define RTCL2CNTHREG 0x1e
74
75/* RTC 2 registers */
76#define TCLKLREG 0x00
77#define TCLKHREG 0x02
78#define TCLKCNTLREG 0x04
79#define TCLKCNTHREG 0x06
80/* RFU */
81#define RTCINTREG 0x1e
82 #define TCLOCK_INT 0x08
83 #define RTCLONG2_INT 0x04
84 #define RTCLONG1_INT 0x02
85 #define ELAPSEDTIME_INT 0x01
86
87#define RTC_FREQUENCY 32768
88#define MAX_PERIODIC_RATE 6553
89#define MAX_USER_PERIODIC_RATE 64
90
91static void __iomem *rtc1_base;
92static void __iomem *rtc2_base;
93
94#define rtc1_read(offset) readw(rtc1_base + (offset))
95#define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
96
97#define rtc2_read(offset) readw(rtc2_base + (offset))
98#define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
99
100static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
101
102static spinlock_t rtc_task_lock;
103static wait_queue_head_t rtc_wait;
104static unsigned long rtc_irq_data;
105static struct fasync_struct *rtc_async_queue;
106static rtc_task_t *rtc_callback;
107static char rtc_name[] = "RTC";
108static unsigned long periodic_frequency;
109static unsigned long periodic_count;
110
111typedef enum {
112 RTC_RELEASE,
113 RTC_OPEN,
114} rtc_status_t;
115
116static rtc_status_t rtc_status;
117
118typedef enum {
119 FUNCTION_RTC_IOCTL,
120 FUNCTION_RTC_CONTROL,
121} rtc_callfrom_t;
122
123struct resource rtc_resource[2] = {
124 { .name = rtc_name,
125 .flags = IORESOURCE_MEM, },
126 { .name = rtc_name,
127 .flags = IORESOURCE_MEM, },
128};
129
130static inline unsigned long read_elapsed_second(void)
131{
132 unsigned long first_low, first_mid, first_high;
133 unsigned long second_low, second_mid, second_high;
134
135 do {
136 first_low = rtc1_read(ETIMELREG);
137 first_mid = rtc1_read(ETIMEMREG);
138 first_high = rtc1_read(ETIMEHREG);
139 second_low = rtc1_read(ETIMELREG);
140 second_mid = rtc1_read(ETIMEMREG);
141 second_high = rtc1_read(ETIMEHREG);
142 } while (first_low != second_low || first_mid != second_mid ||
143 first_high != second_high);
144
145 return (first_high << 17) | (first_mid << 1) | (first_low >> 15);
146}
147
148static inline void write_elapsed_second(unsigned long sec)
149{
150 spin_lock_irq(&rtc_lock);
151
152 rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
153 rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
154 rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
155
156 spin_unlock_irq(&rtc_lock);
157}
158
159static void set_alarm(struct rtc_time *time)
160{
161 unsigned long alarm_sec;
162
163 alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
164 time->tm_hour, time->tm_min, time->tm_sec);
165
166 spin_lock_irq(&rtc_lock);
167
168 rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
169 rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
170 rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
171
172 spin_unlock_irq(&rtc_lock);
173}
174
175static void read_alarm(struct rtc_time *time)
176{
177 unsigned long low, mid, high;
178
179 spin_lock_irq(&rtc_lock);
180
181 low = rtc1_read(ECMPLREG);
182 mid = rtc1_read(ECMPMREG);
183 high = rtc1_read(ECMPHREG);
184
185 spin_unlock_irq(&rtc_lock);
186
187 to_tm((high << 17) | (mid << 1) | (low >> 15), time);
188 time->tm_year -= 1900;
189}
190
191static void read_time(struct rtc_time *time)
192{
193 unsigned long epoch_sec, elapsed_sec;
194
195 epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
196 elapsed_sec = read_elapsed_second();
197
198 to_tm(epoch_sec + elapsed_sec, time);
199 time->tm_year -= 1900;
200}
201
202static void set_time(struct rtc_time *time)
203{
204 unsigned long epoch_sec, current_sec;
205
206 epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
207 current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
208 time->tm_hour, time->tm_min, time->tm_sec);
209
210 write_elapsed_second(current_sec - epoch_sec);
211}
212
213static ssize_t rtc_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
214{
215 DECLARE_WAITQUEUE(wait, current);
216 unsigned long irq_data;
217 int retval = 0;
218
219 if (count != sizeof(unsigned int) && count != sizeof(unsigned long))
220 return -EINVAL;
221
222 add_wait_queue(&rtc_wait, &wait);
223
224 do {
225 __set_current_state(TASK_INTERRUPTIBLE);
226
227 spin_lock_irq(&rtc_lock);
228 irq_data = rtc_irq_data;
229 rtc_irq_data = 0;
230 spin_unlock_irq(&rtc_lock);
231
232 if (irq_data != 0)
233 break;
234
235 if (file->f_flags & O_NONBLOCK) {
236 retval = -EAGAIN;
237 break;
238 }
239
240 if (signal_pending(current)) {
241 retval = -ERESTARTSYS;
242 break;
243 }
244 } while (1);
245
246 if (retval == 0) {
247 if (count == sizeof(unsigned int)) {
248 retval = put_user(irq_data, (unsigned int __user *)buf);
249 if (retval == 0)
250 retval = sizeof(unsigned int);
251 } else {
252 retval = put_user(irq_data, (unsigned long __user *)buf);
253 if (retval == 0)
254 retval = sizeof(unsigned long);
255 }
256
257 }
258
259 __set_current_state(TASK_RUNNING);
260 remove_wait_queue(&rtc_wait, &wait);
261
262 return retval;
263}
264
265static unsigned int rtc_poll(struct file *file, struct poll_table_struct *table)
266{
267 poll_wait(file, &rtc_wait, table);
268
269 if (rtc_irq_data != 0)
270 return POLLIN | POLLRDNORM;
271
272 return 0;
273}
274
275static int rtc_do_ioctl(unsigned int cmd, unsigned long arg, rtc_callfrom_t from)
276{
277 struct rtc_time time;
278 unsigned long count;
279
280 switch (cmd) {
281 case RTC_AIE_ON:
282 enable_irq(ELAPSEDTIME_IRQ);
283 break;
284 case RTC_AIE_OFF:
285 disable_irq(ELAPSEDTIME_IRQ);
286 break;
287 case RTC_PIE_ON:
288 enable_irq(RTCLONG1_IRQ);
289 break;
290 case RTC_PIE_OFF:
291 disable_irq(RTCLONG1_IRQ);
292 break;
293 case RTC_ALM_SET:
294 if (copy_from_user(&time, (struct rtc_time __user *)arg,
295 sizeof(struct rtc_time)))
296 return -EFAULT;
297
298 set_alarm(&time);
299 break;
300 case RTC_ALM_READ:
301 memset(&time, 0, sizeof(struct rtc_time));
302 read_alarm(&time);
303 break;
304 case RTC_RD_TIME:
305 memset(&time, 0, sizeof(struct rtc_time));
306 read_time(&time);
307 if (copy_to_user((void __user *)arg, &time, sizeof(struct rtc_time)))
308 return -EFAULT;
309 break;
310 case RTC_SET_TIME:
311 if (capable(CAP_SYS_TIME) == 0)
312 return -EACCES;
313
314 if (copy_from_user(&time, (struct rtc_time __user *)arg,
315 sizeof(struct rtc_time)))
316 return -EFAULT;
317
318 set_time(&time);
319 break;
320 case RTC_IRQP_READ:
321 return put_user(periodic_frequency, (unsigned long __user *)arg);
322 break;
323 case RTC_IRQP_SET:
324 if (arg > MAX_PERIODIC_RATE)
325 return -EINVAL;
326
327 if (from == FUNCTION_RTC_IOCTL && arg > MAX_USER_PERIODIC_RATE &&
328 capable(CAP_SYS_RESOURCE) == 0)
329 return -EACCES;
330
331 periodic_frequency = arg;
332
333 count = RTC_FREQUENCY;
334 do_div(count, arg);
335
336 periodic_count = count;
337
338 spin_lock_irq(&rtc_lock);
339
340 rtc1_write(RTCL1LREG, count);
341 rtc1_write(RTCL1HREG, count >> 16);
342
343 spin_unlock_irq(&rtc_lock);
344 break;
345 case RTC_EPOCH_READ:
346 return put_user(epoch, (unsigned long __user *)arg);
347 case RTC_EPOCH_SET:
348 /* Doesn't support before 1900 */
349 if (arg < 1900)
350 return -EINVAL;
351
352 if (capable(CAP_SYS_TIME) == 0)
353 return -EACCES;
354
355 epoch = arg;
356 break;
357 default:
358 return -EINVAL;
359 }
360
361 return 0;
362}
363
364static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
365 unsigned long arg)
366{
367 return rtc_do_ioctl(cmd, arg, FUNCTION_RTC_IOCTL);
368}
369
370static int rtc_open(struct inode *inode, struct file *file)
371{
372 spin_lock_irq(&rtc_lock);
373
374 if (rtc_status == RTC_OPEN) {
375 spin_unlock_irq(&rtc_lock);
376 return -EBUSY;
377 }
378
379 rtc_status = RTC_OPEN;
380 rtc_irq_data = 0;
381
382 spin_unlock_irq(&rtc_lock);
383
384 return 0;
385}
386
387static int rtc_release(struct inode *inode, struct file *file)
388{
389 if (file->f_flags & FASYNC)
390 (void)fasync_helper(-1, file, 0, &rtc_async_queue);
391
392 spin_lock_irq(&rtc_lock);
393
394 rtc1_write(ECMPLREG, 0);
395 rtc1_write(ECMPMREG, 0);
396 rtc1_write(ECMPHREG, 0);
397 rtc1_write(RTCL1LREG, 0);
398 rtc1_write(RTCL1HREG, 0);
399
400 rtc_status = RTC_RELEASE;
401
402 spin_unlock_irq(&rtc_lock);
403
404 disable_irq(ELAPSEDTIME_IRQ);
405 disable_irq(RTCLONG1_IRQ);
406
407 return 0;
408}
409
410static int rtc_fasync(int fd, struct file *file, int on)
411{
412 return fasync_helper(fd, file, on, &rtc_async_queue);
413}
414
415static struct file_operations rtc_fops = {
416 .owner = THIS_MODULE,
417 .llseek = no_llseek,
418 .read = rtc_read,
419 .poll = rtc_poll,
420 .ioctl = rtc_ioctl,
421 .open = rtc_open,
422 .release = rtc_release,
423 .fasync = rtc_fasync,
424};
425
426static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id, struct pt_regs *regs)
427{
428 spin_lock(&rtc_lock);
429 rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
430
431 rtc_irq_data += 0x100;
432 rtc_irq_data &= ~0xff;
433 rtc_irq_data |= RTC_AF;
434 spin_unlock(&rtc_lock);
435
436 spin_lock(&rtc_lock);
437 if (rtc_callback)
438 rtc_callback->func(rtc_callback->private_data);
439 spin_unlock(&rtc_lock);
440
441 wake_up_interruptible(&rtc_wait);
442
443 kill_fasync(&rtc_async_queue, SIGIO, POLL_IN);
444
445 return IRQ_HANDLED;
446}
447
448static irqreturn_t rtclong1_interrupt(int irq, void *dev_id, struct pt_regs *regs)
449{
450 unsigned long count = periodic_count;
451
452 spin_lock(&rtc_lock);
453 rtc2_write(RTCINTREG, RTCLONG1_INT);
454
455 rtc1_write(RTCL1LREG, count);
456 rtc1_write(RTCL1HREG, count >> 16);
457
458 rtc_irq_data += 0x100;
459 rtc_irq_data &= ~0xff;
460 rtc_irq_data |= RTC_PF;
461 spin_unlock(&rtc_lock);
462
463 spin_lock(&rtc_task_lock);
464 if (rtc_callback)
465 rtc_callback->func(rtc_callback->private_data);
466 spin_unlock(&rtc_task_lock);
467
468 wake_up_interruptible(&rtc_wait);
469
470 kill_fasync(&rtc_async_queue, SIGIO, POLL_IN);
471
472 return IRQ_HANDLED;
473}
474
475int rtc_register(rtc_task_t *task)
476{
477 if (task == NULL || task->func == NULL)
478 return -EINVAL;
479
480 spin_lock_irq(&rtc_lock);
481 if (rtc_status == RTC_OPEN) {
482 spin_unlock_irq(&rtc_lock);
483 return -EBUSY;
484 }
485
486 spin_lock(&rtc_task_lock);
487 if (rtc_callback != NULL) {
488 spin_unlock(&rtc_task_lock);
489 spin_unlock_irq(&rtc_task_lock);
490 return -EBUSY;
491 }
492
493 rtc_callback = task;
494 spin_unlock(&rtc_task_lock);
495
496 rtc_status = RTC_OPEN;
497
498 spin_unlock_irq(&rtc_lock);
499
500 return 0;
501}
502
503EXPORT_SYMBOL_GPL(rtc_register);
504
505int rtc_unregister(rtc_task_t *task)
506{
507 spin_lock_irq(&rtc_task_lock);
508 if (task == NULL || rtc_callback != task) {
509 spin_unlock_irq(&rtc_task_lock);
510 return -ENXIO;
511 }
512
513 spin_lock(&rtc_lock);
514
515 rtc1_write(ECMPLREG, 0);
516 rtc1_write(ECMPMREG, 0);
517 rtc1_write(ECMPHREG, 0);
518 rtc1_write(RTCL1LREG, 0);
519 rtc1_write(RTCL1HREG, 0);
520
521 rtc_status = RTC_RELEASE;
522
523 spin_unlock(&rtc_lock);
524
525 rtc_callback = NULL;
526
527 spin_unlock_irq(&rtc_task_lock);
528
529 disable_irq(ELAPSEDTIME_IRQ);
530 disable_irq(RTCLONG1_IRQ);
531
532 return 0;
533}
534
535EXPORT_SYMBOL_GPL(rtc_unregister);
536
537int rtc_control(rtc_task_t *task, unsigned int cmd, unsigned long arg)
538{
539 int retval = 0;
540
541 spin_lock_irq(&rtc_task_lock);
542
543 if (rtc_callback != task)
544 retval = -ENXIO;
545 else
546 rtc_do_ioctl(cmd, arg, FUNCTION_RTC_CONTROL);
547
548 spin_unlock_irq(&rtc_task_lock);
549
550 return retval;
551}
552
553EXPORT_SYMBOL_GPL(rtc_control);
554
555static struct miscdevice rtc_miscdevice = {
556 .minor = RTC_MINOR,
557 .name = rtc_name,
558 .fops = &rtc_fops,
559};
560
561static int __devinit rtc_probe(struct platform_device *pdev)
562{
563 unsigned int irq;
564 int retval;
565
566 if (pdev->num_resources != 2)
567 return -EBUSY;
568
569 rtc1_base = ioremap(pdev->resource[0].start, RTC1_SIZE);
570 if (rtc1_base == NULL)
571 return -EBUSY;
572
573 rtc2_base = ioremap(pdev->resource[1].start, RTC2_SIZE);
574 if (rtc2_base == NULL) {
575 iounmap(rtc1_base);
576 rtc1_base = NULL;
577 return -EBUSY;
578 }
579
580 retval = misc_register(&rtc_miscdevice);
581 if (retval < 0) {
582 iounmap(rtc1_base);
583 iounmap(rtc2_base);
584 rtc1_base = NULL;
585 rtc2_base = NULL;
586 return retval;
587 }
588
589 spin_lock_irq(&rtc_lock);
590
591 rtc1_write(ECMPLREG, 0);
592 rtc1_write(ECMPMREG, 0);
593 rtc1_write(ECMPHREG, 0);
594 rtc1_write(RTCL1LREG, 0);
595 rtc1_write(RTCL1HREG, 0);
596
597 rtc_status = RTC_RELEASE;
598 rtc_irq_data = 0;
599
600 spin_unlock_irq(&rtc_lock);
601
602 init_waitqueue_head(&rtc_wait);
603
604 irq = ELAPSEDTIME_IRQ;
605 retval = request_irq(irq, elapsedtime_interrupt, SA_INTERRUPT,
606 "elapsed_time", NULL);
607 if (retval == 0) {
608 irq = RTCLONG1_IRQ;
609 retval = request_irq(irq, rtclong1_interrupt, SA_INTERRUPT,
610 "rtclong1", NULL);
611 }
612
613 if (retval < 0) {
614 printk(KERN_ERR "rtc: IRQ%d is busy\n", irq);
615 if (irq == RTCLONG1_IRQ)
616 free_irq(ELAPSEDTIME_IRQ, NULL);
617 iounmap(rtc1_base);
618 iounmap(rtc2_base);
619 rtc1_base = NULL;
620 rtc2_base = NULL;
621 return retval;
622 }
623
624 disable_irq(ELAPSEDTIME_IRQ);
625 disable_irq(RTCLONG1_IRQ);
626
627 spin_lock_init(&rtc_task_lock);
628
629 printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n");
630
631 return 0;
632}
633
634static int __devexit rtc_remove(struct platform_device *dev)
635{
636 int retval;
637
638 retval = misc_deregister(&rtc_miscdevice);
639 if (retval < 0)
640 return retval;
641
642 free_irq(ELAPSEDTIME_IRQ, NULL);
643 free_irq(RTCLONG1_IRQ, NULL);
644 if (rtc1_base != NULL)
645 iounmap(rtc1_base);
646 if (rtc2_base != NULL)
647 iounmap(rtc2_base);
648
649 return 0;
650}
651
652static struct platform_device *rtc_platform_device;
653
654static struct platform_driver rtc_device_driver = {
655 .probe = rtc_probe,
656 .remove = __devexit_p(rtc_remove),
657 .driver = {
658 .name = rtc_name,
659 .owner = THIS_MODULE,
660 },
661};
662
663static int __init vr41xx_rtc_init(void)
664{
665 int retval;
666
667 switch (current_cpu_data.cputype) {
668 case CPU_VR4111:
669 case CPU_VR4121:
670 rtc_resource[0].start = RTC1_TYPE1_START;
671 rtc_resource[0].end = RTC1_TYPE1_END;
672 rtc_resource[1].start = RTC2_TYPE1_START;
673 rtc_resource[1].end = RTC2_TYPE1_END;
674 break;
675 case CPU_VR4122:
676 case CPU_VR4131:
677 case CPU_VR4133:
678 rtc_resource[0].start = RTC1_TYPE2_START;
679 rtc_resource[0].end = RTC1_TYPE2_END;
680 rtc_resource[1].start = RTC2_TYPE2_START;
681 rtc_resource[1].end = RTC2_TYPE2_END;
682 break;
683 default:
684 return -ENODEV;
685 break;
686 }
687
688 rtc_platform_device = platform_device_alloc("RTC", -1);
689 if (!rtc_platform_device)
690 return -ENOMEM;
691
692 retval = platform_device_add_resources(rtc_platform_device,
693 rtc_resource, ARRAY_SIZE(rtc_resource));
694
695 if (retval == 0)
696 retval = platform_device_add(rtc_platform_device);
697
698 if (retval < 0) {
699 platform_device_put(rtc_platform_device);
700 return retval;
701 }
702
703 retval = platform_driver_register(&rtc_device_driver);
704 if (retval < 0)
705 platform_device_unregister(rtc_platform_device);
706
707 return retval;
708}
709
710static void __exit vr41xx_rtc_exit(void)
711{
712 platform_driver_unregister(&rtc_device_driver);
713 platform_device_unregister(rtc_platform_device);
714}
715
716module_init(vr41xx_rtc_init);
717module_exit(vr41xx_rtc_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 01:04:02 -0500