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path: root/drivers/char/synclink_gt.c
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Diffstat (limited to 'drivers/char/synclink_gt.c')
-rw-r--r--drivers/char/synclink_gt.c38
1 files changed, 11 insertions, 27 deletions
diff --git a/drivers/char/synclink_gt.c b/drivers/char/synclink_gt.c
index cf87bb89a77d..0e59cf54adaf 100644
--- a/drivers/char/synclink_gt.c
+++ b/drivers/char/synclink_gt.c
@@ -849,6 +849,7 @@ static int write(struct tty_struct *tty,
849 int ret = 0; 849 int ret = 0;
850 struct slgt_info *info = tty->driver_data; 850 struct slgt_info *info = tty->driver_data;
851 unsigned long flags; 851 unsigned long flags;
852 unsigned int bufs_needed;
852 853
853 if (sanity_check(info, tty->name, "write")) 854 if (sanity_check(info, tty->name, "write"))
854 goto cleanup; 855 goto cleanup;
@@ -865,25 +866,16 @@ static int write(struct tty_struct *tty,
865 if (!count) 866 if (!count)
866 goto cleanup; 867 goto cleanup;
867 868
868 if (info->params.mode == MGSL_MODE_RAW || 869 if (!info->tx_active && info->tx_count) {
869 info->params.mode == MGSL_MODE_MONOSYNC || 870 /* send accumulated data from send_char() */
870 info->params.mode == MGSL_MODE_BISYNC) { 871 tx_load(info, info->tx_buf, info->tx_count);
871 unsigned int bufs_needed = (count/DMABUFSIZE); 872 goto start;
872 unsigned int bufs_free = free_tbuf_count(info);
873 if (count % DMABUFSIZE)
874 ++bufs_needed;
875 if (bufs_needed > bufs_free)
876 goto cleanup;
877 } else {
878 if (info->tx_active)
879 goto cleanup;
880 if (info->tx_count) {
881 /* send accumulated data from send_char() calls */
882 /* as frame and wait before accepting more data. */
883 tx_load(info, info->tx_buf, info->tx_count);
884 goto start;
885 }
886 } 873 }
874 bufs_needed = (count/DMABUFSIZE);
875 if (count % DMABUFSIZE)
876 ++bufs_needed;
877 if (bufs_needed > free_tbuf_count(info))
878 goto cleanup;
887 879
888 ret = info->tx_count = count; 880 ret = info->tx_count = count;
889 tx_load(info, buf, count); 881 tx_load(info, buf, count);
@@ -3935,15 +3927,7 @@ static void tdma_start(struct slgt_info *info)
3935 3927
3936 /* set 1st descriptor address */ 3928 /* set 1st descriptor address */
3937 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc); 3929 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3938 switch(info->params.mode) { 3930 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3939 case MGSL_MODE_RAW:
3940 case MGSL_MODE_MONOSYNC:
3941 case MGSL_MODE_BISYNC:
3942 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3943 break;
3944 default:
3945 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3946 }
3947} 3931}
3948 3932
3949static void tx_stop(struct slgt_info *info) 3933static void tx_stop(struct slgt_info *info)