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-rw-r--r--drivers/char/rio/board.h132
1 files changed, 0 insertions, 132 deletions
diff --git a/drivers/char/rio/board.h b/drivers/char/rio/board.h
deleted file mode 100644
index bdea633a9076..000000000000
--- a/drivers/char/rio/board.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2** -----------------------------------------------------------------------------
3**
4** Perle Specialix driver for Linux
5** Ported from existing RIO Driver for SCO sources.
6 *
7 * (C) 1990 - 2000 Specialix International Ltd., Byfleet, Surrey, UK.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22**
23** Module : board.h
24** SID : 1.2
25** Last Modified : 11/6/98 11:34:07
26** Retrieved : 11/6/98 11:34:20
27**
28** ident @(#)board.h 1.2
29**
30** -----------------------------------------------------------------------------
31*/
32
33#ifndef __rio_board_h__
34#define __rio_board_h__
35
36/*
37** board.h contains the definitions for the *hardware* of the host cards.
38** It describes the memory overlay for the dual port RAM area.
39*/
40
41#define DP_SRAM1_SIZE 0x7C00
42#define DP_SRAM2_SIZE 0x0200
43#define DP_SRAM3_SIZE 0x7000
44#define DP_SCRATCH_SIZE 0x1000
45#define DP_PARMMAP_ADDR 0x01FE /* offset into SRAM2 */
46#define DP_STARTUP_ADDR 0x01F8 /* offset into SRAM2 */
47
48/*
49** The shape of the Host Control area, at offset 0x7C00, Write Only
50*/
51struct s_Ctrl {
52 u8 DpCtl; /* 7C00 */
53 u8 Dp_Unused2_[127];
54 u8 DpIntSet; /* 7C80 */
55 u8 Dp_Unused3_[127];
56 u8 DpTpuReset; /* 7D00 */
57 u8 Dp_Unused4_[127];
58 u8 DpIntReset; /* 7D80 */
59 u8 Dp_Unused5_[127];
60};
61
62/*
63** The PROM data area on the host (0x7C00), Read Only
64*/
65struct s_Prom {
66 u16 DpSlxCode[2];
67 u16 DpRev;
68 u16 Dp_Unused6_;
69 u16 DpUniq[4];
70 u16 DpJahre;
71 u16 DpWoche;
72 u16 DpHwFeature[5];
73 u16 DpOemId;
74 u16 DpSiggy[16];
75};
76
77/*
78** Union of the Ctrl and Prom areas
79*/
80union u_CtrlProm { /* This is the control/PROM area (0x7C00) */
81 struct s_Ctrl DpCtrl;
82 struct s_Prom DpProm;
83};
84
85/*
86** The top end of memory!
87*/
88struct s_ParmMapS { /* Area containing Parm Map Pointer */
89 u8 Dp_Unused8_[DP_PARMMAP_ADDR];
90 u16 DpParmMapAd;
91};
92
93struct s_StartUpS {
94 u8 Dp_Unused9_[DP_STARTUP_ADDR];
95 u8 Dp_LongJump[0x4];
96 u8 Dp_Unused10_[2];
97 u8 Dp_ShortJump[0x2];
98};
99
100union u_Sram2ParmMap { /* This is the top of memory (0x7E00-0x7FFF) */
101 u8 DpSramMem[DP_SRAM2_SIZE];
102 struct s_ParmMapS DpParmMapS;
103 struct s_StartUpS DpStartUpS;
104};
105
106/*
107** This is the DP RAM overlay.
108*/
109struct DpRam {
110 u8 DpSram1[DP_SRAM1_SIZE]; /* 0000 - 7BFF */
111 union u_CtrlProm DpCtrlProm; /* 7C00 - 7DFF */
112 union u_Sram2ParmMap DpSram2ParmMap; /* 7E00 - 7FFF */
113 u8 DpScratch[DP_SCRATCH_SIZE]; /* 8000 - 8FFF */
114 u8 DpSram3[DP_SRAM3_SIZE]; /* 9000 - FFFF */
115};
116
117#define DpControl DpCtrlProm.DpCtrl.DpCtl
118#define DpSetInt DpCtrlProm.DpCtrl.DpIntSet
119#define DpResetTpu DpCtrlProm.DpCtrl.DpTpuReset
120#define DpResetInt DpCtrlProm.DpCtrl.DpIntReset
121
122#define DpSlx DpCtrlProm.DpProm.DpSlxCode
123#define DpRevision DpCtrlProm.DpProm.DpRev
124#define DpUnique DpCtrlProm.DpProm.DpUniq
125#define DpYear DpCtrlProm.DpProm.DpJahre
126#define DpWeek DpCtrlProm.DpProm.DpWoche
127#define DpSignature DpCtrlProm.DpProm.DpSiggy
128
129#define DpParmMapR DpSram2ParmMap.DpParmMapS.DpParmMapAd
130#define DpSram2 DpSram2ParmMap.DpSramMem
131
132#endif