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-rw-r--r--drivers/char/mxser_new.h287
1 files changed, 0 insertions, 287 deletions
diff --git a/drivers/char/mxser_new.h b/drivers/char/mxser_new.h
deleted file mode 100644
index 844171115954..000000000000
--- a/drivers/char/mxser_new.h
+++ /dev/null
@@ -1,287 +0,0 @@
1#ifndef _MXSER_H
2#define _MXSER_H
3
4/*
5 * Semi-public control interfaces
6 */
7
8/*
9 * MOXA ioctls
10 */
11
12#define MOXA 0x400
13#define MOXA_GETDATACOUNT (MOXA + 23)
14#define MOXA_DIAGNOSE (MOXA + 50)
15#define MOXA_CHKPORTENABLE (MOXA + 60)
16#define MOXA_HighSpeedOn (MOXA + 61)
17#define MOXA_GET_MAJOR (MOXA + 63)
18#define MOXA_GETMSTATUS (MOXA + 65)
19#define MOXA_SET_OP_MODE (MOXA + 66)
20#define MOXA_GET_OP_MODE (MOXA + 67)
21
22#define RS232_MODE 0
23#define RS485_2WIRE_MODE 1
24#define RS422_MODE 2
25#define RS485_4WIRE_MODE 3
26#define OP_MODE_MASK 3
27
28#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
29#define MOXA_ASPP_OQUEUE (MOXA + 70)
30#define MOXA_ASPP_MON (MOXA + 73)
31#define MOXA_ASPP_LSTATUS (MOXA + 74)
32#define MOXA_ASPP_MON_EXT (MOXA + 75)
33#define MOXA_SET_BAUD_METHOD (MOXA + 76)
34
35/* --------------------------------------------------- */
36
37#define NPPI_NOTIFY_PARITY 0x01
38#define NPPI_NOTIFY_FRAMING 0x02
39#define NPPI_NOTIFY_HW_OVERRUN 0x04
40#define NPPI_NOTIFY_SW_OVERRUN 0x08
41#define NPPI_NOTIFY_BREAK 0x10
42
43#define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */
44#define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */
45#define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */
46#define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */
47
48/* follow just for Moxa Must chip define. */
49/* */
50/* when LCR register (offset 0x03) write following value, */
51/* the Must chip will enter enchance mode. And write value */
52/* on EFR (offset 0x02) bit 6,7 to change bank. */
53#define MOXA_MUST_ENTER_ENCHANCE 0xBF
54
55/* when enhance mode enable, access on general bank register */
56#define MOXA_MUST_GDL_REGISTER 0x07
57#define MOXA_MUST_GDL_MASK 0x7F
58#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
59
60#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
61/* enchance register bank select and enchance mode setting register */
62/* when LCR register equal to 0xBF */
63#define MOXA_MUST_EFR_REGISTER 0x02
64/* enchance mode enable */
65#define MOXA_MUST_EFR_EFRB_ENABLE 0x10
66/* enchance reister bank set 0, 1, 2 */
67#define MOXA_MUST_EFR_BANK0 0x00
68#define MOXA_MUST_EFR_BANK1 0x40
69#define MOXA_MUST_EFR_BANK2 0x80
70#define MOXA_MUST_EFR_BANK3 0xC0
71#define MOXA_MUST_EFR_BANK_MASK 0xC0
72
73/* set XON1 value register, when LCR=0xBF and change to bank0 */
74#define MOXA_MUST_XON1_REGISTER 0x04
75
76/* set XON2 value register, when LCR=0xBF and change to bank0 */
77#define MOXA_MUST_XON2_REGISTER 0x05
78
79/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
80#define MOXA_MUST_XOFF1_REGISTER 0x06
81
82/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
83#define MOXA_MUST_XOFF2_REGISTER 0x07
84
85#define MOXA_MUST_RBRTL_REGISTER 0x04
86#define MOXA_MUST_RBRTH_REGISTER 0x05
87#define MOXA_MUST_RBRTI_REGISTER 0x06
88#define MOXA_MUST_THRTL_REGISTER 0x07
89#define MOXA_MUST_ENUM_REGISTER 0x04
90#define MOXA_MUST_HWID_REGISTER 0x05
91#define MOXA_MUST_ECR_REGISTER 0x06
92#define MOXA_MUST_CSR_REGISTER 0x07
93
94/* good data mode enable */
95#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
96/* only good data put into RxFIFO */
97#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
98
99/* enable CTS interrupt */
100#define MOXA_MUST_IER_ECTSI 0x80
101/* enable RTS interrupt */
102#define MOXA_MUST_IER_ERTSI 0x40
103/* enable Xon/Xoff interrupt */
104#define MOXA_MUST_IER_XINT 0x20
105/* enable GDA interrupt */
106#define MOXA_MUST_IER_EGDAI 0x10
107
108#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
109
110/* GDA interrupt pending */
111#define MOXA_MUST_IIR_GDA 0x1C
112#define MOXA_MUST_IIR_RDA 0x04
113#define MOXA_MUST_IIR_RTO 0x0C
114#define MOXA_MUST_IIR_LSR 0x06
115
116/* recieved Xon/Xoff or specical interrupt pending */
117#define MOXA_MUST_IIR_XSC 0x10
118
119/* RTS/CTS change state interrupt pending */
120#define MOXA_MUST_IIR_RTSCTS 0x20
121#define MOXA_MUST_IIR_MASK 0x3E
122
123#define MOXA_MUST_MCR_XON_FLAG 0x40
124#define MOXA_MUST_MCR_XON_ANY 0x80
125#define MOXA_MUST_MCR_TX_XON 0x08
126
127/* software flow control on chip mask value */
128#define MOXA_MUST_EFR_SF_MASK 0x0F
129/* send Xon1/Xoff1 */
130#define MOXA_MUST_EFR_SF_TX1 0x08
131/* send Xon2/Xoff2 */
132#define MOXA_MUST_EFR_SF_TX2 0x04
133/* send Xon1,Xon2/Xoff1,Xoff2 */
134#define MOXA_MUST_EFR_SF_TX12 0x0C
135/* don't send Xon/Xoff */
136#define MOXA_MUST_EFR_SF_TX_NO 0x00
137/* Tx software flow control mask */
138#define MOXA_MUST_EFR_SF_TX_MASK 0x0C
139/* don't receive Xon/Xoff */
140#define MOXA_MUST_EFR_SF_RX_NO 0x00
141/* receive Xon1/Xoff1 */
142#define MOXA_MUST_EFR_SF_RX1 0x02
143/* receive Xon2/Xoff2 */
144#define MOXA_MUST_EFR_SF_RX2 0x01
145/* receive Xon1,Xon2/Xoff1,Xoff2 */
146#define MOXA_MUST_EFR_SF_RX12 0x03
147/* Rx software flow control mask */
148#define MOXA_MUST_EFR_SF_RX_MASK 0x03
149
150#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
151 u8 __oldlcr, __efr; \
152 __oldlcr = inb((baseio)+UART_LCR); \
153 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
154 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
155 __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \
156 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
157 outb(__oldlcr, (baseio)+UART_LCR); \
158} while (0)
159
160#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
161 u8 __oldlcr, __efr; \
162 __oldlcr = inb((baseio)+UART_LCR); \
163 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
164 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
165 __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \
166 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
167 outb(__oldlcr, (baseio)+UART_LCR); \
168} while (0)
169
170#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \
171 u8 __oldlcr, __efr; \
172 __oldlcr = inb((baseio)+UART_LCR); \
173 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
174 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
175 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
176 __efr |= MOXA_MUST_EFR_BANK0; \
177 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
178 outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \
179 outb(__oldlcr, (baseio)+UART_LCR); \
180} while (0)
181
182#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \
183 u8 __oldlcr, __efr; \
184 __oldlcr = inb((baseio)+UART_LCR); \
185 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
186 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
187 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
188 __efr |= MOXA_MUST_EFR_BANK0; \
189 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
190 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \
191 outb(__oldlcr, (baseio)+UART_LCR); \
192} while (0)
193
194#define SET_MOXA_MUST_FIFO_VALUE(info) do { \
195 u8 __oldlcr, __efr; \
196 __oldlcr = inb((info)->ioaddr+UART_LCR); \
197 outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\
198 __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
199 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
200 __efr |= MOXA_MUST_EFR_BANK1; \
201 outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
202 outb((u8)((info)->rx_high_water), (info)->ioaddr+ \
203 MOXA_MUST_RBRTH_REGISTER); \
204 outb((u8)((info)->rx_trigger), (info)->ioaddr+ \
205 MOXA_MUST_RBRTI_REGISTER); \
206 outb((u8)((info)->rx_low_water), (info)->ioaddr+ \
207 MOXA_MUST_RBRTL_REGISTER); \
208 outb(__oldlcr, (info)->ioaddr+UART_LCR); \
209} while (0)
210
211#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do { \
212 u8 __oldlcr, __efr; \
213 __oldlcr = inb((baseio)+UART_LCR); \
214 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
215 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
216 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
217 __efr |= MOXA_MUST_EFR_BANK2; \
218 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
219 outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \
220 outb(__oldlcr, (baseio)+UART_LCR); \
221} while (0)
222
223#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \
224 u8 __oldlcr, __efr; \
225 __oldlcr = inb((baseio)+UART_LCR); \
226 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
227 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
228 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
229 __efr |= MOXA_MUST_EFR_BANK2; \
230 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
231 *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
232 outb(__oldlcr, (baseio)+UART_LCR); \
233} while (0)
234
235#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \
236 u8 __oldlcr, __efr; \
237 __oldlcr = inb((baseio)+UART_LCR); \
238 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
239 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
240 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
241 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
242 outb(__oldlcr, (baseio)+UART_LCR); \
243} while (0)
244
245#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
246 u8 __oldlcr, __efr; \
247 __oldlcr = inb((baseio)+UART_LCR); \
248 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
249 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
250 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
251 __efr |= MOXA_MUST_EFR_SF_TX1; \
252 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
253 outb(__oldlcr, (baseio)+UART_LCR); \
254} while (0)
255
256#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
257 u8 __oldlcr, __efr; \
258 __oldlcr = inb((baseio)+UART_LCR); \
259 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
260 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
261 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
262 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
263 outb(__oldlcr, (baseio)+UART_LCR); \
264} while (0)
265
266#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
267 u8 __oldlcr, __efr; \
268 __oldlcr = inb((baseio)+UART_LCR); \
269 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
270 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
271 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
272 __efr |= MOXA_MUST_EFR_SF_RX1; \
273 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
274 outb(__oldlcr, (baseio)+UART_LCR); \
275} while (0)
276
277#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
278 u8 __oldlcr, __efr; \
279 __oldlcr = inb((baseio)+UART_LCR); \
280 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
281 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
282 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
283 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
284 outb(__oldlcr, (baseio)+UART_LCR); \
285} while (0)
286
287#endif
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