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path: root/drivers/char/mxser.h
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-rw-r--r--drivers/char/mxser.h478
1 files changed, 162 insertions, 316 deletions
diff --git a/drivers/char/mxser.h b/drivers/char/mxser.h
index 1f4aa45ec004..844171115954 100644
--- a/drivers/char/mxser.h
+++ b/drivers/char/mxser.h
@@ -4,19 +4,17 @@
4/* 4/*
5 * Semi-public control interfaces 5 * Semi-public control interfaces
6 */ 6 */
7 7
8/* 8/*
9 * MOXA ioctls 9 * MOXA ioctls
10 */ 10 */
11 11
12#define MOXA 0x400 12#define MOXA 0x400
13#define MOXA_GETDATACOUNT (MOXA + 23) 13#define MOXA_GETDATACOUNT (MOXA + 23)
14#define MOXA_GET_CONF (MOXA + 35)
15#define MOXA_DIAGNOSE (MOXA + 50) 14#define MOXA_DIAGNOSE (MOXA + 50)
16#define MOXA_CHKPORTENABLE (MOXA + 60) 15#define MOXA_CHKPORTENABLE (MOXA + 60)
17#define MOXA_HighSpeedOn (MOXA + 61) 16#define MOXA_HighSpeedOn (MOXA + 61)
18#define MOXA_GET_MAJOR (MOXA + 63) 17#define MOXA_GET_MAJOR (MOXA + 63)
19#define MOXA_GET_CUMAJOR (MOXA + 64)
20#define MOXA_GETMSTATUS (MOXA + 65) 18#define MOXA_GETMSTATUS (MOXA + 65)
21#define MOXA_SET_OP_MODE (MOXA + 66) 19#define MOXA_SET_OP_MODE (MOXA + 66)
22#define MOXA_GET_OP_MODE (MOXA + 67) 20#define MOXA_GET_OP_MODE (MOXA + 67)
@@ -26,26 +24,14 @@
26#define RS422_MODE 2 24#define RS422_MODE 2
27#define RS485_4WIRE_MODE 3 25#define RS485_4WIRE_MODE 3
28#define OP_MODE_MASK 3 26#define OP_MODE_MASK 3
29// above add by Victor Yu. 01-05-2004
30
31#define TTY_THRESHOLD_THROTTLE 128
32
33#define HI_WATER 768
34
35// added by James. 03-11-2004.
36#define MOXA_SDS_GETICOUNTER (MOXA + 68)
37#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
38// (above) added by James.
39 27
28#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
40#define MOXA_ASPP_OQUEUE (MOXA + 70) 29#define MOXA_ASPP_OQUEUE (MOXA + 70)
41#define MOXA_ASPP_SETBAUD (MOXA + 71)
42#define MOXA_ASPP_GETBAUD (MOXA + 72)
43#define MOXA_ASPP_MON (MOXA + 73) 30#define MOXA_ASPP_MON (MOXA + 73)
44#define MOXA_ASPP_LSTATUS (MOXA + 74) 31#define MOXA_ASPP_LSTATUS (MOXA + 74)
45#define MOXA_ASPP_MON_EXT (MOXA + 75) 32#define MOXA_ASPP_MON_EXT (MOXA + 75)
46#define MOXA_SET_BAUD_METHOD (MOXA + 76) 33#define MOXA_SET_BAUD_METHOD (MOXA + 76)
47 34
48
49/* --------------------------------------------------- */ 35/* --------------------------------------------------- */
50 36
51#define NPPI_NOTIFY_PARITY 0x01 37#define NPPI_NOTIFY_PARITY 0x01
@@ -54,51 +40,46 @@
54#define NPPI_NOTIFY_SW_OVERRUN 0x08 40#define NPPI_NOTIFY_SW_OVERRUN 0x08
55#define NPPI_NOTIFY_BREAK 0x10 41#define NPPI_NOTIFY_BREAK 0x10
56 42
57#define NPPI_NOTIFY_CTSHOLD 0x01 // Tx hold by CTS low 43#define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */
58#define NPPI_NOTIFY_DSRHOLD 0x02 // Tx hold by DSR low 44#define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */
59#define NPPI_NOTIFY_XOFFHOLD 0x08 // Tx hold by Xoff received 45#define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */
60#define NPPI_NOTIFY_XOFFXENT 0x10 // Xoff Sent 46#define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */
61 47
62//CheckIsMoxaMust return value 48/* follow just for Moxa Must chip define. */
63#define MOXA_OTHER_UART 0x00 49/* */
64#define MOXA_MUST_MU150_HWID 0x01 50/* when LCR register (offset 0x03) write following value, */
65#define MOXA_MUST_MU860_HWID 0x02 51/* the Must chip will enter enchance mode. And write value */
66 52/* on EFR (offset 0x02) bit 6,7 to change bank. */
67// follow just for Moxa Must chip define.
68//
69// when LCR register (offset 0x03) write following value,
70// the Must chip will enter enchance mode. And write value
71// on EFR (offset 0x02) bit 6,7 to change bank.
72#define MOXA_MUST_ENTER_ENCHANCE 0xBF 53#define MOXA_MUST_ENTER_ENCHANCE 0xBF
73 54
74// when enhance mode enable, access on general bank register 55/* when enhance mode enable, access on general bank register */
75#define MOXA_MUST_GDL_REGISTER 0x07 56#define MOXA_MUST_GDL_REGISTER 0x07
76#define MOXA_MUST_GDL_MASK 0x7F 57#define MOXA_MUST_GDL_MASK 0x7F
77#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 58#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
78 59
79#define MOXA_MUST_LSR_RERR 0x80 // error in receive FIFO 60#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
80// enchance register bank select and enchance mode setting register 61/* enchance register bank select and enchance mode setting register */
81// when LCR register equal to 0xBF 62/* when LCR register equal to 0xBF */
82#define MOXA_MUST_EFR_REGISTER 0x02 63#define MOXA_MUST_EFR_REGISTER 0x02
83// enchance mode enable 64/* enchance mode enable */
84#define MOXA_MUST_EFR_EFRB_ENABLE 0x10 65#define MOXA_MUST_EFR_EFRB_ENABLE 0x10
85// enchance reister bank set 0, 1, 2 66/* enchance reister bank set 0, 1, 2 */
86#define MOXA_MUST_EFR_BANK0 0x00 67#define MOXA_MUST_EFR_BANK0 0x00
87#define MOXA_MUST_EFR_BANK1 0x40 68#define MOXA_MUST_EFR_BANK1 0x40
88#define MOXA_MUST_EFR_BANK2 0x80 69#define MOXA_MUST_EFR_BANK2 0x80
89#define MOXA_MUST_EFR_BANK3 0xC0 70#define MOXA_MUST_EFR_BANK3 0xC0
90#define MOXA_MUST_EFR_BANK_MASK 0xC0 71#define MOXA_MUST_EFR_BANK_MASK 0xC0
91 72
92// set XON1 value register, when LCR=0xBF and change to bank0 73/* set XON1 value register, when LCR=0xBF and change to bank0 */
93#define MOXA_MUST_XON1_REGISTER 0x04 74#define MOXA_MUST_XON1_REGISTER 0x04
94 75
95// set XON2 value register, when LCR=0xBF and change to bank0 76/* set XON2 value register, when LCR=0xBF and change to bank0 */
96#define MOXA_MUST_XON2_REGISTER 0x05 77#define MOXA_MUST_XON2_REGISTER 0x05
97 78
98// set XOFF1 value register, when LCR=0xBF and change to bank0 79/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
99#define MOXA_MUST_XOFF1_REGISTER 0x06 80#define MOXA_MUST_XOFF1_REGISTER 0x06
100 81
101// set XOFF2 value register, when LCR=0xBF and change to bank0 82/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
102#define MOXA_MUST_XOFF2_REGISTER 0x07 83#define MOXA_MUST_XOFF2_REGISTER 0x07
103 84
104#define MOXA_MUST_RBRTL_REGISTER 0x04 85#define MOXA_MUST_RBRTL_REGISTER 0x04
@@ -110,32 +91,32 @@
110#define MOXA_MUST_ECR_REGISTER 0x06 91#define MOXA_MUST_ECR_REGISTER 0x06
111#define MOXA_MUST_CSR_REGISTER 0x07 92#define MOXA_MUST_CSR_REGISTER 0x07
112 93
113// good data mode enable 94/* good data mode enable */
114#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 95#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
115// only good data put into RxFIFO 96/* only good data put into RxFIFO */
116#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 97#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
117 98
118// enable CTS interrupt 99/* enable CTS interrupt */
119#define MOXA_MUST_IER_ECTSI 0x80 100#define MOXA_MUST_IER_ECTSI 0x80
120// enable RTS interrupt 101/* enable RTS interrupt */
121#define MOXA_MUST_IER_ERTSI 0x40 102#define MOXA_MUST_IER_ERTSI 0x40
122// enable Xon/Xoff interrupt 103/* enable Xon/Xoff interrupt */
123#define MOXA_MUST_IER_XINT 0x20 104#define MOXA_MUST_IER_XINT 0x20
124// enable GDA interrupt 105/* enable GDA interrupt */
125#define MOXA_MUST_IER_EGDAI 0x10 106#define MOXA_MUST_IER_EGDAI 0x10
126 107
127#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) 108#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
128 109
129// GDA interrupt pending 110/* GDA interrupt pending */
130#define MOXA_MUST_IIR_GDA 0x1C 111#define MOXA_MUST_IIR_GDA 0x1C
131#define MOXA_MUST_IIR_RDA 0x04 112#define MOXA_MUST_IIR_RDA 0x04
132#define MOXA_MUST_IIR_RTO 0x0C 113#define MOXA_MUST_IIR_RTO 0x0C
133#define MOXA_MUST_IIR_LSR 0x06 114#define MOXA_MUST_IIR_LSR 0x06
134 115
135// recieved Xon/Xoff or specical interrupt pending 116/* recieved Xon/Xoff or specical interrupt pending */
136#define MOXA_MUST_IIR_XSC 0x10 117#define MOXA_MUST_IIR_XSC 0x10
137 118
138// RTS/CTS change state interrupt pending 119/* RTS/CTS change state interrupt pending */
139#define MOXA_MUST_IIR_RTSCTS 0x20 120#define MOXA_MUST_IIR_RTSCTS 0x20
140#define MOXA_MUST_IIR_MASK 0x3E 121#define MOXA_MUST_IIR_MASK 0x3E
141 122
@@ -143,299 +124,164 @@
143#define MOXA_MUST_MCR_XON_ANY 0x80 124#define MOXA_MUST_MCR_XON_ANY 0x80
144#define MOXA_MUST_MCR_TX_XON 0x08 125#define MOXA_MUST_MCR_TX_XON 0x08
145 126
146 127/* software flow control on chip mask value */
147// software flow control on chip mask value
148#define MOXA_MUST_EFR_SF_MASK 0x0F 128#define MOXA_MUST_EFR_SF_MASK 0x0F
149// send Xon1/Xoff1 129/* send Xon1/Xoff1 */
150#define MOXA_MUST_EFR_SF_TX1 0x08 130#define MOXA_MUST_EFR_SF_TX1 0x08
151// send Xon2/Xoff2 131/* send Xon2/Xoff2 */
152#define MOXA_MUST_EFR_SF_TX2 0x04 132#define MOXA_MUST_EFR_SF_TX2 0x04
153// send Xon1,Xon2/Xoff1,Xoff2 133/* send Xon1,Xon2/Xoff1,Xoff2 */
154#define MOXA_MUST_EFR_SF_TX12 0x0C 134#define MOXA_MUST_EFR_SF_TX12 0x0C
155// don't send Xon/Xoff 135/* don't send Xon/Xoff */
156#define MOXA_MUST_EFR_SF_TX_NO 0x00 136#define MOXA_MUST_EFR_SF_TX_NO 0x00
157// Tx software flow control mask 137/* Tx software flow control mask */
158#define MOXA_MUST_EFR_SF_TX_MASK 0x0C 138#define MOXA_MUST_EFR_SF_TX_MASK 0x0C
159// don't receive Xon/Xoff 139/* don't receive Xon/Xoff */
160#define MOXA_MUST_EFR_SF_RX_NO 0x00 140#define MOXA_MUST_EFR_SF_RX_NO 0x00
161// receive Xon1/Xoff1 141/* receive Xon1/Xoff1 */
162#define MOXA_MUST_EFR_SF_RX1 0x02 142#define MOXA_MUST_EFR_SF_RX1 0x02
163// receive Xon2/Xoff2 143/* receive Xon2/Xoff2 */
164#define MOXA_MUST_EFR_SF_RX2 0x01 144#define MOXA_MUST_EFR_SF_RX2 0x01
165// receive Xon1,Xon2/Xoff1,Xoff2 145/* receive Xon1,Xon2/Xoff1,Xoff2 */
166#define MOXA_MUST_EFR_SF_RX12 0x03 146#define MOXA_MUST_EFR_SF_RX12 0x03
167// Rx software flow control mask 147/* Rx software flow control mask */
168#define MOXA_MUST_EFR_SF_RX_MASK 0x03 148#define MOXA_MUST_EFR_SF_RX_MASK 0x03
169 149
170//#define MOXA_MUST_MIN_XOFFLIMIT 66 150#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
171//#define MOXA_MUST_MIN_XONLIMIT 20 151 u8 __oldlcr, __efr; \
172//#define ID1_RX_TRIG 120 152 __oldlcr = inb((baseio)+UART_LCR); \
173
174
175#define CHECK_MOXA_MUST_XOFFLIMIT(info) { \
176 if ( (info)->IsMoxaMustChipFlag && \
177 (info)->HandFlow.XoffLimit < MOXA_MUST_MIN_XOFFLIMIT ) { \
178 (info)->HandFlow.XoffLimit = MOXA_MUST_MIN_XOFFLIMIT; \
179 (info)->HandFlow.XonLimit = MOXA_MUST_MIN_XONLIMIT; \
180 } \
181}
182
183#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \
184 u8 __oldlcr, __efr; \
185 __oldlcr = inb((baseio)+UART_LCR); \
186 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 153 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
187 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 154 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
188 __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \ 155 __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \
189 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 156 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
190 outb(__oldlcr, (baseio)+UART_LCR); \ 157 outb(__oldlcr, (baseio)+UART_LCR); \
191} 158} while (0)
192 159
193#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \ 160#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
194 u8 __oldlcr, __efr; \ 161 u8 __oldlcr, __efr; \
195 __oldlcr = inb((baseio)+UART_LCR); \ 162 __oldlcr = inb((baseio)+UART_LCR); \
196 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 163 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
197 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 164 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
198 __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \ 165 __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \
199 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 166 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
200 outb(__oldlcr, (baseio)+UART_LCR); \ 167 outb(__oldlcr, (baseio)+UART_LCR); \
201} 168} while (0)
202 169
203#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) { \ 170#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \
204 u8 __oldlcr, __efr; \ 171 u8 __oldlcr, __efr; \
205 __oldlcr = inb((baseio)+UART_LCR); \ 172 __oldlcr = inb((baseio)+UART_LCR); \
206 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 173 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
207 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 174 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
208 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 175 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
209 __efr |= MOXA_MUST_EFR_BANK0; \ 176 __efr |= MOXA_MUST_EFR_BANK0; \
210 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 177 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
211 outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \ 178 outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \
212 outb(__oldlcr, (baseio)+UART_LCR); \ 179 outb(__oldlcr, (baseio)+UART_LCR); \
213} 180} while (0)
214 181
215#define SET_MOXA_MUST_XON2_VALUE(baseio, Value) { \ 182#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \
216 u8 __oldlcr, __efr; \ 183 u8 __oldlcr, __efr; \
217 __oldlcr = inb((baseio)+UART_LCR); \ 184 __oldlcr = inb((baseio)+UART_LCR); \
218 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 185 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
219 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 186 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
220 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 187 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
221 __efr |= MOXA_MUST_EFR_BANK0; \ 188 __efr |= MOXA_MUST_EFR_BANK0; \
222 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 189 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
223 outb((u8)(Value), (baseio)+MOXA_MUST_XON2_REGISTER); \
224 outb(__oldlcr, (baseio)+UART_LCR); \
225}
226
227#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) { \
228 u8 __oldlcr, __efr; \
229 __oldlcr = inb((baseio)+UART_LCR); \
230 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
231 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
232 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
233 __efr |= MOXA_MUST_EFR_BANK0; \
234 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
235 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \ 190 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \
236 outb(__oldlcr, (baseio)+UART_LCR); \ 191 outb(__oldlcr, (baseio)+UART_LCR); \
237} 192} while (0)
238 193
239#define SET_MOXA_MUST_XOFF2_VALUE(baseio, Value) { \ 194#define SET_MOXA_MUST_FIFO_VALUE(info) do { \
240 u8 __oldlcr, __efr; \ 195 u8 __oldlcr, __efr; \
241 __oldlcr = inb((baseio)+UART_LCR); \ 196 __oldlcr = inb((info)->ioaddr+UART_LCR); \
242 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 197 outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\
243 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 198 __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
244 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 199 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
245 __efr |= MOXA_MUST_EFR_BANK0; \ 200 __efr |= MOXA_MUST_EFR_BANK1; \
246 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 201 outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
247 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF2_REGISTER); \ 202 outb((u8)((info)->rx_high_water), (info)->ioaddr+ \
248 outb(__oldlcr, (baseio)+UART_LCR); \ 203 MOXA_MUST_RBRTH_REGISTER); \
249} 204 outb((u8)((info)->rx_trigger), (info)->ioaddr+ \
250 205 MOXA_MUST_RBRTI_REGISTER); \
251#define SET_MOXA_MUST_RBRTL_VALUE(baseio, Value) { \ 206 outb((u8)((info)->rx_low_water), (info)->ioaddr+ \
252 u8 __oldlcr, __efr; \ 207 MOXA_MUST_RBRTL_REGISTER); \
253 __oldlcr = inb((baseio)+UART_LCR); \ 208 outb(__oldlcr, (info)->ioaddr+UART_LCR); \
254 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 209} while (0)
255 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 210
256 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 211#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do { \
257 __efr |= MOXA_MUST_EFR_BANK1; \ 212 u8 __oldlcr, __efr; \
258 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 213 __oldlcr = inb((baseio)+UART_LCR); \
259 outb((u8)(Value), (baseio)+MOXA_MUST_RBRTL_REGISTER); \
260 outb(__oldlcr, (baseio)+UART_LCR); \
261}
262
263#define SET_MOXA_MUST_RBRTH_VALUE(baseio, Value) { \
264 u8 __oldlcr, __efr; \
265 __oldlcr = inb((baseio)+UART_LCR); \
266 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
267 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
268 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
269 __efr |= MOXA_MUST_EFR_BANK1; \
270 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
271 outb((u8)(Value), (baseio)+MOXA_MUST_RBRTH_REGISTER); \
272 outb(__oldlcr, (baseio)+UART_LCR); \
273}
274
275#define SET_MOXA_MUST_RBRTI_VALUE(baseio, Value) { \
276 u8 __oldlcr, __efr; \
277 __oldlcr = inb((baseio)+UART_LCR); \
278 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 214 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
279 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 215 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
280 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 216 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
281 __efr |= MOXA_MUST_EFR_BANK1; \ 217 __efr |= MOXA_MUST_EFR_BANK2; \
282 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 218 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
283 outb((u8)(Value), (baseio)+MOXA_MUST_RBRTI_REGISTER); \
284 outb(__oldlcr, (baseio)+UART_LCR); \
285}
286
287#define SET_MOXA_MUST_THRTL_VALUE(baseio, Value) { \
288 u8 __oldlcr, __efr; \
289 __oldlcr = inb((baseio)+UART_LCR); \
290 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
291 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
292 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
293 __efr |= MOXA_MUST_EFR_BANK1; \
294 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
295 outb((u8)(Value), (baseio)+MOXA_MUST_THRTL_REGISTER); \
296 outb(__oldlcr, (baseio)+UART_LCR); \
297}
298
299//#define MOXA_MUST_RBRL_VALUE 4
300#define SET_MOXA_MUST_FIFO_VALUE(info) { \
301 u8 __oldlcr, __efr; \
302 __oldlcr = inb((info)->base+UART_LCR); \
303 outb(MOXA_MUST_ENTER_ENCHANCE, (info)->base+UART_LCR); \
304 __efr = inb((info)->base+MOXA_MUST_EFR_REGISTER); \
305 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
306 __efr |= MOXA_MUST_EFR_BANK1; \
307 outb(__efr, (info)->base+MOXA_MUST_EFR_REGISTER); \
308 outb((u8)((info)->rx_high_water), (info)->base+MOXA_MUST_RBRTH_REGISTER); \
309 outb((u8)((info)->rx_trigger), (info)->base+MOXA_MUST_RBRTI_REGISTER); \
310 outb((u8)((info)->rx_low_water), (info)->base+MOXA_MUST_RBRTL_REGISTER); \
311 outb(__oldlcr, (info)->base+UART_LCR); \
312}
313
314
315
316#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) { \
317 u8 __oldlcr, __efr; \
318 __oldlcr = inb((baseio)+UART_LCR); \
319 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
320 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
321 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
322 __efr |= MOXA_MUST_EFR_BANK2; \
323 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
324 outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \ 219 outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \
325 outb(__oldlcr, (baseio)+UART_LCR); \ 220 outb(__oldlcr, (baseio)+UART_LCR); \
326} 221} while (0)
327 222
328#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) { \ 223#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \
329 u8 __oldlcr, __efr; \ 224 u8 __oldlcr, __efr; \
330 __oldlcr = inb((baseio)+UART_LCR); \ 225 __oldlcr = inb((baseio)+UART_LCR); \
331 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
332 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
333 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
334 __efr |= MOXA_MUST_EFR_BANK2; \
335 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
336 *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
337 outb(__oldlcr, (baseio)+UART_LCR); \
338}
339
340#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) { \
341 u8 __oldlcr, __efr; \
342 __oldlcr = inb((baseio)+UART_LCR); \
343 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
344 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
345 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
346 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
347 outb(__oldlcr, (baseio)+UART_LCR); \
348}
349
350#define SET_MOXA_MUST_JUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
351 u8 __oldlcr, __efr; \
352 __oldlcr = inb((baseio)+UART_LCR); \
353 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
354 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
355 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
356 __efr |= MOXA_MUST_EFR_SF_TX1; \
357 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
358 outb(__oldlcr, (baseio)+UART_LCR); \
359}
360
361#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
362 u8 __oldlcr, __efr; \
363 __oldlcr = inb((baseio)+UART_LCR); \
364 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 226 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
365 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 227 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
366 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ 228 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
367 __efr |= MOXA_MUST_EFR_SF_TX1; \ 229 __efr |= MOXA_MUST_EFR_BANK2; \
368 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 230 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
369 outb(__oldlcr, (baseio)+UART_LCR); \ 231 *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
370} 232 outb(__oldlcr, (baseio)+UART_LCR); \
371 233} while (0)
372#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \ 234
373 u8 __oldlcr, __efr; \ 235#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \
374 __oldlcr = inb((baseio)+UART_LCR); \ 236 u8 __oldlcr, __efr; \
237 __oldlcr = inb((baseio)+UART_LCR); \
375 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 238 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
376 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 239 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
377 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ 240 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
378 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 241 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
379 outb(__oldlcr, (baseio)+UART_LCR); \ 242 outb(__oldlcr, (baseio)+UART_LCR); \
380} 243} while (0)
381 244
382#define SET_MOXA_MUST_JUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ 245#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
383 u8 __oldlcr, __efr; \ 246 u8 __oldlcr, __efr; \
384 __oldlcr = inb((baseio)+UART_LCR); \ 247 __oldlcr = inb((baseio)+UART_LCR); \
385 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 248 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
386 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 249 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
387 __efr &= ~MOXA_MUST_EFR_SF_MASK; \ 250 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
388 __efr |= MOXA_MUST_EFR_SF_RX1; \ 251 __efr |= MOXA_MUST_EFR_SF_TX1; \
389 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 252 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
390 outb(__oldlcr, (baseio)+UART_LCR); \ 253 outb(__oldlcr, (baseio)+UART_LCR); \
391} 254} while (0)
392 255
393#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ 256#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
394 u8 __oldlcr, __efr; \ 257 u8 __oldlcr, __efr; \
395 __oldlcr = inb((baseio)+UART_LCR); \ 258 __oldlcr = inb((baseio)+UART_LCR); \
396 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 259 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
397 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 260 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
398 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ 261 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
399 __efr |= MOXA_MUST_EFR_SF_RX1; \ 262 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
400 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 263 outb(__oldlcr, (baseio)+UART_LCR); \
401 outb(__oldlcr, (baseio)+UART_LCR); \ 264} while (0)
402} 265
403 266#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
404#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ 267 u8 __oldlcr, __efr; \
405 u8 __oldlcr, __efr; \ 268 __oldlcr = inb((baseio)+UART_LCR); \
406 __oldlcr = inb((baseio)+UART_LCR); \
407 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 269 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
408 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 270 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
409 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ 271 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
410 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 272 __efr |= MOXA_MUST_EFR_SF_RX1; \
411 outb(__oldlcr, (baseio)+UART_LCR); \ 273 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
412} 274 outb(__oldlcr, (baseio)+UART_LCR); \
413 275} while (0)
414#define ENABLE_MOXA_MUST_TX_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ 276
415 u8 __oldlcr, __efr; \ 277#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
416 __oldlcr = inb((baseio)+UART_LCR); \ 278 u8 __oldlcr, __efr; \
279 __oldlcr = inb((baseio)+UART_LCR); \
417 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 280 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
418 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 281 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
419 __efr &= ~MOXA_MUST_EFR_SF_MASK; \ 282 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
420 __efr |= (MOXA_MUST_EFR_SF_RX1|MOXA_MUST_EFR_SF_TX1); \ 283 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
421 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 284 outb(__oldlcr, (baseio)+UART_LCR); \
422 outb(__oldlcr, (baseio)+UART_LCR); \ 285} while (0)
423}
424
425#define ENABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \
426 u8 __oldmcr; \
427 __oldmcr = inb((baseio)+UART_MCR); \
428 __oldmcr |= MOXA_MUST_MCR_XON_ANY; \
429 outb(__oldmcr, (baseio)+UART_MCR); \
430}
431
432#define DISABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \
433 u8 __oldmcr; \
434 __oldmcr = inb((baseio)+UART_MCR); \
435 __oldmcr &= ~MOXA_MUST_MCR_XON_ANY; \
436 outb(__oldmcr, (baseio)+UART_MCR); \
437}
438
439#define READ_MOXA_MUST_GDL(baseio) inb((baseio)+MOXA_MUST_GDL_REGISTER)
440 286
441#endif 287#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-02 14:34:56 -0500