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path: root/drivers/char/mxser.h
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-rw-r--r--drivers/char/mxser.h137
1 files changed, 0 insertions, 137 deletions
diff --git a/drivers/char/mxser.h b/drivers/char/mxser.h
index 844171115954..41878a69203d 100644
--- a/drivers/char/mxser.h
+++ b/drivers/char/mxser.h
@@ -147,141 +147,4 @@
147/* Rx software flow control mask */ 147/* Rx software flow control mask */
148#define MOXA_MUST_EFR_SF_RX_MASK 0x03 148#define MOXA_MUST_EFR_SF_RX_MASK 0x03
149 149
150#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
151 u8 __oldlcr, __efr; \
152 __oldlcr = inb((baseio)+UART_LCR); \
153 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
154 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
155 __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \
156 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
157 outb(__oldlcr, (baseio)+UART_LCR); \
158} while (0)
159
160#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
161 u8 __oldlcr, __efr; \
162 __oldlcr = inb((baseio)+UART_LCR); \
163 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
164 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
165 __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \
166 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
167 outb(__oldlcr, (baseio)+UART_LCR); \
168} while (0)
169
170#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \
171 u8 __oldlcr, __efr; \
172 __oldlcr = inb((baseio)+UART_LCR); \
173 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
174 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
175 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
176 __efr |= MOXA_MUST_EFR_BANK0; \
177 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
178 outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \
179 outb(__oldlcr, (baseio)+UART_LCR); \
180} while (0)
181
182#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \
183 u8 __oldlcr, __efr; \
184 __oldlcr = inb((baseio)+UART_LCR); \
185 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
186 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
187 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
188 __efr |= MOXA_MUST_EFR_BANK0; \
189 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
190 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \
191 outb(__oldlcr, (baseio)+UART_LCR); \
192} while (0)
193
194#define SET_MOXA_MUST_FIFO_VALUE(info) do { \
195 u8 __oldlcr, __efr; \
196 __oldlcr = inb((info)->ioaddr+UART_LCR); \
197 outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\
198 __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
199 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
200 __efr |= MOXA_MUST_EFR_BANK1; \
201 outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
202 outb((u8)((info)->rx_high_water), (info)->ioaddr+ \
203 MOXA_MUST_RBRTH_REGISTER); \
204 outb((u8)((info)->rx_trigger), (info)->ioaddr+ \
205 MOXA_MUST_RBRTI_REGISTER); \
206 outb((u8)((info)->rx_low_water), (info)->ioaddr+ \
207 MOXA_MUST_RBRTL_REGISTER); \
208 outb(__oldlcr, (info)->ioaddr+UART_LCR); \
209} while (0)
210
211#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do { \
212 u8 __oldlcr, __efr; \
213 __oldlcr = inb((baseio)+UART_LCR); \
214 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
215 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
216 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
217 __efr |= MOXA_MUST_EFR_BANK2; \
218 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
219 outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \
220 outb(__oldlcr, (baseio)+UART_LCR); \
221} while (0)
222
223#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \
224 u8 __oldlcr, __efr; \
225 __oldlcr = inb((baseio)+UART_LCR); \
226 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
227 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
228 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
229 __efr |= MOXA_MUST_EFR_BANK2; \
230 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
231 *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
232 outb(__oldlcr, (baseio)+UART_LCR); \
233} while (0)
234
235#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \
236 u8 __oldlcr, __efr; \
237 __oldlcr = inb((baseio)+UART_LCR); \
238 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
239 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
240 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
241 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
242 outb(__oldlcr, (baseio)+UART_LCR); \
243} while (0)
244
245#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
246 u8 __oldlcr, __efr; \
247 __oldlcr = inb((baseio)+UART_LCR); \
248 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
249 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
250 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
251 __efr |= MOXA_MUST_EFR_SF_TX1; \
252 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
253 outb(__oldlcr, (baseio)+UART_LCR); \
254} while (0)
255
256#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
257 u8 __oldlcr, __efr; \
258 __oldlcr = inb((baseio)+UART_LCR); \
259 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
260 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
261 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
262 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
263 outb(__oldlcr, (baseio)+UART_LCR); \
264} while (0)
265
266#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
267 u8 __oldlcr, __efr; \
268 __oldlcr = inb((baseio)+UART_LCR); \
269 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
270 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
271 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
272 __efr |= MOXA_MUST_EFR_SF_RX1; \
273 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
274 outb(__oldlcr, (baseio)+UART_LCR); \
275} while (0)
276
277#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
278 u8 __oldlcr, __efr; \
279 __oldlcr = inb((baseio)+UART_LCR); \
280 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
281 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
282 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
283 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
284 outb(__oldlcr, (baseio)+UART_LCR); \
285} while (0)
286
287#endif 150#endif
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