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-rw-r--r--drivers/char/ip2/i2ellis.c194
-rw-r--r--drivers/char/ip2/i2ellis.h58
-rw-r--r--drivers/char/ip2/i2hw.h6
-rw-r--r--drivers/char/ip2/i2lib.c141
-rw-r--r--drivers/char/ip2/i2os.h127
-rw-r--r--drivers/char/ip2/ip2main.c68
6 files changed, 211 insertions, 383 deletions
diff --git a/drivers/char/ip2/i2ellis.c b/drivers/char/ip2/i2ellis.c
index 61ef013b8445..3601017f58cf 100644
--- a/drivers/char/ip2/i2ellis.c
+++ b/drivers/char/ip2/i2ellis.c
@@ -53,7 +53,7 @@ static int ii2Safe; // Safe I/O address for delay routine
53 53
54static int iiDelayed; // Set when the iiResetDelay function is 54static int iiDelayed; // Set when the iiResetDelay function is
55 // called. Cleared when ANY board is reset. 55 // called. Cleared when ANY board is reset.
56static rwlock_t Dl_spinlock; 56static DEFINE_RWLOCK(Dl_spinlock);
57 57
58//******** 58//********
59//* Code * 59//* Code *
@@ -82,7 +82,6 @@ static rwlock_t Dl_spinlock;
82static void 82static void
83iiEllisInit(void) 83iiEllisInit(void)
84{ 84{
85 LOCK_INIT(&Dl_spinlock);
86} 85}
87 86
88//****************************************************************************** 87//******************************************************************************
@@ -132,7 +131,7 @@ iiSetAddress( i2eBordStrPtr pB, int address, delayFunc_t delay )
132 || (address & 0x7) 131 || (address & 0x7)
133 ) 132 )
134 { 133 {
135 COMPLETE(pB,I2EE_BADADDR); 134 I2_COMPLETE(pB, I2EE_BADADDR);
136 } 135 }
137 136
138 // Initialize accelerators 137 // Initialize accelerators
@@ -152,7 +151,7 @@ iiSetAddress( i2eBordStrPtr pB, int address, delayFunc_t delay )
152 pB->i2eValid = I2E_MAGIC; 151 pB->i2eValid = I2E_MAGIC;
153 pB->i2eState = II_STATE_COLD; 152 pB->i2eState = II_STATE_COLD;
154 153
155 COMPLETE(pB, I2EE_GOOD); 154 I2_COMPLETE(pB, I2EE_GOOD);
156} 155}
157 156
158//****************************************************************************** 157//******************************************************************************
@@ -177,12 +176,12 @@ iiReset(i2eBordStrPtr pB)
177 // Magic number should be set, else even the address is suspect 176 // Magic number should be set, else even the address is suspect
178 if (pB->i2eValid != I2E_MAGIC) 177 if (pB->i2eValid != I2E_MAGIC)
179 { 178 {
180 COMPLETE(pB, I2EE_BADMAGIC); 179 I2_COMPLETE(pB, I2EE_BADMAGIC);
181 } 180 }
182 181
183 OUTB(pB->i2eBase + FIFO_RESET, 0); // Any data will do 182 outb(0, pB->i2eBase + FIFO_RESET); /* Any data will do */
184 iiDelay(pB, 50); // Pause between resets 183 iiDelay(pB, 50); // Pause between resets
185 OUTB(pB->i2eBase + FIFO_RESET, 0); // Second reset 184 outb(0, pB->i2eBase + FIFO_RESET); /* Second reset */
186 185
187 // We must wait before even attempting to read anything from the FIFO: the 186 // We must wait before even attempting to read anything from the FIFO: the
188 // board's P.O.S.T may actually attempt to read and write its end of the 187 // board's P.O.S.T may actually attempt to read and write its end of the
@@ -203,7 +202,7 @@ iiReset(i2eBordStrPtr pB)
203 // Ensure anything which would have been of use to standard loadware is 202 // Ensure anything which would have been of use to standard loadware is
204 // blanked out, since board has now forgotten everything!. 203 // blanked out, since board has now forgotten everything!.
205 204
206 pB->i2eUsingIrq = IRQ_UNDEFINED; // Not set up to use an interrupt yet 205 pB->i2eUsingIrq = I2_IRQ_UNDEFINED; /* to not use an interrupt so far */
207 pB->i2eWaitingForEmptyFifo = 0; 206 pB->i2eWaitingForEmptyFifo = 0;
208 pB->i2eOutMailWaiting = 0; 207 pB->i2eOutMailWaiting = 0;
209 pB->i2eChannelPtr = NULL; 208 pB->i2eChannelPtr = NULL;
@@ -215,7 +214,7 @@ iiReset(i2eBordStrPtr pB)
215 pB->i2eFatalTrap = NULL; 214 pB->i2eFatalTrap = NULL;
216 pB->i2eFatal = 0; 215 pB->i2eFatal = 0;
217 216
218 COMPLETE(pB, I2EE_GOOD); 217 I2_COMPLETE(pB, I2EE_GOOD);
219} 218}
220 219
221//****************************************************************************** 220//******************************************************************************
@@ -235,14 +234,14 @@ static int
235iiResetDelay(i2eBordStrPtr pB) 234iiResetDelay(i2eBordStrPtr pB)
236{ 235{
237 if (pB->i2eValid != I2E_MAGIC) { 236 if (pB->i2eValid != I2E_MAGIC) {
238 COMPLETE(pB, I2EE_BADMAGIC); 237 I2_COMPLETE(pB, I2EE_BADMAGIC);
239 } 238 }
240 if (pB->i2eState != II_STATE_RESET) { 239 if (pB->i2eState != II_STATE_RESET) {
241 COMPLETE(pB, I2EE_BADSTATE); 240 I2_COMPLETE(pB, I2EE_BADSTATE);
242 } 241 }
243 iiDelay(pB,2000); /* Now we wait for two seconds. */ 242 iiDelay(pB,2000); /* Now we wait for two seconds. */
244 iiDelayed = 1; /* Delay has been called: ok to initialize */ 243 iiDelayed = 1; /* Delay has been called: ok to initialize */
245 COMPLETE(pB, I2EE_GOOD); 244 I2_COMPLETE(pB, I2EE_GOOD);
246} 245}
247 246
248//****************************************************************************** 247//******************************************************************************
@@ -273,12 +272,12 @@ iiInitialize(i2eBordStrPtr pB)
273 272
274 if (pB->i2eValid != I2E_MAGIC) 273 if (pB->i2eValid != I2E_MAGIC)
275 { 274 {
276 COMPLETE(pB, I2EE_BADMAGIC); 275 I2_COMPLETE(pB, I2EE_BADMAGIC);
277 } 276 }
278 277
279 if (pB->i2eState != II_STATE_RESET || !iiDelayed) 278 if (pB->i2eState != II_STATE_RESET || !iiDelayed)
280 { 279 {
281 COMPLETE(pB, I2EE_BADSTATE); 280 I2_COMPLETE(pB, I2EE_BADSTATE);
282 } 281 }
283 282
284 // In case there is a failure short of our completely reading the power-up 283 // In case there is a failure short of our completely reading the power-up
@@ -291,13 +290,12 @@ iiInitialize(i2eBordStrPtr pB)
291 for (itemp = 0; itemp < sizeof(porStr); itemp++) 290 for (itemp = 0; itemp < sizeof(porStr); itemp++)
292 { 291 {
293 // We expect the entire message is ready. 292 // We expect the entire message is ready.
294 if (HAS_NO_INPUT(pB)) 293 if (!I2_HAS_INPUT(pB)) {
295 {
296 pB->i2ePomSize = itemp; 294 pB->i2ePomSize = itemp;
297 COMPLETE(pB, I2EE_PORM_SHORT); 295 I2_COMPLETE(pB, I2EE_PORM_SHORT);
298 } 296 }
299 297
300 pB->i2ePom.c[itemp] = c = BYTE_FROM(pB); 298 pB->i2ePom.c[itemp] = c = inb(pB->i2eData);
301 299
302 // We check the magic numbers as soon as they are supposed to be read 300 // We check the magic numbers as soon as they are supposed to be read
303 // (rather than after) to minimize effect of reading something we 301 // (rather than after) to minimize effect of reading something we
@@ -306,22 +304,22 @@ iiInitialize(i2eBordStrPtr pB)
306 (itemp == POR_2_INDEX && c != POR_MAGIC_2)) 304 (itemp == POR_2_INDEX && c != POR_MAGIC_2))
307 { 305 {
308 pB->i2ePomSize = itemp+1; 306 pB->i2ePomSize = itemp+1;
309 COMPLETE(pB, I2EE_BADMAGIC); 307 I2_COMPLETE(pB, I2EE_BADMAGIC);
310 } 308 }
311 } 309 }
312 310
313 pB->i2ePomSize = itemp; 311 pB->i2ePomSize = itemp;
314 312
315 // Ensure that this was all the data... 313 // Ensure that this was all the data...
316 if (HAS_INPUT(pB)) 314 if (I2_HAS_INPUT(pB))
317 COMPLETE(pB, I2EE_PORM_LONG); 315 I2_COMPLETE(pB, I2EE_PORM_LONG);
318 316
319 // For now, we'll fail to initialize if P.O.S.T reports bad chip mapper: 317 // For now, we'll fail to initialize if P.O.S.T reports bad chip mapper:
320 // Implying we will not be able to download any code either: That's ok: the 318 // Implying we will not be able to download any code either: That's ok: the
321 // condition is pretty explicit. 319 // condition is pretty explicit.
322 if (pB->i2ePom.e.porDiag1 & POR_BAD_MAPPER) 320 if (pB->i2ePom.e.porDiag1 & POR_BAD_MAPPER)
323 { 321 {
324 COMPLETE(pB, I2EE_POSTERR); 322 I2_COMPLETE(pB, I2EE_POSTERR);
325 } 323 }
326 324
327 // Determine anything which must be done differently depending on the family 325 // Determine anything which must be done differently depending on the family
@@ -332,7 +330,7 @@ iiInitialize(i2eBordStrPtr pB)
332 330
333 pB->i2eFifoStyle = FIFO_II; 331 pB->i2eFifoStyle = FIFO_II;
334 pB->i2eFifoSize = 512; // 512 bytes, always 332 pB->i2eFifoSize = 512; // 512 bytes, always
335 pB->i2eDataWidth16 = NO; 333 pB->i2eDataWidth16 = false;
336 334
337 pB->i2eMaxIrq = 15; // Because board cannot tell us it is in an 8-bit 335 pB->i2eMaxIrq = 15; // Because board cannot tell us it is in an 8-bit
338 // slot, we do allow it to be done (documentation!) 336 // slot, we do allow it to be done (documentation!)
@@ -354,7 +352,7 @@ iiInitialize(i2eBordStrPtr pB)
354 // should always be consistent for IntelliPort-II. Ditto below... 352 // should always be consistent for IntelliPort-II. Ditto below...
355 if (pB->i2ePom.e.porPorts1 != 4) 353 if (pB->i2ePom.e.porPorts1 != 4)
356 { 354 {
357 COMPLETE(pB, I2EE_INCONSIST); 355 I2_COMPLETE(pB, I2EE_INCONSIST);
358 } 356 }
359 break; 357 break;
360 358
@@ -364,7 +362,7 @@ iiInitialize(i2eBordStrPtr pB)
364 pB->i2eChannelMap[0] = 0xff; // Eight port 362 pB->i2eChannelMap[0] = 0xff; // Eight port
365 if (pB->i2ePom.e.porPorts1 != 8) 363 if (pB->i2ePom.e.porPorts1 != 8)
366 { 364 {
367 COMPLETE(pB, I2EE_INCONSIST); 365 I2_COMPLETE(pB, I2EE_INCONSIST);
368 } 366 }
369 break; 367 break;
370 368
@@ -373,7 +371,7 @@ iiInitialize(i2eBordStrPtr pB)
373 pB->i2eChannelMap[0] = 0x3f; // Six Port 371 pB->i2eChannelMap[0] = 0x3f; // Six Port
374 if (pB->i2ePom.e.porPorts1 != 6) 372 if (pB->i2ePom.e.porPorts1 != 6)
375 { 373 {
376 COMPLETE(pB, I2EE_INCONSIST); 374 I2_COMPLETE(pB, I2EE_INCONSIST);
377 } 375 }
378 break; 376 break;
379 } 377 }
@@ -402,7 +400,7 @@ iiInitialize(i2eBordStrPtr pB)
402 400
403 if (itemp < 8 || itemp > 15) 401 if (itemp < 8 || itemp > 15)
404 { 402 {
405 COMPLETE(pB, I2EE_INCONSIST); 403 I2_COMPLETE(pB, I2EE_INCONSIST);
406 } 404 }
407 pB->i2eFifoSize = (1 << itemp); 405 pB->i2eFifoSize = (1 << itemp);
408 406
@@ -450,26 +448,26 @@ iiInitialize(i2eBordStrPtr pB)
450 switch (pB->i2ePom.e.porBus & (POR_BUS_SLOT16 | POR_BUS_DIP16) ) 448 switch (pB->i2ePom.e.porBus & (POR_BUS_SLOT16 | POR_BUS_DIP16) )
451 { 449 {
452 case POR_BUS_SLOT16 | POR_BUS_DIP16: 450 case POR_BUS_SLOT16 | POR_BUS_DIP16:
453 pB->i2eDataWidth16 = YES; 451 pB->i2eDataWidth16 = true;
454 pB->i2eMaxIrq = 15; 452 pB->i2eMaxIrq = 15;
455 break; 453 break;
456 454
457 case POR_BUS_SLOT16: 455 case POR_BUS_SLOT16:
458 pB->i2eDataWidth16 = NO; 456 pB->i2eDataWidth16 = false;
459 pB->i2eMaxIrq = 15; 457 pB->i2eMaxIrq = 15;
460 break; 458 break;
461 459
462 case 0: 460 case 0:
463 case POR_BUS_DIP16: // In an 8-bit slot, DIP switch don't care. 461 case POR_BUS_DIP16: // In an 8-bit slot, DIP switch don't care.
464 default: 462 default:
465 pB->i2eDataWidth16 = NO; 463 pB->i2eDataWidth16 = false;
466 pB->i2eMaxIrq = 7; 464 pB->i2eMaxIrq = 7;
467 break; 465 break;
468 } 466 }
469 break; // POR_ID_FIIEX case 467 break; // POR_ID_FIIEX case
470 468
471 default: // Unknown type of board 469 default: // Unknown type of board
472 COMPLETE(pB, I2EE_BAD_FAMILY); 470 I2_COMPLETE(pB, I2EE_BAD_FAMILY);
473 break; 471 break;
474 } // End the switch based on family 472 } // End the switch based on family
475 473
@@ -483,17 +481,14 @@ iiInitialize(i2eBordStrPtr pB)
483 { 481 {
484 case POR_BUS_T_ISA: 482 case POR_BUS_T_ISA:
485 case POR_BUS_T_UNK: // If the type of bus is undeclared, assume ok. 483 case POR_BUS_T_UNK: // If the type of bus is undeclared, assume ok.
486 pB->i2eChangeIrq = YES;
487 break;
488 case POR_BUS_T_MCA: 484 case POR_BUS_T_MCA:
489 case POR_BUS_T_EISA: 485 case POR_BUS_T_EISA:
490 pB->i2eChangeIrq = NO;
491 break; 486 break;
492 default: 487 default:
493 COMPLETE(pB, I2EE_BADBUS); 488 I2_COMPLETE(pB, I2EE_BADBUS);
494 } 489 }
495 490
496 if (pB->i2eDataWidth16 == YES) 491 if (pB->i2eDataWidth16)
497 { 492 {
498 pB->i2eWriteBuf = iiWriteBuf16; 493 pB->i2eWriteBuf = iiWriteBuf16;
499 pB->i2eReadBuf = iiReadBuf16; 494 pB->i2eReadBuf = iiReadBuf16;
@@ -529,7 +524,7 @@ iiInitialize(i2eBordStrPtr pB)
529 break; 524 break;
530 525
531 default: 526 default:
532 COMPLETE(pB, I2EE_INCONSIST); 527 I2_COMPLETE(pB, I2EE_INCONSIST);
533 } 528 }
534 529
535 // Initialize state information. 530 // Initialize state information.
@@ -549,7 +544,7 @@ iiInitialize(i2eBordStrPtr pB)
549 // Everything is ok now, return with good status/ 544 // Everything is ok now, return with good status/
550 545
551 pB->i2eValid = I2E_MAGIC; 546 pB->i2eValid = I2E_MAGIC;
552 COMPLETE(pB, I2EE_GOOD); 547 I2_COMPLETE(pB, I2EE_GOOD);
553} 548}
554 549
555//****************************************************************************** 550//******************************************************************************
@@ -658,7 +653,7 @@ ii2DelayIO(unsigned int mseconds)
658 while(mseconds--) { 653 while(mseconds--) {
659 int i = ii2DelValue; 654 int i = ii2DelValue;
660 while ( i-- ) { 655 while ( i-- ) {
661 INB ( ii2Safe ); 656 inb(ii2Safe);
662 } 657 }
663 } 658 }
664} 659}
@@ -709,11 +704,11 @@ iiWriteBuf16(i2eBordStrPtr pB, unsigned char *address, int count)
709{ 704{
710 // Rudimentary sanity checking here. 705 // Rudimentary sanity checking here.
711 if (pB->i2eValid != I2E_MAGIC) 706 if (pB->i2eValid != I2E_MAGIC)
712 COMPLETE(pB, I2EE_INVALID); 707 I2_COMPLETE(pB, I2EE_INVALID);
713 708
714 OUTSW ( pB->i2eData, address, count); 709 I2_OUTSW(pB->i2eData, address, count);
715 710
716 COMPLETE(pB, I2EE_GOOD); 711 I2_COMPLETE(pB, I2EE_GOOD);
717} 712}
718 713
719//****************************************************************************** 714//******************************************************************************
@@ -738,11 +733,11 @@ iiWriteBuf8(i2eBordStrPtr pB, unsigned char *address, int count)
738{ 733{
739 /* Rudimentary sanity checking here */ 734 /* Rudimentary sanity checking here */
740 if (pB->i2eValid != I2E_MAGIC) 735 if (pB->i2eValid != I2E_MAGIC)
741 COMPLETE(pB, I2EE_INVALID); 736 I2_COMPLETE(pB, I2EE_INVALID);
742 737
743 OUTSB ( pB->i2eData, address, count ); 738 I2_OUTSB(pB->i2eData, address, count);
744 739
745 COMPLETE(pB, I2EE_GOOD); 740 I2_COMPLETE(pB, I2EE_GOOD);
746} 741}
747 742
748//****************************************************************************** 743//******************************************************************************
@@ -767,11 +762,11 @@ iiReadBuf16(i2eBordStrPtr pB, unsigned char *address, int count)
767{ 762{
768 // Rudimentary sanity checking here. 763 // Rudimentary sanity checking here.
769 if (pB->i2eValid != I2E_MAGIC) 764 if (pB->i2eValid != I2E_MAGIC)
770 COMPLETE(pB, I2EE_INVALID); 765 I2_COMPLETE(pB, I2EE_INVALID);
771 766
772 INSW ( pB->i2eData, address, count); 767 I2_INSW(pB->i2eData, address, count);
773 768
774 COMPLETE(pB, I2EE_GOOD); 769 I2_COMPLETE(pB, I2EE_GOOD);
775} 770}
776 771
777//****************************************************************************** 772//******************************************************************************
@@ -796,11 +791,11 @@ iiReadBuf8(i2eBordStrPtr pB, unsigned char *address, int count)
796{ 791{
797 // Rudimentary sanity checking here. 792 // Rudimentary sanity checking here.
798 if (pB->i2eValid != I2E_MAGIC) 793 if (pB->i2eValid != I2E_MAGIC)
799 COMPLETE(pB, I2EE_INVALID); 794 I2_COMPLETE(pB, I2EE_INVALID);
800 795
801 INSB ( pB->i2eData, address, count); 796 I2_INSB(pB->i2eData, address, count);
802 797
803 COMPLETE(pB, I2EE_GOOD); 798 I2_COMPLETE(pB, I2EE_GOOD);
804} 799}
805 800
806//****************************************************************************** 801//******************************************************************************
@@ -820,7 +815,7 @@ iiReadBuf8(i2eBordStrPtr pB, unsigned char *address, int count)
820static unsigned short 815static unsigned short
821iiReadWord16(i2eBordStrPtr pB) 816iiReadWord16(i2eBordStrPtr pB)
822{ 817{
823 return (unsigned short)( INW(pB->i2eData) ); 818 return inw(pB->i2eData);
824} 819}
825 820
826//****************************************************************************** 821//******************************************************************************
@@ -842,9 +837,9 @@ iiReadWord8(i2eBordStrPtr pB)
842{ 837{
843 unsigned short urs; 838 unsigned short urs;
844 839
845 urs = INB ( pB->i2eData ); 840 urs = inb(pB->i2eData);
846 841
847 return ( ( INB ( pB->i2eData ) << 8 ) | urs ); 842 return (inb(pB->i2eData) << 8) | urs;
848} 843}
849 844
850//****************************************************************************** 845//******************************************************************************
@@ -865,7 +860,7 @@ iiReadWord8(i2eBordStrPtr pB)
865static void 860static void
866iiWriteWord16(i2eBordStrPtr pB, unsigned short value) 861iiWriteWord16(i2eBordStrPtr pB, unsigned short value)
867{ 862{
868 WORD_TO(pB, (int)value); 863 outw((int)value, pB->i2eData);
869} 864}
870 865
871//****************************************************************************** 866//******************************************************************************
@@ -886,8 +881,8 @@ iiWriteWord16(i2eBordStrPtr pB, unsigned short value)
886static void 881static void
887iiWriteWord8(i2eBordStrPtr pB, unsigned short value) 882iiWriteWord8(i2eBordStrPtr pB, unsigned short value)
888{ 883{
889 BYTE_TO(pB, (char)value); 884 outb((char)value, pB->i2eData);
890 BYTE_TO(pB, (char)(value >> 8) ); 885 outb((char)(value >> 8), pB->i2eData);
891} 886}
892 887
893//****************************************************************************** 888//******************************************************************************
@@ -939,30 +934,30 @@ iiWaitForTxEmptyII(i2eBordStrPtr pB, int mSdelay)
939 // interrupts of any kind. 934 // interrupts of any kind.
940 935
941 936
942 WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags) 937 write_lock_irqsave(&Dl_spinlock, flags);
943 OUTB(pB->i2ePointer, SEL_COMMAND); 938 outb(SEL_COMMAND, pB->i2ePointer);
944 OUTB(pB->i2ePointer, SEL_CMD_SH); 939 outb(SEL_CMD_SH, pB->i2ePointer);
945 940
946 itemp = INB(pB->i2eStatus); 941 itemp = inb(pB->i2eStatus);
947 942
948 OUTB(pB->i2ePointer, SEL_COMMAND); 943 outb(SEL_COMMAND, pB->i2ePointer);
949 OUTB(pB->i2ePointer, SEL_CMD_UNSH); 944 outb(SEL_CMD_UNSH, pB->i2ePointer);
950 945
951 if (itemp & ST_IN_EMPTY) 946 if (itemp & ST_IN_EMPTY)
952 { 947 {
953 UPDATE_FIFO_ROOM(pB); 948 I2_UPDATE_FIFO_ROOM(pB);
954 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) 949 write_unlock_irqrestore(&Dl_spinlock, flags);
955 COMPLETE(pB, I2EE_GOOD); 950 I2_COMPLETE(pB, I2EE_GOOD);
956 } 951 }
957 952
958 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) 953 write_unlock_irqrestore(&Dl_spinlock, flags);
959 954
960 if (mSdelay-- == 0) 955 if (mSdelay-- == 0)
961 break; 956 break;
962 957
963 iiDelay(pB, 1); /* 1 mS granularity on checking condition */ 958 iiDelay(pB, 1); /* 1 mS granularity on checking condition */
964 } 959 }
965 COMPLETE(pB, I2EE_TXE_TIME); 960 I2_COMPLETE(pB, I2EE_TXE_TIME);
966} 961}
967 962
968//****************************************************************************** 963//******************************************************************************
@@ -1002,21 +997,21 @@ iiWaitForTxEmptyIIEX(i2eBordStrPtr pB, int mSdelay)
1002 // you will generally not want to service interrupts or in any way 997 // you will generally not want to service interrupts or in any way
1003 // disrupt the assumptions implicit in the larger context. 998 // disrupt the assumptions implicit in the larger context.
1004 999
1005 WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags) 1000 write_lock_irqsave(&Dl_spinlock, flags);
1006 1001
1007 if (INB(pB->i2eStatus) & STE_OUT_MT) { 1002 if (inb(pB->i2eStatus) & STE_OUT_MT) {
1008 UPDATE_FIFO_ROOM(pB); 1003 I2_UPDATE_FIFO_ROOM(pB);
1009 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) 1004 write_unlock_irqrestore(&Dl_spinlock, flags);
1010 COMPLETE(pB, I2EE_GOOD); 1005 I2_COMPLETE(pB, I2EE_GOOD);
1011 } 1006 }
1012 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) 1007 write_unlock_irqrestore(&Dl_spinlock, flags);
1013 1008
1014 if (mSdelay-- == 0) 1009 if (mSdelay-- == 0)
1015 break; 1010 break;
1016 1011
1017 iiDelay(pB, 1); // 1 mS granularity on checking condition 1012 iiDelay(pB, 1); // 1 mS granularity on checking condition
1018 } 1013 }
1019 COMPLETE(pB, I2EE_TXE_TIME); 1014 I2_COMPLETE(pB, I2EE_TXE_TIME);
1020} 1015}
1021 1016
1022//****************************************************************************** 1017//******************************************************************************
@@ -1038,8 +1033,8 @@ static int
1038iiTxMailEmptyII(i2eBordStrPtr pB) 1033iiTxMailEmptyII(i2eBordStrPtr pB)
1039{ 1034{
1040 int port = pB->i2ePointer; 1035 int port = pB->i2ePointer;
1041 OUTB ( port, SEL_OUTMAIL ); 1036 outb(SEL_OUTMAIL, port);
1042 return ( INB(port) == 0 ); 1037 return inb(port) == 0;
1043} 1038}
1044 1039
1045//****************************************************************************** 1040//******************************************************************************
@@ -1060,7 +1055,7 @@ iiTxMailEmptyII(i2eBordStrPtr pB)
1060static int 1055static int
1061iiTxMailEmptyIIEX(i2eBordStrPtr pB) 1056iiTxMailEmptyIIEX(i2eBordStrPtr pB)
1062{ 1057{
1063 return !(INB(pB->i2eStatus) & STE_OUT_MAIL); 1058 return !(inb(pB->i2eStatus) & STE_OUT_MAIL);
1064} 1059}
1065 1060
1066//****************************************************************************** 1061//******************************************************************************
@@ -1084,10 +1079,10 @@ iiTrySendMailII(i2eBordStrPtr pB, unsigned char mail)
1084{ 1079{
1085 int port = pB->i2ePointer; 1080 int port = pB->i2ePointer;
1086 1081
1087 OUTB(port, SEL_OUTMAIL); 1082 outb(SEL_OUTMAIL, port);
1088 if (INB(port) == 0) { 1083 if (inb(port) == 0) {
1089 OUTB(port, SEL_OUTMAIL); 1084 outb(SEL_OUTMAIL, port);
1090 OUTB(port, mail); 1085 outb(mail, port);
1091 return 1; 1086 return 1;
1092 } 1087 }
1093 return 0; 1088 return 0;
@@ -1112,10 +1107,9 @@ iiTrySendMailII(i2eBordStrPtr pB, unsigned char mail)
1112static int 1107static int
1113iiTrySendMailIIEX(i2eBordStrPtr pB, unsigned char mail) 1108iiTrySendMailIIEX(i2eBordStrPtr pB, unsigned char mail)
1114{ 1109{
1115 if(INB(pB->i2eStatus) & STE_OUT_MAIL) { 1110 if (inb(pB->i2eStatus) & STE_OUT_MAIL)
1116 return 0; 1111 return 0;
1117 } 1112 outb(mail, pB->i2eXMail);
1118 OUTB(pB->i2eXMail, mail);
1119 return 1; 1113 return 1;
1120} 1114}
1121 1115
@@ -1136,9 +1130,9 @@ iiTrySendMailIIEX(i2eBordStrPtr pB, unsigned char mail)
1136static unsigned short 1130static unsigned short
1137iiGetMailII(i2eBordStrPtr pB) 1131iiGetMailII(i2eBordStrPtr pB)
1138{ 1132{
1139 if (HAS_MAIL(pB)) { 1133 if (I2_HAS_MAIL(pB)) {
1140 OUTB(pB->i2ePointer, SEL_INMAIL); 1134 outb(SEL_INMAIL, pB->i2ePointer);
1141 return INB(pB->i2ePointer); 1135 return inb(pB->i2ePointer);
1142 } else { 1136 } else {
1143 return NO_MAIL_HERE; 1137 return NO_MAIL_HERE;
1144 } 1138 }
@@ -1161,11 +1155,10 @@ iiGetMailII(i2eBordStrPtr pB)
1161static unsigned short 1155static unsigned short
1162iiGetMailIIEX(i2eBordStrPtr pB) 1156iiGetMailIIEX(i2eBordStrPtr pB)
1163{ 1157{
1164 if (HAS_MAIL(pB)) { 1158 if (I2_HAS_MAIL(pB))
1165 return INB(pB->i2eXMail); 1159 return inb(pB->i2eXMail);
1166 } else { 1160 else
1167 return NO_MAIL_HERE; 1161 return NO_MAIL_HERE;
1168 }
1169} 1162}
1170 1163
1171//****************************************************************************** 1164//******************************************************************************
@@ -1184,8 +1177,8 @@ iiGetMailIIEX(i2eBordStrPtr pB)
1184static void 1177static void
1185iiEnableMailIrqII(i2eBordStrPtr pB) 1178iiEnableMailIrqII(i2eBordStrPtr pB)
1186{ 1179{
1187 OUTB(pB->i2ePointer, SEL_MASK); 1180 outb(SEL_MASK, pB->i2ePointer);
1188 OUTB(pB->i2ePointer, ST_IN_MAIL); 1181 outb(ST_IN_MAIL, pB->i2ePointer);
1189} 1182}
1190 1183
1191//****************************************************************************** 1184//******************************************************************************
@@ -1204,7 +1197,7 @@ iiEnableMailIrqII(i2eBordStrPtr pB)
1204static void 1197static void
1205iiEnableMailIrqIIEX(i2eBordStrPtr pB) 1198iiEnableMailIrqIIEX(i2eBordStrPtr pB)
1206{ 1199{
1207 OUTB(pB->i2eXMask, MX_IN_MAIL); 1200 outb(MX_IN_MAIL, pB->i2eXMask);
1208} 1201}
1209 1202
1210//****************************************************************************** 1203//******************************************************************************
@@ -1223,8 +1216,8 @@ iiEnableMailIrqIIEX(i2eBordStrPtr pB)
1223static void 1216static void
1224iiWriteMaskII(i2eBordStrPtr pB, unsigned char value) 1217iiWriteMaskII(i2eBordStrPtr pB, unsigned char value)
1225{ 1218{
1226 OUTB(pB->i2ePointer, SEL_MASK); 1219 outb(SEL_MASK, pB->i2ePointer);
1227 OUTB(pB->i2ePointer, value); 1220 outb(value, pB->i2ePointer);
1228} 1221}
1229 1222
1230//****************************************************************************** 1223//******************************************************************************
@@ -1243,7 +1236,7 @@ iiWriteMaskII(i2eBordStrPtr pB, unsigned char value)
1243static void 1236static void
1244iiWriteMaskIIEX(i2eBordStrPtr pB, unsigned char value) 1237iiWriteMaskIIEX(i2eBordStrPtr pB, unsigned char value)
1245{ 1238{
1246 OUTB(pB->i2eXMask, value); 1239 outb(value, pB->i2eXMask);
1247} 1240}
1248 1241
1249//****************************************************************************** 1242//******************************************************************************
@@ -1354,9 +1347,8 @@ iiDownloadBlock ( i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard)
1354 // immediately and be harmless, though not strictly necessary. 1347 // immediately and be harmless, though not strictly necessary.
1355 itemp = MAX_DLOAD_ACK_TIME/10; 1348 itemp = MAX_DLOAD_ACK_TIME/10;
1356 while (--itemp) { 1349 while (--itemp) {
1357 if (HAS_INPUT(pB)) { 1350 if (I2_HAS_INPUT(pB)) {
1358 switch(BYTE_FROM(pB)) 1351 switch (inb(pB->i2eData)) {
1359 {
1360 case LOADWARE_OK: 1352 case LOADWARE_OK:
1361 pB->i2eState = 1353 pB->i2eState =
1362 isStandard ? II_STATE_STDLOADED :II_STATE_LOADED; 1354 isStandard ? II_STATE_STDLOADED :II_STATE_LOADED;
diff --git a/drivers/char/ip2/i2ellis.h b/drivers/char/ip2/i2ellis.h
index 433305062fb8..c88a64e527aa 100644
--- a/drivers/char/ip2/i2ellis.h
+++ b/drivers/char/ip2/i2ellis.h
@@ -185,10 +185,6 @@ typedef struct _i2eBordStr
185 // The highest allowable IRQ, based on the 185 // The highest allowable IRQ, based on the
186 // slot size. 186 // slot size.
187 187
188 unsigned char i2eChangeIrq;
189 // Whether tis valid to change IRQ's
190 // ISA = ok, EISA, MicroChannel, no
191
192 // Accelerators for various addresses on the board 188 // Accelerators for various addresses on the board
193 int i2eBase; // I/O Address of the Board 189 int i2eBase; // I/O Address of the Board
194 int i2eData; // From here data transfers happen 190 int i2eData; // From here data transfers happen
@@ -431,12 +427,6 @@ typedef struct _i2eBordStr
431// Manifests for i2eBordStr: 427// Manifests for i2eBordStr:
432//------------------------------------------- 428//-------------------------------------------
433 429
434#define YES 1
435#define NO 0
436
437#define NULLFUNC (void (*)(void))0
438#define NULLPTR (void *)0
439
440typedef void (*delayFunc_t)(unsigned int); 430typedef void (*delayFunc_t)(unsigned int);
441 431
442// i2eValid 432// i2eValid
@@ -494,8 +484,8 @@ typedef void (*delayFunc_t)(unsigned int);
494 484
495// i2eUsingIrq 485// i2eUsingIrq
496// 486//
497#define IRQ_UNDEFINED 0x1352 // No valid irq (or polling = 0) can ever 487#define I2_IRQ_UNDEFINED 0x1352 /* No valid irq (or polling = 0) can
498 // promote to this! 488 * ever promote to this! */
499//------------------------------------------ 489//------------------------------------------
500// Handy Macros for i2ellis.c and others 490// Handy Macros for i2ellis.c and others
501// Note these are common to -II and -IIEX 491// Note these are common to -II and -IIEX
@@ -504,41 +494,14 @@ typedef void (*delayFunc_t)(unsigned int);
504// Given a pointer to the board structure, does the input FIFO have any data or 494// Given a pointer to the board structure, does the input FIFO have any data or
505// not? 495// not?
506// 496//
507#define HAS_INPUT(pB) !(INB(pB->i2eStatus) & ST_IN_EMPTY) 497#define I2_HAS_INPUT(pB) !(inb(pB->i2eStatus) & ST_IN_EMPTY)
508#define HAS_NO_INPUT(pB) (INB(pB->i2eStatus) & ST_IN_EMPTY)
509
510// Given a pointer to board structure, read a byte or word from the fifo
511//
512#define BYTE_FROM(pB) (unsigned char)INB(pB->i2eData)
513#define WORD_FROM(pB) (unsigned short)INW(pB->i2eData)
514
515// Given a pointer to board structure, is there room for any data to be written
516// to the data fifo?
517//
518#define HAS_OUTROOM(pB) !(INB(pB->i2eStatus) & ST_OUT_FULL)
519#define HAS_NO_OUTROOM(pB) (INB(pB->i2eStatus) & ST_OUT_FULL)
520
521// Given a pointer to board structure, write a single byte to the fifo
522// structure. Note that for 16-bit interfaces, the high order byte is undefined
523// and unknown.
524//
525#define BYTE_TO(pB, c) OUTB(pB->i2eData,(c))
526
527// Write a word to the fifo structure. For 8-bit interfaces, this may have
528// unknown results.
529//
530#define WORD_TO(pB, c) OUTW(pB->i2eData,(c))
531 498
532// Given a pointer to the board structure, is there anything in the incoming 499// Given a pointer to the board structure, is there anything in the incoming
533// mailbox? 500// mailbox?
534// 501//
535#define HAS_MAIL(pB) (INB(pB->i2eStatus) & ST_IN_MAIL) 502#define I2_HAS_MAIL(pB) (inb(pB->i2eStatus) & ST_IN_MAIL)
536 503
537#define UPDATE_FIFO_ROOM(pB) (pB)->i2eFifoRemains=(pB)->i2eFifoSize 504#define I2_UPDATE_FIFO_ROOM(pB) ((pB)->i2eFifoRemains = (pB)->i2eFifoSize)
538
539// Handy macro to round up a number (like the buffer write and read routines do)
540//
541#define ROUNDUP(number) (((number)+1) & (~1))
542 505
543//------------------------------------------ 506//------------------------------------------
544// Function Declarations for i2ellis.c 507// Function Declarations for i2ellis.c
@@ -593,20 +556,11 @@ static int iiDownloadBlock(i2eBordStrPtr, loadHdrStrPtr, int);
593// 556//
594static int iiDownloadAll(i2eBordStrPtr, loadHdrStrPtr, int, int); 557static int iiDownloadAll(i2eBordStrPtr, loadHdrStrPtr, int, int);
595 558
596// Called indirectly always. Needed externally so the routine might be
597// SPECIFIED as an argument to iiReset()
598//
599//static void ii2DelayIO(unsigned int); // N-millisecond delay using
600 //hardware spin
601//static void ii2DelayTimer(unsigned int); // N-millisecond delay using Linux
602 //timer
603
604// Many functions defined here return True if good, False otherwise, with an 559// Many functions defined here return True if good, False otherwise, with an
605// error code in i2eError field. Here is a handy macro for setting the error 560// error code in i2eError field. Here is a handy macro for setting the error
606// code and returning. 561// code and returning.
607// 562//
608#define COMPLETE(pB,code) \ 563#define I2_COMPLETE(pB,code) do { \
609 do { \
610 pB->i2eError = code; \ 564 pB->i2eError = code; \
611 return (code == I2EE_GOOD);\ 565 return (code == I2EE_GOOD);\
612 } while (0) 566 } while (0)
diff --git a/drivers/char/ip2/i2hw.h b/drivers/char/ip2/i2hw.h
index 15fe04e748f4..8aa6e7ab8d5b 100644
--- a/drivers/char/ip2/i2hw.h
+++ b/drivers/char/ip2/i2hw.h
@@ -129,7 +129,6 @@ registers, use byte operations only.
129//------------------------------------------------ 129//------------------------------------------------
130// 130//
131#include "ip2types.h" 131#include "ip2types.h"
132#include "i2os.h" /* For any o.s., compiler, or host-related issues */
133 132
134//------------------------------------------------------------------------- 133//-------------------------------------------------------------------------
135// Manifests for the I/O map: 134// Manifests for the I/O map:
@@ -644,5 +643,10 @@ typedef union _loadHdrStr
644#define ABS_BIGGEST_BOX 16 // Absolute the most ports per box 643#define ABS_BIGGEST_BOX 16 // Absolute the most ports per box
645#define ABS_MOST_PORTS (ABS_MAX_BOXES * ABS_BIGGEST_BOX) 644#define ABS_MOST_PORTS (ABS_MAX_BOXES * ABS_BIGGEST_BOX)
646 645
646#define I2_OUTSW(port, addr, count) outsw((port), (addr), (((count)+1)/2))
647#define I2_OUTSB(port, addr, count) outsb((port), (addr), (((count)+1))&-2)
648#define I2_INSW(port, addr, count) insw((port), (addr), (((count)+1)/2))
649#define I2_INSB(port, addr, count) insb((port), (addr), (((count)+1))&-2)
650
647#endif // I2HW_H 651#endif // I2HW_H
648 652
diff --git a/drivers/char/ip2/i2lib.c b/drivers/char/ip2/i2lib.c
index 9c25320121ef..938879cc7bcc 100644
--- a/drivers/char/ip2/i2lib.c
+++ b/drivers/char/ip2/i2lib.c
@@ -227,17 +227,17 @@ i2InitChannels ( i2eBordStrPtr pB, int nChannels, i2ChanStrPtr pCh)
227 i2ChanStrPtr *ppCh; 227 i2ChanStrPtr *ppCh;
228 228
229 if (pB->i2eValid != I2E_MAGIC) { 229 if (pB->i2eValid != I2E_MAGIC) {
230 COMPLETE(pB, I2EE_BADMAGIC); 230 I2_COMPLETE(pB, I2EE_BADMAGIC);
231 } 231 }
232 if (pB->i2eState != II_STATE_STDLOADED) { 232 if (pB->i2eState != II_STATE_STDLOADED) {
233 COMPLETE(pB, I2EE_BADSTATE); 233 I2_COMPLETE(pB, I2EE_BADSTATE);
234 } 234 }
235 235
236 LOCK_INIT(&pB->read_fifo_spinlock); 236 rwlock_init(&pB->read_fifo_spinlock);
237 LOCK_INIT(&pB->write_fifo_spinlock); 237 rwlock_init(&pB->write_fifo_spinlock);
238 LOCK_INIT(&pB->Dbuf_spinlock); 238 rwlock_init(&pB->Dbuf_spinlock);
239 LOCK_INIT(&pB->Bbuf_spinlock); 239 rwlock_init(&pB->Bbuf_spinlock);
240 LOCK_INIT(&pB->Fbuf_spinlock); 240 rwlock_init(&pB->Fbuf_spinlock);
241 241
242 // NO LOCK needed yet - this is init 242 // NO LOCK needed yet - this is init
243 243
@@ -259,10 +259,10 @@ i2InitChannels ( i2eBordStrPtr pB, int nChannels, i2ChanStrPtr pCh)
259 if ( !(pB->i2eChannelMap[index >> 4] & (1 << (index & 0xf)) ) ) { 259 if ( !(pB->i2eChannelMap[index >> 4] & (1 << (index & 0xf)) ) ) {
260 continue; 260 continue;
261 } 261 }
262 LOCK_INIT(&pCh->Ibuf_spinlock); 262 rwlock_init(&pCh->Ibuf_spinlock);
263 LOCK_INIT(&pCh->Obuf_spinlock); 263 rwlock_init(&pCh->Obuf_spinlock);
264 LOCK_INIT(&pCh->Cbuf_spinlock); 264 rwlock_init(&pCh->Cbuf_spinlock);
265 LOCK_INIT(&pCh->Pbuf_spinlock); 265 rwlock_init(&pCh->Pbuf_spinlock);
266 // NO LOCK needed yet - this is init 266 // NO LOCK needed yet - this is init
267 // Set up validity flag according to support level 267 // Set up validity flag according to support level
268 if (pB->i2eGoodMap[index >> 4] & (1 << (index & 0xf)) ) { 268 if (pB->i2eGoodMap[index >> 4] & (1 << (index & 0xf)) ) {
@@ -347,7 +347,7 @@ i2InitChannels ( i2eBordStrPtr pB, int nChannels, i2ChanStrPtr pCh)
347 } 347 }
348 // No need to check for wrap here; this is initialization. 348 // No need to check for wrap here; this is initialization.
349 pB->i2Fbuf_stuff = stuffIndex; 349 pB->i2Fbuf_stuff = stuffIndex;
350 COMPLETE(pB, I2EE_GOOD); 350 I2_COMPLETE(pB, I2EE_GOOD);
351 351
352} 352}
353 353
@@ -374,7 +374,7 @@ i2DeQueueNeeds(i2eBordStrPtr pB, int type)
374 374
375 case NEED_INLINE: 375 case NEED_INLINE:
376 376
377 WRITE_LOCK_IRQSAVE(&pB->Dbuf_spinlock,flags); 377 write_lock_irqsave(&pB->Dbuf_spinlock, flags);
378 if ( pB->i2Dbuf_stuff != pB->i2Dbuf_strip) 378 if ( pB->i2Dbuf_stuff != pB->i2Dbuf_strip)
379 { 379 {
380 queueIndex = pB->i2Dbuf_strip; 380 queueIndex = pB->i2Dbuf_strip;
@@ -386,12 +386,12 @@ i2DeQueueNeeds(i2eBordStrPtr pB, int type)
386 pB->i2Dbuf_strip = queueIndex; 386 pB->i2Dbuf_strip = queueIndex;
387 pCh->channelNeeds &= ~NEED_INLINE; 387 pCh->channelNeeds &= ~NEED_INLINE;
388 } 388 }
389 WRITE_UNLOCK_IRQRESTORE(&pB->Dbuf_spinlock,flags); 389 write_unlock_irqrestore(&pB->Dbuf_spinlock, flags);
390 break; 390 break;
391 391
392 case NEED_BYPASS: 392 case NEED_BYPASS:
393 393
394 WRITE_LOCK_IRQSAVE(&pB->Bbuf_spinlock,flags); 394 write_lock_irqsave(&pB->Bbuf_spinlock, flags);
395 if (pB->i2Bbuf_stuff != pB->i2Bbuf_strip) 395 if (pB->i2Bbuf_stuff != pB->i2Bbuf_strip)
396 { 396 {
397 queueIndex = pB->i2Bbuf_strip; 397 queueIndex = pB->i2Bbuf_strip;
@@ -403,12 +403,12 @@ i2DeQueueNeeds(i2eBordStrPtr pB, int type)
403 pB->i2Bbuf_strip = queueIndex; 403 pB->i2Bbuf_strip = queueIndex;
404 pCh->channelNeeds &= ~NEED_BYPASS; 404 pCh->channelNeeds &= ~NEED_BYPASS;
405 } 405 }
406 WRITE_UNLOCK_IRQRESTORE(&pB->Bbuf_spinlock,flags); 406 write_unlock_irqrestore(&pB->Bbuf_spinlock, flags);
407 break; 407 break;
408 408
409 case NEED_FLOW: 409 case NEED_FLOW:
410 410
411 WRITE_LOCK_IRQSAVE(&pB->Fbuf_spinlock,flags); 411 write_lock_irqsave(&pB->Fbuf_spinlock, flags);
412 if (pB->i2Fbuf_stuff != pB->i2Fbuf_strip) 412 if (pB->i2Fbuf_stuff != pB->i2Fbuf_strip)
413 { 413 {
414 queueIndex = pB->i2Fbuf_strip; 414 queueIndex = pB->i2Fbuf_strip;
@@ -420,7 +420,7 @@ i2DeQueueNeeds(i2eBordStrPtr pB, int type)
420 pB->i2Fbuf_strip = queueIndex; 420 pB->i2Fbuf_strip = queueIndex;
421 pCh->channelNeeds &= ~NEED_FLOW; 421 pCh->channelNeeds &= ~NEED_FLOW;
422 } 422 }
423 WRITE_UNLOCK_IRQRESTORE(&pB->Fbuf_spinlock,flags); 423 write_unlock_irqrestore(&pB->Fbuf_spinlock, flags);
424 break; 424 break;
425 default: 425 default:
426 printk(KERN_ERR "i2DeQueueNeeds called with bad type:%x\n",type); 426 printk(KERN_ERR "i2DeQueueNeeds called with bad type:%x\n",type);
@@ -453,7 +453,7 @@ i2QueueNeeds(i2eBordStrPtr pB, i2ChanStrPtr pCh, int type)
453 453
454 case NEED_INLINE: 454 case NEED_INLINE:
455 455
456 WRITE_LOCK_IRQSAVE(&pB->Dbuf_spinlock,flags); 456 write_lock_irqsave(&pB->Dbuf_spinlock, flags);
457 if ( !(pCh->channelNeeds & NEED_INLINE) ) 457 if ( !(pCh->channelNeeds & NEED_INLINE) )
458 { 458 {
459 pCh->channelNeeds |= NEED_INLINE; 459 pCh->channelNeeds |= NEED_INLINE;
@@ -463,12 +463,12 @@ i2QueueNeeds(i2eBordStrPtr pB, i2ChanStrPtr pCh, int type)
463 queueIndex = 0; 463 queueIndex = 0;
464 pB->i2Dbuf_stuff = queueIndex; 464 pB->i2Dbuf_stuff = queueIndex;
465 } 465 }
466 WRITE_UNLOCK_IRQRESTORE(&pB->Dbuf_spinlock,flags); 466 write_unlock_irqrestore(&pB->Dbuf_spinlock, flags);
467 break; 467 break;
468 468
469 case NEED_BYPASS: 469 case NEED_BYPASS:
470 470
471 WRITE_LOCK_IRQSAVE(&pB->Bbuf_spinlock,flags); 471 write_lock_irqsave(&pB->Bbuf_spinlock, flags);
472 if ((type & NEED_BYPASS) && !(pCh->channelNeeds & NEED_BYPASS)) 472 if ((type & NEED_BYPASS) && !(pCh->channelNeeds & NEED_BYPASS))
473 { 473 {
474 pCh->channelNeeds |= NEED_BYPASS; 474 pCh->channelNeeds |= NEED_BYPASS;
@@ -478,12 +478,12 @@ i2QueueNeeds(i2eBordStrPtr pB, i2ChanStrPtr pCh, int type)
478 queueIndex = 0; 478 queueIndex = 0;
479 pB->i2Bbuf_stuff = queueIndex; 479 pB->i2Bbuf_stuff = queueIndex;
480 } 480 }
481 WRITE_UNLOCK_IRQRESTORE(&pB->Bbuf_spinlock,flags); 481 write_unlock_irqrestore(&pB->Bbuf_spinlock, flags);
482 break; 482 break;
483 483
484 case NEED_FLOW: 484 case NEED_FLOW:
485 485
486 WRITE_LOCK_IRQSAVE(&pB->Fbuf_spinlock,flags); 486 write_lock_irqsave(&pB->Fbuf_spinlock, flags);
487 if ((type & NEED_FLOW) && !(pCh->channelNeeds & NEED_FLOW)) 487 if ((type & NEED_FLOW) && !(pCh->channelNeeds & NEED_FLOW))
488 { 488 {
489 pCh->channelNeeds |= NEED_FLOW; 489 pCh->channelNeeds |= NEED_FLOW;
@@ -493,7 +493,7 @@ i2QueueNeeds(i2eBordStrPtr pB, i2ChanStrPtr pCh, int type)
493 queueIndex = 0; 493 queueIndex = 0;
494 pB->i2Fbuf_stuff = queueIndex; 494 pB->i2Fbuf_stuff = queueIndex;
495 } 495 }
496 WRITE_UNLOCK_IRQRESTORE(&pB->Fbuf_spinlock,flags); 496 write_unlock_irqrestore(&pB->Fbuf_spinlock, flags);
497 break; 497 break;
498 498
499 case NEED_CREDIT: 499 case NEED_CREDIT:
@@ -562,9 +562,8 @@ i2QueueCommands(int type, i2ChanStrPtr pCh, int timeout, int nCommands,
562 pB = pCh->pMyBord; 562 pB = pCh->pMyBord;
563 563
564 // Board must also exist, and THE INTERRUPT COMMAND ALREADY SENT 564 // Board must also exist, and THE INTERRUPT COMMAND ALREADY SENT
565 if (pB->i2eValid != I2E_MAGIC || pB->i2eUsingIrq == IRQ_UNDEFINED) { 565 if (pB->i2eValid != I2E_MAGIC || pB->i2eUsingIrq == I2_IRQ_UNDEFINED)
566 return -2; 566 return -2;
567 }
568 // If the board has gone fatal, return bad, and also hit the trap routine if 567 // If the board has gone fatal, return bad, and also hit the trap routine if
569 // it exists. 568 // it exists.
570 if (pB->i2eFatal) { 569 if (pB->i2eFatal) {
@@ -620,13 +619,13 @@ i2QueueCommands(int type, i2ChanStrPtr pCh, int timeout, int nCommands,
620 switch(type) { 619 switch(type) {
621 case PTYPE_INLINE: 620 case PTYPE_INLINE:
622 lock_var_p = &pCh->Obuf_spinlock; 621 lock_var_p = &pCh->Obuf_spinlock;
623 WRITE_LOCK_IRQSAVE(lock_var_p,flags); 622 write_lock_irqsave(lock_var_p, flags);
624 stuffIndex = pCh->Obuf_stuff; 623 stuffIndex = pCh->Obuf_stuff;
625 bufroom = pCh->Obuf_strip - stuffIndex; 624 bufroom = pCh->Obuf_strip - stuffIndex;
626 break; 625 break;
627 case PTYPE_BYPASS: 626 case PTYPE_BYPASS:
628 lock_var_p = &pCh->Cbuf_spinlock; 627 lock_var_p = &pCh->Cbuf_spinlock;
629 WRITE_LOCK_IRQSAVE(lock_var_p,flags); 628 write_lock_irqsave(lock_var_p, flags);
630 stuffIndex = pCh->Cbuf_stuff; 629 stuffIndex = pCh->Cbuf_stuff;
631 bufroom = pCh->Cbuf_strip - stuffIndex; 630 bufroom = pCh->Cbuf_strip - stuffIndex;
632 break; 631 break;
@@ -645,7 +644,7 @@ i2QueueCommands(int type, i2ChanStrPtr pCh, int timeout, int nCommands,
645 break; /* from for()- Enough room: goto proceed */ 644 break; /* from for()- Enough room: goto proceed */
646 } 645 }
647 ip2trace(CHANN, ITRC_QUEUE, 3, 1, totalsize); 646 ip2trace(CHANN, ITRC_QUEUE, 3, 1, totalsize);
648 WRITE_UNLOCK_IRQRESTORE(lock_var_p, flags); 647 write_unlock_irqrestore(lock_var_p, flags);
649 } else 648 } else
650 ip2trace(CHANN, ITRC_QUEUE, 3, 1, totalsize); 649 ip2trace(CHANN, ITRC_QUEUE, 3, 1, totalsize);
651 650
@@ -747,7 +746,7 @@ i2QueueCommands(int type, i2ChanStrPtr pCh, int timeout, int nCommands,
747 { 746 {
748 case PTYPE_INLINE: 747 case PTYPE_INLINE:
749 pCh->Obuf_stuff = stuffIndex; // Store buffer pointer 748 pCh->Obuf_stuff = stuffIndex; // Store buffer pointer
750 WRITE_UNLOCK_IRQRESTORE(&pCh->Obuf_spinlock,flags); 749 write_unlock_irqrestore(&pCh->Obuf_spinlock, flags);
751 750
752 pB->debugInlineQueued++; 751 pB->debugInlineQueued++;
753 // Add the channel pointer to list of channels needing service (first 752 // Add the channel pointer to list of channels needing service (first
@@ -757,7 +756,7 @@ i2QueueCommands(int type, i2ChanStrPtr pCh, int timeout, int nCommands,
757 756
758 case PTYPE_BYPASS: 757 case PTYPE_BYPASS:
759 pCh->Cbuf_stuff = stuffIndex; // Store buffer pointer 758 pCh->Cbuf_stuff = stuffIndex; // Store buffer pointer
760 WRITE_UNLOCK_IRQRESTORE(&pCh->Cbuf_spinlock,flags); 759 write_unlock_irqrestore(&pCh->Cbuf_spinlock, flags);
761 760
762 pB->debugBypassQueued++; 761 pB->debugBypassQueued++;
763 // Add the channel pointer to list of channels needing service (first 762 // Add the channel pointer to list of channels needing service (first
@@ -840,7 +839,7 @@ i2Input(i2ChanStrPtr pCh)
840 count = -1; 839 count = -1;
841 goto i2Input_exit; 840 goto i2Input_exit;
842 } 841 }
843 WRITE_LOCK_IRQSAVE(&pCh->Ibuf_spinlock,flags); 842 write_lock_irqsave(&pCh->Ibuf_spinlock, flags);
844 843
845 // initialize some accelerators and private copies 844 // initialize some accelerators and private copies
846 stripIndex = pCh->Ibuf_strip; 845 stripIndex = pCh->Ibuf_strip;
@@ -850,7 +849,7 @@ i2Input(i2ChanStrPtr pCh)
850 // If buffer is empty or requested data count was 0, (trivial case) return 849 // If buffer is empty or requested data count was 0, (trivial case) return
851 // without any further thought. 850 // without any further thought.
852 if ( count == 0 ) { 851 if ( count == 0 ) {
853 WRITE_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags); 852 write_unlock_irqrestore(&pCh->Ibuf_spinlock, flags);
854 goto i2Input_exit; 853 goto i2Input_exit;
855 } 854 }
856 // Adjust for buffer wrap 855 // Adjust for buffer wrap
@@ -891,10 +890,10 @@ i2Input(i2ChanStrPtr pCh)
891 890
892 if ((pCh->sinceLastFlow += count) >= pCh->whenSendFlow) { 891 if ((pCh->sinceLastFlow += count) >= pCh->whenSendFlow) {
893 pCh->sinceLastFlow -= pCh->whenSendFlow; 892 pCh->sinceLastFlow -= pCh->whenSendFlow;
894 WRITE_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags); 893 write_unlock_irqrestore(&pCh->Ibuf_spinlock, flags);
895 i2QueueNeeds(pCh->pMyBord, pCh, NEED_FLOW); 894 i2QueueNeeds(pCh->pMyBord, pCh, NEED_FLOW);
896 } else { 895 } else {
897 WRITE_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags); 896 write_unlock_irqrestore(&pCh->Ibuf_spinlock, flags);
898 } 897 }
899 898
900i2Input_exit: 899i2Input_exit:
@@ -926,7 +925,7 @@ i2InputFlush(i2ChanStrPtr pCh)
926 925
927 ip2trace (CHANN, ITRC_INPUT, 10, 0); 926 ip2trace (CHANN, ITRC_INPUT, 10, 0);
928 927
929 WRITE_LOCK_IRQSAVE(&pCh->Ibuf_spinlock,flags); 928 write_lock_irqsave(&pCh->Ibuf_spinlock, flags);
930 count = pCh->Ibuf_stuff - pCh->Ibuf_strip; 929 count = pCh->Ibuf_stuff - pCh->Ibuf_strip;
931 930
932 // Adjust for buffer wrap 931 // Adjust for buffer wrap
@@ -947,10 +946,10 @@ i2InputFlush(i2ChanStrPtr pCh)
947 if ( (pCh->sinceLastFlow += count) >= pCh->whenSendFlow ) 946 if ( (pCh->sinceLastFlow += count) >= pCh->whenSendFlow )
948 { 947 {
949 pCh->sinceLastFlow -= pCh->whenSendFlow; 948 pCh->sinceLastFlow -= pCh->whenSendFlow;
950 WRITE_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags); 949 write_unlock_irqrestore(&pCh->Ibuf_spinlock, flags);
951 i2QueueNeeds(pCh->pMyBord, pCh, NEED_FLOW); 950 i2QueueNeeds(pCh->pMyBord, pCh, NEED_FLOW);
952 } else { 951 } else {
953 WRITE_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags); 952 write_unlock_irqrestore(&pCh->Ibuf_spinlock, flags);
954 } 953 }
955 954
956 ip2trace (CHANN, ITRC_INPUT, 19, 1, count); 955 ip2trace (CHANN, ITRC_INPUT, 19, 1, count);
@@ -979,9 +978,9 @@ i2InputAvailable(i2ChanStrPtr pCh)
979 978
980 979
981 // initialize some accelerators and private copies 980 // initialize some accelerators and private copies
982 READ_LOCK_IRQSAVE(&pCh->Ibuf_spinlock,flags); 981 read_lock_irqsave(&pCh->Ibuf_spinlock, flags);
983 count = pCh->Ibuf_stuff - pCh->Ibuf_strip; 982 count = pCh->Ibuf_stuff - pCh->Ibuf_strip;
984 READ_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags); 983 read_unlock_irqrestore(&pCh->Ibuf_spinlock, flags);
985 984
986 // Adjust for buffer wrap 985 // Adjust for buffer wrap
987 if (count < 0) 986 if (count < 0)
@@ -1045,9 +1044,9 @@ i2Output(i2ChanStrPtr pCh, const char *pSource, int count)
1045 while ( count > 0 ) { 1044 while ( count > 0 ) {
1046 1045
1047 // How much room in output buffer is there? 1046 // How much room in output buffer is there?
1048 READ_LOCK_IRQSAVE(&pCh->Obuf_spinlock,flags); 1047 read_lock_irqsave(&pCh->Obuf_spinlock, flags);
1049 amountToMove = pCh->Obuf_strip - pCh->Obuf_stuff - 1; 1048 amountToMove = pCh->Obuf_strip - pCh->Obuf_stuff - 1;
1050 READ_UNLOCK_IRQRESTORE(&pCh->Obuf_spinlock,flags); 1049 read_unlock_irqrestore(&pCh->Obuf_spinlock, flags);
1051 if (amountToMove < 0) { 1050 if (amountToMove < 0) {
1052 amountToMove += OBUF_SIZE; 1051 amountToMove += OBUF_SIZE;
1053 } 1052 }
@@ -1075,7 +1074,7 @@ i2Output(i2ChanStrPtr pCh, const char *pSource, int count)
1075 if ( !(pCh->flush_flags && i2RetryFlushOutput(pCh) ) 1074 if ( !(pCh->flush_flags && i2RetryFlushOutput(pCh) )
1076 && amountToMove > 0 ) 1075 && amountToMove > 0 )
1077 { 1076 {
1078 WRITE_LOCK_IRQSAVE(&pCh->Obuf_spinlock,flags); 1077 write_lock_irqsave(&pCh->Obuf_spinlock, flags);
1079 stuffIndex = pCh->Obuf_stuff; 1078 stuffIndex = pCh->Obuf_stuff;
1080 1079
1081 // Had room to move some data: don't know whether the block size, 1080 // Had room to move some data: don't know whether the block size,
@@ -1102,7 +1101,7 @@ i2Output(i2ChanStrPtr pCh, const char *pSource, int count)
1102 } 1101 }
1103 pCh->Obuf_stuff = stuffIndex; 1102 pCh->Obuf_stuff = stuffIndex;
1104 1103
1105 WRITE_UNLOCK_IRQRESTORE(&pCh->Obuf_spinlock,flags); 1104 write_unlock_irqrestore(&pCh->Obuf_spinlock, flags);
1106 1105
1107 ip2trace (CHANN, ITRC_OUTPUT, 13, 1, stuffIndex ); 1106 ip2trace (CHANN, ITRC_OUTPUT, 13, 1, stuffIndex );
1108 1107
@@ -1352,9 +1351,9 @@ i2OutputFree(i2ChanStrPtr pCh)
1352 if ( !i2Validate ( pCh ) ) { 1351 if ( !i2Validate ( pCh ) ) {
1353 return -1; 1352 return -1;
1354 } 1353 }
1355 READ_LOCK_IRQSAVE(&pCh->Obuf_spinlock,flags); 1354 read_lock_irqsave(&pCh->Obuf_spinlock, flags);
1356 amountToMove = pCh->Obuf_strip - pCh->Obuf_stuff - 1; 1355 amountToMove = pCh->Obuf_strip - pCh->Obuf_stuff - 1;
1357 READ_UNLOCK_IRQRESTORE(&pCh->Obuf_spinlock,flags); 1356 read_unlock_irqrestore(&pCh->Obuf_spinlock, flags);
1358 1357
1359 if (amountToMove < 0) { 1358 if (amountToMove < 0) {
1360 amountToMove += OBUF_SIZE; 1359 amountToMove += OBUF_SIZE;
@@ -1464,11 +1463,11 @@ i2StripFifo(i2eBordStrPtr pB)
1464 1463
1465// ip2trace (ITRC_NO_PORT, ITRC_SFIFO, ITRC_ENTER, 0 ); 1464// ip2trace (ITRC_NO_PORT, ITRC_SFIFO, ITRC_ENTER, 0 );
1466 1465
1467 while (HAS_INPUT(pB)) { 1466 while (I2_HAS_INPUT(pB)) {
1468// ip2trace (ITRC_NO_PORT, ITRC_SFIFO, 2, 0 ); 1467// ip2trace (ITRC_NO_PORT, ITRC_SFIFO, 2, 0 );
1469 1468
1470 // Process packet from fifo a one atomic unit 1469 // Process packet from fifo a one atomic unit
1471 WRITE_LOCK_IRQSAVE(&pB->read_fifo_spinlock,bflags); 1470 write_lock_irqsave(&pB->read_fifo_spinlock, bflags);
1472 1471
1473 // The first word (or two bytes) will have channel number and type of 1472 // The first word (or two bytes) will have channel number and type of
1474 // packet, possibly other information 1473 // packet, possibly other information
@@ -1490,7 +1489,8 @@ i2StripFifo(i2eBordStrPtr pB)
1490// sick! 1489// sick!
1491 if ( ((unsigned int)count) > IBUF_SIZE ) { 1490 if ( ((unsigned int)count) > IBUF_SIZE ) {
1492 pB->i2eFatal = 2; 1491 pB->i2eFatal = 2;
1493 WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock,bflags); 1492 write_unlock_irqrestore(&pB->read_fifo_spinlock,
1493 bflags);
1494 return; /* Bail out ASAP */ 1494 return; /* Bail out ASAP */
1495 } 1495 }
1496 // Channel is illegally big ? 1496 // Channel is illegally big ?
@@ -1498,7 +1498,8 @@ i2StripFifo(i2eBordStrPtr pB)
1498 (NULL==(pCh = ((i2ChanStrPtr*)pB->i2eChannelPtr)[channel]))) 1498 (NULL==(pCh = ((i2ChanStrPtr*)pB->i2eChannelPtr)[channel])))
1499 { 1499 {
1500 iiReadBuf(pB, junkBuffer, count); 1500 iiReadBuf(pB, junkBuffer, count);
1501 WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock,bflags); 1501 write_unlock_irqrestore(&pB->read_fifo_spinlock,
1502 bflags);
1502 break; /* From switch: ready for next packet */ 1503 break; /* From switch: ready for next packet */
1503 } 1504 }
1504 1505
@@ -1512,14 +1513,15 @@ i2StripFifo(i2eBordStrPtr pB)
1512 if(ID_OF(pB->i2eLeadoffWord) == ID_HOT_KEY) 1513 if(ID_OF(pB->i2eLeadoffWord) == ID_HOT_KEY)
1513 { 1514 {
1514 pCh->hotKeyIn = iiReadWord(pB) & 0xff; 1515 pCh->hotKeyIn = iiReadWord(pB) & 0xff;
1515 WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock,bflags); 1516 write_unlock_irqrestore(&pB->read_fifo_spinlock,
1517 bflags);
1516 i2QueueCommands(PTYPE_BYPASS, pCh, 0, 1, CMD_HOTACK); 1518 i2QueueCommands(PTYPE_BYPASS, pCh, 0, 1, CMD_HOTACK);
1517 break; /* From the switch: ready for next packet */ 1519 break; /* From the switch: ready for next packet */
1518 } 1520 }
1519 1521
1520 // Normal data! We crudely assume there is room for the data in our 1522 // Normal data! We crudely assume there is room for the data in our
1521 // buffer because the board wouldn't have exceeded his credit limit. 1523 // buffer because the board wouldn't have exceeded his credit limit.
1522 WRITE_LOCK_IRQSAVE(&pCh->Ibuf_spinlock,cflags); 1524 write_lock_irqsave(&pCh->Ibuf_spinlock, cflags);
1523 // We have 2 locks now 1525 // We have 2 locks now
1524 stuffIndex = pCh->Ibuf_stuff; 1526 stuffIndex = pCh->Ibuf_stuff;
1525 amountToRead = IBUF_SIZE - stuffIndex; 1527 amountToRead = IBUF_SIZE - stuffIndex;
@@ -1562,8 +1564,9 @@ i2StripFifo(i2eBordStrPtr pB)
1562 1564
1563 // Update stuff index 1565 // Update stuff index
1564 pCh->Ibuf_stuff = stuffIndex; 1566 pCh->Ibuf_stuff = stuffIndex;
1565 WRITE_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,cflags); 1567 write_unlock_irqrestore(&pCh->Ibuf_spinlock, cflags);
1566 WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock,bflags); 1568 write_unlock_irqrestore(&pB->read_fifo_spinlock,
1569 bflags);
1567 1570
1568#ifdef USE_IQ 1571#ifdef USE_IQ
1569 schedule_work(&pCh->tqueue_input); 1572 schedule_work(&pCh->tqueue_input);
@@ -1585,7 +1588,8 @@ i2StripFifo(i2eBordStrPtr pB)
1585 1588
1586 iiReadBuf(pB, cmdBuffer, count); 1589 iiReadBuf(pB, cmdBuffer, count);
1587 // We can release early with buffer grab 1590 // We can release early with buffer grab
1588 WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock,bflags); 1591 write_unlock_irqrestore(&pB->read_fifo_spinlock,
1592 bflags);
1589 1593
1590 pc = cmdBuffer; 1594 pc = cmdBuffer;
1591 pcLimit = &(cmdBuffer[count]); 1595 pcLimit = &(cmdBuffer[count]);
@@ -1830,12 +1834,12 @@ i2StripFifo(i2eBordStrPtr pB)
1830 default: // Neither packet? should be impossible 1834 default: // Neither packet? should be impossible
1831 ip2trace (ITRC_NO_PORT, ITRC_SFIFO, 5, 1, 1835 ip2trace (ITRC_NO_PORT, ITRC_SFIFO, 5, 1,
1832 PTYPE_OF(pB->i2eLeadoffWord) ); 1836 PTYPE_OF(pB->i2eLeadoffWord) );
1833 WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock, 1837 write_unlock_irqrestore(&pB->read_fifo_spinlock,
1834 bflags); 1838 bflags);
1835 1839
1836 break; 1840 break;
1837 } // End of switch on type of packets 1841 } // End of switch on type of packets
1838 } //while(board HAS_INPUT) 1842 } /*while(board I2_HAS_INPUT)*/
1839 1843
1840 ip2trace (ITRC_NO_PORT, ITRC_SFIFO, ITRC_RETURN, 0 ); 1844 ip2trace (ITRC_NO_PORT, ITRC_SFIFO, ITRC_RETURN, 0 );
1841 1845
@@ -1858,7 +1862,7 @@ i2Write2Fifo(i2eBordStrPtr pB, unsigned char *source, int count,int reserve)
1858{ 1862{
1859 int rc = 0; 1863 int rc = 0;
1860 unsigned long flags; 1864 unsigned long flags;
1861 WRITE_LOCK_IRQSAVE(&pB->write_fifo_spinlock,flags); 1865 write_lock_irqsave(&pB->write_fifo_spinlock, flags);
1862 if (!pB->i2eWaitingForEmptyFifo) { 1866 if (!pB->i2eWaitingForEmptyFifo) {
1863 if (pB->i2eFifoRemains > (count+reserve)) { 1867 if (pB->i2eFifoRemains > (count+reserve)) {
1864 pB->i2eFifoRemains -= count; 1868 pB->i2eFifoRemains -= count;
@@ -1867,7 +1871,7 @@ i2Write2Fifo(i2eBordStrPtr pB, unsigned char *source, int count,int reserve)
1867 rc = count; 1871 rc = count;
1868 } 1872 }
1869 } 1873 }
1870 WRITE_UNLOCK_IRQRESTORE(&pB->write_fifo_spinlock,flags); 1874 write_unlock_irqrestore(&pB->write_fifo_spinlock, flags);
1871 return rc; 1875 return rc;
1872} 1876}
1873//****************************************************************************** 1877//******************************************************************************
@@ -1898,7 +1902,7 @@ i2StuffFifoBypass(i2eBordStrPtr pB)
1898 while ( --bailout && notClogged && 1902 while ( --bailout && notClogged &&
1899 (NULL != (pCh = i2DeQueueNeeds(pB,NEED_BYPASS)))) 1903 (NULL != (pCh = i2DeQueueNeeds(pB,NEED_BYPASS))))
1900 { 1904 {
1901 WRITE_LOCK_IRQSAVE(&pCh->Cbuf_spinlock,flags); 1905 write_lock_irqsave(&pCh->Cbuf_spinlock, flags);
1902 stripIndex = pCh->Cbuf_strip; 1906 stripIndex = pCh->Cbuf_strip;
1903 1907
1904 // as long as there are packets for this channel... 1908 // as long as there are packets for this channel...
@@ -1906,7 +1910,7 @@ i2StuffFifoBypass(i2eBordStrPtr pB)
1906 while (stripIndex != pCh->Cbuf_stuff) { 1910 while (stripIndex != pCh->Cbuf_stuff) {
1907 pRemove = &(pCh->Cbuf[stripIndex]); 1911 pRemove = &(pCh->Cbuf[stripIndex]);
1908 packetSize = CMD_COUNT_OF(pRemove) + sizeof(i2CmdHeader); 1912 packetSize = CMD_COUNT_OF(pRemove) + sizeof(i2CmdHeader);
1909 paddedSize = ROUNDUP(packetSize); 1913 paddedSize = roundup(packetSize, 2);
1910 1914
1911 if (paddedSize > 0) { 1915 if (paddedSize > 0) {
1912 if ( 0 == i2Write2Fifo(pB, pRemove, paddedSize,0)) { 1916 if ( 0 == i2Write2Fifo(pB, pRemove, paddedSize,0)) {
@@ -1930,7 +1934,7 @@ WriteDBGBuf("BYPS", pRemove, paddedSize);
1930 // Done with this channel. Move to next, removing this one from 1934 // Done with this channel. Move to next, removing this one from
1931 // the queue of channels if we cleaned it out (i.e., didn't get clogged. 1935 // the queue of channels if we cleaned it out (i.e., didn't get clogged.
1932 pCh->Cbuf_strip = stripIndex; 1936 pCh->Cbuf_strip = stripIndex;
1933 WRITE_UNLOCK_IRQRESTORE(&pCh->Cbuf_spinlock,flags); 1937 write_unlock_irqrestore(&pCh->Cbuf_spinlock, flags);
1934 } // Either clogged or finished all the work 1938 } // Either clogged or finished all the work
1935 1939
1936#ifdef IP2DEBUG_TRACE 1940#ifdef IP2DEBUG_TRACE
@@ -1954,7 +1958,7 @@ static inline void
1954i2StuffFifoFlow(i2eBordStrPtr pB) 1958i2StuffFifoFlow(i2eBordStrPtr pB)
1955{ 1959{
1956 i2ChanStrPtr pCh; 1960 i2ChanStrPtr pCh;
1957 unsigned short paddedSize = ROUNDUP(sizeof(flowIn)); 1961 unsigned short paddedSize = roundup(sizeof(flowIn), 2);
1958 1962
1959 ip2trace (ITRC_NO_PORT, ITRC_SFLOW, ITRC_ENTER, 2, 1963 ip2trace (ITRC_NO_PORT, ITRC_SFLOW, ITRC_ENTER, 2,
1960 pB->i2eFifoRemains, paddedSize ); 1964 pB->i2eFifoRemains, paddedSize );
@@ -2010,7 +2014,7 @@ i2StuffFifoInline(i2eBordStrPtr pB)
2010 while ( --bailout && notClogged && 2014 while ( --bailout && notClogged &&
2011 (NULL != (pCh = i2DeQueueNeeds(pB,NEED_INLINE))) ) 2015 (NULL != (pCh = i2DeQueueNeeds(pB,NEED_INLINE))) )
2012 { 2016 {
2013 WRITE_LOCK_IRQSAVE(&pCh->Obuf_spinlock,flags); 2017 write_lock_irqsave(&pCh->Obuf_spinlock, flags);
2014 stripIndex = pCh->Obuf_strip; 2018 stripIndex = pCh->Obuf_strip;
2015 2019
2016 ip2trace (CHANN, ITRC_SICMD, 3, 2, stripIndex, pCh->Obuf_stuff ); 2020 ip2trace (CHANN, ITRC_SICMD, 3, 2, stripIndex, pCh->Obuf_stuff );
@@ -2031,7 +2035,7 @@ i2StuffFifoInline(i2eBordStrPtr pB)
2031 packetSize = flowsize + sizeof(i2CmdHeader); 2035 packetSize = flowsize + sizeof(i2CmdHeader);
2032 } 2036 }
2033 flowsize = CREDIT_USAGE(flowsize); 2037 flowsize = CREDIT_USAGE(flowsize);
2034 paddedSize = ROUNDUP(packetSize); 2038 paddedSize = roundup(packetSize, 2);
2035 2039
2036 ip2trace (CHANN, ITRC_SICMD, 4, 2, pB->i2eFifoRemains, paddedSize ); 2040 ip2trace (CHANN, ITRC_SICMD, 4, 2, pB->i2eFifoRemains, paddedSize );
2037 2041
@@ -2086,7 +2090,7 @@ WriteDBGBuf("DATA", pRemove, paddedSize);
2086 // Done with this channel. Move to next, removing this one from the 2090 // Done with this channel. Move to next, removing this one from the
2087 // queue of channels if we cleaned it out (i.e., didn't get clogged. 2091 // queue of channels if we cleaned it out (i.e., didn't get clogged.
2088 pCh->Obuf_strip = stripIndex; 2092 pCh->Obuf_strip = stripIndex;
2089 WRITE_UNLOCK_IRQRESTORE(&pCh->Obuf_spinlock,flags); 2093 write_unlock_irqrestore(&pCh->Obuf_spinlock, flags);
2090 if ( notClogged ) 2094 if ( notClogged )
2091 { 2095 {
2092 2096
@@ -2190,10 +2194,11 @@ i2ServiceBoard ( i2eBordStrPtr pB )
2190 2194
2191 if (inmail & MB_OUT_STRIPPED) { 2195 if (inmail & MB_OUT_STRIPPED) {
2192 pB->i2eFifoOutInts++; 2196 pB->i2eFifoOutInts++;
2193 WRITE_LOCK_IRQSAVE(&pB->write_fifo_spinlock,flags); 2197 write_lock_irqsave(&pB->write_fifo_spinlock, flags);
2194 pB->i2eFifoRemains = pB->i2eFifoSize; 2198 pB->i2eFifoRemains = pB->i2eFifoSize;
2195 pB->i2eWaitingForEmptyFifo = 0; 2199 pB->i2eWaitingForEmptyFifo = 0;
2196 WRITE_UNLOCK_IRQRESTORE(&pB->write_fifo_spinlock,flags); 2200 write_unlock_irqrestore(&pB->write_fifo_spinlock,
2201 flags);
2197 2202
2198 ip2trace (ITRC_NO_PORT, ITRC_INTR, 30, 1, pB->i2eFifoRemains ); 2203 ip2trace (ITRC_NO_PORT, ITRC_INTR, 30, 1, pB->i2eFifoRemains );
2199 2204
diff --git a/drivers/char/ip2/i2os.h b/drivers/char/ip2/i2os.h
deleted file mode 100644
index eff9b542d699..000000000000
--- a/drivers/char/ip2/i2os.h
+++ /dev/null
@@ -1,127 +0,0 @@
1/*******************************************************************************
2*
3* (c) 1999 by Computone Corporation
4*
5********************************************************************************
6*
7*
8* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
9* serial I/O controllers.
10*
11* DESCRIPTION: Defines, definitions and includes which are heavily dependent
12* on O/S, host, compiler, etc. This file is tailored for:
13* Linux v2.0.0 and later
14* Gnu gcc c2.7.2
15* 80x86 architecture
16*
17*******************************************************************************/
18
19#ifndef I2OS_H /* To prevent multiple includes */
20#define I2OS_H 1
21
22//-------------------------------------------------
23// Required Includes
24//-------------------------------------------------
25
26#include "ip2types.h"
27#include <asm/io.h> /* For inb, etc */
28
29//------------------------------------
30// Defines for I/O instructions:
31//------------------------------------
32
33#define INB(port) inb(port)
34#define OUTB(port,value) outb((value),(port))
35#define INW(port) inw(port)
36#define OUTW(port,value) outw((value),(port))
37#define OUTSW(port,addr,count) outsw((port),(addr),(((count)+1)/2))
38#define OUTSB(port,addr,count) outsb((port),(addr),(((count)+1))&-2)
39#define INSW(port,addr,count) insw((port),(addr),(((count)+1)/2))
40#define INSB(port,addr,count) insb((port),(addr),(((count)+1))&-2)
41
42//--------------------------------------------
43// Interrupt control
44//--------------------------------------------
45
46#define LOCK_INIT(a) rwlock_init(a)
47
48#define SAVE_AND_DISABLE_INTS(a,b) { \
49 /* printk("get_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
50 spin_lock_irqsave(a,b); \
51}
52
53#define RESTORE_INTS(a,b) { \
54 /* printk("rel_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
55 spin_unlock_irqrestore(a,b); \
56}
57
58#define READ_LOCK_IRQSAVE(a,b) { \
59 /* printk("get_read_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
60 read_lock_irqsave(a,b); \
61}
62
63#define READ_UNLOCK_IRQRESTORE(a,b) { \
64 /* printk("rel_read_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
65 read_unlock_irqrestore(a,b); \
66}
67
68#define WRITE_LOCK_IRQSAVE(a,b) { \
69 /* printk("get_write_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
70 write_lock_irqsave(a,b); \
71}
72
73#define WRITE_UNLOCK_IRQRESTORE(a,b) { \
74 /* printk("rel_write_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
75 write_unlock_irqrestore(a,b); \
76}
77
78
79//------------------------------------------------------------------------------
80// Hardware-delay loop
81//
82// Probably used in only one place (see i2ellis.c) but this helps keep things
83// together. Note we have unwound the IN instructions. On machines with a
84// reasonable cache, the eight instructions (1 byte each) should fit in cache
85// nicely, and on un-cached machines, the code-fetch would tend not to dominate.
86// Note that cx is shifted so that "count" still reflects the total number of
87// iterations assuming no unwinding.
88//------------------------------------------------------------------------------
89
90//#define DELAY1MS(port,count,label)
91
92//------------------------------------------------------------------------------
93// Macros to switch to a new stack, saving stack pointers, and to restore the
94// old stack (Used, for example, in i2lib.c) "heap" is the address of some
95// buffer which will become the new stack (working down from highest address).
96// The two words at the two lowest addresses in this stack are for storing the
97// SS and SP.
98//------------------------------------------------------------------------------
99
100//#define TO_NEW_STACK(heap,size)
101//#define TO_OLD_STACK(heap)
102
103//------------------------------------------------------------------------------
104// Macros to save the original IRQ vectors and masks, and to patch in new ones.
105//------------------------------------------------------------------------------
106
107//#define SAVE_IRQ_MASKS(dest)
108//#define WRITE_IRQ_MASKS(src)
109//#define SAVE_IRQ_VECTOR(value,dest)
110//#define WRITE_IRQ_VECTOR(value,src)
111
112//------------------------------------------------------------------------------
113// Macro to copy data from one far pointer to another.
114//------------------------------------------------------------------------------
115
116#define I2_MOVE_DATA(fpSource,fpDest,count) memmove(fpDest,fpSource,count);
117
118//------------------------------------------------------------------------------
119// Macros to issue eoi's to host interrupt control (IBM AT 8259-style).
120//------------------------------------------------------------------------------
121
122//#define MASTER_EOI
123//#define SLAVE_EOI
124
125#endif /* I2OS_H */
126
127
diff --git a/drivers/char/ip2/ip2main.c b/drivers/char/ip2/ip2main.c
index 319f804fc4d6..c4f4ca31f7c0 100644
--- a/drivers/char/ip2/ip2main.c
+++ b/drivers/char/ip2/ip2main.c
@@ -1052,9 +1052,9 @@ set_irq( int boardnum, int boardIrq )
1052 * Write to FIFO; don't bother to adjust fifo capacity for this, since 1052 * Write to FIFO; don't bother to adjust fifo capacity for this, since
1053 * board will respond almost immediately after SendMail hit. 1053 * board will respond almost immediately after SendMail hit.
1054 */ 1054 */
1055 WRITE_LOCK_IRQSAVE(&pB->write_fifo_spinlock,flags); 1055 write_lock_irqsave(&pB->write_fifo_spinlock, flags);
1056 iiWriteBuf(pB, tempCommand, 4); 1056 iiWriteBuf(pB, tempCommand, 4);
1057 WRITE_UNLOCK_IRQRESTORE(&pB->write_fifo_spinlock,flags); 1057 write_unlock_irqrestore(&pB->write_fifo_spinlock, flags);
1058 pB->i2eUsingIrq = boardIrq; 1058 pB->i2eUsingIrq = boardIrq;
1059 pB->i2eOutMailWaiting |= MB_OUT_STUFFED; 1059 pB->i2eOutMailWaiting |= MB_OUT_STUFFED;
1060 1060
@@ -1072,9 +1072,9 @@ set_irq( int boardnum, int boardIrq )
1072 (CMD_OF(tempCommand))[4] = 64; // chars 1072 (CMD_OF(tempCommand))[4] = 64; // chars
1073 1073
1074 (CMD_OF(tempCommand))[5] = 87; // HW_TEST 1074 (CMD_OF(tempCommand))[5] = 87; // HW_TEST
1075 WRITE_LOCK_IRQSAVE(&pB->write_fifo_spinlock,flags); 1075 write_lock_irqsave(&pB->write_fifo_spinlock, flags);
1076 iiWriteBuf(pB, tempCommand, 8); 1076 iiWriteBuf(pB, tempCommand, 8);
1077 WRITE_UNLOCK_IRQRESTORE(&pB->write_fifo_spinlock,flags); 1077 write_unlock_irqrestore(&pB->write_fifo_spinlock, flags);
1078 1078
1079 CHANNEL_OF(tempCommand) = 0; 1079 CHANNEL_OF(tempCommand) = 0;
1080 PTYPE_OF(tempCommand) = PTYPE_BYPASS; 1080 PTYPE_OF(tempCommand) = PTYPE_BYPASS;
@@ -1089,9 +1089,9 @@ set_irq( int boardnum, int boardIrq )
1089 CMD_COUNT_OF(tempCommand) = 2; 1089 CMD_COUNT_OF(tempCommand) = 2;
1090 (CMD_OF(tempCommand))[0] = 44; /* get ping */ 1090 (CMD_OF(tempCommand))[0] = 44; /* get ping */
1091 (CMD_OF(tempCommand))[1] = 200; /* 200 ms */ 1091 (CMD_OF(tempCommand))[1] = 200; /* 200 ms */
1092 WRITE_LOCK_IRQSAVE(&pB->write_fifo_spinlock,flags); 1092 write_lock_irqsave(&pB->write_fifo_spinlock, flags);
1093 iiWriteBuf(pB, tempCommand, 4); 1093 iiWriteBuf(pB, tempCommand, 4);
1094 WRITE_UNLOCK_IRQRESTORE(&pB->write_fifo_spinlock,flags); 1094 write_unlock_irqrestore(&pB->write_fifo_spinlock, flags);
1095#endif 1095#endif
1096 1096
1097 iiEnableMailIrq(pB); 1097 iiEnableMailIrq(pB);
@@ -1270,12 +1270,12 @@ static void do_input(struct work_struct *work)
1270 1270
1271 // Data input 1271 // Data input
1272 if ( pCh->pTTY != NULL ) { 1272 if ( pCh->pTTY != NULL ) {
1273 READ_LOCK_IRQSAVE(&pCh->Ibuf_spinlock,flags) 1273 read_lock_irqsave(&pCh->Ibuf_spinlock, flags);
1274 if (!pCh->throttled && (pCh->Ibuf_stuff != pCh->Ibuf_strip)) { 1274 if (!pCh->throttled && (pCh->Ibuf_stuff != pCh->Ibuf_strip)) {
1275 READ_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags) 1275 read_unlock_irqrestore(&pCh->Ibuf_spinlock, flags);
1276 i2Input( pCh ); 1276 i2Input( pCh );
1277 } else 1277 } else
1278 READ_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags) 1278 read_unlock_irqrestore(&pCh->Ibuf_spinlock, flags);
1279 } else { 1279 } else {
1280 ip2trace(CHANN, ITRC_INPUT, 22, 0 ); 1280 ip2trace(CHANN, ITRC_INPUT, 22, 0 );
1281 1281
@@ -1719,9 +1719,9 @@ ip2_write( PTTY tty, const unsigned char *pData, int count)
1719 ip2_flush_chars( tty ); 1719 ip2_flush_chars( tty );
1720 1720
1721 /* This is the actual move bit. Make sure it does what we need!!!!! */ 1721 /* This is the actual move bit. Make sure it does what we need!!!!! */
1722 WRITE_LOCK_IRQSAVE(&pCh->Pbuf_spinlock,flags); 1722 write_lock_irqsave(&pCh->Pbuf_spinlock, flags);
1723 bytesSent = i2Output( pCh, pData, count); 1723 bytesSent = i2Output( pCh, pData, count);
1724 WRITE_UNLOCK_IRQRESTORE(&pCh->Pbuf_spinlock,flags); 1724 write_unlock_irqrestore(&pCh->Pbuf_spinlock, flags);
1725 1725
1726 ip2trace (CHANN, ITRC_WRITE, ITRC_RETURN, 1, bytesSent ); 1726 ip2trace (CHANN, ITRC_WRITE, ITRC_RETURN, 1, bytesSent );
1727 1727
@@ -1746,13 +1746,13 @@ ip2_putchar( PTTY tty, unsigned char ch )
1746 1746
1747// ip2trace (CHANN, ITRC_PUTC, ITRC_ENTER, 1, ch ); 1747// ip2trace (CHANN, ITRC_PUTC, ITRC_ENTER, 1, ch );
1748 1748
1749 WRITE_LOCK_IRQSAVE(&pCh->Pbuf_spinlock,flags); 1749 write_lock_irqsave(&pCh->Pbuf_spinlock, flags);
1750 pCh->Pbuf[pCh->Pbuf_stuff++] = ch; 1750 pCh->Pbuf[pCh->Pbuf_stuff++] = ch;
1751 if ( pCh->Pbuf_stuff == sizeof pCh->Pbuf ) { 1751 if ( pCh->Pbuf_stuff == sizeof pCh->Pbuf ) {
1752 WRITE_UNLOCK_IRQRESTORE(&pCh->Pbuf_spinlock,flags); 1752 write_unlock_irqrestore(&pCh->Pbuf_spinlock, flags);
1753 ip2_flush_chars( tty ); 1753 ip2_flush_chars( tty );
1754 } else 1754 } else
1755 WRITE_UNLOCK_IRQRESTORE(&pCh->Pbuf_spinlock,flags); 1755 write_unlock_irqrestore(&pCh->Pbuf_spinlock, flags);
1756 1756
1757// ip2trace (CHANN, ITRC_PUTC, ITRC_RETURN, 1, ch ); 1757// ip2trace (CHANN, ITRC_PUTC, ITRC_RETURN, 1, ch );
1758} 1758}
@@ -1772,7 +1772,7 @@ ip2_flush_chars( PTTY tty )
1772 i2ChanStrPtr pCh = tty->driver_data; 1772 i2ChanStrPtr pCh = tty->driver_data;
1773 unsigned long flags; 1773 unsigned long flags;
1774 1774
1775 WRITE_LOCK_IRQSAVE(&pCh->Pbuf_spinlock,flags); 1775 write_lock_irqsave(&pCh->Pbuf_spinlock, flags);
1776 if ( pCh->Pbuf_stuff ) { 1776 if ( pCh->Pbuf_stuff ) {
1777 1777
1778// ip2trace (CHANN, ITRC_PUTC, 10, 1, strip ); 1778// ip2trace (CHANN, ITRC_PUTC, 10, 1, strip );
@@ -1786,7 +1786,7 @@ ip2_flush_chars( PTTY tty )
1786 } 1786 }
1787 pCh->Pbuf_stuff -= strip; 1787 pCh->Pbuf_stuff -= strip;
1788 } 1788 }
1789 WRITE_UNLOCK_IRQRESTORE(&pCh->Pbuf_spinlock,flags); 1789 write_unlock_irqrestore(&pCh->Pbuf_spinlock, flags);
1790} 1790}
1791 1791
1792/******************************************************************************/ 1792/******************************************************************************/
@@ -1804,9 +1804,9 @@ ip2_write_room ( PTTY tty )
1804 i2ChanStrPtr pCh = tty->driver_data; 1804 i2ChanStrPtr pCh = tty->driver_data;
1805 unsigned long flags; 1805 unsigned long flags;
1806 1806
1807 READ_LOCK_IRQSAVE(&pCh->Pbuf_spinlock,flags); 1807 read_lock_irqsave(&pCh->Pbuf_spinlock, flags);
1808 bytesFree = i2OutputFree( pCh ) - pCh->Pbuf_stuff; 1808 bytesFree = i2OutputFree( pCh ) - pCh->Pbuf_stuff;
1809 READ_UNLOCK_IRQRESTORE(&pCh->Pbuf_spinlock,flags); 1809 read_unlock_irqrestore(&pCh->Pbuf_spinlock, flags);
1810 1810
1811 ip2trace (CHANN, ITRC_WRITE, 11, 1, bytesFree ); 1811 ip2trace (CHANN, ITRC_WRITE, 11, 1, bytesFree );
1812 1812
@@ -1836,12 +1836,12 @@ ip2_chars_in_buf ( PTTY tty )
1836 pCh->Obuf_char_count + pCh->Pbuf_stuff, 1836 pCh->Obuf_char_count + pCh->Pbuf_stuff,
1837 pCh->Obuf_char_count, pCh->Pbuf_stuff ); 1837 pCh->Obuf_char_count, pCh->Pbuf_stuff );
1838#endif 1838#endif
1839 READ_LOCK_IRQSAVE(&pCh->Obuf_spinlock,flags); 1839 read_lock_irqsave(&pCh->Obuf_spinlock, flags);
1840 rc = pCh->Obuf_char_count; 1840 rc = pCh->Obuf_char_count;
1841 READ_UNLOCK_IRQRESTORE(&pCh->Obuf_spinlock,flags); 1841 read_unlock_irqrestore(&pCh->Obuf_spinlock, flags);
1842 READ_LOCK_IRQSAVE(&pCh->Pbuf_spinlock,flags); 1842 read_lock_irqsave(&pCh->Pbuf_spinlock, flags);
1843 rc += pCh->Pbuf_stuff; 1843 rc += pCh->Pbuf_stuff;
1844 READ_UNLOCK_IRQRESTORE(&pCh->Pbuf_spinlock,flags); 1844 read_unlock_irqrestore(&pCh->Pbuf_spinlock, flags);
1845 return rc; 1845 return rc;
1846} 1846}
1847 1847
@@ -1865,9 +1865,9 @@ ip2_flush_buffer( PTTY tty )
1865#ifdef IP2DEBUG_WRITE 1865#ifdef IP2DEBUG_WRITE
1866 printk (KERN_DEBUG "IP2: flush buffer\n" ); 1866 printk (KERN_DEBUG "IP2: flush buffer\n" );
1867#endif 1867#endif
1868 WRITE_LOCK_IRQSAVE(&pCh->Pbuf_spinlock,flags); 1868 write_lock_irqsave(&pCh->Pbuf_spinlock, flags);
1869 pCh->Pbuf_stuff = 0; 1869 pCh->Pbuf_stuff = 0;
1870 WRITE_UNLOCK_IRQRESTORE(&pCh->Pbuf_spinlock,flags); 1870 write_unlock_irqrestore(&pCh->Pbuf_spinlock, flags);
1871 i2FlushOutput( pCh ); 1871 i2FlushOutput( pCh );
1872 ip2_owake(tty); 1872 ip2_owake(tty);
1873 1873
@@ -1953,15 +1953,15 @@ ip2_unthrottle ( PTTY tty )
1953 pCh->throttled = 0; 1953 pCh->throttled = 0;
1954 i2QueueCommands(PTYPE_BYPASS, pCh, 0, 1, CMD_RESUME); 1954 i2QueueCommands(PTYPE_BYPASS, pCh, 0, 1, CMD_RESUME);
1955 serviceOutgoingFifo( pCh->pMyBord ); 1955 serviceOutgoingFifo( pCh->pMyBord );
1956 READ_LOCK_IRQSAVE(&pCh->Ibuf_spinlock,flags) 1956 read_lock_irqsave(&pCh->Ibuf_spinlock, flags);
1957 if ( pCh->Ibuf_stuff != pCh->Ibuf_strip ) { 1957 if ( pCh->Ibuf_stuff != pCh->Ibuf_strip ) {
1958 READ_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags) 1958 read_unlock_irqrestore(&pCh->Ibuf_spinlock, flags);
1959#ifdef IP2DEBUG_READ 1959#ifdef IP2DEBUG_READ
1960 printk (KERN_DEBUG "i2Input called from unthrottle\n" ); 1960 printk (KERN_DEBUG "i2Input called from unthrottle\n" );
1961#endif 1961#endif
1962 i2Input( pCh ); 1962 i2Input( pCh );
1963 } else 1963 } else
1964 READ_UNLOCK_IRQRESTORE(&pCh->Ibuf_spinlock,flags) 1964 read_unlock_irqrestore(&pCh->Ibuf_spinlock, flags);
1965} 1965}
1966 1966
1967static void 1967static void
@@ -2204,9 +2204,9 @@ ip2_ioctl ( PTTY tty, struct file *pFile, UINT cmd, ULONG arg )
2204 * for masking). Caller should use TIOCGICOUNT to see which one it was 2204 * for masking). Caller should use TIOCGICOUNT to see which one it was
2205 */ 2205 */
2206 case TIOCMIWAIT: 2206 case TIOCMIWAIT:
2207 WRITE_LOCK_IRQSAVE(&pB->read_fifo_spinlock, flags); 2207 write_lock_irqsave(&pB->read_fifo_spinlock, flags);
2208 cprev = pCh->icount; /* note the counters on entry */ 2208 cprev = pCh->icount; /* note the counters on entry */
2209 WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock, flags); 2209 write_unlock_irqrestore(&pB->read_fifo_spinlock, flags);
2210 i2QueueCommands(PTYPE_BYPASS, pCh, 100, 4, 2210 i2QueueCommands(PTYPE_BYPASS, pCh, 100, 4,
2211 CMD_DCD_REP, CMD_CTS_REP, CMD_DSR_REP, CMD_RI_REP); 2211 CMD_DCD_REP, CMD_CTS_REP, CMD_DSR_REP, CMD_RI_REP);
2212 init_waitqueue_entry(&wait, current); 2212 init_waitqueue_entry(&wait, current);
@@ -2226,9 +2226,9 @@ ip2_ioctl ( PTTY tty, struct file *pFile, UINT cmd, ULONG arg )
2226 rc = -ERESTARTSYS; 2226 rc = -ERESTARTSYS;
2227 break; 2227 break;
2228 } 2228 }
2229 WRITE_LOCK_IRQSAVE(&pB->read_fifo_spinlock, flags); 2229 write_lock_irqsave(&pB->read_fifo_spinlock, flags);
2230 cnow = pCh->icount; /* atomic copy */ 2230 cnow = pCh->icount; /* atomic copy */
2231 WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock, flags); 2231 write_unlock_irqrestore(&pB->read_fifo_spinlock, flags);
2232 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && 2232 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2233 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { 2233 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2234 rc = -EIO; /* no change => rc */ 2234 rc = -EIO; /* no change => rc */
@@ -2266,9 +2266,9 @@ ip2_ioctl ( PTTY tty, struct file *pFile, UINT cmd, ULONG arg )
2266 case TIOCGICOUNT: 2266 case TIOCGICOUNT:
2267 ip2trace (CHANN, ITRC_IOCTL, 11, 1, rc ); 2267 ip2trace (CHANN, ITRC_IOCTL, 11, 1, rc );
2268 2268
2269 WRITE_LOCK_IRQSAVE(&pB->read_fifo_spinlock, flags); 2269 write_lock_irqsave(&pB->read_fifo_spinlock, flags);
2270 cnow = pCh->icount; 2270 cnow = pCh->icount;
2271 WRITE_UNLOCK_IRQRESTORE(&pB->read_fifo_spinlock, flags); 2271 write_unlock_irqrestore(&pB->read_fifo_spinlock, flags);
2272 p_cuser = argp; 2272 p_cuser = argp;
2273 rc = put_user(cnow.cts, &p_cuser->cts); 2273 rc = put_user(cnow.cts, &p_cuser->cts);
2274 rc = put_user(cnow.dsr, &p_cuser->dsr); 2274 rc = put_user(cnow.dsr, &p_cuser->dsr);
@@ -2874,7 +2874,7 @@ ip2_ipl_ioctl ( struct inode *pInode, struct file *pFile, UINT cmd, ULONG arg )
2874 case 65: /* Board - ip2stat */ 2874 case 65: /* Board - ip2stat */
2875 if ( pB ) { 2875 if ( pB ) {
2876 rc = copy_to_user(argp, pB, sizeof(i2eBordStr)); 2876 rc = copy_to_user(argp, pB, sizeof(i2eBordStr));
2877 rc = put_user(INB(pB->i2eStatus), 2877 rc = put_user(inb(pB->i2eStatus),
2878 (ULONG __user *)(arg + (ULONG)(&pB->i2eStatus) - (ULONG)pB ) ); 2878 (ULONG __user *)(arg + (ULONG)(&pB->i2eStatus) - (ULONG)pB ) );
2879 } else { 2879 } else {
2880 rc = -ENODEV; 2880 rc = -ENODEV;
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 03:51:13 -0400