aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/char/drm
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/char/drm')
-rw-r--r--drivers/char/drm/ati_pcigart.c8
-rw-r--r--drivers/char/drm/drm.h19
-rw-r--r--drivers/char/drm/drmP.h91
-rw-r--r--drivers/char/drm/drm_drv.c7
-rw-r--r--drivers/char/drm/drm_fops.c7
-rw-r--r--drivers/char/drm/drm_irq.c381
-rw-r--r--drivers/char/drm/drm_lock.c35
-rw-r--r--drivers/char/drm/drm_pciids.h17
-rw-r--r--drivers/char/drm/drm_sysfs.c2
-rw-r--r--drivers/char/drm/i915_dma.c160
-rw-r--r--drivers/char/drm/i915_drm.h45
-rw-r--r--drivers/char/drm/i915_drv.c24
-rw-r--r--drivers/char/drm/i915_drv.h126
-rw-r--r--drivers/char/drm/i915_irq.c601
-rw-r--r--drivers/char/drm/mga_drv.c7
-rw-r--r--drivers/char/drm/mga_drv.h6
-rw-r--r--drivers/char/drm/mga_irq.c69
-rw-r--r--drivers/char/drm/r128_drv.c7
-rw-r--r--drivers/char/drm/r128_drv.h9
-rw-r--r--drivers/char/drm/r128_irq.c55
-rw-r--r--drivers/char/drm/r300_cmdbuf.c117
-rw-r--r--drivers/char/drm/r300_reg.h242
-rw-r--r--drivers/char/drm/radeon_cp.c1148
-rw-r--r--drivers/char/drm/radeon_drm.h8
-rw-r--r--drivers/char/drm/radeon_drv.c8
-rw-r--r--drivers/char/drm/radeon_drv.h270
-rw-r--r--drivers/char/drm/radeon_irq.c171
-rw-r--r--drivers/char/drm/radeon_microcode.h1844
-rw-r--r--drivers/char/drm/radeon_state.c17
-rw-r--r--drivers/char/drm/via_drv.c6
-rw-r--r--drivers/char/drm/via_drv.h7
-rw-r--r--drivers/char/drm/via_irq.c81
32 files changed, 3119 insertions, 2476 deletions
diff --git a/drivers/char/drm/ati_pcigart.c b/drivers/char/drm/ati_pcigart.c
index b710426bab3e..c533d0c9ec61 100644
--- a/drivers/char/drm/ati_pcigart.c
+++ b/drivers/char/drm/ati_pcigart.c
@@ -76,7 +76,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info
76 for (i = 0; i < pages; i++) { 76 for (i = 0; i < pages; i++) {
77 if (!entry->busaddr[i]) 77 if (!entry->busaddr[i])
78 break; 78 break;
79 pci_unmap_single(dev->pdev, entry->busaddr[i], 79 pci_unmap_page(dev->pdev, entry->busaddr[i],
80 PAGE_SIZE, PCI_DMA_TODEVICE); 80 PAGE_SIZE, PCI_DMA_TODEVICE);
81 } 81 }
82 82
@@ -137,10 +137,8 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
137 137
138 for (i = 0; i < pages; i++) { 138 for (i = 0; i < pages; i++) {
139 /* we need to support large memory configurations */ 139 /* we need to support large memory configurations */
140 entry->busaddr[i] = pci_map_single(dev->pdev, 140 entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
141 page_address(entry-> 141 0, PAGE_SIZE, PCI_DMA_TODEVICE);
142 pagelist[i]),
143 PAGE_SIZE, PCI_DMA_TODEVICE);
144 if (entry->busaddr[i] == 0) { 142 if (entry->busaddr[i] == 0) {
145 DRM_ERROR("unable to map PCIGART pages!\n"); 143 DRM_ERROR("unable to map PCIGART pages!\n");
146 drm_ati_pcigart_cleanup(dev, gart_info); 144 drm_ati_pcigart_cleanup(dev, gart_info);
diff --git a/drivers/char/drm/drm.h b/drivers/char/drm/drm.h
index 6874f31ca8ca..38d3c6b8276a 100644
--- a/drivers/char/drm/drm.h
+++ b/drivers/char/drm/drm.h
@@ -471,7 +471,6 @@ struct drm_irq_busid {
471enum drm_vblank_seq_type { 471enum drm_vblank_seq_type {
472 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 472 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
473 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 473 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
474 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
475 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 474 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
476 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 475 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
477 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ 476 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
@@ -504,21 +503,6 @@ union drm_wait_vblank {
504 struct drm_wait_vblank_reply reply; 503 struct drm_wait_vblank_reply reply;
505}; 504};
506 505
507enum drm_modeset_ctl_cmd {
508 _DRM_PRE_MODESET = 1,
509 _DRM_POST_MODESET = 2,
510};
511
512/**
513 * DRM_IOCTL_MODESET_CTL ioctl argument type
514 *
515 * \sa drmModesetCtl().
516 */
517struct drm_modeset_ctl {
518 unsigned long arg;
519 enum drm_modeset_ctl_cmd cmd;
520};
521
522/** 506/**
523 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 507 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
524 * 508 *
@@ -603,7 +587,6 @@ struct drm_set_version {
603#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) 587#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
604#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) 588#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
605#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) 589#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
606#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
607 590
608#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) 591#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
609#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) 592#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
@@ -645,7 +628,7 @@ struct drm_set_version {
645#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 628#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
646#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 629#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
647 630
648#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather) 631#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
649#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 632#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
650 633
651#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 634#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
diff --git a/drivers/char/drm/drmP.h b/drivers/char/drm/drmP.h
index 213b3ca3468e..0764b662b339 100644
--- a/drivers/char/drm/drmP.h
+++ b/drivers/char/drm/drmP.h
@@ -100,8 +100,10 @@ struct drm_device;
100#define DRIVER_HAVE_DMA 0x20 100#define DRIVER_HAVE_DMA 0x20
101#define DRIVER_HAVE_IRQ 0x40 101#define DRIVER_HAVE_IRQ 0x40
102#define DRIVER_IRQ_SHARED 0x80 102#define DRIVER_IRQ_SHARED 0x80
103#define DRIVER_IRQ_VBL 0x100
103#define DRIVER_DMA_QUEUE 0x200 104#define DRIVER_DMA_QUEUE 0x200
104#define DRIVER_FB_DMA 0x400 105#define DRIVER_FB_DMA 0x400
106#define DRIVER_IRQ_VBL2 0x800
105 107
106/***********************************************************************/ 108/***********************************************************************/
107/** \name Begin the DRM... */ 109/** \name Begin the DRM... */
@@ -577,52 +579,10 @@ struct drm_driver {
577 int (*context_dtor) (struct drm_device *dev, int context); 579 int (*context_dtor) (struct drm_device *dev, int context);
578 int (*kernel_context_switch) (struct drm_device *dev, int old, 580 int (*kernel_context_switch) (struct drm_device *dev, int old,
579 int new); 581 int new);
580 void (*kernel_context_switch_unlock) (struct drm_device * dev); 582 void (*kernel_context_switch_unlock) (struct drm_device *dev);
581 /** 583 int (*vblank_wait) (struct drm_device *dev, unsigned int *sequence);
582 * get_vblank_counter - get raw hardware vblank counter 584 int (*vblank_wait2) (struct drm_device *dev, unsigned int *sequence);
583 * @dev: DRM device 585 int (*dri_library_name) (struct drm_device *dev, char *buf);
584 * @crtc: counter to fetch
585 *
586 * Driver callback for fetching a raw hardware vblank counter
587 * for @crtc. If a device doesn't have a hardware counter, the
588 * driver can simply return the value of drm_vblank_count and
589 * make the enable_vblank() and disable_vblank() hooks into no-ops,
590 * leaving interrupts enabled at all times.
591 *
592 * Wraparound handling and loss of events due to modesetting is dealt
593 * with in the DRM core code.
594 *
595 * RETURNS
596 * Raw vblank counter value.
597 */
598 u32 (*get_vblank_counter) (struct drm_device *dev, int crtc);
599
600 /**
601 * enable_vblank - enable vblank interrupt events
602 * @dev: DRM device
603 * @crtc: which irq to enable
604 *
605 * Enable vblank interrupts for @crtc. If the device doesn't have
606 * a hardware vblank counter, this routine should be a no-op, since
607 * interrupts will have to stay on to keep the count accurate.
608 *
609 * RETURNS
610 * Zero on success, appropriate errno if the given @crtc's vblank
611 * interrupt cannot be enabled.
612 */
613 int (*enable_vblank) (struct drm_device *dev, int crtc);
614
615 /**
616 * disable_vblank - disable vblank interrupt events
617 * @dev: DRM device
618 * @crtc: which irq to enable
619 *
620 * Disable vblank interrupts for @crtc. If the device doesn't have
621 * a hardware vblank counter, this routine should be a no-op, since
622 * interrupts will have to stay on to keep the count accurate.
623 */
624 void (*disable_vblank) (struct drm_device *dev, int crtc);
625 int (*dri_library_name) (struct drm_device *dev, char * buf);
626 586
627 /** 587 /**
628 * Called by \c drm_device_is_agp. Typically used to determine if a 588 * Called by \c drm_device_is_agp. Typically used to determine if a
@@ -641,7 +601,7 @@ struct drm_driver {
641 601
642 irqreturn_t(*irq_handler) (DRM_IRQ_ARGS); 602 irqreturn_t(*irq_handler) (DRM_IRQ_ARGS);
643 void (*irq_preinstall) (struct drm_device *dev); 603 void (*irq_preinstall) (struct drm_device *dev);
644 int (*irq_postinstall) (struct drm_device *dev); 604 void (*irq_postinstall) (struct drm_device *dev);
645 void (*irq_uninstall) (struct drm_device *dev); 605 void (*irq_uninstall) (struct drm_device *dev);
646 void (*reclaim_buffers) (struct drm_device *dev, 606 void (*reclaim_buffers) (struct drm_device *dev,
647 struct drm_file * file_priv); 607 struct drm_file * file_priv);
@@ -770,21 +730,13 @@ struct drm_device {
770 /** \name VBLANK IRQ support */ 730 /** \name VBLANK IRQ support */
771 /*@{ */ 731 /*@{ */
772 732
773 wait_queue_head_t *vbl_queue; /**< VBLANK wait queue */ 733 wait_queue_head_t vbl_queue; /**< VBLANK wait queue */
774 atomic_t *_vblank_count; /**< number of VBLANK interrupts (driver must alloc the right number of counters) */ 734 atomic_t vbl_received;
735 atomic_t vbl_received2; /**< number of secondary VBLANK interrupts */
775 spinlock_t vbl_lock; 736 spinlock_t vbl_lock;
776 struct list_head *vbl_sigs; /**< signal list to send on VBLANK */ 737 struct list_head vbl_sigs; /**< signal list to send on VBLANK */
777 atomic_t vbl_signal_pending; /* number of signals pending on all crtcs*/ 738 struct list_head vbl_sigs2; /**< signals to send on secondary VBLANK */
778 atomic_t *vblank_refcount; /* number of users of vblank interrupts per crtc */ 739 unsigned int vbl_pending;
779 u32 *last_vblank; /* protected by dev->vbl_lock, used */
780 /* for wraparound handling */
781 u32 *vblank_offset; /* used to track how many vblanks */
782 int *vblank_enabled; /* so we don't call enable more than
783 once per disable */
784 u32 *vblank_premodeset; /* were lost during modeset */
785 struct timer_list vblank_disable_timer;
786
787 unsigned long max_vblank_count; /**< size of vblank counter register */
788 spinlock_t tasklet_lock; /**< For drm_locked_tasklet */ 740 spinlock_t tasklet_lock; /**< For drm_locked_tasklet */
789 void (*locked_tasklet_func)(struct drm_device *dev); 741 void (*locked_tasklet_func)(struct drm_device *dev);
790 742
@@ -804,7 +756,6 @@ struct drm_device {
804#ifdef __alpha__ 756#ifdef __alpha__
805 struct pci_controller *hose; 757 struct pci_controller *hose;
806#endif 758#endif
807 int num_crtcs; /**< Number of CRTCs on this device */
808 struct drm_sg_mem *sg; /**< Scatter gather memory */ 759 struct drm_sg_mem *sg; /**< Scatter gather memory */
809 void *dev_private; /**< device private data */ 760 void *dev_private; /**< device private data */
810 struct drm_sigdata sigdata; /**< For block_all_signals */ 761 struct drm_sigdata sigdata; /**< For block_all_signals */
@@ -1039,19 +990,11 @@ extern void drm_driver_irq_preinstall(struct drm_device *dev);
1039extern void drm_driver_irq_postinstall(struct drm_device *dev); 990extern void drm_driver_irq_postinstall(struct drm_device *dev);
1040extern void drm_driver_irq_uninstall(struct drm_device *dev); 991extern void drm_driver_irq_uninstall(struct drm_device *dev);
1041 992
1042extern int drm_vblank_init(struct drm_device *dev, int num_crtcs); 993extern int drm_wait_vblank(struct drm_device *dev, void *data,
1043extern int drm_wait_vblank(struct drm_device *dev, void *data, struct drm_file *filp);
1044extern int drm_vblank_wait(struct drm_device * dev, unsigned int *vbl_seq);
1045extern void drm_locked_tasklet(struct drm_device *dev, void(*func)(struct drm_device*));
1046extern u32 drm_vblank_count(struct drm_device *dev, int crtc);
1047extern void drm_update_vblank_count(struct drm_device *dev, int crtc);
1048extern void drm_handle_vblank(struct drm_device *dev, int crtc);
1049extern int drm_vblank_get(struct drm_device *dev, int crtc);
1050extern void drm_vblank_put(struct drm_device *dev, int crtc);
1051
1052 /* Modesetting support */
1053extern int drm_modeset_ctl(struct drm_device *dev, void *data,
1054 struct drm_file *file_priv); 994 struct drm_file *file_priv);
995extern int drm_vblank_wait(struct drm_device *dev, unsigned int *vbl_seq);
996extern void drm_vbl_send_signals(struct drm_device *dev);
997extern void drm_locked_tasklet(struct drm_device *dev, void(*func)(struct drm_device*));
1055 998
1056 /* AGP/GART support (drm_agpsupport.h) */ 999 /* AGP/GART support (drm_agpsupport.h) */
1057extern struct drm_agp_head *drm_agp_init(struct drm_device *dev); 1000extern struct drm_agp_head *drm_agp_init(struct drm_device *dev);
diff --git a/drivers/char/drm/drm_drv.c b/drivers/char/drm/drm_drv.c
index fc54140551a7..564138714bb5 100644
--- a/drivers/char/drm/drm_drv.c
+++ b/drivers/char/drm/drm_drv.c
@@ -470,17 +470,18 @@ int drm_ioctl(struct inode *inode, struct file *filp,
470 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) && 470 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) &&
471 (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) 471 (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls))
472 ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE]; 472 ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];
473 else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) 473 else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) {
474 ioctl = &drm_ioctls[nr]; 474 ioctl = &drm_ioctls[nr];
475 else 475 cmd = ioctl->cmd;
476 } else
476 goto err_i1; 477 goto err_i1;
477 478
479 /* Do not trust userspace, use our own definition */
478 func = ioctl->func; 480 func = ioctl->func;
479 /* is there a local override? */ 481 /* is there a local override? */
480 if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl) 482 if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl)
481 func = dev->driver->dma_ioctl; 483 func = dev->driver->dma_ioctl;
482 484
483
484 if (!func) { 485 if (!func) {
485 DRM_DEBUG("no function\n"); 486 DRM_DEBUG("no function\n");
486 retcode = -EINVAL; 487 retcode = -EINVAL;
diff --git a/drivers/char/drm/drm_fops.c b/drivers/char/drm/drm_fops.c
index 7a25726f07f7..851a53f1acce 100644
--- a/drivers/char/drm/drm_fops.c
+++ b/drivers/char/drm/drm_fops.c
@@ -328,7 +328,6 @@ int drm_release(struct inode *inode, struct file *filp)
328 struct drm_file *file_priv = filp->private_data; 328 struct drm_file *file_priv = filp->private_data;
329 struct drm_device *dev = file_priv->minor->dev; 329 struct drm_device *dev = file_priv->minor->dev;
330 int retcode = 0; 330 int retcode = 0;
331 unsigned long irqflags;
332 331
333 lock_kernel(); 332 lock_kernel();
334 333
@@ -360,11 +359,9 @@ int drm_release(struct inode *inode, struct file *filp)
360 */ 359 */
361 360
362 do{ 361 do{
363 spin_lock_irqsave(&dev->lock.spinlock, 362 spin_lock_bh(&dev->lock.spinlock);
364 irqflags);
365 locked = dev->lock.idle_has_lock; 363 locked = dev->lock.idle_has_lock;
366 spin_unlock_irqrestore(&dev->lock.spinlock, 364 spin_unlock_bh(&dev->lock.spinlock);
367 irqflags);
368 if (locked) 365 if (locked)
369 break; 366 break;
370 schedule(); 367 schedule();
diff --git a/drivers/char/drm/drm_irq.c b/drivers/char/drm/drm_irq.c
index 286f9d61e7d5..089c015c01d1 100644
--- a/drivers/char/drm/drm_irq.c
+++ b/drivers/char/drm/drm_irq.c
@@ -71,117 +71,6 @@ int drm_irq_by_busid(struct drm_device *dev, void *data,
71 return 0; 71 return 0;
72} 72}
73 73
74static void vblank_disable_fn(unsigned long arg)
75{
76 struct drm_device *dev = (struct drm_device *)arg;
77 unsigned long irqflags;
78 int i;
79
80 for (i = 0; i < dev->num_crtcs; i++) {
81 spin_lock_irqsave(&dev->vbl_lock, irqflags);
82 if (atomic_read(&dev->vblank_refcount[i]) == 0 &&
83 dev->vblank_enabled[i]) {
84 dev->driver->disable_vblank(dev, i);
85 dev->vblank_enabled[i] = 0;
86 }
87 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
88 }
89}
90
91static void drm_vblank_cleanup(struct drm_device *dev)
92{
93 /* Bail if the driver didn't call drm_vblank_init() */
94 if (dev->num_crtcs == 0)
95 return;
96
97 del_timer(&dev->vblank_disable_timer);
98
99 vblank_disable_fn((unsigned long)dev);
100
101 drm_free(dev->vbl_queue, sizeof(*dev->vbl_queue) * dev->num_crtcs,
102 DRM_MEM_DRIVER);
103 drm_free(dev->vbl_sigs, sizeof(*dev->vbl_sigs) * dev->num_crtcs,
104 DRM_MEM_DRIVER);
105 drm_free(dev->_vblank_count, sizeof(*dev->_vblank_count) *
106 dev->num_crtcs, DRM_MEM_DRIVER);
107 drm_free(dev->vblank_refcount, sizeof(*dev->vblank_refcount) *
108 dev->num_crtcs, DRM_MEM_DRIVER);
109 drm_free(dev->vblank_enabled, sizeof(*dev->vblank_enabled) *
110 dev->num_crtcs, DRM_MEM_DRIVER);
111 drm_free(dev->last_vblank, sizeof(*dev->last_vblank) * dev->num_crtcs,
112 DRM_MEM_DRIVER);
113 drm_free(dev->vblank_premodeset, sizeof(*dev->vblank_premodeset) *
114 dev->num_crtcs, DRM_MEM_DRIVER);
115 drm_free(dev->vblank_offset, sizeof(*dev->vblank_offset) * dev->num_crtcs,
116 DRM_MEM_DRIVER);
117
118 dev->num_crtcs = 0;
119}
120
121int drm_vblank_init(struct drm_device *dev, int num_crtcs)
122{
123 int i, ret = -ENOMEM;
124
125 setup_timer(&dev->vblank_disable_timer, vblank_disable_fn,
126 (unsigned long)dev);
127 spin_lock_init(&dev->vbl_lock);
128 atomic_set(&dev->vbl_signal_pending, 0);
129 dev->num_crtcs = num_crtcs;
130
131 dev->vbl_queue = drm_alloc(sizeof(wait_queue_head_t) * num_crtcs,
132 DRM_MEM_DRIVER);
133 if (!dev->vbl_queue)
134 goto err;
135
136 dev->vbl_sigs = drm_alloc(sizeof(struct list_head) * num_crtcs,
137 DRM_MEM_DRIVER);
138 if (!dev->vbl_sigs)
139 goto err;
140
141 dev->_vblank_count = drm_alloc(sizeof(atomic_t) * num_crtcs,
142 DRM_MEM_DRIVER);
143 if (!dev->_vblank_count)
144 goto err;
145
146 dev->vblank_refcount = drm_alloc(sizeof(atomic_t) * num_crtcs,
147 DRM_MEM_DRIVER);
148 if (!dev->vblank_refcount)
149 goto err;
150
151 dev->vblank_enabled = drm_calloc(num_crtcs, sizeof(int),
152 DRM_MEM_DRIVER);
153 if (!dev->vblank_enabled)
154 goto err;
155
156 dev->last_vblank = drm_calloc(num_crtcs, sizeof(u32), DRM_MEM_DRIVER);
157 if (!dev->last_vblank)
158 goto err;
159
160 dev->vblank_premodeset = drm_calloc(num_crtcs, sizeof(u32),
161 DRM_MEM_DRIVER);
162 if (!dev->vblank_premodeset)
163 goto err;
164
165 dev->vblank_offset = drm_calloc(num_crtcs, sizeof(u32), DRM_MEM_DRIVER);
166 if (!dev->vblank_offset)
167 goto err;
168
169 /* Zero per-crtc vblank stuff */
170 for (i = 0; i < num_crtcs; i++) {
171 init_waitqueue_head(&dev->vbl_queue[i]);
172 INIT_LIST_HEAD(&dev->vbl_sigs[i]);
173 atomic_set(&dev->_vblank_count[i], 0);
174 atomic_set(&dev->vblank_refcount[i], 0);
175 }
176
177 return 0;
178
179err:
180 drm_vblank_cleanup(dev);
181 return ret;
182}
183EXPORT_SYMBOL(drm_vblank_init);
184
185/** 74/**
186 * Install IRQ handler. 75 * Install IRQ handler.
187 * 76 *
@@ -220,6 +109,17 @@ static int drm_irq_install(struct drm_device * dev)
220 109
221 DRM_DEBUG("irq=%d\n", dev->irq); 110 DRM_DEBUG("irq=%d\n", dev->irq);
222 111
112 if (drm_core_check_feature(dev, DRIVER_IRQ_VBL)) {
113 init_waitqueue_head(&dev->vbl_queue);
114
115 spin_lock_init(&dev->vbl_lock);
116
117 INIT_LIST_HEAD(&dev->vbl_sigs);
118 INIT_LIST_HEAD(&dev->vbl_sigs2);
119
120 dev->vbl_pending = 0;
121 }
122
223 /* Before installing handler */ 123 /* Before installing handler */
224 dev->driver->irq_preinstall(dev); 124 dev->driver->irq_preinstall(dev);
225 125
@@ -237,14 +137,9 @@ static int drm_irq_install(struct drm_device * dev)
237 } 137 }
238 138
239 /* After installing handler */ 139 /* After installing handler */
240 ret = dev->driver->irq_postinstall(dev); 140 dev->driver->irq_postinstall(dev);
241 if (ret < 0) {
242 mutex_lock(&dev->struct_mutex);
243 dev->irq_enabled = 0;
244 mutex_unlock(&dev->struct_mutex);
245 }
246 141
247 return ret; 142 return 0;
248} 143}
249 144
250/** 145/**
@@ -275,8 +170,6 @@ int drm_irq_uninstall(struct drm_device * dev)
275 170
276 free_irq(dev->irq, dev); 171 free_irq(dev->irq, dev);
277 172
278 drm_vblank_cleanup(dev);
279
280 dev->locked_tasklet_func = NULL; 173 dev->locked_tasklet_func = NULL;
281 174
282 return 0; 175 return 0;
@@ -321,148 +214,6 @@ int drm_control(struct drm_device *dev, void *data,
321} 214}
322 215
323/** 216/**
324 * drm_vblank_count - retrieve "cooked" vblank counter value
325 * @dev: DRM device
326 * @crtc: which counter to retrieve
327 *
328 * Fetches the "cooked" vblank count value that represents the number of
329 * vblank events since the system was booted, including lost events due to
330 * modesetting activity.
331 */
332u32 drm_vblank_count(struct drm_device *dev, int crtc)
333{
334 return atomic_read(&dev->_vblank_count[crtc]) +
335 dev->vblank_offset[crtc];
336}
337EXPORT_SYMBOL(drm_vblank_count);
338
339/**
340 * drm_update_vblank_count - update the master vblank counter
341 * @dev: DRM device
342 * @crtc: counter to update
343 *
344 * Call back into the driver to update the appropriate vblank counter
345 * (specified by @crtc). Deal with wraparound, if it occurred, and
346 * update the last read value so we can deal with wraparound on the next
347 * call if necessary.
348 */
349void drm_update_vblank_count(struct drm_device *dev, int crtc)
350{
351 unsigned long irqflags;
352 u32 cur_vblank, diff;
353
354 /*
355 * Interrupts were disabled prior to this call, so deal with counter
356 * wrap if needed.
357 * NOTE! It's possible we lost a full dev->max_vblank_count events
358 * here if the register is small or we had vblank interrupts off for
359 * a long time.
360 */
361 cur_vblank = dev->driver->get_vblank_counter(dev, crtc);
362 spin_lock_irqsave(&dev->vbl_lock, irqflags);
363 if (cur_vblank < dev->last_vblank[crtc]) {
364 diff = dev->max_vblank_count -
365 dev->last_vblank[crtc];
366 diff += cur_vblank;
367 } else {
368 diff = cur_vblank - dev->last_vblank[crtc];
369 }
370 dev->last_vblank[crtc] = cur_vblank;
371 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
372
373 atomic_add(diff, &dev->_vblank_count[crtc]);
374}
375EXPORT_SYMBOL(drm_update_vblank_count);
376
377/**
378 * drm_vblank_get - get a reference count on vblank events
379 * @dev: DRM device
380 * @crtc: which CRTC to own
381 *
382 * Acquire a reference count on vblank events to avoid having them disabled
383 * while in use. Note callers will probably want to update the master counter
384 * using drm_update_vblank_count() above before calling this routine so that
385 * wakeups occur on the right vblank event.
386 *
387 * RETURNS
388 * Zero on success, nonzero on failure.
389 */
390int drm_vblank_get(struct drm_device *dev, int crtc)
391{
392 unsigned long irqflags;
393 int ret = 0;
394
395 spin_lock_irqsave(&dev->vbl_lock, irqflags);
396 /* Going from 0->1 means we have to enable interrupts again */
397 if (atomic_add_return(1, &dev->vblank_refcount[crtc]) == 1 &&
398 !dev->vblank_enabled[crtc]) {
399 ret = dev->driver->enable_vblank(dev, crtc);
400 if (ret)
401 atomic_dec(&dev->vblank_refcount[crtc]);
402 else
403 dev->vblank_enabled[crtc] = 1;
404 }
405 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
406
407 return ret;
408}
409EXPORT_SYMBOL(drm_vblank_get);
410
411/**
412 * drm_vblank_put - give up ownership of vblank events
413 * @dev: DRM device
414 * @crtc: which counter to give up
415 *
416 * Release ownership of a given vblank counter, turning off interrupts
417 * if possible.
418 */
419void drm_vblank_put(struct drm_device *dev, int crtc)
420{
421 /* Last user schedules interrupt disable */
422 if (atomic_dec_and_test(&dev->vblank_refcount[crtc]))
423 mod_timer(&dev->vblank_disable_timer, jiffies + 5*DRM_HZ);
424}
425EXPORT_SYMBOL(drm_vblank_put);
426
427/**
428 * drm_modeset_ctl - handle vblank event counter changes across mode switch
429 * @DRM_IOCTL_ARGS: standard ioctl arguments
430 *
431 * Applications should call the %_DRM_PRE_MODESET and %_DRM_POST_MODESET
432 * ioctls around modesetting so that any lost vblank events are accounted for.
433 */
434int drm_modeset_ctl(struct drm_device *dev, void *data,
435 struct drm_file *file_priv)
436{
437 struct drm_modeset_ctl *modeset = data;
438 int crtc, ret = 0;
439 u32 new;
440
441 crtc = modeset->arg;
442 if (crtc >= dev->num_crtcs) {
443 ret = -EINVAL;
444 goto out;
445 }
446
447 switch (modeset->cmd) {
448 case _DRM_PRE_MODESET:
449 dev->vblank_premodeset[crtc] =
450 dev->driver->get_vblank_counter(dev, crtc);
451 break;
452 case _DRM_POST_MODESET:
453 new = dev->driver->get_vblank_counter(dev, crtc);
454 dev->vblank_offset[crtc] = dev->vblank_premodeset[crtc] - new;
455 break;
456 default:
457 ret = -EINVAL;
458 break;
459 }
460
461out:
462 return ret;
463}
464
465/**
466 * Wait for VBLANK. 217 * Wait for VBLANK.
467 * 218 *
468 * \param inode device inode. 219 * \param inode device inode.
@@ -481,13 +232,12 @@ out:
481 * 232 *
482 * If a signal is not requested, then calls vblank_wait(). 233 * If a signal is not requested, then calls vblank_wait().
483 */ 234 */
484int drm_wait_vblank(struct drm_device *dev, void *data, 235int drm_wait_vblank(struct drm_device *dev, void *data, struct drm_file *file_priv)
485 struct drm_file *file_priv)
486{ 236{
487 union drm_wait_vblank *vblwait = data; 237 union drm_wait_vblank *vblwait = data;
488 struct timeval now; 238 struct timeval now;
489 int ret = 0; 239 int ret = 0;
490 unsigned int flags, seq, crtc; 240 unsigned int flags, seq;
491 241
492 if ((!dev->irq) || (!dev->irq_enabled)) 242 if ((!dev->irq) || (!dev->irq_enabled))
493 return -EINVAL; 243 return -EINVAL;
@@ -501,13 +251,13 @@ int drm_wait_vblank(struct drm_device *dev, void *data,
501 } 251 }
502 252
503 flags = vblwait->request.type & _DRM_VBLANK_FLAGS_MASK; 253 flags = vblwait->request.type & _DRM_VBLANK_FLAGS_MASK;
504 crtc = flags & _DRM_VBLANK_SECONDARY ? 1 : 0;
505 254
506 if (crtc >= dev->num_crtcs) 255 if (!drm_core_check_feature(dev, (flags & _DRM_VBLANK_SECONDARY) ?
256 DRIVER_IRQ_VBL2 : DRIVER_IRQ_VBL))
507 return -EINVAL; 257 return -EINVAL;
508 258
509 drm_update_vblank_count(dev, crtc); 259 seq = atomic_read((flags & _DRM_VBLANK_SECONDARY) ? &dev->vbl_received2
510 seq = drm_vblank_count(dev, crtc); 260 : &dev->vbl_received);
511 261
512 switch (vblwait->request.type & _DRM_VBLANK_TYPES_MASK) { 262 switch (vblwait->request.type & _DRM_VBLANK_TYPES_MASK) {
513 case _DRM_VBLANK_RELATIVE: 263 case _DRM_VBLANK_RELATIVE:
@@ -526,7 +276,8 @@ int drm_wait_vblank(struct drm_device *dev, void *data,
526 276
527 if (flags & _DRM_VBLANK_SIGNAL) { 277 if (flags & _DRM_VBLANK_SIGNAL) {
528 unsigned long irqflags; 278 unsigned long irqflags;
529 struct list_head *vbl_sigs = &dev->vbl_sigs[crtc]; 279 struct list_head *vbl_sigs = (flags & _DRM_VBLANK_SECONDARY)
280 ? &dev->vbl_sigs2 : &dev->vbl_sigs;
530 struct drm_vbl_sig *vbl_sig; 281 struct drm_vbl_sig *vbl_sig;
531 282
532 spin_lock_irqsave(&dev->vbl_lock, irqflags); 283 spin_lock_irqsave(&dev->vbl_lock, irqflags);
@@ -547,26 +298,22 @@ int drm_wait_vblank(struct drm_device *dev, void *data,
547 } 298 }
548 } 299 }
549 300
550 if (atomic_read(&dev->vbl_signal_pending) >= 100) { 301 if (dev->vbl_pending >= 100) {
551 spin_unlock_irqrestore(&dev->vbl_lock, irqflags); 302 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
552 return -EBUSY; 303 return -EBUSY;
553 } 304 }
554 305
306 dev->vbl_pending++;
307
555 spin_unlock_irqrestore(&dev->vbl_lock, irqflags); 308 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
556 309
557 vbl_sig = drm_calloc(1, sizeof(struct drm_vbl_sig), 310 if (!
558 DRM_MEM_DRIVER); 311 (vbl_sig =
559 if (!vbl_sig) 312 drm_alloc(sizeof(struct drm_vbl_sig), DRM_MEM_DRIVER))) {
560 return -ENOMEM; 313 return -ENOMEM;
561
562 ret = drm_vblank_get(dev, crtc);
563 if (ret) {
564 drm_free(vbl_sig, sizeof(struct drm_vbl_sig),
565 DRM_MEM_DRIVER);
566 return ret;
567 } 314 }
568 315
569 atomic_inc(&dev->vbl_signal_pending); 316 memset((void *)vbl_sig, 0, sizeof(*vbl_sig));
570 317
571 vbl_sig->sequence = vblwait->request.sequence; 318 vbl_sig->sequence = vblwait->request.sequence;
572 vbl_sig->info.si_signo = vblwait->request.signal; 319 vbl_sig->info.si_signo = vblwait->request.signal;
@@ -580,20 +327,17 @@ int drm_wait_vblank(struct drm_device *dev, void *data,
580 327
581 vblwait->reply.sequence = seq; 328 vblwait->reply.sequence = seq;
582 } else { 329 } else {
583 unsigned long cur_vblank; 330 if (flags & _DRM_VBLANK_SECONDARY) {
584 331 if (dev->driver->vblank_wait2)
585 ret = drm_vblank_get(dev, crtc); 332 ret = dev->driver->vblank_wait2(dev, &vblwait->request.sequence);
586 if (ret) 333 } else if (dev->driver->vblank_wait)
587 return ret; 334 ret =
588 DRM_WAIT_ON(ret, dev->vbl_queue[crtc], 3 * DRM_HZ, 335 dev->driver->vblank_wait(dev,
589 (((cur_vblank = drm_vblank_count(dev, crtc)) 336 &vblwait->request.sequence);
590 - vblwait->request.sequence) <= (1 << 23)));
591 drm_vblank_put(dev, crtc);
592 do_gettimeofday(&now);
593 337
338 do_gettimeofday(&now);
594 vblwait->reply.tval_sec = now.tv_sec; 339 vblwait->reply.tval_sec = now.tv_sec;
595 vblwait->reply.tval_usec = now.tv_usec; 340 vblwait->reply.tval_usec = now.tv_usec;
596 vblwait->reply.sequence = cur_vblank;
597 } 341 }
598 342
599 done: 343 done:
@@ -604,57 +348,44 @@ int drm_wait_vblank(struct drm_device *dev, void *data,
604 * Send the VBLANK signals. 348 * Send the VBLANK signals.
605 * 349 *
606 * \param dev DRM device. 350 * \param dev DRM device.
607 * \param crtc CRTC where the vblank event occurred
608 * 351 *
609 * Sends a signal for each task in drm_device::vbl_sigs and empties the list. 352 * Sends a signal for each task in drm_device::vbl_sigs and empties the list.
610 * 353 *
611 * If a signal is not requested, then calls vblank_wait(). 354 * If a signal is not requested, then calls vblank_wait().
612 */ 355 */
613static void drm_vbl_send_signals(struct drm_device * dev, int crtc) 356void drm_vbl_send_signals(struct drm_device * dev)
614{ 357{
615 struct drm_vbl_sig *vbl_sig, *tmp;
616 struct list_head *vbl_sigs;
617 unsigned int vbl_seq;
618 unsigned long flags; 358 unsigned long flags;
359 int i;
619 360
620 spin_lock_irqsave(&dev->vbl_lock, flags); 361 spin_lock_irqsave(&dev->vbl_lock, flags);
621 362
622 vbl_sigs = &dev->vbl_sigs[crtc]; 363 for (i = 0; i < 2; i++) {
623 vbl_seq = drm_vblank_count(dev, crtc); 364 struct drm_vbl_sig *vbl_sig, *tmp;
365 struct list_head *vbl_sigs = i ? &dev->vbl_sigs2 : &dev->vbl_sigs;
366 unsigned int vbl_seq = atomic_read(i ? &dev->vbl_received2 :
367 &dev->vbl_received);
624 368
625 list_for_each_entry_safe(vbl_sig, tmp, vbl_sigs, head) { 369 list_for_each_entry_safe(vbl_sig, tmp, vbl_sigs, head) {
626 if ((vbl_seq - vbl_sig->sequence) <= (1 << 23)) { 370 if ((vbl_seq - vbl_sig->sequence) <= (1 << 23)) {
627 vbl_sig->info.si_code = vbl_seq; 371 vbl_sig->info.si_code = vbl_seq;
628 send_sig_info(vbl_sig->info.si_signo, 372 send_sig_info(vbl_sig->info.si_signo,
629 &vbl_sig->info, vbl_sig->task); 373 &vbl_sig->info, vbl_sig->task);
630 374
631 list_del(&vbl_sig->head); 375 list_del(&vbl_sig->head);
632 376
633 drm_free(vbl_sig, sizeof(*vbl_sig), 377 drm_free(vbl_sig, sizeof(*vbl_sig),
634 DRM_MEM_DRIVER); 378 DRM_MEM_DRIVER);
635 atomic_dec(&dev->vbl_signal_pending); 379
636 drm_vblank_put(dev, crtc); 380 dev->vbl_pending--;
637 } 381 }
382 }
638 } 383 }
639 384
640 spin_unlock_irqrestore(&dev->vbl_lock, flags); 385 spin_unlock_irqrestore(&dev->vbl_lock, flags);
641} 386}
642 387
643/** 388EXPORT_SYMBOL(drm_vbl_send_signals);
644 * drm_handle_vblank - handle a vblank event
645 * @dev: DRM device
646 * @crtc: where this event occurred
647 *
648 * Drivers should call this routine in their vblank interrupt handlers to
649 * update the vblank counter and send any signals that may be pending.
650 */
651void drm_handle_vblank(struct drm_device *dev, int crtc)
652{
653 drm_update_vblank_count(dev, crtc);
654 DRM_WAKEUP(&dev->vbl_queue[crtc]);
655 drm_vbl_send_signals(dev, crtc);
656}
657EXPORT_SYMBOL(drm_handle_vblank);
658 389
659/** 390/**
660 * Tasklet wrapper function. 391 * Tasklet wrapper function.
diff --git a/drivers/char/drm/drm_lock.c b/drivers/char/drm/drm_lock.c
index 12dcdd1832f0..0998723cde79 100644
--- a/drivers/char/drm/drm_lock.c
+++ b/drivers/char/drm/drm_lock.c
@@ -53,7 +53,6 @@ int drm_lock(struct drm_device *dev, void *data, struct drm_file *file_priv)
53 DECLARE_WAITQUEUE(entry, current); 53 DECLARE_WAITQUEUE(entry, current);
54 struct drm_lock *lock = data; 54 struct drm_lock *lock = data;
55 int ret = 0; 55 int ret = 0;
56 unsigned long irqflags;
57 56
58 ++file_priv->lock_count; 57 ++file_priv->lock_count;
59 58
@@ -72,9 +71,9 @@ int drm_lock(struct drm_device *dev, void *data, struct drm_file *file_priv)
72 return -EINVAL; 71 return -EINVAL;
73 72
74 add_wait_queue(&dev->lock.lock_queue, &entry); 73 add_wait_queue(&dev->lock.lock_queue, &entry);
75 spin_lock_irqsave(&dev->lock.spinlock, irqflags); 74 spin_lock_bh(&dev->lock.spinlock);
76 dev->lock.user_waiters++; 75 dev->lock.user_waiters++;
77 spin_unlock_irqrestore(&dev->lock.spinlock, irqflags); 76 spin_unlock_bh(&dev->lock.spinlock);
78 for (;;) { 77 for (;;) {
79 __set_current_state(TASK_INTERRUPTIBLE); 78 __set_current_state(TASK_INTERRUPTIBLE);
80 if (!dev->lock.hw_lock) { 79 if (!dev->lock.hw_lock) {
@@ -96,9 +95,9 @@ int drm_lock(struct drm_device *dev, void *data, struct drm_file *file_priv)
96 break; 95 break;
97 } 96 }
98 } 97 }
99 spin_lock_irqsave(&dev->lock.spinlock, irqflags); 98 spin_lock_bh(&dev->lock.spinlock);
100 dev->lock.user_waiters--; 99 dev->lock.user_waiters--;
101 spin_unlock_irqrestore(&dev->lock.spinlock, irqflags); 100 spin_unlock_bh(&dev->lock.spinlock);
102 __set_current_state(TASK_RUNNING); 101 __set_current_state(TASK_RUNNING);
103 remove_wait_queue(&dev->lock.lock_queue, &entry); 102 remove_wait_queue(&dev->lock.lock_queue, &entry);
104 103
@@ -199,9 +198,8 @@ int drm_lock_take(struct drm_lock_data *lock_data,
199{ 198{
200 unsigned int old, new, prev; 199 unsigned int old, new, prev;
201 volatile unsigned int *lock = &lock_data->hw_lock->lock; 200 volatile unsigned int *lock = &lock_data->hw_lock->lock;
202 unsigned long irqflags;
203 201
204 spin_lock_irqsave(&lock_data->spinlock, irqflags); 202 spin_lock_bh(&lock_data->spinlock);
205 do { 203 do {
206 old = *lock; 204 old = *lock;
207 if (old & _DRM_LOCK_HELD) 205 if (old & _DRM_LOCK_HELD)
@@ -213,7 +211,7 @@ int drm_lock_take(struct drm_lock_data *lock_data,
213 } 211 }
214 prev = cmpxchg(lock, old, new); 212 prev = cmpxchg(lock, old, new);
215 } while (prev != old); 213 } while (prev != old);
216 spin_unlock_irqrestore(&lock_data->spinlock, irqflags); 214 spin_unlock_bh(&lock_data->spinlock);
217 215
218 if (_DRM_LOCKING_CONTEXT(old) == context) { 216 if (_DRM_LOCKING_CONTEXT(old) == context) {
219 if (old & _DRM_LOCK_HELD) { 217 if (old & _DRM_LOCK_HELD) {
@@ -274,16 +272,15 @@ int drm_lock_free(struct drm_lock_data *lock_data, unsigned int context)
274{ 272{
275 unsigned int old, new, prev; 273 unsigned int old, new, prev;
276 volatile unsigned int *lock = &lock_data->hw_lock->lock; 274 volatile unsigned int *lock = &lock_data->hw_lock->lock;
277 unsigned long irqflags;
278 275
279 spin_lock_irqsave(&lock_data->spinlock, irqflags); 276 spin_lock_bh(&lock_data->spinlock);
280 if (lock_data->kernel_waiters != 0) { 277 if (lock_data->kernel_waiters != 0) {
281 drm_lock_transfer(lock_data, 0); 278 drm_lock_transfer(lock_data, 0);
282 lock_data->idle_has_lock = 1; 279 lock_data->idle_has_lock = 1;
283 spin_unlock_irqrestore(&lock_data->spinlock, irqflags); 280 spin_unlock_bh(&lock_data->spinlock);
284 return 1; 281 return 1;
285 } 282 }
286 spin_unlock_irqrestore(&lock_data->spinlock, irqflags); 283 spin_unlock_bh(&lock_data->spinlock);
287 284
288 do { 285 do {
289 old = *lock; 286 old = *lock;
@@ -347,20 +344,19 @@ static int drm_notifier(void *priv)
347void drm_idlelock_take(struct drm_lock_data *lock_data) 344void drm_idlelock_take(struct drm_lock_data *lock_data)
348{ 345{
349 int ret = 0; 346 int ret = 0;
350 unsigned long irqflags;
351 347
352 spin_lock_irqsave(&lock_data->spinlock, irqflags); 348 spin_lock_bh(&lock_data->spinlock);
353 lock_data->kernel_waiters++; 349 lock_data->kernel_waiters++;
354 if (!lock_data->idle_has_lock) { 350 if (!lock_data->idle_has_lock) {
355 351
356 spin_unlock_irqrestore(&lock_data->spinlock, irqflags); 352 spin_unlock_bh(&lock_data->spinlock);
357 ret = drm_lock_take(lock_data, DRM_KERNEL_CONTEXT); 353 ret = drm_lock_take(lock_data, DRM_KERNEL_CONTEXT);
358 spin_lock_irqsave(&lock_data->spinlock, irqflags); 354 spin_lock_bh(&lock_data->spinlock);
359 355
360 if (ret == 1) 356 if (ret == 1)
361 lock_data->idle_has_lock = 1; 357 lock_data->idle_has_lock = 1;
362 } 358 }
363 spin_unlock_irqrestore(&lock_data->spinlock, irqflags); 359 spin_unlock_bh(&lock_data->spinlock);
364} 360}
365EXPORT_SYMBOL(drm_idlelock_take); 361EXPORT_SYMBOL(drm_idlelock_take);
366 362
@@ -368,9 +364,8 @@ void drm_idlelock_release(struct drm_lock_data *lock_data)
368{ 364{
369 unsigned int old, prev; 365 unsigned int old, prev;
370 volatile unsigned int *lock = &lock_data->hw_lock->lock; 366 volatile unsigned int *lock = &lock_data->hw_lock->lock;
371 unsigned long irqflags;
372 367
373 spin_lock_irqsave(&lock_data->spinlock, irqflags); 368 spin_lock_bh(&lock_data->spinlock);
374 if (--lock_data->kernel_waiters == 0) { 369 if (--lock_data->kernel_waiters == 0) {
375 if (lock_data->idle_has_lock) { 370 if (lock_data->idle_has_lock) {
376 do { 371 do {
@@ -381,7 +376,7 @@ void drm_idlelock_release(struct drm_lock_data *lock_data)
381 lock_data->idle_has_lock = 0; 376 lock_data->idle_has_lock = 0;
382 } 377 }
383 } 378 }
384 spin_unlock_irqrestore(&lock_data->spinlock, irqflags); 379 spin_unlock_bh(&lock_data->spinlock);
385} 380}
386EXPORT_SYMBOL(drm_idlelock_release); 381EXPORT_SYMBOL(drm_idlelock_release);
387 382
diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h
index a6a499f97e22..135bd19499fc 100644
--- a/drivers/char/drm/drm_pciids.h
+++ b/drivers/char/drm/drm_pciids.h
@@ -103,20 +103,18 @@
103 {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 103 {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
104 {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \ 104 {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \
105 {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ 105 {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
106 {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 106 {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
107 {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 107 {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
108 {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 108 {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
109 {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 109 {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
110 {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 110 {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
111 {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 111 {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
112 {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 112 {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
113 {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 113 {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
114 {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 114 {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
115 {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ 115 {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
116 {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 116 {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
117 {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 117 {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
118 {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
119 {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
120 {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 118 {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
121 {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 119 {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
122 {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 120 {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
@@ -411,4 +409,7 @@
411 {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 409 {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
412 {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 410 {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
413 {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 411 {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
412 {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
413 {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
414 {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
414 {0, 0, 0} 415 {0, 0, 0}
diff --git a/drivers/char/drm/drm_sysfs.c b/drivers/char/drm/drm_sysfs.c
index 9a32169e88fb..af211a0ef179 100644
--- a/drivers/char/drm/drm_sysfs.c
+++ b/drivers/char/drm/drm_sysfs.c
@@ -34,8 +34,6 @@ static int drm_sysfs_suspend(struct device *dev, pm_message_t state)
34 struct drm_minor *drm_minor = to_drm_minor(dev); 34 struct drm_minor *drm_minor = to_drm_minor(dev);
35 struct drm_device *drm_dev = drm_minor->dev; 35 struct drm_device *drm_dev = drm_minor->dev;
36 36
37 printk(KERN_ERR "%s\n", __func__);
38
39 if (drm_dev->driver->suspend) 37 if (drm_dev->driver->suspend)
40 return drm_dev->driver->suspend(drm_dev, state); 38 return drm_dev->driver->suspend(drm_dev, state);
41 39
diff --git a/drivers/char/drm/i915_dma.c b/drivers/char/drm/i915_dma.c
index f47e46e3529f..88974342933c 100644
--- a/drivers/char/drm/i915_dma.c
+++ b/drivers/char/drm/i915_dma.c
@@ -415,13 +415,10 @@ static void i915_emit_breadcrumb(struct drm_device *dev)
415 drm_i915_private_t *dev_priv = dev->dev_private; 415 drm_i915_private_t *dev_priv = dev->dev_private;
416 RING_LOCALS; 416 RING_LOCALS;
417 417
418 if (++dev_priv->counter > BREADCRUMB_MASK) { 418 dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
419 dev_priv->counter = 1;
420 DRM_DEBUG("Breadcrumb counter wrapped around\n");
421 }
422 419
423 if (dev_priv->sarea_priv) 420 if (dev_priv->counter > 0x7FFFFFFFUL)
424 dev_priv->sarea_priv->last_enqueue = dev_priv->counter; 421 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
425 422
426 BEGIN_LP_RING(4); 423 BEGIN_LP_RING(4);
427 OUT_RING(CMD_STORE_DWORD_IDX); 424 OUT_RING(CMD_STORE_DWORD_IDX);
@@ -431,26 +428,6 @@ static void i915_emit_breadcrumb(struct drm_device *dev)
431 ADVANCE_LP_RING(); 428 ADVANCE_LP_RING();
432} 429}
433 430
434int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
435{
436 drm_i915_private_t *dev_priv = dev->dev_private;
437 uint32_t flush_cmd = CMD_MI_FLUSH;
438 RING_LOCALS;
439
440 flush_cmd |= flush;
441
442 i915_kernel_lost_context(dev);
443
444 BEGIN_LP_RING(4);
445 OUT_RING(flush_cmd);
446 OUT_RING(0);
447 OUT_RING(0);
448 OUT_RING(0);
449 ADVANCE_LP_RING();
450
451 return 0;
452}
453
454static int i915_dispatch_cmdbuffer(struct drm_device * dev, 431static int i915_dispatch_cmdbuffer(struct drm_device * dev,
455 drm_i915_cmdbuffer_t * cmd) 432 drm_i915_cmdbuffer_t * cmd)
456{ 433{
@@ -534,74 +511,52 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev,
534 return 0; 511 return 0;
535} 512}
536 513
537static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync) 514static int i915_dispatch_flip(struct drm_device * dev)
538{ 515{
539 drm_i915_private_t *dev_priv = dev->dev_private; 516 drm_i915_private_t *dev_priv = dev->dev_private;
540 u32 num_pages, current_page, next_page, dspbase;
541 int shift = 2 * plane, x, y;
542 RING_LOCALS; 517 RING_LOCALS;
543 518
544 /* Calculate display base offset */ 519 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
545 num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2; 520 __FUNCTION__,
546 current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3; 521 dev_priv->current_page,
547 next_page = (current_page + 1) % num_pages; 522 dev_priv->sarea_priv->pf_current_page);
548 523
549 switch (next_page) { 524 i915_kernel_lost_context(dev);
550 default: 525
551 case 0: 526 BEGIN_LP_RING(2);
552 dspbase = dev_priv->sarea_priv->front_offset; 527 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
553 break; 528 OUT_RING(0);
554 case 1: 529 ADVANCE_LP_RING();
555 dspbase = dev_priv->sarea_priv->back_offset;
556 break;
557 case 2:
558 dspbase = dev_priv->sarea_priv->third_offset;
559 break;
560 }
561 530
562 if (plane == 0) { 531 BEGIN_LP_RING(6);
563 x = dev_priv->sarea_priv->planeA_x; 532 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
564 y = dev_priv->sarea_priv->planeA_y; 533 OUT_RING(0);
534 if (dev_priv->current_page == 0) {
535 OUT_RING(dev_priv->back_offset);
536 dev_priv->current_page = 1;
565 } else { 537 } else {
566 x = dev_priv->sarea_priv->planeB_x; 538 OUT_RING(dev_priv->front_offset);
567 y = dev_priv->sarea_priv->planeB_y; 539 dev_priv->current_page = 0;
568 } 540 }
541 OUT_RING(0);
542 ADVANCE_LP_RING();
569 543
570 dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp; 544 BEGIN_LP_RING(2);
545 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
546 OUT_RING(0);
547 ADVANCE_LP_RING();
571 548
572 DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page, 549 dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
573 dspbase);
574 550
575 BEGIN_LP_RING(4); 551 BEGIN_LP_RING(4);
576 OUT_RING(sync ? 0 : 552 OUT_RING(CMD_STORE_DWORD_IDX);
577 (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP : 553 OUT_RING(20);
578 MI_WAIT_FOR_PLANE_A_FLIP))); 554 OUT_RING(dev_priv->counter);
579 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) | 555 OUT_RING(0);
580 (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
581 OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
582 OUT_RING(dspbase);
583 ADVANCE_LP_RING(); 556 ADVANCE_LP_RING();
584 557
585 dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift); 558 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
586 dev_priv->sarea_priv->pf_current_page |= next_page << shift; 559 return 0;
587}
588
589void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
590{
591 drm_i915_private_t *dev_priv = dev->dev_private;
592 int i;
593
594 DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
595 planes, dev_priv->sarea_priv->pf_current_page);
596
597 i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
598
599 for (i = 0; i < 2; i++)
600 if (planes & (1 << i))
601 i915_do_dispatch_flip(dev, i, sync);
602
603 i915_emit_breadcrumb(dev);
604
605} 560}
606 561
607static int i915_quiescent(struct drm_device * dev) 562static int i915_quiescent(struct drm_device * dev)
@@ -624,6 +579,7 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
624 struct drm_file *file_priv) 579 struct drm_file *file_priv)
625{ 580{
626 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 581 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
582 u32 *hw_status = dev_priv->hw_status_page;
627 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 583 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
628 dev_priv->sarea_priv; 584 dev_priv->sarea_priv;
629 drm_i915_batchbuffer_t *batch = data; 585 drm_i915_batchbuffer_t *batch = data;
@@ -646,7 +602,7 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
646 602
647 ret = i915_dispatch_batchbuffer(dev, batch); 603 ret = i915_dispatch_batchbuffer(dev, batch);
648 604
649 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 605 sarea_priv->last_dispatch = (int)hw_status[5];
650 return ret; 606 return ret;
651} 607}
652 608
@@ -654,6 +610,7 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
654 struct drm_file *file_priv) 610 struct drm_file *file_priv)
655{ 611{
656 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 612 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
613 u32 *hw_status = dev_priv->hw_status_page;
657 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 614 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
658 dev_priv->sarea_priv; 615 dev_priv->sarea_priv;
659 drm_i915_cmdbuffer_t *cmdbuf = data; 616 drm_i915_cmdbuffer_t *cmdbuf = data;
@@ -678,51 +635,18 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
678 return ret; 635 return ret;
679 } 636 }
680 637
681 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 638 sarea_priv->last_dispatch = (int)hw_status[5];
682 return 0;
683}
684
685static int i915_do_cleanup_pageflip(struct drm_device * dev)
686{
687 drm_i915_private_t *dev_priv = dev->dev_private;
688 int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
689
690 DRM_DEBUG("\n");
691
692 for (i = 0, planes = 0; i < 2; i++)
693 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
694 dev_priv->sarea_priv->pf_current_page =
695 (dev_priv->sarea_priv->pf_current_page &
696 ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
697
698 planes |= 1 << i;
699 }
700
701 if (planes)
702 i915_dispatch_flip(dev, planes, 0);
703
704 return 0; 639 return 0;
705} 640}
706 641
707static int i915_flip_bufs(struct drm_device *dev, void *data, 642static int i915_flip_bufs(struct drm_device *dev, void *data,
708 struct drm_file *file_priv) 643 struct drm_file *file_priv)
709{ 644{
710 drm_i915_flip_t *param = data; 645 DRM_DEBUG("%s\n", __FUNCTION__);
711
712 DRM_DEBUG("\n");
713 646
714 LOCK_TEST_WITH_RETURN(dev, file_priv); 647 LOCK_TEST_WITH_RETURN(dev, file_priv);
715 648
716 /* This is really planes */ 649 return i915_dispatch_flip(dev);
717 if (param->pipes & ~0x3) {
718 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
719 param->pipes);
720 return -EINVAL;
721 }
722
723 i915_dispatch_flip(dev, param->pipes, 0);
724
725 return 0;
726} 650}
727 651
728static int i915_getparam(struct drm_device *dev, void *data, 652static int i915_getparam(struct drm_device *dev, void *data,
@@ -883,8 +807,6 @@ void i915_driver_lastclose(struct drm_device * dev)
883 if (!dev_priv) 807 if (!dev_priv)
884 return; 808 return;
885 809
886 if (drm_getsarea(dev) && dev_priv->sarea_priv)
887 i915_do_cleanup_pageflip(dev);
888 if (dev_priv->agp_heap) 810 if (dev_priv->agp_heap)
889 i915_mem_takedown(&(dev_priv->agp_heap)); 811 i915_mem_takedown(&(dev_priv->agp_heap));
890 812
diff --git a/drivers/char/drm/i915_drm.h b/drivers/char/drm/i915_drm.h
index 0431c00e2289..05c66cf03a9e 100644
--- a/drivers/char/drm/i915_drm.h
+++ b/drivers/char/drm/i915_drm.h
@@ -105,29 +105,14 @@ typedef struct _drm_i915_sarea {
105 unsigned int rotated_tiled; 105 unsigned int rotated_tiled;
106 unsigned int rotated2_tiled; 106 unsigned int rotated2_tiled;
107 107
108 int planeA_x; 108 int pipeA_x;
109 int planeA_y; 109 int pipeA_y;
110 int planeA_w; 110 int pipeA_w;
111 int planeA_h; 111 int pipeA_h;
112 int planeB_x; 112 int pipeB_x;
113 int planeB_y; 113 int pipeB_y;
114 int planeB_w; 114 int pipeB_w;
115 int planeB_h; 115 int pipeB_h;
116
117 /* Triple buffering */
118 drm_handle_t third_handle;
119 int third_offset;
120 int third_size;
121 unsigned int third_tiled;
122
123 /* buffer object handles for the static buffers. May change
124 * over the lifetime of the client, though it doesn't in our current
125 * implementation.
126 */
127 unsigned int front_bo_handle;
128 unsigned int back_bo_handle;
129 unsigned int third_bo_handle;
130 unsigned int depth_bo_handle;
131} drm_i915_sarea_t; 116} drm_i915_sarea_t;
132 117
133/* Flags for perf_boxes 118/* Flags for perf_boxes
@@ -161,7 +146,7 @@ typedef struct _drm_i915_sarea {
161 146
162#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 147#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
163#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 148#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
164#define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t) 149#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
165#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 150#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
166#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 151#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
167#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 152#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
@@ -176,18 +161,6 @@ typedef struct _drm_i915_sarea {
176#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 161#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
177#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 162#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
178 163
179/* Asynchronous page flipping:
180 */
181typedef struct drm_i915_flip {
182 /*
183 * This is really talking about planes, and we could rename it
184 * except for the fact that some of the duplicated i915_drm.h files
185 * out there check for HAVE_I915_FLIP and so might pick up this
186 * version.
187 */
188 int pipes;
189} drm_i915_flip_t;
190
191/* Allow drivers to submit batchbuffers directly to hardware, relying 164/* Allow drivers to submit batchbuffers directly to hardware, relying
192 * on the security mechanisms provided by hardware. 165 * on the security mechanisms provided by hardware.
193 */ 166 */
diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c
index bb8f1b2fb383..93aed1c38bd2 100644
--- a/drivers/char/drm/i915_drv.c
+++ b/drivers/char/drm/i915_drv.c
@@ -147,7 +147,7 @@ static void i915_save_vga(struct drm_device *dev)
147 i915_write_indexed(cr_index, cr_data, 0x11, 147 i915_write_indexed(cr_index, cr_data, 0x11,
148 i915_read_indexed(cr_index, cr_data, 0x11) & 148 i915_read_indexed(cr_index, cr_data, 0x11) &
149 (~0x80)); 149 (~0x80));
150 for (i = 0; i < 0x24; i++) 150 for (i = 0; i <= 0x24; i++)
151 dev_priv->saveCR[i] = 151 dev_priv->saveCR[i] =
152 i915_read_indexed(cr_index, cr_data, i); 152 i915_read_indexed(cr_index, cr_data, i);
153 /* Make sure we don't turn off CR group 0 writes */ 153 /* Make sure we don't turn off CR group 0 writes */
@@ -156,7 +156,7 @@ static void i915_save_vga(struct drm_device *dev)
156 /* Attribute controller registers */ 156 /* Attribute controller registers */
157 inb(st01); 157 inb(st01);
158 dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX); 158 dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
159 for (i = 0; i < 20; i++) 159 for (i = 0; i <= 0x14; i++)
160 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0); 160 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
161 inb(st01); 161 inb(st01);
162 outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX); 162 outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
@@ -206,7 +206,7 @@ static void i915_restore_vga(struct drm_device *dev)
206 /* CRT controller regs */ 206 /* CRT controller regs */
207 /* Enable CR group 0 writes */ 207 /* Enable CR group 0 writes */
208 i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]); 208 i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
209 for (i = 0; i < 0x24; i++) 209 for (i = 0; i <= 0x24; i++)
210 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]); 210 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
211 211
212 /* Graphics controller regs */ 212 /* Graphics controller regs */
@@ -223,7 +223,7 @@ static void i915_restore_vga(struct drm_device *dev)
223 223
224 /* Attribute controller registers */ 224 /* Attribute controller registers */
225 inb(st01); 225 inb(st01);
226 for (i = 0; i < 20; i++) 226 for (i = 0; i <= 0x14; i++)
227 i915_write_ar(st01, i, dev_priv->saveAR[i], 0); 227 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
228 inb(st01); /* switch back to index mode */ 228 inb(st01); /* switch back to index mode */
229 outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX); 229 outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
@@ -256,6 +256,9 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
256 pci_save_state(dev->pdev); 256 pci_save_state(dev->pdev);
257 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 257 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
258 258
259 /* Display arbitration control */
260 dev_priv->saveDSPARB = I915_READ(DSPARB);
261
259 /* Pipe & plane A info */ 262 /* Pipe & plane A info */
260 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 263 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
261 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 264 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
@@ -349,6 +352,7 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
349 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); 352 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
350 353
351 /* Clock gating state */ 354 /* Clock gating state */
355 dev_priv->saveD_STATE = I915_READ(D_STATE);
352 dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); 356 dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
353 357
354 /* Cache mode state */ 358 /* Cache mode state */
@@ -385,9 +389,12 @@ static int i915_resume(struct drm_device *dev)
385 pci_restore_state(dev->pdev); 389 pci_restore_state(dev->pdev);
386 if (pci_enable_device(dev->pdev)) 390 if (pci_enable_device(dev->pdev))
387 return -1; 391 return -1;
392 pci_set_master(dev->pdev);
388 393
389 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 394 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
390 395
396 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
397
391 /* Pipe & plane A info */ 398 /* Pipe & plane A info */
392 /* Prime the clock */ 399 /* Prime the clock */
393 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { 400 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
@@ -507,6 +514,7 @@ static int i915_resume(struct drm_device *dev)
507 udelay(150); 514 udelay(150);
508 515
509 /* Clock gating state */ 516 /* Clock gating state */
517 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
510 I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); 518 I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
511 519
512 /* Cache mode state */ 520 /* Cache mode state */
@@ -533,7 +541,8 @@ static struct drm_driver driver = {
533 */ 541 */
534 .driver_features = 542 .driver_features =
535 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ 543 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
536 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED, 544 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL |
545 DRIVER_IRQ_VBL2,
537 .load = i915_driver_load, 546 .load = i915_driver_load,
538 .unload = i915_driver_unload, 547 .unload = i915_driver_unload,
539 .lastclose = i915_driver_lastclose, 548 .lastclose = i915_driver_lastclose,
@@ -541,9 +550,8 @@ static struct drm_driver driver = {
541 .suspend = i915_suspend, 550 .suspend = i915_suspend,
542 .resume = i915_resume, 551 .resume = i915_resume,
543 .device_is_agp = i915_driver_device_is_agp, 552 .device_is_agp = i915_driver_device_is_agp,
544 .get_vblank_counter = i915_get_vblank_counter, 553 .vblank_wait = i915_driver_vblank_wait,
545 .enable_vblank = i915_enable_vblank, 554 .vblank_wait2 = i915_driver_vblank_wait2,
546 .disable_vblank = i915_disable_vblank,
547 .irq_preinstall = i915_driver_irq_preinstall, 555 .irq_preinstall = i915_driver_irq_preinstall,
548 .irq_postinstall = i915_driver_irq_postinstall, 556 .irq_postinstall = i915_driver_irq_postinstall,
549 .irq_uninstall = i915_driver_irq_uninstall, 557 .irq_uninstall = i915_driver_irq_uninstall,
diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h
index db7001f22561..d7326d92a237 100644
--- a/drivers/char/drm/i915_drv.h
+++ b/drivers/char/drm/i915_drv.h
@@ -76,9 +76,8 @@ struct mem_block {
76typedef struct _drm_i915_vbl_swap { 76typedef struct _drm_i915_vbl_swap {
77 struct list_head head; 77 struct list_head head;
78 drm_drawable_t drw_id; 78 drm_drawable_t drw_id;
79 unsigned int plane; 79 unsigned int pipe;
80 unsigned int sequence; 80 unsigned int sequence;
81 int flip;
82} drm_i915_vbl_swap_t; 81} drm_i915_vbl_swap_t;
83 82
84typedef struct drm_i915_private { 83typedef struct drm_i915_private {
@@ -91,7 +90,7 @@ typedef struct drm_i915_private {
91 drm_dma_handle_t *status_page_dmah; 90 drm_dma_handle_t *status_page_dmah;
92 void *hw_status_page; 91 void *hw_status_page;
93 dma_addr_t dma_status_page; 92 dma_addr_t dma_status_page;
94 uint32_t counter; 93 unsigned long counter;
95 unsigned int status_gfx_addr; 94 unsigned int status_gfx_addr;
96 drm_local_map_t hws_map; 95 drm_local_map_t hws_map;
97 96
@@ -104,18 +103,13 @@ typedef struct drm_i915_private {
104 103
105 wait_queue_head_t irq_queue; 104 wait_queue_head_t irq_queue;
106 atomic_t irq_received; 105 atomic_t irq_received;
107 atomic_t irq_emited; 106 atomic_t irq_emitted;
108 107
109 int tex_lru_log_granularity; 108 int tex_lru_log_granularity;
110 int allow_batchbuffer; 109 int allow_batchbuffer;
111 struct mem_block *agp_heap; 110 struct mem_block *agp_heap;
112 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 111 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
113 int vblank_pipe; 112 int vblank_pipe;
114 spinlock_t user_irq_lock;
115 int user_irq_refcount;
116 int fence_irq_on;
117 uint32_t irq_enable_reg;
118 int irq_enabled;
119 113
120 spinlock_t swaps_lock; 114 spinlock_t swaps_lock;
121 drm_i915_vbl_swap_t vbl_swaps; 115 drm_i915_vbl_swap_t vbl_swaps;
@@ -125,6 +119,7 @@ typedef struct drm_i915_private {
125 u8 saveLBB; 119 u8 saveLBB;
126 u32 saveDSPACNTR; 120 u32 saveDSPACNTR;
127 u32 saveDSPBCNTR; 121 u32 saveDSPBCNTR;
122 u32 saveDSPARB;
128 u32 savePIPEACONF; 123 u32 savePIPEACONF;
129 u32 savePIPEBCONF; 124 u32 savePIPEBCONF;
130 u32 savePIPEASRC; 125 u32 savePIPEASRC;
@@ -194,6 +189,7 @@ typedef struct drm_i915_private {
194 u32 saveIIR; 189 u32 saveIIR;
195 u32 saveIMR; 190 u32 saveIMR;
196 u32 saveCACHE_MODE_0; 191 u32 saveCACHE_MODE_0;
192 u32 saveD_STATE;
197 u32 saveDSPCLK_GATE_D; 193 u32 saveDSPCLK_GATE_D;
198 u32 saveMI_ARB_STATE; 194 u32 saveMI_ARB_STATE;
199 u32 saveSWF0[16]; 195 u32 saveSWF0[16];
@@ -203,10 +199,10 @@ typedef struct drm_i915_private {
203 u8 saveSR[8]; 199 u8 saveSR[8];
204 u8 saveGR[25]; 200 u8 saveGR[25];
205 u8 saveAR_INDEX; 201 u8 saveAR_INDEX;
206 u8 saveAR[20]; 202 u8 saveAR[21];
207 u8 saveDACMASK; 203 u8 saveDACMASK;
208 u8 saveDACDATA[256*3]; /* 256 3-byte colors */ 204 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
209 u8 saveCR[36]; 205 u8 saveCR[37];
210} drm_i915_private_t; 206} drm_i915_private_t;
211 207
212extern struct drm_ioctl_desc i915_ioctls[]; 208extern struct drm_ioctl_desc i915_ioctls[];
@@ -222,7 +218,7 @@ extern void i915_driver_preclose(struct drm_device *dev,
222extern int i915_driver_device_is_agp(struct drm_device * dev); 218extern int i915_driver_device_is_agp(struct drm_device * dev);
223extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 219extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
224 unsigned long arg); 220 unsigned long arg);
225extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync); 221
226/* i915_irq.c */ 222/* i915_irq.c */
227extern int i915_irq_emit(struct drm_device *dev, void *data, 223extern int i915_irq_emit(struct drm_device *dev, void *data,
228 struct drm_file *file_priv); 224 struct drm_file *file_priv);
@@ -233,7 +229,7 @@ extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequenc
233extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence); 229extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
234extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 230extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
235extern void i915_driver_irq_preinstall(struct drm_device * dev); 231extern void i915_driver_irq_preinstall(struct drm_device * dev);
236extern int i915_driver_irq_postinstall(struct drm_device * dev); 232extern void i915_driver_irq_postinstall(struct drm_device * dev);
237extern void i915_driver_irq_uninstall(struct drm_device * dev); 233extern void i915_driver_irq_uninstall(struct drm_device * dev);
238extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 234extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
239 struct drm_file *file_priv); 235 struct drm_file *file_priv);
@@ -241,9 +237,6 @@ extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
241 struct drm_file *file_priv); 237 struct drm_file *file_priv);
242extern int i915_vblank_swap(struct drm_device *dev, void *data, 238extern int i915_vblank_swap(struct drm_device *dev, void *data,
243 struct drm_file *file_priv); 239 struct drm_file *file_priv);
244extern int i915_enable_vblank(struct drm_device *dev, int crtc);
245extern void i915_disable_vblank(struct drm_device *dev, int crtc);
246extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
247 240
248/* i915_mem.c */ 241/* i915_mem.c */
249extern int i915_mem_alloc(struct drm_device *dev, void *data, 242extern int i915_mem_alloc(struct drm_device *dev, void *data,
@@ -388,91 +381,21 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
388 381
389/* Interrupt bits: 382/* Interrupt bits:
390 */ 383 */
391#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 384#define USER_INT_FLAG (1<<1)
392#define I915_DISPLAY_PORT_INTERRUPT (1<<17) 385#define VSYNC_PIPEB_FLAG (1<<5)
393#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 386#define VSYNC_PIPEA_FLAG (1<<7)
394#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) 387#define HWB_OOM_FLAG (1<<13) /* binner out of memory */
395#define I915_HWB_OOM_INTERRUPT (1<<13) /* binner out of memory */
396#define I915_SYNC_STATUS_INTERRUPT (1<<12)
397#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
398#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
399#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
400#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
401#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
402#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
403#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
404#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
405#define I915_DEBUG_INTERRUPT (1<<2)
406#define I915_USER_INTERRUPT (1<<1)
407
408 388
409#define I915REG_HWSTAM 0x02098 389#define I915REG_HWSTAM 0x02098
410#define I915REG_INT_IDENTITY_R 0x020a4 390#define I915REG_INT_IDENTITY_R 0x020a4
411#define I915REG_INT_MASK_R 0x020a8 391#define I915REG_INT_MASK_R 0x020a8
412#define I915REG_INT_ENABLE_R 0x020a0 392#define I915REG_INT_ENABLE_R 0x020a0
413#define I915REG_INSTPM 0x020c0
414
415#define PIPEADSL 0x70000
416#define PIPEBDSL 0x71000
417 393
418#define I915REG_PIPEASTAT 0x70024 394#define I915REG_PIPEASTAT 0x70024
419#define I915REG_PIPEBSTAT 0x71024 395#define I915REG_PIPEBSTAT 0x71024
420/*
421 * The two pipe frame counter registers are not synchronized, so
422 * reading a stable value is somewhat tricky. The following code
423 * should work:
424 *
425 * do {
426 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
427 * PIPE_FRAME_HIGH_SHIFT;
428 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
429 * PIPE_FRAME_LOW_SHIFT);
430 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
431 * PIPE_FRAME_HIGH_SHIFT);
432 * } while (high1 != high2);
433 * frame = (high1 << 8) | low1;
434 */
435#define PIPEAFRAMEHIGH 0x70040
436#define PIPEBFRAMEHIGH 0x71040
437#define PIPE_FRAME_HIGH_MASK 0x0000ffff
438#define PIPE_FRAME_HIGH_SHIFT 0
439#define PIPEAFRAMEPIXEL 0x70044
440#define PIPEBFRAMEPIXEL 0x71044
441 396
442#define PIPE_FRAME_LOW_MASK 0xff000000 397#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
443#define PIPE_FRAME_LOW_SHIFT 24 398#define I915_VBLANK_CLEAR (1UL<<1)
444/*
445 * Pixel within the current frame is counted in the PIPEAFRAMEPIXEL register
446 * and is 24 bits wide.
447 */
448#define PIPE_PIXEL_MASK 0x00ffffff
449#define PIPE_PIXEL_SHIFT 0
450
451#define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
452#define I915_CRC_ERROR_ENABLE (1UL<<29)
453#define I915_CRC_DONE_ENABLE (1UL<<28)
454#define I915_GMBUS_EVENT_ENABLE (1UL<<27)
455#define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
456#define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
457#define I915_DPST_EVENT_ENABLE (1UL<<23)
458#define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
459#define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
460#define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
461#define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
462#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
463#define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
464#define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
465#define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
466#define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
467#define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
468#define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
469#define I915_DPST_EVENT_STATUS (1UL<<7)
470#define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
471#define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
472#define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
473#define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
474#define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
475#define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
476 399
477#define SRX_INDEX 0x3c4 400#define SRX_INDEX 0x3c4
478#define SRX_DATA 0x3c5 401#define SRX_DATA 0x3c5
@@ -749,6 +672,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
749/** P1 value is 2 greater than this field */ 672/** P1 value is 2 greater than this field */
750# define VGA0_PD_P1_MASK (0x1f << 0) 673# define VGA0_PD_P1_MASK (0x1f << 0)
751 674
675/* PCI D state control register */
676#define D_STATE 0x6104
752#define DSPCLK_GATE_D 0x6200 677#define DSPCLK_GATE_D 0x6200
753 678
754/* I830 CRTC registers */ 679/* I830 CRTC registers */
@@ -1059,6 +984,12 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1059#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 984#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1060#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 985#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1061 986
987#define DSPARB 0x70030
988#define DSPARB_CSTART_MASK (0x7f << 7)
989#define DSPARB_CSTART_SHIFT 7
990#define DSPARB_BSTART_MASK (0x7f)
991#define DSPARB_BSTART_SHIFT 0
992
1062#define PIPEBCONF 0x71008 993#define PIPEBCONF 0x71008
1063#define PIPEBCONF_ENABLE (1<<31) 994#define PIPEBCONF_ENABLE (1<<31)
1064#define PIPEBCONF_DISABLE 0 995#define PIPEBCONF_DISABLE 0
@@ -1181,12 +1112,19 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1181 (dev)->pci_device == 0x29A2 || \ 1112 (dev)->pci_device == 0x29A2 || \
1182 (dev)->pci_device == 0x2A02 || \ 1113 (dev)->pci_device == 0x2A02 || \
1183 (dev)->pci_device == 0x2A12 || \ 1114 (dev)->pci_device == 0x2A12 || \
1184 (dev)->pci_device == 0x2A42) 1115 (dev)->pci_device == 0x2A42 || \
1116 (dev)->pci_device == 0x2E02 || \
1117 (dev)->pci_device == 0x2E12 || \
1118 (dev)->pci_device == 0x2E22)
1185 1119
1186#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 1120#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
1187 1121
1188#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42) 1122#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
1189 1123
1124#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
1125 (dev)->pci_device == 0x2E12 || \
1126 (dev)->pci_device == 0x2E22)
1127
1190#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 1128#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1191 (dev)->pci_device == 0x29B2 || \ 1129 (dev)->pci_device == 0x29B2 || \
1192 (dev)->pci_device == 0x29D2) 1130 (dev)->pci_device == 0x29D2)
@@ -1197,7 +1135,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1197#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 1135#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1198 IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev)) 1136 IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
1199 1137
1200#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev)) 1138#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))
1201 1139
1202#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1140#define PRIMARY_RINGBUFFER_SIZE (128*1024)
1203 1141
diff --git a/drivers/char/drm/i915_irq.c b/drivers/char/drm/i915_irq.c
index 023ce66ef3ab..df036118b8b1 100644
--- a/drivers/char/drm/i915_irq.c
+++ b/drivers/char/drm/i915_irq.c
@@ -38,109 +38,6 @@
38#define MAX_NOPID ((u32)~0) 38#define MAX_NOPID ((u32)~0)
39 39
40/** 40/**
41 * i915_get_pipe - return the the pipe associated with a given plane
42 * @dev: DRM device
43 * @plane: plane to look for
44 *
45 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
46 * rather than a pipe number, since they may not always be equal. This routine
47 * maps the given @plane back to a pipe number.
48 */
49static int
50i915_get_pipe(struct drm_device *dev, int plane)
51{
52 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
53 u32 dspcntr;
54
55 dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
56
57 return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
58}
59
60/**
61 * i915_get_plane - return the the plane associated with a given pipe
62 * @dev: DRM device
63 * @pipe: pipe to look for
64 *
65 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
66 * rather than a plane number, since they may not always be equal. This routine
67 * maps the given @pipe back to a plane number.
68 */
69static int
70i915_get_plane(struct drm_device *dev, int pipe)
71{
72 if (i915_get_pipe(dev, 0) == pipe)
73 return 0;
74 return 1;
75}
76
77/**
78 * i915_pipe_enabled - check if a pipe is enabled
79 * @dev: DRM device
80 * @pipe: pipe to check
81 *
82 * Reading certain registers when the pipe is disabled can hang the chip.
83 * Use this routine to make sure the PLL is running and the pipe is active
84 * before reading such registers if unsure.
85 */
86static int
87i915_pipe_enabled(struct drm_device *dev, int pipe)
88{
89 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
90 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
91
92 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
93 return 1;
94
95 return 0;
96}
97
98/**
99 * Emit a synchronous flip.
100 *
101 * This function must be called with the drawable spinlock held.
102 */
103static void
104i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
105 int plane)
106{
107 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
108 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
109 u16 x1, y1, x2, y2;
110 int pf_planes = 1 << plane;
111
112 /* If the window is visible on the other plane, we have to flip on that
113 * plane as well.
114 */
115 if (plane == 1) {
116 x1 = sarea_priv->planeA_x;
117 y1 = sarea_priv->planeA_y;
118 x2 = x1 + sarea_priv->planeA_w;
119 y2 = y1 + sarea_priv->planeA_h;
120 } else {
121 x1 = sarea_priv->planeB_x;
122 y1 = sarea_priv->planeB_y;
123 x2 = x1 + sarea_priv->planeB_w;
124 y2 = y1 + sarea_priv->planeB_h;
125 }
126
127 if (x2 > 0 && y2 > 0) {
128 int i, num_rects = drw->num_rects;
129 struct drm_clip_rect *rect = drw->rects;
130
131 for (i = 0; i < num_rects; i++)
132 if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||
133 rect[i].x2 <= x1 || rect[i].y2 <= y1)) {
134 pf_planes = 0x3;
135
136 break;
137 }
138 }
139
140 i915_dispatch_flip(dev, pf_planes, 1);
141}
142
143/**
144 * Emit blits for scheduled buffer swaps. 41 * Emit blits for scheduled buffer swaps.
145 * 42 *
146 * This function will be called with the HW lock held. 43 * This function will be called with the HW lock held.
@@ -148,59 +45,50 @@ i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
148static void i915_vblank_tasklet(struct drm_device *dev) 45static void i915_vblank_tasklet(struct drm_device *dev)
149{ 46{
150 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 47 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
48 unsigned long irqflags;
151 struct list_head *list, *tmp, hits, *hit; 49 struct list_head *list, *tmp, hits, *hit;
152 int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages; 50 int nhits, nrects, slice[2], upper[2], lower[2], i;
153 unsigned counter[2]; 51 unsigned counter[2] = { atomic_read(&dev->vbl_received),
52 atomic_read(&dev->vbl_received2) };
154 struct drm_drawable_info *drw; 53 struct drm_drawable_info *drw;
155 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; 54 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
156 u32 cpp = dev_priv->cpp, offsets[3]; 55 u32 cpp = dev_priv->cpp;
157 u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD | 56 u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
158 XY_SRC_COPY_BLT_WRITE_ALPHA | 57 XY_SRC_COPY_BLT_WRITE_ALPHA |
159 XY_SRC_COPY_BLT_WRITE_RGB) 58 XY_SRC_COPY_BLT_WRITE_RGB)
160 : XY_SRC_COPY_BLT_CMD; 59 : XY_SRC_COPY_BLT_CMD;
161 u32 src_pitch = sarea_priv->pitch * cpp; 60 u32 src_pitch = sarea_priv->pitch * cpp;
162 u32 dst_pitch = sarea_priv->pitch * cpp; 61 u32 dst_pitch = sarea_priv->pitch * cpp;
163 /* COPY rop (0xcc), map cpp to magic color depth constants */
164 u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24); 62 u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
165 RING_LOCALS; 63 RING_LOCALS;
166 64
167 if (sarea_priv->front_tiled) { 65 if (IS_I965G(dev) && sarea_priv->front_tiled) {
168 cmd |= XY_SRC_COPY_BLT_DST_TILED; 66 cmd |= XY_SRC_COPY_BLT_DST_TILED;
169 dst_pitch >>= 2; 67 dst_pitch >>= 2;
170 } 68 }
171 if (sarea_priv->back_tiled) { 69 if (IS_I965G(dev) && sarea_priv->back_tiled) {
172 cmd |= XY_SRC_COPY_BLT_SRC_TILED; 70 cmd |= XY_SRC_COPY_BLT_SRC_TILED;
173 src_pitch >>= 2; 71 src_pitch >>= 2;
174 } 72 }
175 73
176 counter[0] = drm_vblank_count(dev, 0);
177 counter[1] = drm_vblank_count(dev, 1);
178
179 DRM_DEBUG("\n"); 74 DRM_DEBUG("\n");
180 75
181 INIT_LIST_HEAD(&hits); 76 INIT_LIST_HEAD(&hits);
182 77
183 nhits = nrects = 0; 78 nhits = nrects = 0;
184 79
185 /* No irqsave/restore necessary. This tasklet may be run in an 80 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
186 * interrupt context or normal context, but we don't have to worry
187 * about getting interrupted by something acquiring the lock, because
188 * we are the interrupt context thing that acquires the lock.
189 */
190 spin_lock(&dev_priv->swaps_lock);
191 81
192 /* Find buffer swaps scheduled for this vertical blank */ 82 /* Find buffer swaps scheduled for this vertical blank */
193 list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) { 83 list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
194 drm_i915_vbl_swap_t *vbl_swap = 84 drm_i915_vbl_swap_t *vbl_swap =
195 list_entry(list, drm_i915_vbl_swap_t, head); 85 list_entry(list, drm_i915_vbl_swap_t, head);
196 int pipe = i915_get_pipe(dev, vbl_swap->plane);
197 86
198 if ((counter[pipe] - vbl_swap->sequence) > (1<<23)) 87 if ((counter[vbl_swap->pipe] - vbl_swap->sequence) > (1<<23))
199 continue; 88 continue;
200 89
201 list_del(list); 90 list_del(list);
202 dev_priv->swaps_pending--; 91 dev_priv->swaps_pending--;
203 drm_vblank_put(dev, pipe);
204 92
205 spin_unlock(&dev_priv->swaps_lock); 93 spin_unlock(&dev_priv->swaps_lock);
206 spin_lock(&dev->drw_lock); 94 spin_lock(&dev->drw_lock);
@@ -238,23 +126,43 @@ static void i915_vblank_tasklet(struct drm_device *dev)
238 spin_lock(&dev_priv->swaps_lock); 126 spin_lock(&dev_priv->swaps_lock);
239 } 127 }
240 128
241 spin_unlock(&dev_priv->swaps_lock); 129 if (nhits == 0) {
242 130 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
243 if (nhits == 0)
244 return; 131 return;
132 }
133
134 spin_unlock(&dev_priv->swaps_lock);
245 135
246 i915_kernel_lost_context(dev); 136 i915_kernel_lost_context(dev);
247 137
248 upper[0] = upper[1] = 0; 138 if (IS_I965G(dev)) {
249 slice[0] = max(sarea_priv->planeA_h / nhits, 1); 139 BEGIN_LP_RING(4);
250 slice[1] = max(sarea_priv->planeB_h / nhits, 1); 140
251 lower[0] = sarea_priv->planeA_y + slice[0]; 141 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
252 lower[1] = sarea_priv->planeB_y + slice[0]; 142 OUT_RING(0);
143 OUT_RING(((sarea_priv->width - 1) & 0xffff) | ((sarea_priv->height - 1) << 16));
144 OUT_RING(0);
145 ADVANCE_LP_RING();
146 } else {
147 BEGIN_LP_RING(6);
253 148
254 offsets[0] = sarea_priv->front_offset; 149 OUT_RING(GFX_OP_DRAWRECT_INFO);
255 offsets[1] = sarea_priv->back_offset; 150 OUT_RING(0);
256 offsets[2] = sarea_priv->third_offset; 151 OUT_RING(0);
257 num_pages = sarea_priv->third_handle ? 3 : 2; 152 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
153 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
154 OUT_RING(0);
155
156 ADVANCE_LP_RING();
157 }
158
159 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
160
161 upper[0] = upper[1] = 0;
162 slice[0] = max(sarea_priv->pipeA_h / nhits, 1);
163 slice[1] = max(sarea_priv->pipeB_h / nhits, 1);
164 lower[0] = sarea_priv->pipeA_y + slice[0];
165 lower[1] = sarea_priv->pipeB_y + slice[0];
258 166
259 spin_lock(&dev->drw_lock); 167 spin_lock(&dev->drw_lock);
260 168
@@ -266,8 +174,6 @@ static void i915_vblank_tasklet(struct drm_device *dev)
266 for (i = 0; i++ < nhits; 174 for (i = 0; i++ < nhits;
267 upper[0] = lower[0], lower[0] += slice[0], 175 upper[0] = lower[0], lower[0] += slice[0],
268 upper[1] = lower[1], lower[1] += slice[1]) { 176 upper[1] = lower[1], lower[1] += slice[1]) {
269 int init_drawrect = 1;
270
271 if (i == nhits) 177 if (i == nhits)
272 lower[0] = lower[1] = sarea_priv->height; 178 lower[0] = lower[1] = sarea_priv->height;
273 179
@@ -275,7 +181,7 @@ static void i915_vblank_tasklet(struct drm_device *dev)
275 drm_i915_vbl_swap_t *swap_hit = 181 drm_i915_vbl_swap_t *swap_hit =
276 list_entry(hit, drm_i915_vbl_swap_t, head); 182 list_entry(hit, drm_i915_vbl_swap_t, head);
277 struct drm_clip_rect *rect; 183 struct drm_clip_rect *rect;
278 int num_rects, plane, front, back; 184 int num_rects, pipe;
279 unsigned short top, bottom; 185 unsigned short top, bottom;
280 186
281 drw = drm_get_drawable_info(dev, swap_hit->drw_id); 187 drw = drm_get_drawable_info(dev, swap_hit->drw_id);
@@ -283,50 +189,10 @@ static void i915_vblank_tasklet(struct drm_device *dev)
283 if (!drw) 189 if (!drw)
284 continue; 190 continue;
285 191
286 plane = swap_hit->plane;
287
288 if (swap_hit->flip) {
289 i915_dispatch_vsync_flip(dev, drw, plane);
290 continue;
291 }
292
293 if (init_drawrect) {
294 int width = sarea_priv->width;
295 int height = sarea_priv->height;
296 if (IS_I965G(dev)) {
297 BEGIN_LP_RING(4);
298
299 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
300 OUT_RING(0);
301 OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
302 OUT_RING(0);
303
304 ADVANCE_LP_RING();
305 } else {
306 BEGIN_LP_RING(6);
307
308 OUT_RING(GFX_OP_DRAWRECT_INFO);
309 OUT_RING(0);
310 OUT_RING(0);
311 OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
312 OUT_RING(0);
313 OUT_RING(0);
314
315 ADVANCE_LP_RING();
316 }
317
318 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
319
320 init_drawrect = 0;
321 }
322
323 rect = drw->rects; 192 rect = drw->rects;
324 top = upper[plane]; 193 pipe = swap_hit->pipe;
325 bottom = lower[plane]; 194 top = upper[pipe];
326 195 bottom = lower[pipe];
327 front = (dev_priv->sarea_priv->pf_current_page >>
328 (2 * plane)) & 0x3;
329 back = (front + 1) % num_pages;
330 196
331 for (num_rects = drw->num_rects; num_rects--; rect++) { 197 for (num_rects = drw->num_rects; num_rects--; rect++) {
332 int y1 = max(rect->y1, top); 198 int y1 = max(rect->y1, top);
@@ -341,17 +207,17 @@ static void i915_vblank_tasklet(struct drm_device *dev)
341 OUT_RING(ropcpp | dst_pitch); 207 OUT_RING(ropcpp | dst_pitch);
342 OUT_RING((y1 << 16) | rect->x1); 208 OUT_RING((y1 << 16) | rect->x1);
343 OUT_RING((y2 << 16) | rect->x2); 209 OUT_RING((y2 << 16) | rect->x2);
344 OUT_RING(offsets[front]); 210 OUT_RING(sarea_priv->front_offset);
345 OUT_RING((y1 << 16) | rect->x1); 211 OUT_RING((y1 << 16) | rect->x1);
346 OUT_RING(src_pitch); 212 OUT_RING(src_pitch);
347 OUT_RING(offsets[back]); 213 OUT_RING(sarea_priv->back_offset);
348 214
349 ADVANCE_LP_RING(); 215 ADVANCE_LP_RING();
350 } 216 }
351 } 217 }
352 } 218 }
353 219
354 spin_unlock(&dev->drw_lock); 220 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
355 221
356 list_for_each_safe(hit, tmp, &hits) { 222 list_for_each_safe(hit, tmp, &hits) {
357 drm_i915_vbl_swap_t *swap_hit = 223 drm_i915_vbl_swap_t *swap_hit =
@@ -363,112 +229,67 @@ static void i915_vblank_tasklet(struct drm_device *dev)
363 } 229 }
364} 230}
365 231
366u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
367{
368 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
369 unsigned long high_frame;
370 unsigned long low_frame;
371 u32 high1, high2, low, count;
372 int pipe;
373
374 pipe = i915_get_pipe(dev, plane);
375 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
376 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
377
378 if (!i915_pipe_enabled(dev, pipe)) {
379 printk(KERN_ERR "trying to get vblank count for disabled "
380 "pipe %d\n", pipe);
381 return 0;
382 }
383
384 /*
385 * High & low register fields aren't synchronized, so make sure
386 * we get a low value that's stable across two reads of the high
387 * register.
388 */
389 do {
390 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
391 PIPE_FRAME_HIGH_SHIFT);
392 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
393 PIPE_FRAME_LOW_SHIFT);
394 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
395 PIPE_FRAME_HIGH_SHIFT);
396 } while (high1 != high2);
397
398 count = (high1 << 8) | low;
399
400 /* count may be reset by other driver(e.g. 2D driver),
401 we have no way to know if it is wrapped or resetted
402 when count is zero. do a rough guess.
403 */
404 if (count == 0 && dev->last_vblank[pipe] < dev->max_vblank_count/2)
405 dev->last_vblank[pipe] = 0;
406
407 return count;
408}
409
410irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 232irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
411{ 233{
412 struct drm_device *dev = (struct drm_device *) arg; 234 struct drm_device *dev = (struct drm_device *) arg;
413 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 235 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
414 u32 iir; 236 u16 temp;
415 u32 pipea_stats, pipeb_stats; 237 u32 pipea_stats, pipeb_stats;
416 int vblank = 0;
417
418 iir = I915_READ(I915REG_INT_IDENTITY_R);
419 if (iir == 0) {
420 DRM_DEBUG ("iir 0x%08x im 0x%08x ie 0x%08x pipea 0x%08x pipeb 0x%08x\n",
421 iir,
422 I915_READ(I915REG_INT_MASK_R),
423 I915_READ(I915REG_INT_ENABLE_R),
424 I915_READ(I915REG_PIPEASTAT),
425 I915_READ(I915REG_PIPEBSTAT));
426 return IRQ_NONE;
427 }
428 238
429 /* 239 pipea_stats = I915_READ(I915REG_PIPEASTAT);
430 * Clear the PIPE(A|B)STAT regs before the IIR otherwise 240 pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
431 * we may get extra interrupts.
432 */
433 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
434 pipea_stats = I915_READ(I915REG_PIPEASTAT);
435 if (pipea_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
436 I915_VBLANK_INTERRUPT_STATUS))
437 {
438 vblank++;
439 drm_handle_vblank(dev, i915_get_plane(dev, 0));
440 }
441 I915_WRITE(I915REG_PIPEASTAT, pipea_stats);
442 }
443 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
444 pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
445 if (pipeb_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
446 I915_VBLANK_INTERRUPT_STATUS))
447 {
448 vblank++;
449 drm_handle_vblank(dev, i915_get_plane(dev, 1));
450 }
451 I915_WRITE(I915REG_PIPEBSTAT, pipeb_stats);
452 }
453 241
454 if (dev_priv->sarea_priv) 242 temp = I915_READ16(I915REG_INT_IDENTITY_R);
455 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
456 243
457 I915_WRITE(I915REG_INT_IDENTITY_R, iir); 244 temp &= (USER_INT_FLAG | VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG);
458 (void) I915_READ(I915REG_INT_IDENTITY_R); /* Flush posted write */
459 245
460 if (iir & I915_USER_INTERRUPT) { 246 DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
247
248 if (temp == 0)
249 return IRQ_NONE;
250
251 I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
252 (void) I915_READ16(I915REG_INT_IDENTITY_R);
253 DRM_READMEMORYBARRIER();
254
255 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
256
257 if (temp & USER_INT_FLAG)
461 DRM_WAKEUP(&dev_priv->irq_queue); 258 DRM_WAKEUP(&dev_priv->irq_queue);
462 } 259
463 if (vblank) { 260 if (temp & (VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG)) {
261 int vblank_pipe = dev_priv->vblank_pipe;
262
263 if ((vblank_pipe &
264 (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B))
265 == (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) {
266 if (temp & VSYNC_PIPEA_FLAG)
267 atomic_inc(&dev->vbl_received);
268 if (temp & VSYNC_PIPEB_FLAG)
269 atomic_inc(&dev->vbl_received2);
270 } else if (((temp & VSYNC_PIPEA_FLAG) &&
271 (vblank_pipe & DRM_I915_VBLANK_PIPE_A)) ||
272 ((temp & VSYNC_PIPEB_FLAG) &&
273 (vblank_pipe & DRM_I915_VBLANK_PIPE_B)))
274 atomic_inc(&dev->vbl_received);
275
276 DRM_WAKEUP(&dev->vbl_queue);
277 drm_vbl_send_signals(dev);
278
464 if (dev_priv->swaps_pending > 0) 279 if (dev_priv->swaps_pending > 0)
465 drm_locked_tasklet(dev, i915_vblank_tasklet); 280 drm_locked_tasklet(dev, i915_vblank_tasklet);
281 I915_WRITE(I915REG_PIPEASTAT,
282 pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
283 I915_VBLANK_CLEAR);
284 I915_WRITE(I915REG_PIPEBSTAT,
285 pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
286 I915_VBLANK_CLEAR);
466 } 287 }
467 288
468 return IRQ_HANDLED; 289 return IRQ_HANDLED;
469} 290}
470 291
471static int i915_emit_irq(struct drm_device *dev) 292static int i915_emit_irq(struct drm_device * dev)
472{ 293{
473 drm_i915_private_t *dev_priv = dev->dev_private; 294 drm_i915_private_t *dev_priv = dev->dev_private;
474 RING_LOCALS; 295 RING_LOCALS;
@@ -515,12 +336,42 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
515 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); 336 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
516 } 337 }
517 338
518 if (dev_priv->sarea_priv) 339 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
519 dev_priv->sarea_priv->last_dispatch =
520 READ_BREADCRUMB(dev_priv);
521 return ret; 340 return ret;
522} 341}
523 342
343static int i915_driver_vblank_do_wait(struct drm_device *dev, unsigned int *sequence,
344 atomic_t *counter)
345{
346 drm_i915_private_t *dev_priv = dev->dev_private;
347 unsigned int cur_vblank;
348 int ret = 0;
349
350 if (!dev_priv) {
351 DRM_ERROR("called with no initialization\n");
352 return -EINVAL;
353 }
354
355 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
356 (((cur_vblank = atomic_read(counter))
357 - *sequence) <= (1<<23)));
358
359 *sequence = cur_vblank;
360
361 return ret;
362}
363
364
365int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
366{
367 return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received);
368}
369
370int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
371{
372 return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received2);
373}
374
524/* Needs the lock as it touches the ring. 375/* Needs the lock as it touches the ring.
525 */ 376 */
526int i915_irq_emit(struct drm_device *dev, void *data, 377int i915_irq_emit(struct drm_device *dev, void *data,
@@ -563,96 +414,18 @@ int i915_irq_wait(struct drm_device *dev, void *data,
563 return i915_wait_irq(dev, irqwait->irq_seq); 414 return i915_wait_irq(dev, irqwait->irq_seq);
564} 415}
565 416
566int i915_enable_vblank(struct drm_device *dev, int plane)
567{
568 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
569 int pipe = i915_get_pipe(dev, plane);
570 u32 pipestat_reg = 0;
571 u32 pipestat;
572
573 switch (pipe) {
574 case 0:
575 pipestat_reg = I915REG_PIPEASTAT;
576 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
577 break;
578 case 1:
579 pipestat_reg = I915REG_PIPEBSTAT;
580 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
581 break;
582 default:
583 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
584 pipe);
585 break;
586 }
587
588 if (pipestat_reg)
589 {
590 pipestat = I915_READ (pipestat_reg);
591 /*
592 * Older chips didn't have the start vblank interrupt,
593 * but
594 */
595 if (IS_I965G (dev))
596 pipestat |= I915_START_VBLANK_INTERRUPT_ENABLE;
597 else
598 pipestat |= I915_VBLANK_INTERRUPT_ENABLE;
599 /*
600 * Clear any pending status
601 */
602 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
603 I915_VBLANK_INTERRUPT_STATUS);
604 I915_WRITE(pipestat_reg, pipestat);
605 }
606 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
607
608 return 0;
609}
610
611void i915_disable_vblank(struct drm_device *dev, int plane)
612{
613 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
614 int pipe = i915_get_pipe(dev, plane);
615 u32 pipestat_reg = 0;
616 u32 pipestat;
617
618 switch (pipe) {
619 case 0:
620 pipestat_reg = I915REG_PIPEASTAT;
621 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
622 break;
623 case 1:
624 pipestat_reg = I915REG_PIPEBSTAT;
625 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
626 break;
627 default:
628 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
629 pipe);
630 break;
631 }
632
633 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
634 if (pipestat_reg)
635 {
636 pipestat = I915_READ (pipestat_reg);
637 pipestat &= ~(I915_START_VBLANK_INTERRUPT_ENABLE |
638 I915_VBLANK_INTERRUPT_ENABLE);
639 /*
640 * Clear any pending status
641 */
642 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
643 I915_VBLANK_INTERRUPT_STATUS);
644 I915_WRITE(pipestat_reg, pipestat);
645 }
646}
647
648static void i915_enable_interrupt (struct drm_device *dev) 417static void i915_enable_interrupt (struct drm_device *dev)
649{ 418{
650 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 419 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
420 u16 flag;
651 421
652 dev_priv->irq_enable_reg |= I915_USER_INTERRUPT; 422 flag = 0;
423 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
424 flag |= VSYNC_PIPEA_FLAG;
425 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
426 flag |= VSYNC_PIPEB_FLAG;
653 427
654 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg); 428 I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG | flag);
655 dev_priv->irq_enabled = 1;
656} 429}
657 430
658/* Set the vblank monitor pipe 431/* Set the vblank monitor pipe
@@ -675,6 +448,8 @@ int i915_vblank_pipe_set(struct drm_device *dev, void *data,
675 448
676 dev_priv->vblank_pipe = pipe->pipe; 449 dev_priv->vblank_pipe = pipe->pipe;
677 450
451 i915_enable_interrupt (dev);
452
678 return 0; 453 return 0;
679} 454}
680 455
@@ -692,9 +467,9 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data,
692 467
693 flag = I915_READ(I915REG_INT_ENABLE_R); 468 flag = I915_READ(I915REG_INT_ENABLE_R);
694 pipe->pipe = 0; 469 pipe->pipe = 0;
695 if (flag & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) 470 if (flag & VSYNC_PIPEA_FLAG)
696 pipe->pipe |= DRM_I915_VBLANK_PIPE_A; 471 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
697 if (flag & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) 472 if (flag & VSYNC_PIPEB_FLAG)
698 pipe->pipe |= DRM_I915_VBLANK_PIPE_B; 473 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
699 474
700 return 0; 475 return 0;
@@ -709,30 +484,27 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
709 drm_i915_private_t *dev_priv = dev->dev_private; 484 drm_i915_private_t *dev_priv = dev->dev_private;
710 drm_i915_vblank_swap_t *swap = data; 485 drm_i915_vblank_swap_t *swap = data;
711 drm_i915_vbl_swap_t *vbl_swap; 486 drm_i915_vbl_swap_t *vbl_swap;
712 unsigned int pipe, seqtype, curseq, plane; 487 unsigned int pipe, seqtype, curseq;
713 unsigned long irqflags; 488 unsigned long irqflags;
714 struct list_head *list; 489 struct list_head *list;
715 int ret;
716 490
717 if (!dev_priv) { 491 if (!dev_priv) {
718 DRM_ERROR("%s called with no initialization\n", __func__); 492 DRM_ERROR("%s called with no initialization\n", __func__);
719 return -EINVAL; 493 return -EINVAL;
720 } 494 }
721 495
722 if (!dev_priv->sarea_priv || dev_priv->sarea_priv->rotation) { 496 if (dev_priv->sarea_priv->rotation) {
723 DRM_DEBUG("Rotation not supported\n"); 497 DRM_DEBUG("Rotation not supported\n");
724 return -EINVAL; 498 return -EINVAL;
725 } 499 }
726 500
727 if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE | 501 if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
728 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS | 502 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)) {
729 _DRM_VBLANK_FLIP)) {
730 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype); 503 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
731 return -EINVAL; 504 return -EINVAL;
732 } 505 }
733 506
734 plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0; 507 pipe = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
735 pipe = i915_get_pipe(dev, plane);
736 508
737 seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE); 509 seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
738 510
@@ -743,11 +515,6 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
743 515
744 spin_lock_irqsave(&dev->drw_lock, irqflags); 516 spin_lock_irqsave(&dev->drw_lock, irqflags);
745 517
746 /* It makes no sense to schedule a swap for a drawable that doesn't have
747 * valid information at this point. E.g. this could mean that the X
748 * server is too old to push drawable information to the DRM, in which
749 * case all such swaps would become ineffective.
750 */
751 if (!drm_get_drawable_info(dev, swap->drawable)) { 518 if (!drm_get_drawable_info(dev, swap->drawable)) {
752 spin_unlock_irqrestore(&dev->drw_lock, irqflags); 519 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
753 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable); 520 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
@@ -756,8 +523,7 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
756 523
757 spin_unlock_irqrestore(&dev->drw_lock, irqflags); 524 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
758 525
759 drm_update_vblank_count(dev, pipe); 526 curseq = atomic_read(pipe ? &dev->vbl_received2 : &dev->vbl_received);
760 curseq = drm_vblank_count(dev, pipe);
761 527
762 if (seqtype == _DRM_VBLANK_RELATIVE) 528 if (seqtype == _DRM_VBLANK_RELATIVE)
763 swap->sequence += curseq; 529 swap->sequence += curseq;
@@ -771,43 +537,14 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
771 } 537 }
772 } 538 }
773 539
774 if (swap->seqtype & _DRM_VBLANK_FLIP) {
775 swap->sequence--;
776
777 if ((curseq - swap->sequence) <= (1<<23)) {
778 struct drm_drawable_info *drw;
779
780 LOCK_TEST_WITH_RETURN(dev, file_priv);
781
782 spin_lock_irqsave(&dev->drw_lock, irqflags);
783
784 drw = drm_get_drawable_info(dev, swap->drawable);
785
786 if (!drw) {
787 spin_unlock_irqrestore(&dev->drw_lock,
788 irqflags);
789 DRM_DEBUG("Invalid drawable ID %d\n",
790 swap->drawable);
791 return -EINVAL;
792 }
793
794 i915_dispatch_vsync_flip(dev, drw, plane);
795
796 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
797
798 return 0;
799 }
800 }
801
802 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); 540 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
803 541
804 list_for_each(list, &dev_priv->vbl_swaps.head) { 542 list_for_each(list, &dev_priv->vbl_swaps.head) {
805 vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head); 543 vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
806 544
807 if (vbl_swap->drw_id == swap->drawable && 545 if (vbl_swap->drw_id == swap->drawable &&
808 vbl_swap->plane == plane && 546 vbl_swap->pipe == pipe &&
809 vbl_swap->sequence == swap->sequence) { 547 vbl_swap->sequence == swap->sequence) {
810 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
811 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); 548 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
812 DRM_DEBUG("Already scheduled\n"); 549 DRM_DEBUG("Already scheduled\n");
813 return 0; 550 return 0;
@@ -830,19 +567,9 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
830 567
831 DRM_DEBUG("\n"); 568 DRM_DEBUG("\n");
832 569
833 ret = drm_vblank_get(dev, pipe);
834 if (ret) {
835 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
836 return ret;
837 }
838
839 vbl_swap->drw_id = swap->drawable; 570 vbl_swap->drw_id = swap->drawable;
840 vbl_swap->plane = plane; 571 vbl_swap->pipe = pipe;
841 vbl_swap->sequence = swap->sequence; 572 vbl_swap->sequence = swap->sequence;
842 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
843
844 if (vbl_swap->flip)
845 swap->sequence++;
846 573
847 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); 574 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
848 575
@@ -860,57 +587,37 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
860{ 587{
861 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 588 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
862 589
863 I915_WRITE16(I915REG_HWSTAM, 0xeffe); 590 I915_WRITE16(I915REG_HWSTAM, 0xfffe);
864 I915_WRITE16(I915REG_INT_MASK_R, 0x0); 591 I915_WRITE16(I915REG_INT_MASK_R, 0x0);
865 I915_WRITE16(I915REG_INT_ENABLE_R, 0x0); 592 I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
866} 593}
867 594
868int i915_driver_irq_postinstall(struct drm_device * dev) 595void i915_driver_irq_postinstall(struct drm_device * dev)
869{ 596{
870 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 597 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
871 int ret, num_pipes = 2;
872 598
873 spin_lock_init(&dev_priv->swaps_lock); 599 spin_lock_init(&dev_priv->swaps_lock);
874 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head); 600 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
875 dev_priv->swaps_pending = 0; 601 dev_priv->swaps_pending = 0;
876 602
877 dev_priv->user_irq_refcount = 0; 603 if (!dev_priv->vblank_pipe)
878 dev_priv->irq_enable_reg = 0; 604 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
879
880 ret = drm_vblank_init(dev, num_pipes);
881 if (ret)
882 return ret;
883
884 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
885
886 i915_enable_interrupt(dev); 605 i915_enable_interrupt(dev);
887 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); 606 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
888
889 /*
890 * Initialize the hardware status page IRQ location.
891 */
892
893 I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));
894 return 0;
895} 607}
896 608
897void i915_driver_irq_uninstall(struct drm_device * dev) 609void i915_driver_irq_uninstall(struct drm_device * dev)
898{ 610{
899 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 611 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
900 u32 temp; 612 u16 temp;
901 613
902 if (!dev_priv) 614 if (!dev_priv)
903 return; 615 return;
904 616
905 dev_priv->irq_enabled = 0; 617 I915_WRITE16(I915REG_HWSTAM, 0xffff);
906 I915_WRITE(I915REG_HWSTAM, 0xffffffff); 618 I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
907 I915_WRITE(I915REG_INT_MASK_R, 0xffffffff); 619 I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
908 I915_WRITE(I915REG_INT_ENABLE_R, 0x0); 620
909 621 temp = I915_READ16(I915REG_INT_IDENTITY_R);
910 temp = I915_READ(I915REG_PIPEASTAT); 622 I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
911 I915_WRITE(I915REG_PIPEASTAT, temp);
912 temp = I915_READ(I915REG_PIPEBSTAT);
913 I915_WRITE(I915REG_PIPEBSTAT, temp);
914 temp = I915_READ(I915REG_INT_IDENTITY_R);
915 I915_WRITE(I915REG_INT_IDENTITY_R, temp);
916} 623}
diff --git a/drivers/char/drm/mga_drv.c b/drivers/char/drm/mga_drv.c
index 6b3790939e76..5572939fc7d1 100644
--- a/drivers/char/drm/mga_drv.c
+++ b/drivers/char/drm/mga_drv.c
@@ -45,16 +45,15 @@ static struct pci_device_id pciidlist[] = {
45static struct drm_driver driver = { 45static struct drm_driver driver = {
46 .driver_features = 46 .driver_features =
47 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | 47 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA |
48 DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED, 48 DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
49 DRIVER_IRQ_VBL,
49 .dev_priv_size = sizeof(drm_mga_buf_priv_t), 50 .dev_priv_size = sizeof(drm_mga_buf_priv_t),
50 .load = mga_driver_load, 51 .load = mga_driver_load,
51 .unload = mga_driver_unload, 52 .unload = mga_driver_unload,
52 .lastclose = mga_driver_lastclose, 53 .lastclose = mga_driver_lastclose,
53 .dma_quiescent = mga_driver_dma_quiescent, 54 .dma_quiescent = mga_driver_dma_quiescent,
54 .device_is_agp = mga_driver_device_is_agp, 55 .device_is_agp = mga_driver_device_is_agp,
55 .get_vblank_counter = mga_get_vblank_counter, 56 .vblank_wait = mga_driver_vblank_wait,
56 .enable_vblank = mga_enable_vblank,
57 .disable_vblank = mga_disable_vblank,
58 .irq_preinstall = mga_driver_irq_preinstall, 57 .irq_preinstall = mga_driver_irq_preinstall,
59 .irq_postinstall = mga_driver_irq_postinstall, 58 .irq_postinstall = mga_driver_irq_postinstall,
60 .irq_uninstall = mga_driver_irq_uninstall, 59 .irq_uninstall = mga_driver_irq_uninstall,
diff --git a/drivers/char/drm/mga_drv.h b/drivers/char/drm/mga_drv.h
index 8f7291f36363..f6ebd24bd587 100644
--- a/drivers/char/drm/mga_drv.h
+++ b/drivers/char/drm/mga_drv.h
@@ -120,7 +120,6 @@ typedef struct drm_mga_private {
120 u32 clear_cmd; 120 u32 clear_cmd;
121 u32 maccess; 121 u32 maccess;
122 122
123 atomic_t vbl_received; /**< Number of vblanks received. */
124 wait_queue_head_t fence_queue; 123 wait_queue_head_t fence_queue;
125 atomic_t last_fence_retired; 124 atomic_t last_fence_retired;
126 u32 next_fence_to_post; 125 u32 next_fence_to_post;
@@ -182,14 +181,11 @@ extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv);
182extern int mga_warp_init(drm_mga_private_t * dev_priv); 181extern int mga_warp_init(drm_mga_private_t * dev_priv);
183 182
184 /* mga_irq.c */ 183 /* mga_irq.c */
185extern int mga_enable_vblank(struct drm_device *dev, int crtc);
186extern void mga_disable_vblank(struct drm_device *dev, int crtc);
187extern u32 mga_get_vblank_counter(struct drm_device *dev, int crtc);
188extern int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence); 184extern int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence);
189extern int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence); 185extern int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence);
190extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS); 186extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS);
191extern void mga_driver_irq_preinstall(struct drm_device * dev); 187extern void mga_driver_irq_preinstall(struct drm_device * dev);
192extern int mga_driver_irq_postinstall(struct drm_device * dev); 188extern void mga_driver_irq_postinstall(struct drm_device * dev);
193extern void mga_driver_irq_uninstall(struct drm_device * dev); 189extern void mga_driver_irq_uninstall(struct drm_device * dev);
194extern long mga_compat_ioctl(struct file *filp, unsigned int cmd, 190extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
195 unsigned long arg); 191 unsigned long arg);
diff --git a/drivers/char/drm/mga_irq.c b/drivers/char/drm/mga_irq.c
index 06852fb4b278..9302cb8f0f83 100644
--- a/drivers/char/drm/mga_irq.c
+++ b/drivers/char/drm/mga_irq.c
@@ -35,20 +35,6 @@
35#include "mga_drm.h" 35#include "mga_drm.h"
36#include "mga_drv.h" 36#include "mga_drv.h"
37 37
38u32 mga_get_vblank_counter(struct drm_device *dev, int crtc)
39{
40 const drm_mga_private_t *const dev_priv =
41 (drm_mga_private_t *) dev->dev_private;
42
43 if (crtc != 0) {
44 return 0;
45 }
46
47
48 return atomic_read(&dev_priv->vbl_received);
49}
50
51
52irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS) 38irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS)
53{ 39{
54 struct drm_device *dev = (struct drm_device *) arg; 40 struct drm_device *dev = (struct drm_device *) arg;
@@ -61,8 +47,9 @@ irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS)
61 /* VBLANK interrupt */ 47 /* VBLANK interrupt */
62 if (status & MGA_VLINEPEN) { 48 if (status & MGA_VLINEPEN) {
63 MGA_WRITE(MGA_ICLEAR, MGA_VLINEICLR); 49 MGA_WRITE(MGA_ICLEAR, MGA_VLINEICLR);
64 atomic_inc(&dev_priv->vbl_received); 50 atomic_inc(&dev->vbl_received);
65 drm_handle_vblank(dev, 0); 51 DRM_WAKEUP(&dev->vbl_queue);
52 drm_vbl_send_signals(dev);
66 handled = 1; 53 handled = 1;
67 } 54 }
68 55
@@ -91,34 +78,22 @@ irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS)
91 return IRQ_NONE; 78 return IRQ_NONE;
92} 79}
93 80
94int mga_enable_vblank(struct drm_device *dev, int crtc) 81int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence)
95{ 82{
96 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; 83 unsigned int cur_vblank;
97 84 int ret = 0;
98 if (crtc != 0) {
99 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
100 crtc);
101 return 0;
102 }
103
104 MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN);
105 return 0;
106}
107 85
86 /* Assume that the user has missed the current sequence number
87 * by about a day rather than she wants to wait for years
88 * using vertical blanks...
89 */
90 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
91 (((cur_vblank = atomic_read(&dev->vbl_received))
92 - *sequence) <= (1 << 23)));
108 93
109void mga_disable_vblank(struct drm_device *dev, int crtc) 94 *sequence = cur_vblank;
110{
111 if (crtc != 0) {
112 DRM_ERROR("tried to disable vblank on non-existent crtc %d\n",
113 crtc);
114 }
115 95
116 /* Do *NOT* disable the vertical refresh interrupt. MGA doesn't have 96 return ret;
117 * a nice hardware counter that tracks the number of refreshes when
118 * the interrupt is disabled, and the kernel doesn't know the refresh
119 * rate to calculate an estimate.
120 */
121 /* MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN); */
122} 97}
123 98
124int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence) 99int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence)
@@ -150,22 +125,14 @@ void mga_driver_irq_preinstall(struct drm_device * dev)
150 MGA_WRITE(MGA_ICLEAR, ~0); 125 MGA_WRITE(MGA_ICLEAR, ~0);
151} 126}
152 127
153int mga_driver_irq_postinstall(struct drm_device * dev) 128void mga_driver_irq_postinstall(struct drm_device * dev)
154{ 129{
155 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; 130 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
156 int ret;
157
158 ret = drm_vblank_init(dev, 1);
159 if (ret)
160 return ret;
161 131
162 DRM_INIT_WAITQUEUE(&dev_priv->fence_queue); 132 DRM_INIT_WAITQUEUE(&dev_priv->fence_queue);
163 133
164 /* Turn on soft trap interrupt. Vertical blank interrupts are enabled 134 /* Turn on vertical blank interrupt and soft trap interrupt. */
165 * in mga_enable_vblank. 135 MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN);
166 */
167 MGA_WRITE(MGA_IEN, MGA_SOFTRAPEN);
168 return 0;
169} 136}
170 137
171void mga_driver_irq_uninstall(struct drm_device * dev) 138void mga_driver_irq_uninstall(struct drm_device * dev)
diff --git a/drivers/char/drm/r128_drv.c b/drivers/char/drm/r128_drv.c
index 2888aa01ebc7..6108e7587e12 100644
--- a/drivers/char/drm/r128_drv.c
+++ b/drivers/char/drm/r128_drv.c
@@ -43,13 +43,12 @@ static struct pci_device_id pciidlist[] = {
43static struct drm_driver driver = { 43static struct drm_driver driver = {
44 .driver_features = 44 .driver_features =
45 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | 45 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
46 DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED, 46 DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
47 DRIVER_IRQ_VBL,
47 .dev_priv_size = sizeof(drm_r128_buf_priv_t), 48 .dev_priv_size = sizeof(drm_r128_buf_priv_t),
48 .preclose = r128_driver_preclose, 49 .preclose = r128_driver_preclose,
49 .lastclose = r128_driver_lastclose, 50 .lastclose = r128_driver_lastclose,
50 .get_vblank_counter = r128_get_vblank_counter, 51 .vblank_wait = r128_driver_vblank_wait,
51 .enable_vblank = r128_enable_vblank,
52 .disable_vblank = r128_disable_vblank,
53 .irq_preinstall = r128_driver_irq_preinstall, 52 .irq_preinstall = r128_driver_irq_preinstall,
54 .irq_postinstall = r128_driver_irq_postinstall, 53 .irq_postinstall = r128_driver_irq_postinstall,
55 .irq_uninstall = r128_driver_irq_uninstall, 54 .irq_uninstall = r128_driver_irq_uninstall,
diff --git a/drivers/char/drm/r128_drv.h b/drivers/char/drm/r128_drv.h
index 80af9e09e75d..011105e51ac6 100644
--- a/drivers/char/drm/r128_drv.h
+++ b/drivers/char/drm/r128_drv.h
@@ -97,8 +97,6 @@ typedef struct drm_r128_private {
97 u32 crtc_offset; 97 u32 crtc_offset;
98 u32 crtc_offset_cntl; 98 u32 crtc_offset_cntl;
99 99
100 atomic_t vbl_received;
101
102 u32 color_fmt; 100 u32 color_fmt;
103 unsigned int front_offset; 101 unsigned int front_offset;
104 unsigned int front_pitch; 102 unsigned int front_pitch;
@@ -151,12 +149,11 @@ extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n);
151extern int r128_do_cce_idle(drm_r128_private_t * dev_priv); 149extern int r128_do_cce_idle(drm_r128_private_t * dev_priv);
152extern int r128_do_cleanup_cce(struct drm_device * dev); 150extern int r128_do_cleanup_cce(struct drm_device * dev);
153 151
154extern int r128_enable_vblank(struct drm_device *dev, int crtc); 152extern int r128_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence);
155extern void r128_disable_vblank(struct drm_device *dev, int crtc); 153
156extern u32 r128_get_vblank_counter(struct drm_device *dev, int crtc);
157extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS); 154extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS);
158extern void r128_driver_irq_preinstall(struct drm_device * dev); 155extern void r128_driver_irq_preinstall(struct drm_device * dev);
159extern int r128_driver_irq_postinstall(struct drm_device * dev); 156extern void r128_driver_irq_postinstall(struct drm_device * dev);
160extern void r128_driver_irq_uninstall(struct drm_device * dev); 157extern void r128_driver_irq_uninstall(struct drm_device * dev);
161extern void r128_driver_lastclose(struct drm_device * dev); 158extern void r128_driver_lastclose(struct drm_device * dev);
162extern void r128_driver_preclose(struct drm_device * dev, 159extern void r128_driver_preclose(struct drm_device * dev,
diff --git a/drivers/char/drm/r128_irq.c b/drivers/char/drm/r128_irq.c
index 5b95bd898f95..c76fdca7662d 100644
--- a/drivers/char/drm/r128_irq.c
+++ b/drivers/char/drm/r128_irq.c
@@ -35,16 +35,6 @@
35#include "r128_drm.h" 35#include "r128_drm.h"
36#include "r128_drv.h" 36#include "r128_drv.h"
37 37
38u32 r128_get_vblank_counter(struct drm_device *dev, int crtc)
39{
40 const drm_r128_private_t *dev_priv = dev->dev_private;
41
42 if (crtc != 0)
43 return 0;
44
45 return atomic_read(&dev_priv->vbl_received);
46}
47
48irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS) 38irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS)
49{ 39{
50 struct drm_device *dev = (struct drm_device *) arg; 40 struct drm_device *dev = (struct drm_device *) arg;
@@ -56,38 +46,30 @@ irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS)
56 /* VBLANK interrupt */ 46 /* VBLANK interrupt */
57 if (status & R128_CRTC_VBLANK_INT) { 47 if (status & R128_CRTC_VBLANK_INT) {
58 R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK); 48 R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
59 atomic_inc(&dev_priv->vbl_received); 49 atomic_inc(&dev->vbl_received);
60 drm_handle_vblank(dev, 0); 50 DRM_WAKEUP(&dev->vbl_queue);
51 drm_vbl_send_signals(dev);
61 return IRQ_HANDLED; 52 return IRQ_HANDLED;
62 } 53 }
63 return IRQ_NONE; 54 return IRQ_NONE;
64} 55}
65 56
66int r128_enable_vblank(struct drm_device *dev, int crtc) 57int r128_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence)
67{ 58{
68 drm_r128_private_t *dev_priv = dev->dev_private; 59 unsigned int cur_vblank;
69 60 int ret = 0;
70 if (crtc != 0) {
71 DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc);
72 return -EINVAL;
73 }
74 61
75 R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN); 62 /* Assume that the user has missed the current sequence number
76 return 0; 63 * by about a day rather than she wants to wait for years
77} 64 * using vertical blanks...
65 */
66 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
67 (((cur_vblank = atomic_read(&dev->vbl_received))
68 - *sequence) <= (1 << 23)));
78 69
79void r128_disable_vblank(struct drm_device *dev, int crtc) 70 *sequence = cur_vblank;
80{
81 if (crtc != 0)
82 DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc);
83 71
84 /* 72 return ret;
85 * FIXME: implement proper interrupt disable by using the vblank
86 * counter register (if available)
87 *
88 * R128_WRITE(R128_GEN_INT_CNTL,
89 * R128_READ(R128_GEN_INT_CNTL) & ~R128_CRTC_VBLANK_INT_EN);
90 */
91} 73}
92 74
93void r128_driver_irq_preinstall(struct drm_device * dev) 75void r128_driver_irq_preinstall(struct drm_device * dev)
@@ -100,9 +82,12 @@ void r128_driver_irq_preinstall(struct drm_device * dev)
100 R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK); 82 R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
101} 83}
102 84
103int r128_driver_irq_postinstall(struct drm_device * dev) 85void r128_driver_irq_postinstall(struct drm_device * dev)
104{ 86{
105 return drm_vblank_init(dev, 1); 87 drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
88
89 /* Turn on VBL interrupt */
90 R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN);
106} 91}
107 92
108void r128_driver_irq_uninstall(struct drm_device * dev) 93void r128_driver_irq_uninstall(struct drm_device * dev)
diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c
index f535812e4057..702df45320f7 100644
--- a/drivers/char/drm/r300_cmdbuf.c
+++ b/drivers/char/drm/r300_cmdbuf.c
@@ -189,18 +189,12 @@ void r300_init_reg_flags(struct drm_device *dev)
189 ADD_RANGE(R300_RE_CULL_CNTL, 1); 189 ADD_RANGE(R300_RE_CULL_CNTL, 1);
190 ADD_RANGE(0x42C0, 2); 190 ADD_RANGE(0x42C0, 2);
191 ADD_RANGE(R300_RS_CNTL_0, 2); 191 ADD_RANGE(R300_RS_CNTL_0, 2);
192 ADD_RANGE(R300_RS_INTERP_0, 8); 192
193 ADD_RANGE(R300_RS_ROUTE_0, 8); 193 ADD_RANGE(R300_SC_HYPERZ, 2);
194 ADD_RANGE(0x43A4, 2);
195 ADD_RANGE(0x43E8, 1); 194 ADD_RANGE(0x43E8, 1);
196 ADD_RANGE(R300_PFS_CNTL_0, 3); 195
197 ADD_RANGE(R300_PFS_NODE_0, 4);
198 ADD_RANGE(R300_PFS_TEXI_0, 64);
199 ADD_RANGE(0x46A4, 5); 196 ADD_RANGE(0x46A4, 5);
200 ADD_RANGE(R300_PFS_INSTR0_0, 64); 197
201 ADD_RANGE(R300_PFS_INSTR1_0, 64);
202 ADD_RANGE(R300_PFS_INSTR2_0, 64);
203 ADD_RANGE(R300_PFS_INSTR3_0, 64);
204 ADD_RANGE(R300_RE_FOG_STATE, 1); 198 ADD_RANGE(R300_RE_FOG_STATE, 1);
205 ADD_RANGE(R300_FOG_COLOR_R, 3); 199 ADD_RANGE(R300_FOG_COLOR_R, 3);
206 ADD_RANGE(R300_PP_ALPHA_TEST, 2); 200 ADD_RANGE(R300_PP_ALPHA_TEST, 2);
@@ -215,14 +209,12 @@ void r300_init_reg_flags(struct drm_device *dev)
215 ADD_RANGE(0x4E50, 9); 209 ADD_RANGE(0x4E50, 9);
216 ADD_RANGE(0x4E88, 1); 210 ADD_RANGE(0x4E88, 1);
217 ADD_RANGE(0x4EA0, 2); 211 ADD_RANGE(0x4EA0, 2);
218 ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3); 212 ADD_RANGE(R300_ZB_CNTL, 3);
219 ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4); 213 ADD_RANGE(R300_ZB_FORMAT, 4);
220 ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ 214 ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
221 ADD_RANGE(R300_RB3D_DEPTHPITCH, 1); 215 ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
222 ADD_RANGE(0x4F28, 1); 216 ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
223 ADD_RANGE(0x4F30, 2); 217 ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
224 ADD_RANGE(0x4F44, 1);
225 ADD_RANGE(0x4F54, 1);
226 218
227 ADD_RANGE(R300_TX_FILTER_0, 16); 219 ADD_RANGE(R300_TX_FILTER_0, 16);
228 ADD_RANGE(R300_TX_FILTER1_0, 16); 220 ADD_RANGE(R300_TX_FILTER1_0, 16);
@@ -235,13 +227,32 @@ void r300_init_reg_flags(struct drm_device *dev)
235 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); 227 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
236 228
237 /* Sporadic registers used as primitives are emitted */ 229 /* Sporadic registers used as primitives are emitted */
238 ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1); 230 ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
239 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1); 231 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
240 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8); 232 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
241 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8); 233 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
242 234
243 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { 235 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
244 ADD_RANGE(0x4074, 16); 236 ADD_RANGE(R500_VAP_INDEX_OFFSET, 1);
237 ADD_RANGE(R500_US_CONFIG, 2);
238 ADD_RANGE(R500_US_CODE_ADDR, 3);
239 ADD_RANGE(R500_US_FC_CTRL, 1);
240 ADD_RANGE(R500_RS_IP_0, 16);
241 ADD_RANGE(R500_RS_INST_0, 16);
242 ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
243 ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
244 ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
245 } else {
246 ADD_RANGE(R300_PFS_CNTL_0, 3);
247 ADD_RANGE(R300_PFS_NODE_0, 4);
248 ADD_RANGE(R300_PFS_TEXI_0, 64);
249 ADD_RANGE(R300_PFS_INSTR0_0, 64);
250 ADD_RANGE(R300_PFS_INSTR1_0, 64);
251 ADD_RANGE(R300_PFS_INSTR2_0, 64);
252 ADD_RANGE(R300_PFS_INSTR3_0, 64);
253 ADD_RANGE(R300_RS_INTERP_0, 8);
254 ADD_RANGE(R300_RS_ROUTE_0, 8);
255
245 } 256 }
246} 257}
247 258
@@ -707,8 +718,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
707 BEGIN_RING(6); 718 BEGIN_RING(6);
708 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 719 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
709 OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A); 720 OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
710 OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 721 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
711 OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03); 722 OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE|
723 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
712 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0)); 724 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
713 OUT_RING(0x0); 725 OUT_RING(0x0);
714 ADVANCE_RING(); 726 ADVANCE_RING();
@@ -829,6 +841,54 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
829} 841}
830 842
831/** 843/**
844 * Uploads user-supplied vertex program instructions or parameters onto
845 * the graphics card.
846 * Called by r300_do_cp_cmdbuf.
847 */
848static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
849 drm_radeon_kcmd_buffer_t *cmdbuf,
850 drm_r300_cmd_header_t header)
851{
852 int sz;
853 int addr;
854 int type;
855 int clamp;
856 int stride;
857 RING_LOCALS;
858
859 sz = header.r500fp.count;
860 /* address is 9 bits 0 - 8, bit 1 of flags is part of address */
861 addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo;
862
863 type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
864 clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
865
866 addr |= (type << 16);
867 addr |= (clamp << 17);
868
869 stride = type ? 4 : 6;
870
871 DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type);
872 if (!sz)
873 return 0;
874 if (sz * stride * 4 > cmdbuf->bufsz)
875 return -EINVAL;
876
877 BEGIN_RING(3 + sz * stride);
878 OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr);
879 OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1));
880 OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride);
881
882 ADVANCE_RING();
883
884 cmdbuf->buf += sz * stride * 4;
885 cmdbuf->bufsz -= sz * stride * 4;
886
887 return 0;
888}
889
890
891/**
832 * Parses and validates a user-supplied command buffer and emits appropriate 892 * Parses and validates a user-supplied command buffer and emits appropriate
833 * commands on the DMA ring buffer. 893 * commands on the DMA ring buffer.
834 * Called by the ioctl handler function radeon_cp_cmdbuf. 894 * Called by the ioctl handler function radeon_cp_cmdbuf.
@@ -963,6 +1023,19 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
963 } 1023 }
964 break; 1024 break;
965 1025
1026 case R300_CMD_R500FP:
1027 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
1028 DRM_ERROR("Calling r500 command on r300 card\n");
1029 ret = -EINVAL;
1030 goto cleanup;
1031 }
1032 DRM_DEBUG("R300_CMD_R500FP\n");
1033 ret = r300_emit_r500fp(dev_priv, cmdbuf, header);
1034 if (ret) {
1035 DRM_ERROR("r300_emit_r500fp failed\n");
1036 goto cleanup;
1037 }
1038 break;
966 default: 1039 default:
967 DRM_ERROR("bad cmd_type %i at %p\n", 1040 DRM_ERROR("bad cmd_type %i at %p\n",
968 header.header.cmd_type, 1041 header.header.cmd_type,
diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h
index 8f664af9c4a4..a6802f26afc4 100644
--- a/drivers/char/drm/r300_reg.h
+++ b/drivers/char/drm/r300_reg.h
@@ -702,6 +702,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
702# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) 702# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11)
703/* END: Rasterization / Interpolators - many guesses */ 703/* END: Rasterization / Interpolators - many guesses */
704 704
705/* Hierarchical Z Enable */
706#define R300_SC_HYPERZ 0x43a4
707# define R300_SC_HYPERZ_DISABLE (0 << 0)
708# define R300_SC_HYPERZ_ENABLE (1 << 0)
709# define R300_SC_HYPERZ_MIN (0 << 1)
710# define R300_SC_HYPERZ_MAX (1 << 1)
711# define R300_SC_HYPERZ_ADJ_256 (0 << 2)
712# define R300_SC_HYPERZ_ADJ_128 (1 << 2)
713# define R300_SC_HYPERZ_ADJ_64 (2 << 2)
714# define R300_SC_HYPERZ_ADJ_32 (3 << 2)
715# define R300_SC_HYPERZ_ADJ_16 (4 << 2)
716# define R300_SC_HYPERZ_ADJ_8 (5 << 2)
717# define R300_SC_HYPERZ_ADJ_4 (6 << 2)
718# define R300_SC_HYPERZ_ADJ_2 (7 << 2)
719# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
720# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)
721# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
722# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)
723
724#define R300_SC_EDGERULE 0x43a8
725
705/* BEGIN: Scissors and cliprects */ 726/* BEGIN: Scissors and cliprects */
706 727
707/* There are four clipping rectangles. Their corner coordinates are inclusive. 728/* There are four clipping rectangles. Their corner coordinates are inclusive.
@@ -1346,7 +1367,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1346/* Guess by Vladimir. 1367/* Guess by Vladimir.
1347 * Set to 0A before 3D operations, set to 02 afterwards. 1368 * Set to 0A before 3D operations, set to 02 afterwards.
1348 */ 1369 */
1349#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C 1370/*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/
1350# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002 1371# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002
1351# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A 1372# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A
1352 1373
@@ -1355,19 +1376,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1355 * for this. 1376 * for this.
1356 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd 1377 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
1357 */ 1378 */
1358#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00 1379#define R300_ZB_CNTL 0x4F00
1359# define R300_RB3D_Z_DISABLED_1 0x00000010 1380# define R300_STENCIL_ENABLE (1 << 0)
1360# define R300_RB3D_Z_DISABLED_2 0x00000014 1381# define R300_Z_ENABLE (1 << 1)
1361# define R300_RB3D_Z_TEST 0x00000012 1382# define R300_Z_WRITE_ENABLE (1 << 2)
1362# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 1383# define R300_Z_SIGNED_COMPARE (1 << 3)
1363# define R300_RB3D_Z_WRITE_ONLY 0x00000006 1384# define R300_STENCIL_FRONT_BACK (1 << 4)
1364 1385
1365# define R300_RB3D_Z_TEST 0x00000012 1386#define R300_ZB_ZSTENCILCNTL 0x4f04
1366# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
1367# define R300_RB3D_Z_WRITE_ONLY 0x00000006
1368# define R300_RB3D_STENCIL_ENABLE 0x00000001
1369
1370#define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04
1371 /* functions */ 1387 /* functions */
1372# define R300_ZS_NEVER 0 1388# define R300_ZS_NEVER 0
1373# define R300_ZS_LESS 1 1389# define R300_ZS_LESS 1
@@ -1387,52 +1403,166 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1387# define R300_ZS_INVERT 5 1403# define R300_ZS_INVERT 5
1388# define R300_ZS_INCR_WRAP 6 1404# define R300_ZS_INCR_WRAP 6
1389# define R300_ZS_DECR_WRAP 7 1405# define R300_ZS_DECR_WRAP 7
1406# define R300_Z_FUNC_SHIFT 0
1390 /* front and back refer to operations done for front 1407 /* front and back refer to operations done for front
1391 and back faces, i.e. separate stencil function support */ 1408 and back faces, i.e. separate stencil function support */
1392# define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0 1409# define R300_S_FRONT_FUNC_SHIFT 3
1393# define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3 1410# define R300_S_FRONT_SFAIL_OP_SHIFT 6
1394# define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6 1411# define R300_S_FRONT_ZPASS_OP_SHIFT 9
1395# define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9 1412# define R300_S_FRONT_ZFAIL_OP_SHIFT 12
1396# define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12 1413# define R300_S_BACK_FUNC_SHIFT 15
1397# define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15 1414# define R300_S_BACK_SFAIL_OP_SHIFT 18
1398# define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18 1415# define R300_S_BACK_ZPASS_OP_SHIFT 21
1399# define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21 1416# define R300_S_BACK_ZFAIL_OP_SHIFT 24
1400# define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24 1417
1401 1418#define R300_ZB_STENCILREFMASK 0x4f08
1402#define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08 1419# define R300_STENCILREF_SHIFT 0
1403# define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0 1420# define R300_STENCILREF_MASK 0x000000ff
1404# define R300_RB3D_ZS2_STENCIL_MASK 0xFF 1421# define R300_STENCILMASK_SHIFT 8
1405# define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8 1422# define R300_STENCILMASK_MASK 0x0000ff00
1406# define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16 1423# define R300_STENCILWRITEMASK_SHIFT 16
1424# define R300_STENCILWRITEMASK_MASK 0x00ff0000
1407 1425
1408/* gap */ 1426/* gap */
1409 1427
1410#define R300_RB3D_ZSTENCIL_FORMAT 0x4F10 1428#define R300_ZB_FORMAT 0x4f10
1411# define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1429# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
1412# define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1430# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
1413 /* 16 bit format or some aditional bit ? */ 1431# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
1414# define R300_DEPTH_FORMAT_UNK32 (32 << 0) 1432/* reserved up to (15 << 0) */
1433# define R300_INVERT_13E3_LEADING_ONES (0 << 4)
1434# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
1415 1435
1416#define R300_RB3D_EARLY_Z 0x4F14 1436#define R300_ZB_ZTOP 0x4F14
1417# define R300_EARLY_Z_DISABLE (0 << 0) 1437# define R300_ZTOP_DISABLE (0 << 0)
1418# define R300_EARLY_Z_ENABLE (1 << 0) 1438# define R300_ZTOP_ENABLE (1 << 0)
1419 1439
1420/* gap */ 1440/* gap */
1421 1441
1422#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */ 1442#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
1423# define R300_RB3D_ZCACHE_UNKNOWN_01 0x1 1443# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
1424# define R300_RB3D_ZCACHE_UNKNOWN_03 0x3 1444# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
1445# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
1446# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
1447# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
1448# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
1449
1450#define R300_ZB_BW_CNTL 0x4f1c
1451# define R300_HIZ_DISABLE (0 << 0)
1452# define R300_HIZ_ENABLE (1 << 0)
1453# define R300_HIZ_MIN (0 << 1)
1454# define R300_HIZ_MAX (1 << 1)
1455# define R300_FAST_FILL_DISABLE (0 << 2)
1456# define R300_FAST_FILL_ENABLE (1 << 2)
1457# define R300_RD_COMP_DISABLE (0 << 3)
1458# define R300_RD_COMP_ENABLE (1 << 3)
1459# define R300_WR_COMP_DISABLE (0 << 4)
1460# define R300_WR_COMP_ENABLE (1 << 4)
1461# define R300_ZB_CB_CLEAR_RMW (0 << 5)
1462# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
1463# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
1464# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
1465
1466# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
1467# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
1468# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
1469# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
1470
1471# define R500_BMASK_ENABLE (0 << 10)
1472# define R500_BMASK_DISABLE (1 << 10)
1473# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
1474# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
1475# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
1476# define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
1477# define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
1478# define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
1479# define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
1480# define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
1481# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
1482# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
1483# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
1484# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
1485# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
1486# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
1487# define R500_PEQ_PACKING_DISABLE (0 << 18)
1488# define R500_PEQ_PACKING_ENABLE (1 << 18)
1489# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
1490# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
1491
1425 1492
1426/* gap */ 1493/* gap */
1427 1494
1428#define R300_RB3D_DEPTHOFFSET 0x4F20 1495/* Z Buffer Address Offset.
1429#define R300_RB3D_DEPTHPITCH 0x4F24 1496 * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
1430# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ 1497 */
1431# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ 1498#define R300_ZB_DEPTHOFFSET 0x4f20
1432# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */ 1499
1433# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ 1500/* Z Buffer Pitch and Endian Control */
1434# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ 1501#define R300_ZB_DEPTHPITCH 0x4f24
1435# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ 1502# define R300_DEPTHPITCH_MASK 0x00003FFC
1503# define R300_DEPTHMACROTILE_DISABLE (0 << 16)
1504# define R300_DEPTHMACROTILE_ENABLE (1 << 16)
1505# define R300_DEPTHMICROTILE_LINEAR (0 << 17)
1506# define R300_DEPTHMICROTILE_TILED (1 << 17)
1507# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
1508# define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
1509# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
1510# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
1511# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
1512
1513/* Z Buffer Clear Value */
1514#define R300_ZB_DEPTHCLEARVALUE 0x4f28
1515
1516#define R300_ZB_ZMASK_OFFSET 0x4f30
1517#define R300_ZB_ZMASK_PITCH 0x4f34
1518#define R300_ZB_ZMASK_WRINDEX 0x4f38
1519#define R300_ZB_ZMASK_DWORD 0x4f3c
1520#define R300_ZB_ZMASK_RDINDEX 0x4f40
1521
1522/* Hierarchical Z Memory Offset */
1523#define R300_ZB_HIZ_OFFSET 0x4f44
1524
1525/* Hierarchical Z Write Index */
1526#define R300_ZB_HIZ_WRINDEX 0x4f48
1527
1528/* Hierarchical Z Data */
1529#define R300_ZB_HIZ_DWORD 0x4f4c
1530
1531/* Hierarchical Z Read Index */
1532#define R300_ZB_HIZ_RDINDEX 0x4f50
1533
1534/* Hierarchical Z Pitch */
1535#define R300_ZB_HIZ_PITCH 0x4f54
1536
1537/* Z Buffer Z Pass Counter Data */
1538#define R300_ZB_ZPASS_DATA 0x4f58
1539
1540/* Z Buffer Z Pass Counter Address */
1541#define R300_ZB_ZPASS_ADDR 0x4f5c
1542
1543/* Depth buffer X and Y coordinate offset */
1544#define R300_ZB_DEPTHXY_OFFSET 0x4f60
1545# define R300_DEPTHX_OFFSET_SHIFT 1
1546# define R300_DEPTHX_OFFSET_MASK 0x000007FE
1547# define R300_DEPTHY_OFFSET_SHIFT 17
1548# define R300_DEPTHY_OFFSET_MASK 0x07FE0000
1549
1550/* Sets the fifo sizes */
1551#define R500_ZB_FIFO_SIZE 0x4fd0
1552# define R500_OP_FIFO_SIZE_FULL (0 << 0)
1553# define R500_OP_FIFO_SIZE_HALF (1 << 0)
1554# define R500_OP_FIFO_SIZE_QUATER (2 << 0)
1555# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
1556
1557/* Stencil Reference Value and Mask for backfacing quads */
1558/* R300_ZB_STENCILREFMASK handles front face */
1559#define R500_ZB_STENCILREFMASK_BF 0x4fd4
1560# define R500_STENCILREF_SHIFT 0
1561# define R500_STENCILREF_MASK 0x000000ff
1562# define R500_STENCILMASK_SHIFT 8
1563# define R500_STENCILMASK_MASK 0x0000ff00
1564# define R500_STENCILWRITEMASK_SHIFT 16
1565# define R500_STENCILWRITEMASK_MASK 0x00ff0000
1436 1566
1437/* BEGIN: Vertex program instruction set */ 1567/* BEGIN: Vertex program instruction set */
1438 1568
@@ -1623,4 +1753,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1623 */ 1753 */
1624#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 1754#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
1625 1755
1756#define R500_VAP_INDEX_OFFSET 0x208c
1757
1758#define R500_GA_US_VECTOR_INDEX 0x4250
1759#define R500_GA_US_VECTOR_DATA 0x4254
1760
1761#define R500_RS_IP_0 0x4074
1762#define R500_RS_INST_0 0x4320
1763
1764#define R500_US_CONFIG 0x4600
1765
1766#define R500_US_FC_CTRL 0x4624
1767#define R500_US_CODE_ADDR 0x4630
1768
1769#define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0
1770#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8
1771
1626#endif /* _R300_REG_H */ 1772#endif /* _R300_REG_H */
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index f6f6c92bf771..e53158f0ecb5 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -2,6 +2,7 @@
2/* 2/*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
5 * All Rights Reserved. 6 * All Rights Reserved.
6 * 7 *
7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,789 +35,13 @@
34#include "radeon_drv.h" 35#include "radeon_drv.h"
35#include "r300_reg.h" 36#include "r300_reg.h"
36 37
38#include "radeon_microcode.h"
39
37#define RADEON_FIFO_DEBUG 0 40#define RADEON_FIFO_DEBUG 0
38 41
39static int radeon_do_cleanup_cp(struct drm_device * dev); 42static int radeon_do_cleanup_cp(struct drm_device * dev);
40 43
41/* CP microcode (from ATI) */ 44static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
42static const u32 R200_cp_microcode[][2] = {
43 {0x21007000, 0000000000},
44 {0x20007000, 0000000000},
45 {0x000000ab, 0x00000004},
46 {0x000000af, 0x00000004},
47 {0x66544a49, 0000000000},
48 {0x49494174, 0000000000},
49 {0x54517d83, 0000000000},
50 {0x498d8b64, 0000000000},
51 {0x49494949, 0000000000},
52 {0x49da493c, 0000000000},
53 {0x49989898, 0000000000},
54 {0xd34949d5, 0000000000},
55 {0x9dc90e11, 0000000000},
56 {0xce9b9b9b, 0000000000},
57 {0x000f0000, 0x00000016},
58 {0x352e232c, 0000000000},
59 {0x00000013, 0x00000004},
60 {0x000f0000, 0x00000016},
61 {0x352e272c, 0000000000},
62 {0x000f0001, 0x00000016},
63 {0x3239362f, 0000000000},
64 {0x000077ef, 0x00000002},
65 {0x00061000, 0x00000002},
66 {0x00000020, 0x0000001a},
67 {0x00004000, 0x0000001e},
68 {0x00061000, 0x00000002},
69 {0x00000020, 0x0000001a},
70 {0x00004000, 0x0000001e},
71 {0x00061000, 0x00000002},
72 {0x00000020, 0x0000001a},
73 {0x00004000, 0x0000001e},
74 {0x00000016, 0x00000004},
75 {0x0003802a, 0x00000002},
76 {0x040067e0, 0x00000002},
77 {0x00000016, 0x00000004},
78 {0x000077e0, 0x00000002},
79 {0x00065000, 0x00000002},
80 {0x000037e1, 0x00000002},
81 {0x040067e1, 0x00000006},
82 {0x000077e0, 0x00000002},
83 {0x000077e1, 0x00000002},
84 {0x000077e1, 0x00000006},
85 {0xffffffff, 0000000000},
86 {0x10000000, 0000000000},
87 {0x0003802a, 0x00000002},
88 {0x040067e0, 0x00000006},
89 {0x00007675, 0x00000002},
90 {0x00007676, 0x00000002},
91 {0x00007677, 0x00000002},
92 {0x00007678, 0x00000006},
93 {0x0003802b, 0x00000002},
94 {0x04002676, 0x00000002},
95 {0x00007677, 0x00000002},
96 {0x00007678, 0x00000006},
97 {0x0000002e, 0x00000018},
98 {0x0000002e, 0x00000018},
99 {0000000000, 0x00000006},
100 {0x0000002f, 0x00000018},
101 {0x0000002f, 0x00000018},
102 {0000000000, 0x00000006},
103 {0x01605000, 0x00000002},
104 {0x00065000, 0x00000002},
105 {0x00098000, 0x00000002},
106 {0x00061000, 0x00000002},
107 {0x64c0603d, 0x00000004},
108 {0x00080000, 0x00000016},
109 {0000000000, 0000000000},
110 {0x0400251d, 0x00000002},
111 {0x00007580, 0x00000002},
112 {0x00067581, 0x00000002},
113 {0x04002580, 0x00000002},
114 {0x00067581, 0x00000002},
115 {0x00000046, 0x00000004},
116 {0x00005000, 0000000000},
117 {0x00061000, 0x00000002},
118 {0x0000750e, 0x00000002},
119 {0x00019000, 0x00000002},
120 {0x00011055, 0x00000014},
121 {0x00000055, 0x00000012},
122 {0x0400250f, 0x00000002},
123 {0x0000504a, 0x00000004},
124 {0x00007565, 0x00000002},
125 {0x00007566, 0x00000002},
126 {0x00000051, 0x00000004},
127 {0x01e655b4, 0x00000002},
128 {0x4401b0dc, 0x00000002},
129 {0x01c110dc, 0x00000002},
130 {0x2666705d, 0x00000018},
131 {0x040c2565, 0x00000002},
132 {0x0000005d, 0x00000018},
133 {0x04002564, 0x00000002},
134 {0x00007566, 0x00000002},
135 {0x00000054, 0x00000004},
136 {0x00401060, 0x00000008},
137 {0x00101000, 0x00000002},
138 {0x000d80ff, 0x00000002},
139 {0x00800063, 0x00000008},
140 {0x000f9000, 0x00000002},
141 {0x000e00ff, 0x00000002},
142 {0000000000, 0x00000006},
143 {0x00000080, 0x00000018},
144 {0x00000054, 0x00000004},
145 {0x00007576, 0x00000002},
146 {0x00065000, 0x00000002},
147 {0x00009000, 0x00000002},
148 {0x00041000, 0x00000002},
149 {0x0c00350e, 0x00000002},
150 {0x00049000, 0x00000002},
151 {0x00051000, 0x00000002},
152 {0x01e785f8, 0x00000002},
153 {0x00200000, 0x00000002},
154 {0x00600073, 0x0000000c},
155 {0x00007563, 0x00000002},
156 {0x006075f0, 0x00000021},
157 {0x20007068, 0x00000004},
158 {0x00005068, 0x00000004},
159 {0x00007576, 0x00000002},
160 {0x00007577, 0x00000002},
161 {0x0000750e, 0x00000002},
162 {0x0000750f, 0x00000002},
163 {0x00a05000, 0x00000002},
164 {0x00600076, 0x0000000c},
165 {0x006075f0, 0x00000021},
166 {0x000075f8, 0x00000002},
167 {0x00000076, 0x00000004},
168 {0x000a750e, 0x00000002},
169 {0x0020750f, 0x00000002},
170 {0x00600079, 0x00000004},
171 {0x00007570, 0x00000002},
172 {0x00007571, 0x00000002},
173 {0x00007572, 0x00000006},
174 {0x00005000, 0x00000002},
175 {0x00a05000, 0x00000002},
176 {0x00007568, 0x00000002},
177 {0x00061000, 0x00000002},
178 {0x00000084, 0x0000000c},
179 {0x00058000, 0x00000002},
180 {0x0c607562, 0x00000002},
181 {0x00000086, 0x00000004},
182 {0x00600085, 0x00000004},
183 {0x400070dd, 0000000000},
184 {0x000380dd, 0x00000002},
185 {0x00000093, 0x0000001c},
186 {0x00065095, 0x00000018},
187 {0x040025bb, 0x00000002},
188 {0x00061096, 0x00000018},
189 {0x040075bc, 0000000000},
190 {0x000075bb, 0x00000002},
191 {0x000075bc, 0000000000},
192 {0x00090000, 0x00000006},
193 {0x00090000, 0x00000002},
194 {0x000d8002, 0x00000006},
195 {0x00005000, 0x00000002},
196 {0x00007821, 0x00000002},
197 {0x00007800, 0000000000},
198 {0x00007821, 0x00000002},
199 {0x00007800, 0000000000},
200 {0x01665000, 0x00000002},
201 {0x000a0000, 0x00000002},
202 {0x000671cc, 0x00000002},
203 {0x0286f1cd, 0x00000002},
204 {0x000000a3, 0x00000010},
205 {0x21007000, 0000000000},
206 {0x000000aa, 0x0000001c},
207 {0x00065000, 0x00000002},
208 {0x000a0000, 0x00000002},
209 {0x00061000, 0x00000002},
210 {0x000b0000, 0x00000002},
211 {0x38067000, 0x00000002},
212 {0x000a00a6, 0x00000004},
213 {0x20007000, 0000000000},
214 {0x01200000, 0x00000002},
215 {0x20077000, 0x00000002},
216 {0x01200000, 0x00000002},
217 {0x20007000, 0000000000},
218 {0x00061000, 0x00000002},
219 {0x0120751b, 0x00000002},
220 {0x8040750a, 0x00000002},
221 {0x8040750b, 0x00000002},
222 {0x00110000, 0x00000002},
223 {0x000380dd, 0x00000002},
224 {0x000000bd, 0x0000001c},
225 {0x00061096, 0x00000018},
226 {0x844075bd, 0x00000002},
227 {0x00061095, 0x00000018},
228 {0x840075bb, 0x00000002},
229 {0x00061096, 0x00000018},
230 {0x844075bc, 0x00000002},
231 {0x000000c0, 0x00000004},
232 {0x804075bd, 0x00000002},
233 {0x800075bb, 0x00000002},
234 {0x804075bc, 0x00000002},
235 {0x00108000, 0x00000002},
236 {0x01400000, 0x00000002},
237 {0x006000c4, 0x0000000c},
238 {0x20c07000, 0x00000020},
239 {0x000000c6, 0x00000012},
240 {0x00800000, 0x00000006},
241 {0x0080751d, 0x00000006},
242 {0x000025bb, 0x00000002},
243 {0x000040c0, 0x00000004},
244 {0x0000775c, 0x00000002},
245 {0x00a05000, 0x00000002},
246 {0x00661000, 0x00000002},
247 {0x0460275d, 0x00000020},
248 {0x00004000, 0000000000},
249 {0x00007999, 0x00000002},
250 {0x00a05000, 0x00000002},
251 {0x00661000, 0x00000002},
252 {0x0460299b, 0x00000020},
253 {0x00004000, 0000000000},
254 {0x01e00830, 0x00000002},
255 {0x21007000, 0000000000},
256 {0x00005000, 0x00000002},
257 {0x00038042, 0x00000002},
258 {0x040025e0, 0x00000002},
259 {0x000075e1, 0000000000},
260 {0x00000001, 0000000000},
261 {0x000380d9, 0x00000002},
262 {0x04007394, 0000000000},
263 {0000000000, 0000000000},
264 {0000000000, 0000000000},
265 {0000000000, 0000000000},
266 {0000000000, 0000000000},
267 {0000000000, 0000000000},
268 {0000000000, 0000000000},
269 {0000000000, 0000000000},
270 {0000000000, 0000000000},
271 {0000000000, 0000000000},
272 {0000000000, 0000000000},
273 {0000000000, 0000000000},
274 {0000000000, 0000000000},
275 {0000000000, 0000000000},
276 {0000000000, 0000000000},
277 {0000000000, 0000000000},
278 {0000000000, 0000000000},
279 {0000000000, 0000000000},
280 {0000000000, 0000000000},
281 {0000000000, 0000000000},
282 {0000000000, 0000000000},
283 {0000000000, 0000000000},
284 {0000000000, 0000000000},
285 {0000000000, 0000000000},
286 {0000000000, 0000000000},
287 {0000000000, 0000000000},
288 {0000000000, 0000000000},
289 {0000000000, 0000000000},
290 {0000000000, 0000000000},
291 {0000000000, 0000000000},
292 {0000000000, 0000000000},
293 {0000000000, 0000000000},
294 {0000000000, 0000000000},
295 {0000000000, 0000000000},
296 {0000000000, 0000000000},
297 {0000000000, 0000000000},
298 {0000000000, 0000000000},
299};
300
301static const u32 radeon_cp_microcode[][2] = {
302 {0x21007000, 0000000000},
303 {0x20007000, 0000000000},
304 {0x000000b4, 0x00000004},
305 {0x000000b8, 0x00000004},
306 {0x6f5b4d4c, 0000000000},
307 {0x4c4c427f, 0000000000},
308 {0x5b568a92, 0000000000},
309 {0x4ca09c6d, 0000000000},
310 {0xad4c4c4c, 0000000000},
311 {0x4ce1af3d, 0000000000},
312 {0xd8afafaf, 0000000000},
313 {0xd64c4cdc, 0000000000},
314 {0x4cd10d10, 0000000000},
315 {0x000f0000, 0x00000016},
316 {0x362f242d, 0000000000},
317 {0x00000012, 0x00000004},
318 {0x000f0000, 0x00000016},
319 {0x362f282d, 0000000000},
320 {0x000380e7, 0x00000002},
321 {0x04002c97, 0x00000002},
322 {0x000f0001, 0x00000016},
323 {0x333a3730, 0000000000},
324 {0x000077ef, 0x00000002},
325 {0x00061000, 0x00000002},
326 {0x00000021, 0x0000001a},
327 {0x00004000, 0x0000001e},
328 {0x00061000, 0x00000002},
329 {0x00000021, 0x0000001a},
330 {0x00004000, 0x0000001e},
331 {0x00061000, 0x00000002},
332 {0x00000021, 0x0000001a},
333 {0x00004000, 0x0000001e},
334 {0x00000017, 0x00000004},
335 {0x0003802b, 0x00000002},
336 {0x040067e0, 0x00000002},
337 {0x00000017, 0x00000004},
338 {0x000077e0, 0x00000002},
339 {0x00065000, 0x00000002},
340 {0x000037e1, 0x00000002},
341 {0x040067e1, 0x00000006},
342 {0x000077e0, 0x00000002},
343 {0x000077e1, 0x00000002},
344 {0x000077e1, 0x00000006},
345 {0xffffffff, 0000000000},
346 {0x10000000, 0000000000},
347 {0x0003802b, 0x00000002},
348 {0x040067e0, 0x00000006},
349 {0x00007675, 0x00000002},
350 {0x00007676, 0x00000002},
351 {0x00007677, 0x00000002},
352 {0x00007678, 0x00000006},
353 {0x0003802c, 0x00000002},
354 {0x04002676, 0x00000002},
355 {0x00007677, 0x00000002},
356 {0x00007678, 0x00000006},
357 {0x0000002f, 0x00000018},
358 {0x0000002f, 0x00000018},
359 {0000000000, 0x00000006},
360 {0x00000030, 0x00000018},
361 {0x00000030, 0x00000018},
362 {0000000000, 0x00000006},
363 {0x01605000, 0x00000002},
364 {0x00065000, 0x00000002},
365 {0x00098000, 0x00000002},
366 {0x00061000, 0x00000002},
367 {0x64c0603e, 0x00000004},
368 {0x000380e6, 0x00000002},
369 {0x040025c5, 0x00000002},
370 {0x00080000, 0x00000016},
371 {0000000000, 0000000000},
372 {0x0400251d, 0x00000002},
373 {0x00007580, 0x00000002},
374 {0x00067581, 0x00000002},
375 {0x04002580, 0x00000002},
376 {0x00067581, 0x00000002},
377 {0x00000049, 0x00000004},
378 {0x00005000, 0000000000},
379 {0x000380e6, 0x00000002},
380 {0x040025c5, 0x00000002},
381 {0x00061000, 0x00000002},
382 {0x0000750e, 0x00000002},
383 {0x00019000, 0x00000002},
384 {0x00011055, 0x00000014},
385 {0x00000055, 0x00000012},
386 {0x0400250f, 0x00000002},
387 {0x0000504f, 0x00000004},
388 {0x000380e6, 0x00000002},
389 {0x040025c5, 0x00000002},
390 {0x00007565, 0x00000002},
391 {0x00007566, 0x00000002},
392 {0x00000058, 0x00000004},
393 {0x000380e6, 0x00000002},
394 {0x040025c5, 0x00000002},
395 {0x01e655b4, 0x00000002},
396 {0x4401b0e4, 0x00000002},
397 {0x01c110e4, 0x00000002},
398 {0x26667066, 0x00000018},
399 {0x040c2565, 0x00000002},
400 {0x00000066, 0x00000018},
401 {0x04002564, 0x00000002},
402 {0x00007566, 0x00000002},
403 {0x0000005d, 0x00000004},
404 {0x00401069, 0x00000008},
405 {0x00101000, 0x00000002},
406 {0x000d80ff, 0x00000002},
407 {0x0080006c, 0x00000008},
408 {0x000f9000, 0x00000002},
409 {0x000e00ff, 0x00000002},
410 {0000000000, 0x00000006},
411 {0x0000008f, 0x00000018},
412 {0x0000005b, 0x00000004},
413 {0x000380e6, 0x00000002},
414 {0x040025c5, 0x00000002},
415 {0x00007576, 0x00000002},
416 {0x00065000, 0x00000002},
417 {0x00009000, 0x00000002},
418 {0x00041000, 0x00000002},
419 {0x0c00350e, 0x00000002},
420 {0x00049000, 0x00000002},
421 {0x00051000, 0x00000002},
422 {0x01e785f8, 0x00000002},
423 {0x00200000, 0x00000002},
424 {0x0060007e, 0x0000000c},
425 {0x00007563, 0x00000002},
426 {0x006075f0, 0x00000021},
427 {0x20007073, 0x00000004},
428 {0x00005073, 0x00000004},
429 {0x000380e6, 0x00000002},
430 {0x040025c5, 0x00000002},
431 {0x00007576, 0x00000002},
432 {0x00007577, 0x00000002},
433 {0x0000750e, 0x00000002},
434 {0x0000750f, 0x00000002},
435 {0x00a05000, 0x00000002},
436 {0x00600083, 0x0000000c},
437 {0x006075f0, 0x00000021},
438 {0x000075f8, 0x00000002},
439 {0x00000083, 0x00000004},
440 {0x000a750e, 0x00000002},
441 {0x000380e6, 0x00000002},
442 {0x040025c5, 0x00000002},
443 {0x0020750f, 0x00000002},
444 {0x00600086, 0x00000004},
445 {0x00007570, 0x00000002},
446 {0x00007571, 0x00000002},
447 {0x00007572, 0x00000006},
448 {0x000380e6, 0x00000002},
449 {0x040025c5, 0x00000002},
450 {0x00005000, 0x00000002},
451 {0x00a05000, 0x00000002},
452 {0x00007568, 0x00000002},
453 {0x00061000, 0x00000002},
454 {0x00000095, 0x0000000c},
455 {0x00058000, 0x00000002},
456 {0x0c607562, 0x00000002},
457 {0x00000097, 0x00000004},
458 {0x000380e6, 0x00000002},
459 {0x040025c5, 0x00000002},
460 {0x00600096, 0x00000004},
461 {0x400070e5, 0000000000},
462 {0x000380e6, 0x00000002},
463 {0x040025c5, 0x00000002},
464 {0x000380e5, 0x00000002},
465 {0x000000a8, 0x0000001c},
466 {0x000650aa, 0x00000018},
467 {0x040025bb, 0x00000002},
468 {0x000610ab, 0x00000018},
469 {0x040075bc, 0000000000},
470 {0x000075bb, 0x00000002},
471 {0x000075bc, 0000000000},
472 {0x00090000, 0x00000006},
473 {0x00090000, 0x00000002},
474 {0x000d8002, 0x00000006},
475 {0x00007832, 0x00000002},
476 {0x00005000, 0x00000002},
477 {0x000380e7, 0x00000002},
478 {0x04002c97, 0x00000002},
479 {0x00007820, 0x00000002},
480 {0x00007821, 0x00000002},
481 {0x00007800, 0000000000},
482 {0x01200000, 0x00000002},
483 {0x20077000, 0x00000002},
484 {0x01200000, 0x00000002},
485 {0x20007000, 0x00000002},
486 {0x00061000, 0x00000002},
487 {0x0120751b, 0x00000002},
488 {0x8040750a, 0x00000002},
489 {0x8040750b, 0x00000002},
490 {0x00110000, 0x00000002},
491 {0x000380e5, 0x00000002},
492 {0x000000c6, 0x0000001c},
493 {0x000610ab, 0x00000018},
494 {0x844075bd, 0x00000002},
495 {0x000610aa, 0x00000018},
496 {0x840075bb, 0x00000002},
497 {0x000610ab, 0x00000018},
498 {0x844075bc, 0x00000002},
499 {0x000000c9, 0x00000004},
500 {0x804075bd, 0x00000002},
501 {0x800075bb, 0x00000002},
502 {0x804075bc, 0x00000002},
503 {0x00108000, 0x00000002},
504 {0x01400000, 0x00000002},
505 {0x006000cd, 0x0000000c},
506 {0x20c07000, 0x00000020},
507 {0x000000cf, 0x00000012},
508 {0x00800000, 0x00000006},
509 {0x0080751d, 0x00000006},
510 {0000000000, 0000000000},
511 {0x0000775c, 0x00000002},
512 {0x00a05000, 0x00000002},
513 {0x00661000, 0x00000002},
514 {0x0460275d, 0x00000020},
515 {0x00004000, 0000000000},
516 {0x01e00830, 0x00000002},
517 {0x21007000, 0000000000},
518 {0x6464614d, 0000000000},
519 {0x69687420, 0000000000},
520 {0x00000073, 0000000000},
521 {0000000000, 0000000000},
522 {0x00005000, 0x00000002},
523 {0x000380d0, 0x00000002},
524 {0x040025e0, 0x00000002},
525 {0x000075e1, 0000000000},
526 {0x00000001, 0000000000},
527 {0x000380e0, 0x00000002},
528 {0x04002394, 0x00000002},
529 {0x00005000, 0000000000},
530 {0000000000, 0000000000},
531 {0000000000, 0000000000},
532 {0x00000008, 0000000000},
533 {0x00000004, 0000000000},
534 {0000000000, 0000000000},
535 {0000000000, 0000000000},
536 {0000000000, 0000000000},
537 {0000000000, 0000000000},
538 {0000000000, 0000000000},
539 {0000000000, 0000000000},
540 {0000000000, 0000000000},
541 {0000000000, 0000000000},
542 {0000000000, 0000000000},
543 {0000000000, 0000000000},
544 {0000000000, 0000000000},
545 {0000000000, 0000000000},
546 {0000000000, 0000000000},
547 {0000000000, 0000000000},
548 {0000000000, 0000000000},
549 {0000000000, 0000000000},
550 {0000000000, 0000000000},
551 {0000000000, 0000000000},
552 {0000000000, 0000000000},
553 {0000000000, 0000000000},
554 {0000000000, 0000000000},
555 {0000000000, 0000000000},
556 {0000000000, 0000000000},
557 {0000000000, 0000000000},
558};
559
560static const u32 R300_cp_microcode[][2] = {
561 {0x4200e000, 0000000000},
562 {0x4000e000, 0000000000},
563 {0x000000af, 0x00000008},
564 {0x000000b3, 0x00000008},
565 {0x6c5a504f, 0000000000},
566 {0x4f4f497a, 0000000000},
567 {0x5a578288, 0000000000},
568 {0x4f91906a, 0000000000},
569 {0x4f4f4f4f, 0000000000},
570 {0x4fe24f44, 0000000000},
571 {0x4f9c9c9c, 0000000000},
572 {0xdc4f4fde, 0000000000},
573 {0xa1cd4f4f, 0000000000},
574 {0xd29d9d9d, 0000000000},
575 {0x4f0f9fd7, 0000000000},
576 {0x000ca000, 0x00000004},
577 {0x000d0012, 0x00000038},
578 {0x0000e8b4, 0x00000004},
579 {0x000d0014, 0x00000038},
580 {0x0000e8b6, 0x00000004},
581 {0x000d0016, 0x00000038},
582 {0x0000e854, 0x00000004},
583 {0x000d0018, 0x00000038},
584 {0x0000e855, 0x00000004},
585 {0x000d001a, 0x00000038},
586 {0x0000e856, 0x00000004},
587 {0x000d001c, 0x00000038},
588 {0x0000e857, 0x00000004},
589 {0x000d001e, 0x00000038},
590 {0x0000e824, 0x00000004},
591 {0x000d0020, 0x00000038},
592 {0x0000e825, 0x00000004},
593 {0x000d0022, 0x00000038},
594 {0x0000e830, 0x00000004},
595 {0x000d0024, 0x00000038},
596 {0x0000f0c0, 0x00000004},
597 {0x000d0026, 0x00000038},
598 {0x0000f0c1, 0x00000004},
599 {0x000d0028, 0x00000038},
600 {0x0000f041, 0x00000004},
601 {0x000d002a, 0x00000038},
602 {0x0000f184, 0x00000004},
603 {0x000d002c, 0x00000038},
604 {0x0000f185, 0x00000004},
605 {0x000d002e, 0x00000038},
606 {0x0000f186, 0x00000004},
607 {0x000d0030, 0x00000038},
608 {0x0000f187, 0x00000004},
609 {0x000d0032, 0x00000038},
610 {0x0000f180, 0x00000004},
611 {0x000d0034, 0x00000038},
612 {0x0000f393, 0x00000004},
613 {0x000d0036, 0x00000038},
614 {0x0000f38a, 0x00000004},
615 {0x000d0038, 0x00000038},
616 {0x0000f38e, 0x00000004},
617 {0x0000e821, 0x00000004},
618 {0x0140a000, 0x00000004},
619 {0x00000043, 0x00000018},
620 {0x00cce800, 0x00000004},
621 {0x001b0001, 0x00000004},
622 {0x08004800, 0x00000004},
623 {0x001b0001, 0x00000004},
624 {0x08004800, 0x00000004},
625 {0x001b0001, 0x00000004},
626 {0x08004800, 0x00000004},
627 {0x0000003a, 0x00000008},
628 {0x0000a000, 0000000000},
629 {0x02c0a000, 0x00000004},
630 {0x000ca000, 0x00000004},
631 {0x00130000, 0x00000004},
632 {0x000c2000, 0x00000004},
633 {0xc980c045, 0x00000008},
634 {0x2000451d, 0x00000004},
635 {0x0000e580, 0x00000004},
636 {0x000ce581, 0x00000004},
637 {0x08004580, 0x00000004},
638 {0x000ce581, 0x00000004},
639 {0x0000004c, 0x00000008},
640 {0x0000a000, 0000000000},
641 {0x000c2000, 0x00000004},
642 {0x0000e50e, 0x00000004},
643 {0x00032000, 0x00000004},
644 {0x00022056, 0x00000028},
645 {0x00000056, 0x00000024},
646 {0x0800450f, 0x00000004},
647 {0x0000a050, 0x00000008},
648 {0x0000e565, 0x00000004},
649 {0x0000e566, 0x00000004},
650 {0x00000057, 0x00000008},
651 {0x03cca5b4, 0x00000004},
652 {0x05432000, 0x00000004},
653 {0x00022000, 0x00000004},
654 {0x4ccce063, 0x00000030},
655 {0x08274565, 0x00000004},
656 {0x00000063, 0x00000030},
657 {0x08004564, 0x00000004},
658 {0x0000e566, 0x00000004},
659 {0x0000005a, 0x00000008},
660 {0x00802066, 0x00000010},
661 {0x00202000, 0x00000004},
662 {0x001b00ff, 0x00000004},
663 {0x01000069, 0x00000010},
664 {0x001f2000, 0x00000004},
665 {0x001c00ff, 0x00000004},
666 {0000000000, 0x0000000c},
667 {0x00000085, 0x00000030},
668 {0x0000005a, 0x00000008},
669 {0x0000e576, 0x00000004},
670 {0x000ca000, 0x00000004},
671 {0x00012000, 0x00000004},
672 {0x00082000, 0x00000004},
673 {0x1800650e, 0x00000004},
674 {0x00092000, 0x00000004},
675 {0x000a2000, 0x00000004},
676 {0x000f0000, 0x00000004},
677 {0x00400000, 0x00000004},
678 {0x00000079, 0x00000018},
679 {0x0000e563, 0x00000004},
680 {0x00c0e5f9, 0x000000c2},
681 {0x0000006e, 0x00000008},
682 {0x0000a06e, 0x00000008},
683 {0x0000e576, 0x00000004},
684 {0x0000e577, 0x00000004},
685 {0x0000e50e, 0x00000004},
686 {0x0000e50f, 0x00000004},
687 {0x0140a000, 0x00000004},
688 {0x0000007c, 0x00000018},
689 {0x00c0e5f9, 0x000000c2},
690 {0x0000007c, 0x00000008},
691 {0x0014e50e, 0x00000004},
692 {0x0040e50f, 0x00000004},
693 {0x00c0007f, 0x00000008},
694 {0x0000e570, 0x00000004},
695 {0x0000e571, 0x00000004},
696 {0x0000e572, 0x0000000c},
697 {0x0000a000, 0x00000004},
698 {0x0140a000, 0x00000004},
699 {0x0000e568, 0x00000004},
700 {0x000c2000, 0x00000004},
701 {0x00000089, 0x00000018},
702 {0x000b0000, 0x00000004},
703 {0x18c0e562, 0x00000004},
704 {0x0000008b, 0x00000008},
705 {0x00c0008a, 0x00000008},
706 {0x000700e4, 0x00000004},
707 {0x00000097, 0x00000038},
708 {0x000ca099, 0x00000030},
709 {0x080045bb, 0x00000004},
710 {0x000c209a, 0x00000030},
711 {0x0800e5bc, 0000000000},
712 {0x0000e5bb, 0x00000004},
713 {0x0000e5bc, 0000000000},
714 {0x00120000, 0x0000000c},
715 {0x00120000, 0x00000004},
716 {0x001b0002, 0x0000000c},
717 {0x0000a000, 0x00000004},
718 {0x0000e821, 0x00000004},
719 {0x0000e800, 0000000000},
720 {0x0000e821, 0x00000004},
721 {0x0000e82e, 0000000000},
722 {0x02cca000, 0x00000004},
723 {0x00140000, 0x00000004},
724 {0x000ce1cc, 0x00000004},
725 {0x050de1cd, 0x00000004},
726 {0x000000a7, 0x00000020},
727 {0x4200e000, 0000000000},
728 {0x000000ae, 0x00000038},
729 {0x000ca000, 0x00000004},
730 {0x00140000, 0x00000004},
731 {0x000c2000, 0x00000004},
732 {0x00160000, 0x00000004},
733 {0x700ce000, 0x00000004},
734 {0x001400aa, 0x00000008},
735 {0x4000e000, 0000000000},
736 {0x02400000, 0x00000004},
737 {0x400ee000, 0x00000004},
738 {0x02400000, 0x00000004},
739 {0x4000e000, 0000000000},
740 {0x000c2000, 0x00000004},
741 {0x0240e51b, 0x00000004},
742 {0x0080e50a, 0x00000005},
743 {0x0080e50b, 0x00000005},
744 {0x00220000, 0x00000004},
745 {0x000700e4, 0x00000004},
746 {0x000000c1, 0x00000038},
747 {0x000c209a, 0x00000030},
748 {0x0880e5bd, 0x00000005},
749 {0x000c2099, 0x00000030},
750 {0x0800e5bb, 0x00000005},
751 {0x000c209a, 0x00000030},
752 {0x0880e5bc, 0x00000005},
753 {0x000000c4, 0x00000008},
754 {0x0080e5bd, 0x00000005},
755 {0x0000e5bb, 0x00000005},
756 {0x0080e5bc, 0x00000005},
757 {0x00210000, 0x00000004},
758 {0x02800000, 0x00000004},
759 {0x00c000c8, 0x00000018},
760 {0x4180e000, 0x00000040},
761 {0x000000ca, 0x00000024},
762 {0x01000000, 0x0000000c},
763 {0x0100e51d, 0x0000000c},
764 {0x000045bb, 0x00000004},
765 {0x000080c4, 0x00000008},
766 {0x0000f3ce, 0x00000004},
767 {0x0140a000, 0x00000004},
768 {0x00cc2000, 0x00000004},
769 {0x08c053cf, 0x00000040},
770 {0x00008000, 0000000000},
771 {0x0000f3d2, 0x00000004},
772 {0x0140a000, 0x00000004},
773 {0x00cc2000, 0x00000004},
774 {0x08c053d3, 0x00000040},
775 {0x00008000, 0000000000},
776 {0x0000f39d, 0x00000004},
777 {0x0140a000, 0x00000004},
778 {0x00cc2000, 0x00000004},
779 {0x08c0539e, 0x00000040},
780 {0x00008000, 0000000000},
781 {0x03c00830, 0x00000004},
782 {0x4200e000, 0000000000},
783 {0x0000a000, 0x00000004},
784 {0x200045e0, 0x00000004},
785 {0x0000e5e1, 0000000000},
786 {0x00000001, 0000000000},
787 {0x000700e1, 0x00000004},
788 {0x0800e394, 0000000000},
789 {0000000000, 0000000000},
790 {0000000000, 0000000000},
791 {0000000000, 0000000000},
792 {0000000000, 0000000000},
793 {0000000000, 0000000000},
794 {0000000000, 0000000000},
795 {0000000000, 0000000000},
796 {0000000000, 0000000000},
797 {0000000000, 0000000000},
798 {0000000000, 0000000000},
799 {0000000000, 0000000000},
800 {0000000000, 0000000000},
801 {0000000000, 0000000000},
802 {0000000000, 0000000000},
803 {0000000000, 0000000000},
804 {0000000000, 0000000000},
805 {0000000000, 0000000000},
806 {0000000000, 0000000000},
807 {0000000000, 0000000000},
808 {0000000000, 0000000000},
809 {0000000000, 0000000000},
810 {0000000000, 0000000000},
811 {0000000000, 0000000000},
812 {0000000000, 0000000000},
813 {0000000000, 0000000000},
814 {0000000000, 0000000000},
815 {0000000000, 0000000000},
816 {0000000000, 0000000000},
817};
818
819static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
820{ 45{
821 u32 ret; 46 u32 ret;
822 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); 47 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
@@ -825,21 +50,41 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
825 return ret; 50 return ret;
826} 51}
827 52
53static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
54{
55 u32 ret;
56 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
57 ret = RADEON_READ(RS480_NB_MC_DATA);
58 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
59 return ret;
60}
61
828static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 62static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
829{ 63{
64 u32 ret;
830 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 65 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
831 return RADEON_READ(RS690_MC_DATA); 66 ret = RADEON_READ(RS690_MC_DATA);
67 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
68 return ret;
69}
70
71static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
72{
73 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
74 return RS690_READ_MCIND(dev_priv, addr);
75 else
76 return RS480_READ_MCIND(dev_priv, addr);
832} 77}
833 78
834u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) 79u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
835{ 80{
836 81
837 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 82 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
838 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); 83 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
839 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 84 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
840 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); 85 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
841 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 86 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
842 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); 87 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
843 else 88 else
844 return RADEON_READ(RADEON_MC_FB_LOCATION); 89 return RADEON_READ(RADEON_MC_FB_LOCATION);
845} 90}
@@ -847,11 +92,11 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
847static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) 92static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
848{ 93{
849 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 94 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
850 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); 95 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
851 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 96 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
852 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); 97 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
853 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 98 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
854 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); 99 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
855 else 100 else
856 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); 101 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
857} 102}
@@ -859,15 +104,39 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
859static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) 104static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
860{ 105{
861 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 106 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
862 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); 107 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
863 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 108 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
864 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); 109 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
865 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 110 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
866 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); 111 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
867 else 112 else
868 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); 113 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
869} 114}
870 115
116static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
117{
118 u32 agp_base_hi = upper_32_bits(agp_base);
119 u32 agp_base_lo = agp_base & 0xffffffff;
120
121 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
122 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
123 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
124 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
125 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
126 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
127 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
128 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
129 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
130 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {
131 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
132 RADEON_WRITE(RS480_AGP_BASE_2, 0);
133 } else {
134 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
135 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
136 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
137 }
138}
139
871static int RADEON_READ_PLL(struct drm_device * dev, int addr) 140static int RADEON_READ_PLL(struct drm_device * dev, int addr)
872{ 141{
873 drm_radeon_private_t *dev_priv = dev->dev_private; 142 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -882,15 +151,6 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
882 return RADEON_READ(RADEON_PCIE_DATA); 151 return RADEON_READ(RADEON_PCIE_DATA);
883} 152}
884 153
885static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
886{
887 u32 ret;
888 RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
889 ret = RADEON_READ(RADEON_IGPGART_DATA);
890 RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
891 return ret;
892}
893
894#if RADEON_FIFO_DEBUG 154#if RADEON_FIFO_DEBUG
895static void radeon_status(drm_radeon_private_t * dev_priv) 155static void radeon_status(drm_radeon_private_t * dev_priv)
896{ 156{
@@ -925,16 +185,36 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
925 185
926 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 186 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
927 187
928 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); 188 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
929 tmp |= RADEON_RB3D_DC_FLUSH_ALL; 189 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
930 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); 190 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
191 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
931 192
932 for (i = 0; i < dev_priv->usec_timeout; i++) { 193 for (i = 0; i < dev_priv->usec_timeout; i++) {
933 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) 194 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
934 & RADEON_RB3D_DC_BUSY)) { 195 & RADEON_RB3D_DC_BUSY)) {
935 return 0; 196 return 0;
197 }
198 DRM_UDELAY(1);
199 }
200 } else {
201 /* 3D */
202 tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
203 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
204 RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
205
206 /* 2D */
207 tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT);
208 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
209 RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp);
210
211 for (i = 0; i < dev_priv->usec_timeout; i++) {
212 if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT)
213 & RADEON_RB3D_DC_BUSY)) {
214 return 0;
215 }
216 DRM_UDELAY(1);
936 } 217 }
937 DRM_UDELAY(1);
938 } 218 }
939 219
940#if RADEON_FIFO_DEBUG 220#if RADEON_FIFO_DEBUG
@@ -991,6 +271,50 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
991 return -EBUSY; 271 return -EBUSY;
992} 272}
993 273
274static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
275{
276 uint32_t gb_tile_config, gb_pipe_sel = 0;
277
278 /* RS4xx/RS6xx/R4xx/R5xx */
279 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
280 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
281 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
282 } else {
283 /* R3xx */
284 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
285 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
286 dev_priv->num_gb_pipes = 2;
287 } else {
288 /* R3Vxx */
289 dev_priv->num_gb_pipes = 1;
290 }
291 }
292 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
293
294 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
295
296 switch (dev_priv->num_gb_pipes) {
297 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
298 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
299 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
300 default:
301 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
302 }
303
304 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
305 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
306 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
307 }
308 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
309 radeon_do_wait_for_idle(dev_priv);
310 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
311 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
312 R300_DC_AUTOFLUSH_ENABLE |
313 R300_DC_DC_DISABLE_IGNORE_PE));
314
315
316}
317
994/* ================================================================ 318/* ================================================================
995 * CP control, initialization 319 * CP control, initialization
996 */ 320 */
@@ -1004,8 +328,22 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1004 radeon_do_wait_for_idle(dev_priv); 328 radeon_do_wait_for_idle(dev_priv);
1005 329
1006 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); 330 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
1007 331 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
1008 if (dev_priv->microcode_version == UCODE_R200) { 332 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
333 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
334 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
335 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
336 DRM_INFO("Loading R100 Microcode\n");
337 for (i = 0; i < 256; i++) {
338 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
339 R100_cp_microcode[i][1]);
340 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
341 R100_cp_microcode[i][0]);
342 }
343 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
344 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
345 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
346 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
1009 DRM_INFO("Loading R200 Microcode\n"); 347 DRM_INFO("Loading R200 Microcode\n");
1010 for (i = 0; i < 256; i++) { 348 for (i = 0; i < 256; i++) {
1011 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 349 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -1013,7 +351,11 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1013 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 351 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1014 R200_cp_microcode[i][0]); 352 R200_cp_microcode[i][0]);
1015 } 353 }
1016 } else if (dev_priv->microcode_version == UCODE_R300) { 354 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
355 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
356 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
357 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
358 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
1017 DRM_INFO("Loading R300 Microcode\n"); 359 DRM_INFO("Loading R300 Microcode\n");
1018 for (i = 0; i < 256; i++) { 360 for (i = 0; i < 256; i++) {
1019 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 361 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -1021,12 +363,35 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1021 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 363 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1022 R300_cp_microcode[i][0]); 364 R300_cp_microcode[i][0]);
1023 } 365 }
1024 } else { 366 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
367 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
368 DRM_INFO("Loading R400 Microcode\n");
1025 for (i = 0; i < 256; i++) { 369 for (i = 0; i < 256; i++) {
1026 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 370 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1027 radeon_cp_microcode[i][1]); 371 R420_cp_microcode[i][1]);
1028 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 372 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1029 radeon_cp_microcode[i][0]); 373 R420_cp_microcode[i][0]);
374 }
375 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
376 DRM_INFO("Loading RS690 Microcode\n");
377 for (i = 0; i < 256; i++) {
378 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
379 RS690_cp_microcode[i][1]);
380 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
381 RS690_cp_microcode[i][0]);
382 }
383 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
384 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
385 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
386 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
387 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
388 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
389 DRM_INFO("Loading R500 Microcode\n");
390 for (i = 0; i < 256; i++) {
391 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
392 R520_cp_microcode[i][1]);
393 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
394 R520_cp_microcode[i][0]);
1030 } 395 }
1031 } 396 }
1032} 397}
@@ -1121,12 +486,13 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1121static int radeon_do_engine_reset(struct drm_device * dev) 486static int radeon_do_engine_reset(struct drm_device * dev)
1122{ 487{
1123 drm_radeon_private_t *dev_priv = dev->dev_private; 488 drm_radeon_private_t *dev_priv = dev->dev_private;
1124 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; 489 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
1125 DRM_DEBUG("\n"); 490 DRM_DEBUG("\n");
1126 491
1127 radeon_do_pixcache_flush(dev_priv); 492 radeon_do_pixcache_flush(dev_priv);
1128 493
1129 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { 494 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
495 /* may need something similar for newer chips */
1130 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); 496 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1131 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); 497 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1132 498
@@ -1137,33 +503,39 @@ static int radeon_do_engine_reset(struct drm_device * dev)
1137 RADEON_FORCEON_YCLKB | 503 RADEON_FORCEON_YCLKB |
1138 RADEON_FORCEON_MC | 504 RADEON_FORCEON_MC |
1139 RADEON_FORCEON_AIC)); 505 RADEON_FORCEON_AIC));
506 }
1140 507
1141 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); 508 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1142 509
1143 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | 510 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1144 RADEON_SOFT_RESET_CP | 511 RADEON_SOFT_RESET_CP |
1145 RADEON_SOFT_RESET_HI | 512 RADEON_SOFT_RESET_HI |
1146 RADEON_SOFT_RESET_SE | 513 RADEON_SOFT_RESET_SE |
1147 RADEON_SOFT_RESET_RE | 514 RADEON_SOFT_RESET_RE |
1148 RADEON_SOFT_RESET_PP | 515 RADEON_SOFT_RESET_PP |
1149 RADEON_SOFT_RESET_E2 | 516 RADEON_SOFT_RESET_E2 |
1150 RADEON_SOFT_RESET_RB)); 517 RADEON_SOFT_RESET_RB));
1151 RADEON_READ(RADEON_RBBM_SOFT_RESET); 518 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1152 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 519 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1153 ~(RADEON_SOFT_RESET_CP | 520 ~(RADEON_SOFT_RESET_CP |
1154 RADEON_SOFT_RESET_HI | 521 RADEON_SOFT_RESET_HI |
1155 RADEON_SOFT_RESET_SE | 522 RADEON_SOFT_RESET_SE |
1156 RADEON_SOFT_RESET_RE | 523 RADEON_SOFT_RESET_RE |
1157 RADEON_SOFT_RESET_PP | 524 RADEON_SOFT_RESET_PP |
1158 RADEON_SOFT_RESET_E2 | 525 RADEON_SOFT_RESET_E2 |
1159 RADEON_SOFT_RESET_RB))); 526 RADEON_SOFT_RESET_RB)));
1160 RADEON_READ(RADEON_RBBM_SOFT_RESET); 527 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1161 528
529 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
1162 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); 530 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1163 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); 531 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1164 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); 532 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1165 } 533 }
1166 534
535 /* setup the raster pipes */
536 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
537 radeon_init_pipes(dev_priv);
538
1167 /* Reset the CP ring */ 539 /* Reset the CP ring */
1168 radeon_do_cp_reset(dev_priv); 540 radeon_do_cp_reset(dev_priv);
1169 541
@@ -1194,7 +566,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
1194 566
1195#if __OS_HAS_AGP 567#if __OS_HAS_AGP
1196 if (dev_priv->flags & RADEON_IS_AGP) { 568 if (dev_priv->flags & RADEON_IS_AGP) {
1197 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); 569 radeon_write_agp_base(dev_priv, dev->agp->base);
570
1198 radeon_write_agp_location(dev_priv, 571 radeon_write_agp_location(dev_priv,
1199 (((dev_priv->gart_vm_start - 1 + 572 (((dev_priv->gart_vm_start - 1 +
1200 dev_priv->gart_size) & 0xffff0000) | 573 dev_priv->gart_size) & 0xffff0000) |
@@ -1339,102 +712,70 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1339/* Enable or disable IGP GART on the chip */ 712/* Enable or disable IGP GART on the chip */
1340static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) 713static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
1341{ 714{
1342 u32 temp, tmp;
1343
1344 tmp = RADEON_READ(RADEON_AIC_CNTL);
1345 if (on) {
1346 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
1347 dev_priv->gart_vm_start,
1348 (long)dev_priv->gart_info.bus_addr,
1349 dev_priv->gart_size);
1350
1351 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
1352 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
1353 RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
1354 RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
1355 dev_priv->gart_info.bus_addr);
1356
1357 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
1358 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
1359
1360 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
1361 dev_priv->gart_size = 32*1024*1024;
1362 radeon_write_agp_location(dev_priv,
1363 (((dev_priv->gart_vm_start - 1 +
1364 dev_priv->gart_size) & 0xffff0000) |
1365 (dev_priv->gart_vm_start >> 16)));
1366
1367 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
1368 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
1369
1370 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1371 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
1372 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1373 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
1374 }
1375}
1376
1377/* Enable or disable RS690 GART on the chip */
1378static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
1379{
1380 u32 temp; 715 u32 temp;
1381 716
1382 if (on) { 717 if (on) {
1383 DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n", 718 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
1384 dev_priv->gart_vm_start, 719 dev_priv->gart_vm_start,
1385 (long)dev_priv->gart_info.bus_addr, 720 (long)dev_priv->gart_info.bus_addr,
1386 dev_priv->gart_size); 721 dev_priv->gart_size);
1387 722
1388 temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL); 723 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
1389 RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000); 724 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
725 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
726 RS690_BLOCK_GFX_D3_EN));
727 else
728 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
1390 729
1391 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, 730 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
1392 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); 731 RS480_VA_SIZE_32MB));
1393 732
1394 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID); 733 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
1395 RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800); 734 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
735 RS480_TLB_ENABLE |
736 RS480_GTW_LAC_EN |
737 RS480_1LEVEL_GART));
1396 738
1397 RS690_WRITE_MCIND(RS690_MC_GART_BASE, 739 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
1398 dev_priv->gart_info.bus_addr); 740 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
741 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
1399 742
1400 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL); 743 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
1401 RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000); 744 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
745 RS480_REQ_TYPE_SNOOP_DIS));
1402 746
1403 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, 747 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
1404 (unsigned int)dev_priv->gart_vm_start);
1405 748
1406 dev_priv->gart_size = 32*1024*1024; 749 dev_priv->gart_size = 32*1024*1024;
1407 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & 750 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
1408 0xffff0000) | (dev_priv->gart_vm_start >> 16)); 751 0xffff0000) | (dev_priv->gart_vm_start >> 16));
1409 752
1410 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp); 753 radeon_write_agp_location(dev_priv, temp);
1411 754
1412 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE); 755 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
1413 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, 756 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
1414 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); 757 RS480_VA_SIZE_32MB));
1415 758
1416 do { 759 do {
1417 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); 760 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
1418 if ((temp & RS690_MC_GART_CLEAR_STATUS) == 761 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
1419 RS690_MC_GART_CLEAR_DONE)
1420 break; 762 break;
1421 DRM_UDELAY(1); 763 DRM_UDELAY(1);
1422 } while (1); 764 } while (1);
1423 765
1424 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, 766 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
1425 RS690_MC_GART_CC_CLEAR); 767 RS480_GART_CACHE_INVALIDATE);
768
1426 do { 769 do {
1427 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); 770 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
1428 if ((temp & RS690_MC_GART_CLEAR_STATUS) == 771 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
1429 RS690_MC_GART_CLEAR_DONE)
1430 break; 772 break;
1431 DRM_UDELAY(1); 773 DRM_UDELAY(1);
1432 } while (1); 774 } while (1);
1433 775
1434 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, 776 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
1435 RS690_MC_GART_CC_NO_CHANGE);
1436 } else { 777 } else {
1437 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS); 778 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
1438 } 779 }
1439} 780}
1440 781
@@ -1472,12 +813,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1472{ 813{
1473 u32 tmp; 814 u32 tmp;
1474 815
1475 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { 816 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1476 radeon_set_rs690gart(dev_priv, on); 817 (dev_priv->flags & RADEON_IS_IGPGART)) {
1477 return;
1478 }
1479
1480 if (dev_priv->flags & RADEON_IS_IGPGART) {
1481 radeon_set_igpgart(dev_priv, on); 818 radeon_set_igpgart(dev_priv, on);
1482 return; 819 return;
1483 } 820 }
@@ -1951,6 +1288,7 @@ static int radeon_do_resume_cp(struct drm_device * dev)
1951 radeon_cp_init_ring_buffer(dev, dev_priv); 1288 radeon_cp_init_ring_buffer(dev, dev_priv);
1952 1289
1953 radeon_do_engine_reset(dev); 1290 radeon_do_engine_reset(dev);
1291 radeon_enable_interrupt(dev);
1954 1292
1955 DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1293 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1956 1294
diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h
index aab82e121e07..73ff51f12311 100644
--- a/drivers/char/drm/radeon_drm.h
+++ b/drivers/char/drm/radeon_drm.h
@@ -240,6 +240,7 @@ typedef union {
240# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 240# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
241 241
242#define R300_CMD_SCRATCH 8 242#define R300_CMD_SCRATCH 8
243#define R300_CMD_R500FP 9
243 244
244typedef union { 245typedef union {
245 unsigned int u; 246 unsigned int u;
@@ -268,6 +269,9 @@ typedef union {
268 struct { 269 struct {
269 unsigned char cmd_type, reg, n_bufs, flags; 270 unsigned char cmd_type, reg, n_bufs, flags;
270 } scratch; 271 } scratch;
272 struct {
273 unsigned char cmd_type, count, adrlo, adrhi_flags;
274 } r500fp;
271} drm_r300_cmd_header_t; 275} drm_r300_cmd_header_t;
272 276
273#define RADEON_FRONT 0x1 277#define RADEON_FRONT 0x1
@@ -278,6 +282,9 @@ typedef union {
278#define RADEON_USE_HIERZ 0x40000000 282#define RADEON_USE_HIERZ 0x40000000
279#define RADEON_USE_COMP_ZBUF 0x20000000 283#define RADEON_USE_COMP_ZBUF 0x20000000
280 284
285#define R500FP_CONSTANT_TYPE (1 << 1)
286#define R500FP_CONSTANT_CLAMP (1 << 2)
287
281/* Primitive types 288/* Primitive types
282 */ 289 */
283#define RADEON_POINTS 0x1 290#define RADEON_POINTS 0x1
@@ -669,6 +676,7 @@ typedef struct drm_radeon_indirect {
669#define RADEON_PARAM_CARD_TYPE 12 676#define RADEON_PARAM_CARD_TYPE 12
670#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ 677#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
671#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ 678#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
679#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
672 680
673typedef struct drm_radeon_getparam { 681typedef struct drm_radeon_getparam {
674 int param; 682 int param;
diff --git a/drivers/char/drm/radeon_drv.c b/drivers/char/drm/radeon_drv.c
index a2610319624d..349ac3d3b848 100644
--- a/drivers/char/drm/radeon_drv.c
+++ b/drivers/char/drm/radeon_drv.c
@@ -59,7 +59,8 @@ static struct pci_device_id pciidlist[] = {
59static struct drm_driver driver = { 59static struct drm_driver driver = {
60 .driver_features = 60 .driver_features =
61 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | 61 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
62 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED, 62 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED |
63 DRIVER_IRQ_VBL | DRIVER_IRQ_VBL2,
63 .dev_priv_size = sizeof(drm_radeon_buf_priv_t), 64 .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
64 .load = radeon_driver_load, 65 .load = radeon_driver_load,
65 .firstopen = radeon_driver_firstopen, 66 .firstopen = radeon_driver_firstopen,
@@ -68,9 +69,8 @@ static struct drm_driver driver = {
68 .postclose = radeon_driver_postclose, 69 .postclose = radeon_driver_postclose,
69 .lastclose = radeon_driver_lastclose, 70 .lastclose = radeon_driver_lastclose,
70 .unload = radeon_driver_unload, 71 .unload = radeon_driver_unload,
71 .get_vblank_counter = radeon_get_vblank_counter, 72 .vblank_wait = radeon_driver_vblank_wait,
72 .enable_vblank = radeon_enable_vblank, 73 .vblank_wait2 = radeon_driver_vblank_wait2,
73 .disable_vblank = radeon_disable_vblank,
74 .dri_library_name = dri_library_name, 74 .dri_library_name = dri_library_name,
75 .irq_preinstall = radeon_driver_irq_preinstall, 75 .irq_preinstall = radeon_driver_irq_preinstall,
76 .irq_postinstall = radeon_driver_irq_postinstall, 76 .irq_postinstall = radeon_driver_irq_postinstall,
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index b791420bd3d9..3f0eca957aa7 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -38,7 +38,7 @@
38 38
39#define DRIVER_NAME "radeon" 39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon" 40#define DRIVER_DESC "ATI Radeon"
41#define DRIVER_DATE "20060524" 41#define DRIVER_DATE "20080528"
42 42
43/* Interface history: 43/* Interface history:
44 * 44 *
@@ -98,9 +98,10 @@
98 * 1.26- Add support for variable size PCI(E) gart aperture 98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART 99 * 1.27- Add support for IGP GART
100 * 1.28- Add support for VBL on CRTC2 100 * 1.28- Add support for VBL on CRTC2
101 * 1.29- R500 3D cmd buffer support
101 */ 102 */
102#define DRIVER_MAJOR 1 103#define DRIVER_MAJOR 1
103#define DRIVER_MINOR 28 104#define DRIVER_MINOR 29
104#define DRIVER_PATCHLEVEL 0 105#define DRIVER_PATCHLEVEL 0
105 106
106/* 107/*
@@ -122,7 +123,7 @@ enum radeon_family {
122 CHIP_RV380, 123 CHIP_RV380,
123 CHIP_R420, 124 CHIP_R420,
124 CHIP_RV410, 125 CHIP_RV410,
125 CHIP_RS400, 126 CHIP_RS480,
126 CHIP_RS690, 127 CHIP_RS690,
127 CHIP_RV515, 128 CHIP_RV515,
128 CHIP_R520, 129 CHIP_R520,
@@ -294,6 +295,7 @@ typedef struct drm_radeon_private {
294 int vblank_crtc; 295 int vblank_crtc;
295 uint32_t irq_enable_reg; 296 uint32_t irq_enable_reg;
296 int irq_enabled; 297 int irq_enabled;
298 uint32_t r500_disp_irq_reg;
297 299
298 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 300 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
299 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 301 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
@@ -304,12 +306,11 @@ typedef struct drm_radeon_private {
304 306
305 u32 scratch_ages[5]; 307 u32 scratch_ages[5];
306 308
307 unsigned int crtc_last_cnt;
308 unsigned int crtc2_last_cnt;
309
310 /* starting from here on, data is preserved accross an open */ 309 /* starting from here on, data is preserved accross an open */
311 uint32_t flags; /* see radeon_chip_flags */ 310 uint32_t flags; /* see radeon_chip_flags */
312 unsigned long fb_aper_offset; 311 unsigned long fb_aper_offset;
312
313 int num_gb_pipes;
313} drm_radeon_private_t; 314} drm_radeon_private_t;
314 315
315typedef struct drm_radeon_buf_priv { 316typedef struct drm_radeon_buf_priv {
@@ -377,14 +378,15 @@ extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *
377extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 378extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
378 379
379extern void radeon_do_release(struct drm_device * dev); 380extern void radeon_do_release(struct drm_device * dev);
380extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 381extern int radeon_driver_vblank_wait(struct drm_device * dev,
381extern int radeon_enable_vblank(struct drm_device *dev, int crtc); 382 unsigned int *sequence);
382extern void radeon_disable_vblank(struct drm_device *dev, int crtc); 383extern int radeon_driver_vblank_wait2(struct drm_device * dev,
383extern void radeon_do_release(struct drm_device * dev); 384 unsigned int *sequence);
384extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 385extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
385extern void radeon_driver_irq_preinstall(struct drm_device * dev); 386extern void radeon_driver_irq_preinstall(struct drm_device * dev);
386extern int radeon_driver_irq_postinstall(struct drm_device * dev); 387extern void radeon_driver_irq_postinstall(struct drm_device * dev);
387extern void radeon_driver_irq_uninstall(struct drm_device * dev); 388extern void radeon_driver_irq_uninstall(struct drm_device * dev);
389extern void radeon_enable_interrupt(struct drm_device *dev);
388extern int radeon_vblank_crtc_get(struct drm_device *dev); 390extern int radeon_vblank_crtc_get(struct drm_device *dev);
389extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 391extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
390 392
@@ -447,13 +449,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
447#define RADEON_PCIE_DATA 0x0034 449#define RADEON_PCIE_DATA 0x0034
448#define RADEON_PCIE_TX_GART_CNTL 0x10 450#define RADEON_PCIE_TX_GART_CNTL 0x10
449# define RADEON_PCIE_TX_GART_EN (1 << 0) 451# define RADEON_PCIE_TX_GART_EN (1 << 0)
450# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) 452# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
451# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) 453# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
452# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) 454# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
453# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3) 455# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
454# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3) 456# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
455# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5) 457# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
456# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) 458# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
457#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 459#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
458#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 460#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
459#define RADEON_PCIE_TX_GART_BASE 0x13 461#define RADEON_PCIE_TX_GART_BASE 0x13
@@ -462,14 +464,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
462#define RADEON_PCIE_TX_GART_END_LO 0x16 464#define RADEON_PCIE_TX_GART_END_LO 0x16
463#define RADEON_PCIE_TX_GART_END_HI 0x17 465#define RADEON_PCIE_TX_GART_END_HI 0x17
464 466
465#define RADEON_IGPGART_INDEX 0x168 467#define RS480_NB_MC_INDEX 0x168
466#define RADEON_IGPGART_DATA 0x16c 468# define RS480_NB_MC_IND_WR_EN (1 << 8)
467#define RADEON_IGPGART_UNK_18 0x18 469#define RS480_NB_MC_DATA 0x16c
468#define RADEON_IGPGART_CTRL 0x2b
469#define RADEON_IGPGART_BASE_ADDR 0x2c
470#define RADEON_IGPGART_FLUSH 0x2e
471#define RADEON_IGPGART_ENABLE 0x38
472#define RADEON_IGPGART_UNK_39 0x39
473 470
474#define RS690_MC_INDEX 0x78 471#define RS690_MC_INDEX 0x78
475# define RS690_MC_INDEX_MASK 0x1ff 472# define RS690_MC_INDEX_MASK 0x1ff
@@ -477,45 +474,91 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
477# define RS690_MC_INDEX_WR_ACK 0x7f 474# define RS690_MC_INDEX_WR_ACK 0x7f
478#define RS690_MC_DATA 0x7c 475#define RS690_MC_DATA 0x7c
479 476
480#define RS690_MC_MISC_CNTL 0x18 477/* MC indirect registers */
481#define RS690_MC_GART_FEATURE_ID 0x2b 478#define RS480_MC_MISC_CNTL 0x18
482#define RS690_MC_GART_BASE 0x2c 479# define RS480_DISABLE_GTW (1 << 1)
483#define RS690_MC_GART_CACHE_CNTL 0x2e 480/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
484# define RS690_MC_GART_CC_NO_CHANGE 0x0 481# define RS480_GART_INDEX_REG_EN (1 << 12)
485# define RS690_MC_GART_CC_CLEAR 0x1 482# define RS690_BLOCK_GFX_D3_EN (1 << 14)
486# define RS690_MC_GART_CLEAR_STATUS (1 << 1) 483#define RS480_K8_FB_LOCATION 0x1e
487# define RS690_MC_GART_CLEAR_DONE (0 << 1) 484#define RS480_GART_FEATURE_ID 0x2b
488# define RS690_MC_GART_CLEAR_PENDING (1 << 1) 485# define RS480_HANG_EN (1 << 11)
489#define RS690_MC_AGP_SIZE 0x38 486# define RS480_TLB_ENABLE (1 << 18)
490# define RS690_MC_GART_DIS 0x0 487# define RS480_P2P_ENABLE (1 << 19)
491# define RS690_MC_GART_EN 0x1 488# define RS480_GTW_LAC_EN (1 << 25)
492# define RS690_MC_AGP_SIZE_32MB (0 << 1) 489# define RS480_2LEVEL_GART (0 << 30)
493# define RS690_MC_AGP_SIZE_64MB (1 << 1) 490# define RS480_1LEVEL_GART (1 << 30)
494# define RS690_MC_AGP_SIZE_128MB (2 << 1) 491# define RS480_PDC_EN (1 << 31)
495# define RS690_MC_AGP_SIZE_256MB (3 << 1) 492#define RS480_GART_BASE 0x2c
496# define RS690_MC_AGP_SIZE_512MB (4 << 1) 493#define RS480_GART_CACHE_CNTRL 0x2e
497# define RS690_MC_AGP_SIZE_1GB (5 << 1) 494# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
498# define RS690_MC_AGP_SIZE_2GB (6 << 1) 495#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
499#define RS690_MC_AGP_MODE_CONTROL 0x39 496# define RS480_GART_EN (1 << 0)
497# define RS480_VA_SIZE_32MB (0 << 1)
498# define RS480_VA_SIZE_64MB (1 << 1)
499# define RS480_VA_SIZE_128MB (2 << 1)
500# define RS480_VA_SIZE_256MB (3 << 1)
501# define RS480_VA_SIZE_512MB (4 << 1)
502# define RS480_VA_SIZE_1GB (5 << 1)
503# define RS480_VA_SIZE_2GB (6 << 1)
504#define RS480_AGP_MODE_CNTL 0x39
505# define RS480_POST_GART_Q_SIZE (1 << 18)
506# define RS480_NONGART_SNOOP (1 << 19)
507# define RS480_AGP_RD_BUF_SIZE (1 << 20)
508# define RS480_REQ_TYPE_SNOOP_SHIFT 22
509# define RS480_REQ_TYPE_SNOOP_MASK 0x3
510# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
511#define RS480_MC_MISC_UMA_CNTL 0x5f
512#define RS480_MC_MCLK_CNTL 0x7a
513#define RS480_MC_UMA_DUALCH_CNTL 0x86
514
500#define RS690_MC_FB_LOCATION 0x100 515#define RS690_MC_FB_LOCATION 0x100
501#define RS690_MC_AGP_LOCATION 0x101 516#define RS690_MC_AGP_LOCATION 0x101
502#define RS690_MC_AGP_BASE 0x102 517#define RS690_MC_AGP_BASE 0x102
518#define RS690_MC_AGP_BASE_2 0x103
503 519
504#define R520_MC_IND_INDEX 0x70 520#define R520_MC_IND_INDEX 0x70
505#define R520_MC_IND_WR_EN (1<<24) 521#define R520_MC_IND_WR_EN (1 << 24)
506#define R520_MC_IND_DATA 0x74 522#define R520_MC_IND_DATA 0x74
507 523
508#define RV515_MC_FB_LOCATION 0x01 524#define RV515_MC_FB_LOCATION 0x01
509#define RV515_MC_AGP_LOCATION 0x02 525#define RV515_MC_AGP_LOCATION 0x02
526#define RV515_MC_AGP_BASE 0x03
527#define RV515_MC_AGP_BASE_2 0x04
510 528
511#define R520_MC_FB_LOCATION 0x04 529#define R520_MC_FB_LOCATION 0x04
512#define R520_MC_AGP_LOCATION 0x05 530#define R520_MC_AGP_LOCATION 0x05
531#define R520_MC_AGP_BASE 0x06
532#define R520_MC_AGP_BASE_2 0x07
513 533
514#define RADEON_MPP_TB_CONFIG 0x01c0 534#define RADEON_MPP_TB_CONFIG 0x01c0
515#define RADEON_MEM_CNTL 0x0140 535#define RADEON_MEM_CNTL 0x0140
516#define RADEON_MEM_SDRAM_MODE_REG 0x0158 536#define RADEON_MEM_SDRAM_MODE_REG 0x0158
537#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
538#define RS480_AGP_BASE_2 0x0164
517#define RADEON_AGP_BASE 0x0170 539#define RADEON_AGP_BASE 0x0170
518 540
541/* pipe config regs */
542#define R400_GB_PIPE_SELECT 0x402c
543#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
544#define R500_SU_REG_DEST 0x42c8
545#define R300_GB_TILE_CONFIG 0x4018
546# define R300_ENABLE_TILING (1 << 0)
547# define R300_PIPE_COUNT_RV350 (0 << 1)
548# define R300_PIPE_COUNT_R300 (3 << 1)
549# define R300_PIPE_COUNT_R420_3P (6 << 1)
550# define R300_PIPE_COUNT_R420 (7 << 1)
551# define R300_TILE_SIZE_8 (0 << 4)
552# define R300_TILE_SIZE_16 (1 << 4)
553# define R300_TILE_SIZE_32 (2 << 4)
554# define R300_SUBPIXEL_1_12 (0 << 16)
555# define R300_SUBPIXEL_1_16 (1 << 16)
556#define R300_DST_PIPE_CONFIG 0x170c
557# define R300_PIPE_AUTO_CONFIG (1 << 31)
558#define R300_RB2D_DSTCACHE_MODE 0x3428
559# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
560# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
561
519#define RADEON_RB3D_COLOROFFSET 0x1c40 562#define RADEON_RB3D_COLOROFFSET 0x1c40
520#define RADEON_RB3D_COLORPITCH 0x1c48 563#define RADEON_RB3D_COLORPITCH 0x1c48
521 564
@@ -561,12 +604,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
561 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 604 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
562 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 605 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
563 606
564#define RADEON_CRTC_CRNT_FRAME 0x0214
565#define RADEON_CRTC2_CRNT_FRAME 0x0314
566
567#define RADEON_CRTC_STATUS 0x005c
568#define RADEON_CRTC2_STATUS 0x03fc
569
570#define RADEON_GEN_INT_CNTL 0x0040 607#define RADEON_GEN_INT_CNTL 0x0040
571# define RADEON_CRTC_VBLANK_MASK (1 << 0) 608# define RADEON_CRTC_VBLANK_MASK (1 << 0)
572# define RADEON_CRTC2_VBLANK_MASK (1 << 9) 609# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
@@ -625,11 +662,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
625#define RADEON_PP_TXFILTER_1 0x1c6c 662#define RADEON_PP_TXFILTER_1 0x1c6c
626#define RADEON_PP_TXFILTER_2 0x1c84 663#define RADEON_PP_TXFILTER_2 0x1c84
627 664
628#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 665#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
629# define RADEON_RB2D_DC_FLUSH (3 << 0) 666#define R300_DSTCACHE_CTLSTAT 0x1714
630# define RADEON_RB2D_DC_FREE (3 << 2) 667# define R300_RB2D_DC_FLUSH (3 << 0)
631# define RADEON_RB2D_DC_FLUSH_ALL 0xf 668# define R300_RB2D_DC_FREE (3 << 2)
632# define RADEON_RB2D_DC_BUSY (1 << 31) 669# define R300_RB2D_DC_FLUSH_ALL 0xf
670# define R300_RB2D_DC_BUSY (1 << 31)
633#define RADEON_RB3D_CNTL 0x1c3c 671#define RADEON_RB3D_CNTL 0x1c3c
634# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 672# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
635# define RADEON_PLANE_MASK_ENABLE (1 << 1) 673# define RADEON_PLANE_MASK_ENABLE (1 << 1)
@@ -652,11 +690,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
652# define RADEON_RB3D_ZC_FREE (1 << 2) 690# define RADEON_RB3D_ZC_FREE (1 << 2)
653# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 691# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
654# define RADEON_RB3D_ZC_BUSY (1 << 31) 692# define RADEON_RB3D_ZC_BUSY (1 << 31)
693#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
694# define R300_ZC_FLUSH (1 << 0)
695# define R300_ZC_FREE (1 << 1)
696# define R300_ZC_FLUSH_ALL 0x3
697# define R300_ZC_BUSY (1 << 31)
655#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 698#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
656# define RADEON_RB3D_DC_FLUSH (3 << 0) 699# define RADEON_RB3D_DC_FLUSH (3 << 0)
657# define RADEON_RB3D_DC_FREE (3 << 2) 700# define RADEON_RB3D_DC_FREE (3 << 2)
658# define RADEON_RB3D_DC_FLUSH_ALL 0xf 701# define RADEON_RB3D_DC_FLUSH_ALL 0xf
659# define RADEON_RB3D_DC_BUSY (1 << 31) 702# define RADEON_RB3D_DC_BUSY (1 << 31)
703#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
704# define R300_RB3D_DC_FINISH (1 << 4)
660#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 705#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
661# define RADEON_Z_TEST_MASK (7 << 4) 706# define RADEON_Z_TEST_MASK (7 << 4)
662# define RADEON_Z_TEST_ALWAYS (7 << 4) 707# define RADEON_Z_TEST_ALWAYS (7 << 4)
@@ -1066,6 +1111,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
1066 1111
1067#define R200_VAP_PVS_CNTL_1 0x22D0 1112#define R200_VAP_PVS_CNTL_1 0x22D0
1068 1113
1114#define R500_D1CRTC_STATUS 0x609c
1115#define R500_D2CRTC_STATUS 0x689c
1116#define R500_CRTC_V_BLANK (1<<0)
1117
1118#define R500_D1CRTC_FRAME_COUNT 0x60a4
1119#define R500_D2CRTC_FRAME_COUNT 0x68a4
1120
1121#define R500_D1MODE_V_COUNTER 0x6530
1122#define R500_D2MODE_V_COUNTER 0x6d30
1123
1124#define R500_D1MODE_VBLANK_STATUS 0x6534
1125#define R500_D2MODE_VBLANK_STATUS 0x6d34
1126#define R500_VBLANK_OCCURED (1<<0)
1127#define R500_VBLANK_ACK (1<<4)
1128#define R500_VBLANK_STAT (1<<12)
1129#define R500_VBLANK_INT (1<<16)
1130
1131#define R500_DxMODE_INT_MASK 0x6540
1132#define R500_D1MODE_INT_MASK (1<<0)
1133#define R500_D2MODE_INT_MASK (1<<8)
1134
1135#define R500_DISP_INTERRUPT_STATUS 0x7edc
1136#define R500_D1_VBLANK_INTERRUPT (1 << 4)
1137#define R500_D2_VBLANK_INTERRUPT (1 << 5)
1138
1069/* Constants */ 1139/* Constants */
1070#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1140#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1071 1141
@@ -1087,42 +1157,50 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
1087#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1157#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1088#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1158#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1089 1159
1090#define RADEON_WRITE_PLL( addr, val ) \ 1160#define RADEON_WRITE_PLL(addr, val) \
1091do { \ 1161do { \
1092 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 1162 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1093 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1163 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1094 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 1164 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1095} while (0) 1165} while (0)
1096 1166
1097#define RADEON_WRITE_IGPGART( addr, val ) \ 1167#define RADEON_WRITE_PCIE(addr, val) \
1098do { \ 1168do { \
1099 RADEON_WRITE( RADEON_IGPGART_INDEX, \ 1169 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1100 ((addr) & 0x7f) | (1 << 8)); \ 1170 ((addr) & 0xff)); \
1101 RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \ 1171 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1102 RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
1103} while (0) 1172} while (0)
1104 1173
1105#define RADEON_WRITE_PCIE( addr, val ) \ 1174#define R500_WRITE_MCIND(addr, val) \
1106do { \ 1175do { \
1107 RADEON_WRITE8( RADEON_PCIE_INDEX, \ 1176 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1108 ((addr) & 0xff)); \ 1177 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1109 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 1178 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1110} while (0) 1179} while (0)
1111 1180
1112#define RADEON_WRITE_MCIND( addr, val ) \ 1181#define RS480_WRITE_MCIND(addr, val) \
1113 do { \ 1182do { \
1114 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1183 RADEON_WRITE(RS480_NB_MC_INDEX, \
1115 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1184 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1116 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1185 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1117 } while (0) 1186 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1187} while (0)
1118 1188
1119#define RS690_WRITE_MCIND( addr, val ) \ 1189#define RS690_WRITE_MCIND(addr, val) \
1120do { \ 1190do { \
1121 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1191 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1122 RADEON_WRITE(RS690_MC_DATA, val); \ 1192 RADEON_WRITE(RS690_MC_DATA, val); \
1123 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1193 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1124} while (0) 1194} while (0)
1125 1195
1196#define IGP_WRITE_MCIND(addr, val) \
1197do { \
1198 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
1199 RS690_WRITE_MCIND(addr, val); \
1200 else \
1201 RS480_WRITE_MCIND(addr, val); \
1202} while (0)
1203
1126#define CP_PACKET0( reg, n ) \ 1204#define CP_PACKET0( reg, n ) \
1127 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1205 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1128#define CP_PACKET0_TABLE( reg, n ) \ 1206#define CP_PACKET0_TABLE( reg, n ) \
@@ -1163,23 +1241,43 @@ do { \
1163} while (0) 1241} while (0)
1164 1242
1165#define RADEON_FLUSH_CACHE() do { \ 1243#define RADEON_FLUSH_CACHE() do { \
1166 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ 1244 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1167 OUT_RING( RADEON_RB3D_DC_FLUSH ); \ 1245 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1246 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1247 } else { \
1248 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1249 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1250 } \
1168} while (0) 1251} while (0)
1169 1252
1170#define RADEON_PURGE_CACHE() do { \ 1253#define RADEON_PURGE_CACHE() do { \
1171 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ 1254 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1172 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \ 1255 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1256 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1257 } else { \
1258 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1259 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1260 } \
1173} while (0) 1261} while (0)
1174 1262
1175#define RADEON_FLUSH_ZCACHE() do { \ 1263#define RADEON_FLUSH_ZCACHE() do { \
1176 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1264 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1177 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 1265 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1266 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1267 } else { \
1268 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1269 OUT_RING(R300_ZC_FLUSH); \
1270 } \
1178} while (0) 1271} while (0)
1179 1272
1180#define RADEON_PURGE_ZCACHE() do { \ 1273#define RADEON_PURGE_ZCACHE() do { \
1181 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1274 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1182 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 1275 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1276 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
1277 } else { \
1278 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1279 OUT_RING(R300_ZC_FLUSH_ALL); \
1280 } \
1183} while (0) 1281} while (0)
1184 1282
1185/* ================================================================ 1283/* ================================================================
diff --git a/drivers/char/drm/radeon_irq.c b/drivers/char/drm/radeon_irq.c
index 507d6b747a13..ee40d197deb7 100644
--- a/drivers/char/drm/radeon_irq.c
+++ b/drivers/char/drm/radeon_irq.c
@@ -35,61 +35,12 @@
35#include "radeon_drm.h" 35#include "radeon_drm.h"
36#include "radeon_drv.h" 36#include "radeon_drv.h"
37 37
38static void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state) 38static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv,
39 u32 mask)
39{ 40{
40 drm_radeon_private_t *dev_priv = dev->dev_private; 41 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask;
41
42 if (state)
43 dev_priv->irq_enable_reg |= mask;
44 else
45 dev_priv->irq_enable_reg &= ~mask;
46
47 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
48}
49
50int radeon_enable_vblank(struct drm_device *dev, int crtc)
51{
52 switch (crtc) {
53 case 0:
54 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
55 break;
56 case 1:
57 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
58 break;
59 default:
60 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
61 crtc);
62 return EINVAL;
63 }
64
65 return 0;
66}
67
68void radeon_disable_vblank(struct drm_device *dev, int crtc)
69{
70 switch (crtc) {
71 case 0:
72 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
73 break;
74 case 1:
75 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
76 break;
77 default:
78 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
79 crtc);
80 break;
81 }
82}
83
84static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv)
85{
86 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) &
87 (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
88 RADEON_CRTC2_VBLANK_STAT);
89
90 if (irqs) 42 if (irqs)
91 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs); 43 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
92
93 return irqs; 44 return irqs;
94} 45}
95 46
@@ -121,21 +72,39 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
121 /* Only consider the bits we're interested in - others could be used 72 /* Only consider the bits we're interested in - others could be used
122 * outside the DRM 73 * outside the DRM
123 */ 74 */
124 stat = radeon_acknowledge_irqs(dev_priv); 75 stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
76 RADEON_CRTC_VBLANK_STAT |
77 RADEON_CRTC2_VBLANK_STAT));
125 if (!stat) 78 if (!stat)
126 return IRQ_NONE; 79 return IRQ_NONE;
127 80
128 stat &= dev_priv->irq_enable_reg; 81 stat &= dev_priv->irq_enable_reg;
129 82
130 /* SW interrupt */ 83 /* SW interrupt */
131 if (stat & RADEON_SW_INT_TEST) 84 if (stat & RADEON_SW_INT_TEST) {
132 DRM_WAKEUP(&dev_priv->swi_queue); 85 DRM_WAKEUP(&dev_priv->swi_queue);
86 }
133 87
134 /* VBLANK interrupt */ 88 /* VBLANK interrupt */
135 if (stat & RADEON_CRTC_VBLANK_STAT) 89 if (stat & (RADEON_CRTC_VBLANK_STAT|RADEON_CRTC2_VBLANK_STAT)) {
136 drm_handle_vblank(dev, 0); 90 int vblank_crtc = dev_priv->vblank_crtc;
137 if (stat & RADEON_CRTC2_VBLANK_STAT) 91
138 drm_handle_vblank(dev, 1); 92 if ((vblank_crtc &
93 (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) ==
94 (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
95 if (stat & RADEON_CRTC_VBLANK_STAT)
96 atomic_inc(&dev->vbl_received);
97 if (stat & RADEON_CRTC2_VBLANK_STAT)
98 atomic_inc(&dev->vbl_received2);
99 } else if (((stat & RADEON_CRTC_VBLANK_STAT) &&
100 (vblank_crtc & DRM_RADEON_VBLANK_CRTC1)) ||
101 ((stat & RADEON_CRTC2_VBLANK_STAT) &&
102 (vblank_crtc & DRM_RADEON_VBLANK_CRTC2)))
103 atomic_inc(&dev->vbl_received);
104
105 DRM_WAKEUP(&dev->vbl_queue);
106 drm_vbl_send_signals(dev);
107 }
139 108
140 return IRQ_HANDLED; 109 return IRQ_HANDLED;
141} 110}
@@ -175,27 +144,54 @@ static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
175 return ret; 144 return ret;
176} 145}
177 146
178u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc) 147static int radeon_driver_vblank_do_wait(struct drm_device * dev,
148 unsigned int *sequence, int crtc)
179{ 149{
180 drm_radeon_private_t *dev_priv = dev->dev_private; 150 drm_radeon_private_t *dev_priv =
181 u32 crtc_cnt_reg, crtc_status_reg; 151 (drm_radeon_private_t *) dev->dev_private;
182 152 unsigned int cur_vblank;
153 int ret = 0;
154 int ack = 0;
155 atomic_t *counter;
183 if (!dev_priv) { 156 if (!dev_priv) {
184 DRM_ERROR("called with no initialization\n"); 157 DRM_ERROR("called with no initialization\n");
185 return -EINVAL; 158 return -EINVAL;
186 } 159 }
187 160
188 if (crtc == 0) { 161 if (crtc == DRM_RADEON_VBLANK_CRTC1) {
189 crtc_cnt_reg = RADEON_CRTC_CRNT_FRAME; 162 counter = &dev->vbl_received;
190 crtc_status_reg = RADEON_CRTC_STATUS; 163 ack |= RADEON_CRTC_VBLANK_STAT;
191 } else if (crtc == 1) { 164 } else if (crtc == DRM_RADEON_VBLANK_CRTC2) {
192 crtc_cnt_reg = RADEON_CRTC2_CRNT_FRAME; 165 counter = &dev->vbl_received2;
193 crtc_status_reg = RADEON_CRTC2_STATUS; 166 ack |= RADEON_CRTC2_VBLANK_STAT;
194 } else { 167 } else
195 return -EINVAL; 168 return -EINVAL;
196 }
197 169
198 return RADEON_READ(crtc_cnt_reg) + (RADEON_READ(crtc_status_reg) & 1); 170 radeon_acknowledge_irqs(dev_priv, ack);
171
172 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
173
174 /* Assume that the user has missed the current sequence number
175 * by about a day rather than she wants to wait for years
176 * using vertical blanks...
177 */
178 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
179 (((cur_vblank = atomic_read(counter))
180 - *sequence) <= (1 << 23)));
181
182 *sequence = cur_vblank;
183
184 return ret;
185}
186
187int radeon_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
188{
189 return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC1);
190}
191
192int radeon_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
193{
194 return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC2);
199} 195}
200 196
201/* Needs the lock as it touches the ring. 197/* Needs the lock as it touches the ring.
@@ -238,6 +234,21 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr
238 return radeon_wait_irq(dev, irqwait->irq_seq); 234 return radeon_wait_irq(dev, irqwait->irq_seq);
239} 235}
240 236
237void radeon_enable_interrupt(struct drm_device *dev)
238{
239 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
240
241 dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
242 if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1)
243 dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
244
245 if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2)
246 dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
247
248 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
249 dev_priv->irq_enabled = 1;
250}
251
241/* drm_dma.h hooks 252/* drm_dma.h hooks
242*/ 253*/
243void radeon_driver_irq_preinstall(struct drm_device * dev) 254void radeon_driver_irq_preinstall(struct drm_device * dev)
@@ -249,27 +260,20 @@ void radeon_driver_irq_preinstall(struct drm_device * dev)
249 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 260 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
250 261
251 /* Clear bits if they're already high */ 262 /* Clear bits if they're already high */
252 radeon_acknowledge_irqs(dev_priv); 263 radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
264 RADEON_CRTC_VBLANK_STAT |
265 RADEON_CRTC2_VBLANK_STAT));
253} 266}
254 267
255int radeon_driver_irq_postinstall(struct drm_device * dev) 268void radeon_driver_irq_postinstall(struct drm_device * dev)
256{ 269{
257 drm_radeon_private_t *dev_priv = 270 drm_radeon_private_t *dev_priv =
258 (drm_radeon_private_t *) dev->dev_private; 271 (drm_radeon_private_t *) dev->dev_private;
259 int ret;
260 272
261 atomic_set(&dev_priv->swi_emitted, 0); 273 atomic_set(&dev_priv->swi_emitted, 0);
262 DRM_INIT_WAITQUEUE(&dev_priv->swi_queue); 274 DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
263 275
264 ret = drm_vblank_init(dev, 2); 276 radeon_enable_interrupt(dev);
265 if (ret)
266 return ret;
267
268 dev->max_vblank_count = 0x001fffff;
269
270 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
271
272 return 0;
273} 277}
274 278
275void radeon_driver_irq_uninstall(struct drm_device * dev) 279void radeon_driver_irq_uninstall(struct drm_device * dev)
@@ -311,5 +315,6 @@ int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
311 return -EINVAL; 315 return -EINVAL;
312 } 316 }
313 dev_priv->vblank_crtc = (unsigned int)value; 317 dev_priv->vblank_crtc = (unsigned int)value;
318 radeon_enable_interrupt(dev);
314 return 0; 319 return 0;
315} 320}
diff --git a/drivers/char/drm/radeon_microcode.h b/drivers/char/drm/radeon_microcode.h
new file mode 100644
index 000000000000..a348c9e7db1c
--- /dev/null
+++ b/drivers/char/drm/radeon_microcode.h
@@ -0,0 +1,1844 @@
1/*
2 * Copyright 2007 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
20 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#ifndef RADEON_MICROCODE_H
27#define RADEON_MICROCODE_H
28
29/* production radeon ucode r1xx-r6xx */
30static const u32 R100_cp_microcode[][2] = {
31 { 0x21007000, 0000000000 },
32 { 0x20007000, 0000000000 },
33 { 0x000000b4, 0x00000004 },
34 { 0x000000b8, 0x00000004 },
35 { 0x6f5b4d4c, 0000000000 },
36 { 0x4c4c427f, 0000000000 },
37 { 0x5b568a92, 0000000000 },
38 { 0x4ca09c6d, 0000000000 },
39 { 0xad4c4c4c, 0000000000 },
40 { 0x4ce1af3d, 0000000000 },
41 { 0xd8afafaf, 0000000000 },
42 { 0xd64c4cdc, 0000000000 },
43 { 0x4cd10d10, 0000000000 },
44 { 0x000f0000, 0x00000016 },
45 { 0x362f242d, 0000000000 },
46 { 0x00000012, 0x00000004 },
47 { 0x000f0000, 0x00000016 },
48 { 0x362f282d, 0000000000 },
49 { 0x000380e7, 0x00000002 },
50 { 0x04002c97, 0x00000002 },
51 { 0x000f0001, 0x00000016 },
52 { 0x333a3730, 0000000000 },
53 { 0x000077ef, 0x00000002 },
54 { 0x00061000, 0x00000002 },
55 { 0x00000021, 0x0000001a },
56 { 0x00004000, 0x0000001e },
57 { 0x00061000, 0x00000002 },
58 { 0x00000021, 0x0000001a },
59 { 0x00004000, 0x0000001e },
60 { 0x00061000, 0x00000002 },
61 { 0x00000021, 0x0000001a },
62 { 0x00004000, 0x0000001e },
63 { 0x00000017, 0x00000004 },
64 { 0x0003802b, 0x00000002 },
65 { 0x040067e0, 0x00000002 },
66 { 0x00000017, 0x00000004 },
67 { 0x000077e0, 0x00000002 },
68 { 0x00065000, 0x00000002 },
69 { 0x000037e1, 0x00000002 },
70 { 0x040067e1, 0x00000006 },
71 { 0x000077e0, 0x00000002 },
72 { 0x000077e1, 0x00000002 },
73 { 0x000077e1, 0x00000006 },
74 { 0xffffffff, 0000000000 },
75 { 0x10000000, 0000000000 },
76 { 0x0003802b, 0x00000002 },
77 { 0x040067e0, 0x00000006 },
78 { 0x00007675, 0x00000002 },
79 { 0x00007676, 0x00000002 },
80 { 0x00007677, 0x00000002 },
81 { 0x00007678, 0x00000006 },
82 { 0x0003802c, 0x00000002 },
83 { 0x04002676, 0x00000002 },
84 { 0x00007677, 0x00000002 },
85 { 0x00007678, 0x00000006 },
86 { 0x0000002f, 0x00000018 },
87 { 0x0000002f, 0x00000018 },
88 { 0000000000, 0x00000006 },
89 { 0x00000030, 0x00000018 },
90 { 0x00000030, 0x00000018 },
91 { 0000000000, 0x00000006 },
92 { 0x01605000, 0x00000002 },
93 { 0x00065000, 0x00000002 },
94 { 0x00098000, 0x00000002 },
95 { 0x00061000, 0x00000002 },
96 { 0x64c0603e, 0x00000004 },
97 { 0x000380e6, 0x00000002 },
98 { 0x040025c5, 0x00000002 },
99 { 0x00080000, 0x00000016 },
100 { 0000000000, 0000000000 },
101 { 0x0400251d, 0x00000002 },
102 { 0x00007580, 0x00000002 },
103 { 0x00067581, 0x00000002 },
104 { 0x04002580, 0x00000002 },
105 { 0x00067581, 0x00000002 },
106 { 0x00000049, 0x00000004 },
107 { 0x00005000, 0000000000 },
108 { 0x000380e6, 0x00000002 },
109 { 0x040025c5, 0x00000002 },
110 { 0x00061000, 0x00000002 },
111 { 0x0000750e, 0x00000002 },
112 { 0x00019000, 0x00000002 },
113 { 0x00011055, 0x00000014 },
114 { 0x00000055, 0x00000012 },
115 { 0x0400250f, 0x00000002 },
116 { 0x0000504f, 0x00000004 },
117 { 0x000380e6, 0x00000002 },
118 { 0x040025c5, 0x00000002 },
119 { 0x00007565, 0x00000002 },
120 { 0x00007566, 0x00000002 },
121 { 0x00000058, 0x00000004 },
122 { 0x000380e6, 0x00000002 },
123 { 0x040025c5, 0x00000002 },
124 { 0x01e655b4, 0x00000002 },
125 { 0x4401b0e4, 0x00000002 },
126 { 0x01c110e4, 0x00000002 },
127 { 0x26667066, 0x00000018 },
128 { 0x040c2565, 0x00000002 },
129 { 0x00000066, 0x00000018 },
130 { 0x04002564, 0x00000002 },
131 { 0x00007566, 0x00000002 },
132 { 0x0000005d, 0x00000004 },
133 { 0x00401069, 0x00000008 },
134 { 0x00101000, 0x00000002 },
135 { 0x000d80ff, 0x00000002 },
136 { 0x0080006c, 0x00000008 },
137 { 0x000f9000, 0x00000002 },
138 { 0x000e00ff, 0x00000002 },
139 { 0000000000, 0x00000006 },
140 { 0x0000008f, 0x00000018 },
141 { 0x0000005b, 0x00000004 },
142 { 0x000380e6, 0x00000002 },
143 { 0x040025c5, 0x00000002 },
144 { 0x00007576, 0x00000002 },
145 { 0x00065000, 0x00000002 },
146 { 0x00009000, 0x00000002 },
147 { 0x00041000, 0x00000002 },
148 { 0x0c00350e, 0x00000002 },
149 { 0x00049000, 0x00000002 },
150 { 0x00051000, 0x00000002 },
151 { 0x01e785f8, 0x00000002 },
152 { 0x00200000, 0x00000002 },
153 { 0x0060007e, 0x0000000c },
154 { 0x00007563, 0x00000002 },
155 { 0x006075f0, 0x00000021 },
156 { 0x20007073, 0x00000004 },
157 { 0x00005073, 0x00000004 },
158 { 0x000380e6, 0x00000002 },
159 { 0x040025c5, 0x00000002 },
160 { 0x00007576, 0x00000002 },
161 { 0x00007577, 0x00000002 },
162 { 0x0000750e, 0x00000002 },
163 { 0x0000750f, 0x00000002 },
164 { 0x00a05000, 0x00000002 },
165 { 0x00600083, 0x0000000c },
166 { 0x006075f0, 0x00000021 },
167 { 0x000075f8, 0x00000002 },
168 { 0x00000083, 0x00000004 },
169 { 0x000a750e, 0x00000002 },
170 { 0x000380e6, 0x00000002 },
171 { 0x040025c5, 0x00000002 },
172 { 0x0020750f, 0x00000002 },
173 { 0x00600086, 0x00000004 },
174 { 0x00007570, 0x00000002 },
175 { 0x00007571, 0x00000002 },
176 { 0x00007572, 0x00000006 },
177 { 0x000380e6, 0x00000002 },
178 { 0x040025c5, 0x00000002 },
179 { 0x00005000, 0x00000002 },
180 { 0x00a05000, 0x00000002 },
181 { 0x00007568, 0x00000002 },
182 { 0x00061000, 0x00000002 },
183 { 0x00000095, 0x0000000c },
184 { 0x00058000, 0x00000002 },
185 { 0x0c607562, 0x00000002 },
186 { 0x00000097, 0x00000004 },
187 { 0x000380e6, 0x00000002 },
188 { 0x040025c5, 0x00000002 },
189 { 0x00600096, 0x00000004 },
190 { 0x400070e5, 0000000000 },
191 { 0x000380e6, 0x00000002 },
192 { 0x040025c5, 0x00000002 },
193 { 0x000380e5, 0x00000002 },
194 { 0x000000a8, 0x0000001c },
195 { 0x000650aa, 0x00000018 },
196 { 0x040025bb, 0x00000002 },
197 { 0x000610ab, 0x00000018 },
198 { 0x040075bc, 0000000000 },
199 { 0x000075bb, 0x00000002 },
200 { 0x000075bc, 0000000000 },
201 { 0x00090000, 0x00000006 },
202 { 0x00090000, 0x00000002 },
203 { 0x000d8002, 0x00000006 },
204 { 0x00007832, 0x00000002 },
205 { 0x00005000, 0x00000002 },
206 { 0x000380e7, 0x00000002 },
207 { 0x04002c97, 0x00000002 },
208 { 0x00007820, 0x00000002 },
209 { 0x00007821, 0x00000002 },
210 { 0x00007800, 0000000000 },
211 { 0x01200000, 0x00000002 },
212 { 0x20077000, 0x00000002 },
213 { 0x01200000, 0x00000002 },
214 { 0x20007000, 0x00000002 },
215 { 0x00061000, 0x00000002 },
216 { 0x0120751b, 0x00000002 },
217 { 0x8040750a, 0x00000002 },
218 { 0x8040750b, 0x00000002 },
219 { 0x00110000, 0x00000002 },
220 { 0x000380e5, 0x00000002 },
221 { 0x000000c6, 0x0000001c },
222 { 0x000610ab, 0x00000018 },
223 { 0x844075bd, 0x00000002 },
224 { 0x000610aa, 0x00000018 },
225 { 0x840075bb, 0x00000002 },
226 { 0x000610ab, 0x00000018 },
227 { 0x844075bc, 0x00000002 },
228 { 0x000000c9, 0x00000004 },
229 { 0x804075bd, 0x00000002 },
230 { 0x800075bb, 0x00000002 },
231 { 0x804075bc, 0x00000002 },
232 { 0x00108000, 0x00000002 },
233 { 0x01400000, 0x00000002 },
234 { 0x006000cd, 0x0000000c },
235 { 0x20c07000, 0x00000020 },
236 { 0x000000cf, 0x00000012 },
237 { 0x00800000, 0x00000006 },
238 { 0x0080751d, 0x00000006 },
239 { 0000000000, 0000000000 },
240 { 0x0000775c, 0x00000002 },
241 { 0x00a05000, 0x00000002 },
242 { 0x00661000, 0x00000002 },
243 { 0x0460275d, 0x00000020 },
244 { 0x00004000, 0000000000 },
245 { 0x01e00830, 0x00000002 },
246 { 0x21007000, 0000000000 },
247 { 0x6464614d, 0000000000 },
248 { 0x69687420, 0000000000 },
249 { 0x00000073, 0000000000 },
250 { 0000000000, 0000000000 },
251 { 0x00005000, 0x00000002 },
252 { 0x000380d0, 0x00000002 },
253 { 0x040025e0, 0x00000002 },
254 { 0x000075e1, 0000000000 },
255 { 0x00000001, 0000000000 },
256 { 0x000380e0, 0x00000002 },
257 { 0x04002394, 0x00000002 },
258 { 0x00005000, 0000000000 },
259 { 0000000000, 0000000000 },
260 { 0000000000, 0000000000 },
261 { 0x00000008, 0000000000 },
262 { 0x00000004, 0000000000 },
263 { 0000000000, 0000000000 },
264 { 0000000000, 0000000000 },
265 { 0000000000, 0000000000 },
266 { 0000000000, 0000000000 },
267 { 0000000000, 0000000000 },
268 { 0000000000, 0000000000 },
269 { 0000000000, 0000000000 },
270 { 0000000000, 0000000000 },
271 { 0000000000, 0000000000 },
272 { 0000000000, 0000000000 },
273 { 0000000000, 0000000000 },
274 { 0000000000, 0000000000 },
275 { 0000000000, 0000000000 },
276 { 0000000000, 0000000000 },
277 { 0000000000, 0000000000 },
278 { 0000000000, 0000000000 },
279 { 0000000000, 0000000000 },
280 { 0000000000, 0000000000 },
281 { 0000000000, 0000000000 },
282 { 0000000000, 0000000000 },
283 { 0000000000, 0000000000 },
284 { 0000000000, 0000000000 },
285 { 0000000000, 0000000000 },
286 { 0000000000, 0000000000 },
287};
288
289static const u32 R200_cp_microcode[][2] = {
290 { 0x21007000, 0000000000 },
291 { 0x20007000, 0000000000 },
292 { 0x000000bf, 0x00000004 },
293 { 0x000000c3, 0x00000004 },
294 { 0x7a685e5d, 0000000000 },
295 { 0x5d5d5588, 0000000000 },
296 { 0x68659197, 0000000000 },
297 { 0x5da19f78, 0000000000 },
298 { 0x5d5d5d5d, 0000000000 },
299 { 0x5dee5d50, 0000000000 },
300 { 0xf2acacac, 0000000000 },
301 { 0xe75df9e9, 0000000000 },
302 { 0xb1dd0e11, 0000000000 },
303 { 0xe2afafaf, 0000000000 },
304 { 0x000f0000, 0x00000016 },
305 { 0x452f232d, 0000000000 },
306 { 0x00000013, 0x00000004 },
307 { 0x000f0000, 0x00000016 },
308 { 0x452f272d, 0000000000 },
309 { 0x000f0001, 0x00000016 },
310 { 0x3e4d4a37, 0000000000 },
311 { 0x000077ef, 0x00000002 },
312 { 0x00061000, 0x00000002 },
313 { 0x00000020, 0x0000001a },
314 { 0x00004000, 0x0000001e },
315 { 0x00061000, 0x00000002 },
316 { 0x00000020, 0x0000001a },
317 { 0x00004000, 0x0000001e },
318 { 0x00061000, 0x00000002 },
319 { 0x00000020, 0x0000001a },
320 { 0x00004000, 0x0000001e },
321 { 0x00000016, 0x00000004 },
322 { 0x0003802a, 0x00000002 },
323 { 0x040067e0, 0x00000002 },
324 { 0x00000016, 0x00000004 },
325 { 0x000077e0, 0x00000002 },
326 { 0x00065000, 0x00000002 },
327 { 0x000037e1, 0x00000002 },
328 { 0x040067e1, 0x00000006 },
329 { 0x000077e0, 0x00000002 },
330 { 0x000077e1, 0x00000002 },
331 { 0x000077e1, 0x00000006 },
332 { 0xffffffff, 0000000000 },
333 { 0x10000000, 0000000000 },
334 { 0x07f007f0, 0000000000 },
335 { 0x0003802a, 0x00000002 },
336 { 0x040067e0, 0x00000006 },
337 { 0x0003802c, 0x00000002 },
338 { 0x04002741, 0x00000002 },
339 { 0x04002741, 0x00000002 },
340 { 0x04002743, 0x00000002 },
341 { 0x00007675, 0x00000002 },
342 { 0x00007676, 0x00000002 },
343 { 0x00007677, 0x00000002 },
344 { 0x00007678, 0x00000006 },
345 { 0x0003802c, 0x00000002 },
346 { 0x04002741, 0x00000002 },
347 { 0x04002741, 0x00000002 },
348 { 0x04002743, 0x00000002 },
349 { 0x00007676, 0x00000002 },
350 { 0x00007677, 0x00000002 },
351 { 0x00007678, 0x00000006 },
352 { 0x0003802b, 0x00000002 },
353 { 0x04002676, 0x00000002 },
354 { 0x00007677, 0x00000002 },
355 { 0x0003802c, 0x00000002 },
356 { 0x04002741, 0x00000002 },
357 { 0x04002743, 0x00000002 },
358 { 0x00007678, 0x00000006 },
359 { 0x0003802c, 0x00000002 },
360 { 0x04002741, 0x00000002 },
361 { 0x04002741, 0x00000002 },
362 { 0x04002743, 0x00000002 },
363 { 0x00007678, 0x00000006 },
364 { 0x0000002f, 0x00000018 },
365 { 0x0000002f, 0x00000018 },
366 { 0000000000, 0x00000006 },
367 { 0x00000037, 0x00000018 },
368 { 0x00000037, 0x00000018 },
369 { 0000000000, 0x00000006 },
370 { 0x01605000, 0x00000002 },
371 { 0x00065000, 0x00000002 },
372 { 0x00098000, 0x00000002 },
373 { 0x00061000, 0x00000002 },
374 { 0x64c06051, 0x00000004 },
375 { 0x00080000, 0x00000016 },
376 { 0000000000, 0000000000 },
377 { 0x0400251d, 0x00000002 },
378 { 0x00007580, 0x00000002 },
379 { 0x00067581, 0x00000002 },
380 { 0x04002580, 0x00000002 },
381 { 0x00067581, 0x00000002 },
382 { 0x0000005a, 0x00000004 },
383 { 0x00005000, 0000000000 },
384 { 0x00061000, 0x00000002 },
385 { 0x0000750e, 0x00000002 },
386 { 0x00019000, 0x00000002 },
387 { 0x00011064, 0x00000014 },
388 { 0x00000064, 0x00000012 },
389 { 0x0400250f, 0x00000002 },
390 { 0x0000505e, 0x00000004 },
391 { 0x00007565, 0x00000002 },
392 { 0x00007566, 0x00000002 },
393 { 0x00000065, 0x00000004 },
394 { 0x01e655b4, 0x00000002 },
395 { 0x4401b0f0, 0x00000002 },
396 { 0x01c110f0, 0x00000002 },
397 { 0x26667071, 0x00000018 },
398 { 0x040c2565, 0x00000002 },
399 { 0x00000071, 0x00000018 },
400 { 0x04002564, 0x00000002 },
401 { 0x00007566, 0x00000002 },
402 { 0x00000068, 0x00000004 },
403 { 0x00401074, 0x00000008 },
404 { 0x00101000, 0x00000002 },
405 { 0x000d80ff, 0x00000002 },
406 { 0x00800077, 0x00000008 },
407 { 0x000f9000, 0x00000002 },
408 { 0x000e00ff, 0x00000002 },
409 { 0000000000, 0x00000006 },
410 { 0x00000094, 0x00000018 },
411 { 0x00000068, 0x00000004 },
412 { 0x00007576, 0x00000002 },
413 { 0x00065000, 0x00000002 },
414 { 0x00009000, 0x00000002 },
415 { 0x00041000, 0x00000002 },
416 { 0x0c00350e, 0x00000002 },
417 { 0x00049000, 0x00000002 },
418 { 0x00051000, 0x00000002 },
419 { 0x01e785f8, 0x00000002 },
420 { 0x00200000, 0x00000002 },
421 { 0x00600087, 0x0000000c },
422 { 0x00007563, 0x00000002 },
423 { 0x006075f0, 0x00000021 },
424 { 0x2000707c, 0x00000004 },
425 { 0x0000507c, 0x00000004 },
426 { 0x00007576, 0x00000002 },
427 { 0x00007577, 0x00000002 },
428 { 0x0000750e, 0x00000002 },
429 { 0x0000750f, 0x00000002 },
430 { 0x00a05000, 0x00000002 },
431 { 0x0060008a, 0x0000000c },
432 { 0x006075f0, 0x00000021 },
433 { 0x000075f8, 0x00000002 },
434 { 0x0000008a, 0x00000004 },
435 { 0x000a750e, 0x00000002 },
436 { 0x0020750f, 0x00000002 },
437 { 0x0060008d, 0x00000004 },
438 { 0x00007570, 0x00000002 },
439 { 0x00007571, 0x00000002 },
440 { 0x00007572, 0x00000006 },
441 { 0x00005000, 0x00000002 },
442 { 0x00a05000, 0x00000002 },
443 { 0x00007568, 0x00000002 },
444 { 0x00061000, 0x00000002 },
445 { 0x00000098, 0x0000000c },
446 { 0x00058000, 0x00000002 },
447 { 0x0c607562, 0x00000002 },
448 { 0x0000009a, 0x00000004 },
449 { 0x00600099, 0x00000004 },
450 { 0x400070f1, 0000000000 },
451 { 0x000380f1, 0x00000002 },
452 { 0x000000a7, 0x0000001c },
453 { 0x000650a9, 0x00000018 },
454 { 0x040025bb, 0x00000002 },
455 { 0x000610aa, 0x00000018 },
456 { 0x040075bc, 0000000000 },
457 { 0x000075bb, 0x00000002 },
458 { 0x000075bc, 0000000000 },
459 { 0x00090000, 0x00000006 },
460 { 0x00090000, 0x00000002 },
461 { 0x000d8002, 0x00000006 },
462 { 0x00005000, 0x00000002 },
463 { 0x00007821, 0x00000002 },
464 { 0x00007800, 0000000000 },
465 { 0x00007821, 0x00000002 },
466 { 0x00007800, 0000000000 },
467 { 0x01665000, 0x00000002 },
468 { 0x000a0000, 0x00000002 },
469 { 0x000671cc, 0x00000002 },
470 { 0x0286f1cd, 0x00000002 },
471 { 0x000000b7, 0x00000010 },
472 { 0x21007000, 0000000000 },
473 { 0x000000be, 0x0000001c },
474 { 0x00065000, 0x00000002 },
475 { 0x000a0000, 0x00000002 },
476 { 0x00061000, 0x00000002 },
477 { 0x000b0000, 0x00000002 },
478 { 0x38067000, 0x00000002 },
479 { 0x000a00ba, 0x00000004 },
480 { 0x20007000, 0000000000 },
481 { 0x01200000, 0x00000002 },
482 { 0x20077000, 0x00000002 },
483 { 0x01200000, 0x00000002 },
484 { 0x20007000, 0000000000 },
485 { 0x00061000, 0x00000002 },
486 { 0x0120751b, 0x00000002 },
487 { 0x8040750a, 0x00000002 },
488 { 0x8040750b, 0x00000002 },
489 { 0x00110000, 0x00000002 },
490 { 0x000380f1, 0x00000002 },
491 { 0x000000d1, 0x0000001c },
492 { 0x000610aa, 0x00000018 },
493 { 0x844075bd, 0x00000002 },
494 { 0x000610a9, 0x00000018 },
495 { 0x840075bb, 0x00000002 },
496 { 0x000610aa, 0x00000018 },
497 { 0x844075bc, 0x00000002 },
498 { 0x000000d4, 0x00000004 },
499 { 0x804075bd, 0x00000002 },
500 { 0x800075bb, 0x00000002 },
501 { 0x804075bc, 0x00000002 },
502 { 0x00108000, 0x00000002 },
503 { 0x01400000, 0x00000002 },
504 { 0x006000d8, 0x0000000c },
505 { 0x20c07000, 0x00000020 },
506 { 0x000000da, 0x00000012 },
507 { 0x00800000, 0x00000006 },
508 { 0x0080751d, 0x00000006 },
509 { 0x000025bb, 0x00000002 },
510 { 0x000040d4, 0x00000004 },
511 { 0x0000775c, 0x00000002 },
512 { 0x00a05000, 0x00000002 },
513 { 0x00661000, 0x00000002 },
514 { 0x0460275d, 0x00000020 },
515 { 0x00004000, 0000000000 },
516 { 0x00007999, 0x00000002 },
517 { 0x00a05000, 0x00000002 },
518 { 0x00661000, 0x00000002 },
519 { 0x0460299b, 0x00000020 },
520 { 0x00004000, 0000000000 },
521 { 0x01e00830, 0x00000002 },
522 { 0x21007000, 0000000000 },
523 { 0x00005000, 0x00000002 },
524 { 0x00038056, 0x00000002 },
525 { 0x040025e0, 0x00000002 },
526 { 0x000075e1, 0000000000 },
527 { 0x00000001, 0000000000 },
528 { 0x000380ed, 0x00000002 },
529 { 0x04007394, 0000000000 },
530 { 0000000000, 0000000000 },
531 { 0000000000, 0000000000 },
532 { 0x000078c4, 0x00000002 },
533 { 0x000078c5, 0x00000002 },
534 { 0x000078c6, 0x00000002 },
535 { 0x00007924, 0x00000002 },
536 { 0x00007925, 0x00000002 },
537 { 0x00007926, 0x00000002 },
538 { 0x000000f2, 0x00000004 },
539 { 0x00007924, 0x00000002 },
540 { 0x00007925, 0x00000002 },
541 { 0x00007926, 0x00000002 },
542 { 0x000000f9, 0x00000004 },
543 { 0000000000, 0000000000 },
544 { 0000000000, 0000000000 },
545 { 0000000000, 0000000000 },
546};
547
548static const u32 R300_cp_microcode[][2] = {
549 { 0x4200e000, 0000000000 },
550 { 0x4000e000, 0000000000 },
551 { 0x000000ae, 0x00000008 },
552 { 0x000000b2, 0x00000008 },
553 { 0x67554b4a, 0000000000 },
554 { 0x4a4a4475, 0000000000 },
555 { 0x55527d83, 0000000000 },
556 { 0x4a8c8b65, 0000000000 },
557 { 0x4aef4af6, 0000000000 },
558 { 0x4ae14a4a, 0000000000 },
559 { 0xe4979797, 0000000000 },
560 { 0xdb4aebdd, 0000000000 },
561 { 0x9ccc4a4a, 0000000000 },
562 { 0xd1989898, 0000000000 },
563 { 0x4a0f9ad6, 0000000000 },
564 { 0x000ca000, 0x00000004 },
565 { 0x000d0012, 0x00000038 },
566 { 0x0000e8b4, 0x00000004 },
567 { 0x000d0014, 0x00000038 },
568 { 0x0000e8b6, 0x00000004 },
569 { 0x000d0016, 0x00000038 },
570 { 0x0000e854, 0x00000004 },
571 { 0x000d0018, 0x00000038 },
572 { 0x0000e855, 0x00000004 },
573 { 0x000d001a, 0x00000038 },
574 { 0x0000e856, 0x00000004 },
575 { 0x000d001c, 0x00000038 },
576 { 0x0000e857, 0x00000004 },
577 { 0x000d001e, 0x00000038 },
578 { 0x0000e824, 0x00000004 },
579 { 0x000d0020, 0x00000038 },
580 { 0x0000e825, 0x00000004 },
581 { 0x000d0022, 0x00000038 },
582 { 0x0000e830, 0x00000004 },
583 { 0x000d0024, 0x00000038 },
584 { 0x0000f0c0, 0x00000004 },
585 { 0x000d0026, 0x00000038 },
586 { 0x0000f0c1, 0x00000004 },
587 { 0x000d0028, 0x00000038 },
588 { 0x0000f041, 0x00000004 },
589 { 0x000d002a, 0x00000038 },
590 { 0x0000f184, 0x00000004 },
591 { 0x000d002c, 0x00000038 },
592 { 0x0000f185, 0x00000004 },
593 { 0x000d002e, 0x00000038 },
594 { 0x0000f186, 0x00000004 },
595 { 0x000d0030, 0x00000038 },
596 { 0x0000f187, 0x00000004 },
597 { 0x000d0032, 0x00000038 },
598 { 0x0000f180, 0x00000004 },
599 { 0x000d0034, 0x00000038 },
600 { 0x0000f393, 0x00000004 },
601 { 0x000d0036, 0x00000038 },
602 { 0x0000f38a, 0x00000004 },
603 { 0x000d0038, 0x00000038 },
604 { 0x0000f38e, 0x00000004 },
605 { 0x0000e821, 0x00000004 },
606 { 0x0140a000, 0x00000004 },
607 { 0x00000043, 0x00000018 },
608 { 0x00cce800, 0x00000004 },
609 { 0x001b0001, 0x00000004 },
610 { 0x08004800, 0x00000004 },
611 { 0x001b0001, 0x00000004 },
612 { 0x08004800, 0x00000004 },
613 { 0x001b0001, 0x00000004 },
614 { 0x08004800, 0x00000004 },
615 { 0x0000003a, 0x00000008 },
616 { 0x0000a000, 0000000000 },
617 { 0x2000451d, 0x00000004 },
618 { 0x0000e580, 0x00000004 },
619 { 0x000ce581, 0x00000004 },
620 { 0x08004580, 0x00000004 },
621 { 0x000ce581, 0x00000004 },
622 { 0x00000047, 0x00000008 },
623 { 0x0000a000, 0000000000 },
624 { 0x000c2000, 0x00000004 },
625 { 0x0000e50e, 0x00000004 },
626 { 0x00032000, 0x00000004 },
627 { 0x00022051, 0x00000028 },
628 { 0x00000051, 0x00000024 },
629 { 0x0800450f, 0x00000004 },
630 { 0x0000a04b, 0x00000008 },
631 { 0x0000e565, 0x00000004 },
632 { 0x0000e566, 0x00000004 },
633 { 0x00000052, 0x00000008 },
634 { 0x03cca5b4, 0x00000004 },
635 { 0x05432000, 0x00000004 },
636 { 0x00022000, 0x00000004 },
637 { 0x4ccce05e, 0x00000030 },
638 { 0x08274565, 0x00000004 },
639 { 0x0000005e, 0x00000030 },
640 { 0x08004564, 0x00000004 },
641 { 0x0000e566, 0x00000004 },
642 { 0x00000055, 0x00000008 },
643 { 0x00802061, 0x00000010 },
644 { 0x00202000, 0x00000004 },
645 { 0x001b00ff, 0x00000004 },
646 { 0x01000064, 0x00000010 },
647 { 0x001f2000, 0x00000004 },
648 { 0x001c00ff, 0x00000004 },
649 { 0000000000, 0x0000000c },
650 { 0x00000080, 0x00000030 },
651 { 0x00000055, 0x00000008 },
652 { 0x0000e576, 0x00000004 },
653 { 0x000ca000, 0x00000004 },
654 { 0x00012000, 0x00000004 },
655 { 0x00082000, 0x00000004 },
656 { 0x1800650e, 0x00000004 },
657 { 0x00092000, 0x00000004 },
658 { 0x000a2000, 0x00000004 },
659 { 0x000f0000, 0x00000004 },
660 { 0x00400000, 0x00000004 },
661 { 0x00000074, 0x00000018 },
662 { 0x0000e563, 0x00000004 },
663 { 0x00c0e5f9, 0x000000c2 },
664 { 0x00000069, 0x00000008 },
665 { 0x0000a069, 0x00000008 },
666 { 0x0000e576, 0x00000004 },
667 { 0x0000e577, 0x00000004 },
668 { 0x0000e50e, 0x00000004 },
669 { 0x0000e50f, 0x00000004 },
670 { 0x0140a000, 0x00000004 },
671 { 0x00000077, 0x00000018 },
672 { 0x00c0e5f9, 0x000000c2 },
673 { 0x00000077, 0x00000008 },
674 { 0x0014e50e, 0x00000004 },
675 { 0x0040e50f, 0x00000004 },
676 { 0x00c0007a, 0x00000008 },
677 { 0x0000e570, 0x00000004 },
678 { 0x0000e571, 0x00000004 },
679 { 0x0000e572, 0x0000000c },
680 { 0x0000a000, 0x00000004 },
681 { 0x0140a000, 0x00000004 },
682 { 0x0000e568, 0x00000004 },
683 { 0x000c2000, 0x00000004 },
684 { 0x00000084, 0x00000018 },
685 { 0x000b0000, 0x00000004 },
686 { 0x18c0e562, 0x00000004 },
687 { 0x00000086, 0x00000008 },
688 { 0x00c00085, 0x00000008 },
689 { 0x000700e3, 0x00000004 },
690 { 0x00000092, 0x00000038 },
691 { 0x000ca094, 0x00000030 },
692 { 0x080045bb, 0x00000004 },
693 { 0x000c2095, 0x00000030 },
694 { 0x0800e5bc, 0000000000 },
695 { 0x0000e5bb, 0x00000004 },
696 { 0x0000e5bc, 0000000000 },
697 { 0x00120000, 0x0000000c },
698 { 0x00120000, 0x00000004 },
699 { 0x001b0002, 0x0000000c },
700 { 0x0000a000, 0x00000004 },
701 { 0x0000e821, 0x00000004 },
702 { 0x0000e800, 0000000000 },
703 { 0x0000e821, 0x00000004 },
704 { 0x0000e82e, 0000000000 },
705 { 0x02cca000, 0x00000004 },
706 { 0x00140000, 0x00000004 },
707 { 0x000ce1cc, 0x00000004 },
708 { 0x050de1cd, 0x00000004 },
709 { 0x00400000, 0x00000004 },
710 { 0x000000a4, 0x00000018 },
711 { 0x00c0a000, 0x00000004 },
712 { 0x000000a1, 0x00000008 },
713 { 0x000000a6, 0x00000020 },
714 { 0x4200e000, 0000000000 },
715 { 0x000000ad, 0x00000038 },
716 { 0x000ca000, 0x00000004 },
717 { 0x00140000, 0x00000004 },
718 { 0x000c2000, 0x00000004 },
719 { 0x00160000, 0x00000004 },
720 { 0x700ce000, 0x00000004 },
721 { 0x001400a9, 0x00000008 },
722 { 0x4000e000, 0000000000 },
723 { 0x02400000, 0x00000004 },
724 { 0x400ee000, 0x00000004 },
725 { 0x02400000, 0x00000004 },
726 { 0x4000e000, 0000000000 },
727 { 0x000c2000, 0x00000004 },
728 { 0x0240e51b, 0x00000004 },
729 { 0x0080e50a, 0x00000005 },
730 { 0x0080e50b, 0x00000005 },
731 { 0x00220000, 0x00000004 },
732 { 0x000700e3, 0x00000004 },
733 { 0x000000c0, 0x00000038 },
734 { 0x000c2095, 0x00000030 },
735 { 0x0880e5bd, 0x00000005 },
736 { 0x000c2094, 0x00000030 },
737 { 0x0800e5bb, 0x00000005 },
738 { 0x000c2095, 0x00000030 },
739 { 0x0880e5bc, 0x00000005 },
740 { 0x000000c3, 0x00000008 },
741 { 0x0080e5bd, 0x00000005 },
742 { 0x0000e5bb, 0x00000005 },
743 { 0x0080e5bc, 0x00000005 },
744 { 0x00210000, 0x00000004 },
745 { 0x02800000, 0x00000004 },
746 { 0x00c000c7, 0x00000018 },
747 { 0x4180e000, 0x00000040 },
748 { 0x000000c9, 0x00000024 },
749 { 0x01000000, 0x0000000c },
750 { 0x0100e51d, 0x0000000c },
751 { 0x000045bb, 0x00000004 },
752 { 0x000080c3, 0x00000008 },
753 { 0x0000f3ce, 0x00000004 },
754 { 0x0140a000, 0x00000004 },
755 { 0x00cc2000, 0x00000004 },
756 { 0x08c053cf, 0x00000040 },
757 { 0x00008000, 0000000000 },
758 { 0x0000f3d2, 0x00000004 },
759 { 0x0140a000, 0x00000004 },
760 { 0x00cc2000, 0x00000004 },
761 { 0x08c053d3, 0x00000040 },
762 { 0x00008000, 0000000000 },
763 { 0x0000f39d, 0x00000004 },
764 { 0x0140a000, 0x00000004 },
765 { 0x00cc2000, 0x00000004 },
766 { 0x08c0539e, 0x00000040 },
767 { 0x00008000, 0000000000 },
768 { 0x03c00830, 0x00000004 },
769 { 0x4200e000, 0000000000 },
770 { 0x0000a000, 0x00000004 },
771 { 0x200045e0, 0x00000004 },
772 { 0x0000e5e1, 0000000000 },
773 { 0x00000001, 0000000000 },
774 { 0x000700e0, 0x00000004 },
775 { 0x0800e394, 0000000000 },
776 { 0000000000, 0000000000 },
777 { 0x0000e8c4, 0x00000004 },
778 { 0x0000e8c5, 0x00000004 },
779 { 0x0000e8c6, 0x00000004 },
780 { 0x0000e928, 0x00000004 },
781 { 0x0000e929, 0x00000004 },
782 { 0x0000e92a, 0x00000004 },
783 { 0x000000e4, 0x00000008 },
784 { 0x0000e928, 0x00000004 },
785 { 0x0000e929, 0x00000004 },
786 { 0x0000e92a, 0x00000004 },
787 { 0x000000eb, 0x00000008 },
788 { 0x02c02000, 0x00000004 },
789 { 0x00060000, 0x00000004 },
790 { 0x000000f3, 0x00000034 },
791 { 0x000000f0, 0x00000008 },
792 { 0x00008000, 0x00000004 },
793 { 0xc000e000, 0000000000 },
794 { 0000000000, 0000000000 },
795 { 0x000c2000, 0x00000004 },
796 { 0x001d0018, 0x00000004 },
797 { 0x001a0001, 0x00000004 },
798 { 0x000000fb, 0x00000034 },
799 { 0x0000004a, 0x00000008 },
800 { 0x0500a04a, 0x00000008 },
801 { 0000000000, 0000000000 },
802 { 0000000000, 0000000000 },
803 { 0000000000, 0000000000 },
804 { 0000000000, 0000000000 },
805};
806
807static const u32 R420_cp_microcode[][2] = {
808 { 0x4200e000, 0000000000 },
809 { 0x4000e000, 0000000000 },
810 { 0x00000099, 0x00000008 },
811 { 0x0000009d, 0x00000008 },
812 { 0x4a554b4a, 0000000000 },
813 { 0x4a4a4467, 0000000000 },
814 { 0x55526f75, 0000000000 },
815 { 0x4a7e7d65, 0000000000 },
816 { 0xd9d3dff6, 0000000000 },
817 { 0x4ac54a4a, 0000000000 },
818 { 0xc8828282, 0000000000 },
819 { 0xbf4acfc1, 0000000000 },
820 { 0x87b04a4a, 0000000000 },
821 { 0xb5838383, 0000000000 },
822 { 0x4a0f85ba, 0000000000 },
823 { 0x000ca000, 0x00000004 },
824 { 0x000d0012, 0x00000038 },
825 { 0x0000e8b4, 0x00000004 },
826 { 0x000d0014, 0x00000038 },
827 { 0x0000e8b6, 0x00000004 },
828 { 0x000d0016, 0x00000038 },
829 { 0x0000e854, 0x00000004 },
830 { 0x000d0018, 0x00000038 },
831 { 0x0000e855, 0x00000004 },
832 { 0x000d001a, 0x00000038 },
833 { 0x0000e856, 0x00000004 },
834 { 0x000d001c, 0x00000038 },
835 { 0x0000e857, 0x00000004 },
836 { 0x000d001e, 0x00000038 },
837 { 0x0000e824, 0x00000004 },
838 { 0x000d0020, 0x00000038 },
839 { 0x0000e825, 0x00000004 },
840 { 0x000d0022, 0x00000038 },
841 { 0x0000e830, 0x00000004 },
842 { 0x000d0024, 0x00000038 },
843 { 0x0000f0c0, 0x00000004 },
844 { 0x000d0026, 0x00000038 },
845 { 0x0000f0c1, 0x00000004 },
846 { 0x000d0028, 0x00000038 },
847 { 0x0000f041, 0x00000004 },
848 { 0x000d002a, 0x00000038 },
849 { 0x0000f184, 0x00000004 },
850 { 0x000d002c, 0x00000038 },
851 { 0x0000f185, 0x00000004 },
852 { 0x000d002e, 0x00000038 },
853 { 0x0000f186, 0x00000004 },
854 { 0x000d0030, 0x00000038 },
855 { 0x0000f187, 0x00000004 },
856 { 0x000d0032, 0x00000038 },
857 { 0x0000f180, 0x00000004 },
858 { 0x000d0034, 0x00000038 },
859 { 0x0000f393, 0x00000004 },
860 { 0x000d0036, 0x00000038 },
861 { 0x0000f38a, 0x00000004 },
862 { 0x000d0038, 0x00000038 },
863 { 0x0000f38e, 0x00000004 },
864 { 0x0000e821, 0x00000004 },
865 { 0x0140a000, 0x00000004 },
866 { 0x00000043, 0x00000018 },
867 { 0x00cce800, 0x00000004 },
868 { 0x001b0001, 0x00000004 },
869 { 0x08004800, 0x00000004 },
870 { 0x001b0001, 0x00000004 },
871 { 0x08004800, 0x00000004 },
872 { 0x001b0001, 0x00000004 },
873 { 0x08004800, 0x00000004 },
874 { 0x0000003a, 0x00000008 },
875 { 0x0000a000, 0000000000 },
876 { 0x2000451d, 0x00000004 },
877 { 0x0000e580, 0x00000004 },
878 { 0x000ce581, 0x00000004 },
879 { 0x08004580, 0x00000004 },
880 { 0x000ce581, 0x00000004 },
881 { 0x00000047, 0x00000008 },
882 { 0x0000a000, 0000000000 },
883 { 0x000c2000, 0x00000004 },
884 { 0x0000e50e, 0x00000004 },
885 { 0x00032000, 0x00000004 },
886 { 0x00022051, 0x00000028 },
887 { 0x00000051, 0x00000024 },
888 { 0x0800450f, 0x00000004 },
889 { 0x0000a04b, 0x00000008 },
890 { 0x0000e565, 0x00000004 },
891 { 0x0000e566, 0x00000004 },
892 { 0x00000052, 0x00000008 },
893 { 0x03cca5b4, 0x00000004 },
894 { 0x05432000, 0x00000004 },
895 { 0x00022000, 0x00000004 },
896 { 0x4ccce05e, 0x00000030 },
897 { 0x08274565, 0x00000004 },
898 { 0x0000005e, 0x00000030 },
899 { 0x08004564, 0x00000004 },
900 { 0x0000e566, 0x00000004 },
901 { 0x00000055, 0x00000008 },
902 { 0x00802061, 0x00000010 },
903 { 0x00202000, 0x00000004 },
904 { 0x001b00ff, 0x00000004 },
905 { 0x01000064, 0x00000010 },
906 { 0x001f2000, 0x00000004 },
907 { 0x001c00ff, 0x00000004 },
908 { 0000000000, 0x0000000c },
909 { 0x00000072, 0x00000030 },
910 { 0x00000055, 0x00000008 },
911 { 0x0000e576, 0x00000004 },
912 { 0x0000e577, 0x00000004 },
913 { 0x0000e50e, 0x00000004 },
914 { 0x0000e50f, 0x00000004 },
915 { 0x0140a000, 0x00000004 },
916 { 0x00000069, 0x00000018 },
917 { 0x00c0e5f9, 0x000000c2 },
918 { 0x00000069, 0x00000008 },
919 { 0x0014e50e, 0x00000004 },
920 { 0x0040e50f, 0x00000004 },
921 { 0x00c0006c, 0x00000008 },
922 { 0x0000e570, 0x00000004 },
923 { 0x0000e571, 0x00000004 },
924 { 0x0000e572, 0x0000000c },
925 { 0x0000a000, 0x00000004 },
926 { 0x0140a000, 0x00000004 },
927 { 0x0000e568, 0x00000004 },
928 { 0x000c2000, 0x00000004 },
929 { 0x00000076, 0x00000018 },
930 { 0x000b0000, 0x00000004 },
931 { 0x18c0e562, 0x00000004 },
932 { 0x00000078, 0x00000008 },
933 { 0x00c00077, 0x00000008 },
934 { 0x000700c7, 0x00000004 },
935 { 0x00000080, 0x00000038 },
936 { 0x0000e5bb, 0x00000004 },
937 { 0x0000e5bc, 0000000000 },
938 { 0x0000a000, 0x00000004 },
939 { 0x0000e821, 0x00000004 },
940 { 0x0000e800, 0000000000 },
941 { 0x0000e821, 0x00000004 },
942 { 0x0000e82e, 0000000000 },
943 { 0x02cca000, 0x00000004 },
944 { 0x00140000, 0x00000004 },
945 { 0x000ce1cc, 0x00000004 },
946 { 0x050de1cd, 0x00000004 },
947 { 0x00400000, 0x00000004 },
948 { 0x0000008f, 0x00000018 },
949 { 0x00c0a000, 0x00000004 },
950 { 0x0000008c, 0x00000008 },
951 { 0x00000091, 0x00000020 },
952 { 0x4200e000, 0000000000 },
953 { 0x00000098, 0x00000038 },
954 { 0x000ca000, 0x00000004 },
955 { 0x00140000, 0x00000004 },
956 { 0x000c2000, 0x00000004 },
957 { 0x00160000, 0x00000004 },
958 { 0x700ce000, 0x00000004 },
959 { 0x00140094, 0x00000008 },
960 { 0x4000e000, 0000000000 },
961 { 0x02400000, 0x00000004 },
962 { 0x400ee000, 0x00000004 },
963 { 0x02400000, 0x00000004 },
964 { 0x4000e000, 0000000000 },
965 { 0x000c2000, 0x00000004 },
966 { 0x0240e51b, 0x00000004 },
967 { 0x0080e50a, 0x00000005 },
968 { 0x0080e50b, 0x00000005 },
969 { 0x00220000, 0x00000004 },
970 { 0x000700c7, 0x00000004 },
971 { 0x000000a4, 0x00000038 },
972 { 0x0080e5bd, 0x00000005 },
973 { 0x0000e5bb, 0x00000005 },
974 { 0x0080e5bc, 0x00000005 },
975 { 0x00210000, 0x00000004 },
976 { 0x02800000, 0x00000004 },
977 { 0x00c000ab, 0x00000018 },
978 { 0x4180e000, 0x00000040 },
979 { 0x000000ad, 0x00000024 },
980 { 0x01000000, 0x0000000c },
981 { 0x0100e51d, 0x0000000c },
982 { 0x000045bb, 0x00000004 },
983 { 0x000080a7, 0x00000008 },
984 { 0x0000f3ce, 0x00000004 },
985 { 0x0140a000, 0x00000004 },
986 { 0x00cc2000, 0x00000004 },
987 { 0x08c053cf, 0x00000040 },
988 { 0x00008000, 0000000000 },
989 { 0x0000f3d2, 0x00000004 },
990 { 0x0140a000, 0x00000004 },
991 { 0x00cc2000, 0x00000004 },
992 { 0x08c053d3, 0x00000040 },
993 { 0x00008000, 0000000000 },
994 { 0x0000f39d, 0x00000004 },
995 { 0x0140a000, 0x00000004 },
996 { 0x00cc2000, 0x00000004 },
997 { 0x08c0539e, 0x00000040 },
998 { 0x00008000, 0000000000 },
999 { 0x03c00830, 0x00000004 },
1000 { 0x4200e000, 0000000000 },
1001 { 0x0000a000, 0x00000004 },
1002 { 0x200045e0, 0x00000004 },
1003 { 0x0000e5e1, 0000000000 },
1004 { 0x00000001, 0000000000 },
1005 { 0x000700c4, 0x00000004 },
1006 { 0x0800e394, 0000000000 },
1007 { 0000000000, 0000000000 },
1008 { 0x0000e8c4, 0x00000004 },
1009 { 0x0000e8c5, 0x00000004 },
1010 { 0x0000e8c6, 0x00000004 },
1011 { 0x0000e928, 0x00000004 },
1012 { 0x0000e929, 0x00000004 },
1013 { 0x0000e92a, 0x00000004 },
1014 { 0x000000c8, 0x00000008 },
1015 { 0x0000e928, 0x00000004 },
1016 { 0x0000e929, 0x00000004 },
1017 { 0x0000e92a, 0x00000004 },
1018 { 0x000000cf, 0x00000008 },
1019 { 0x02c02000, 0x00000004 },
1020 { 0x00060000, 0x00000004 },
1021 { 0x000000d7, 0x00000034 },
1022 { 0x000000d4, 0x00000008 },
1023 { 0x00008000, 0x00000004 },
1024 { 0xc000e000, 0000000000 },
1025 { 0x0000e1cc, 0x00000004 },
1026 { 0x0500e1cd, 0x00000004 },
1027 { 0x000ca000, 0x00000004 },
1028 { 0x000000de, 0x00000034 },
1029 { 0x000000da, 0x00000008 },
1030 { 0x0000a000, 0000000000 },
1031 { 0x0019e1cc, 0x00000004 },
1032 { 0x001b0001, 0x00000004 },
1033 { 0x0500a000, 0x00000004 },
1034 { 0x080041cd, 0x00000004 },
1035 { 0x000ca000, 0x00000004 },
1036 { 0x000000fb, 0x00000034 },
1037 { 0x0000004a, 0x00000008 },
1038 { 0000000000, 0000000000 },
1039 { 0000000000, 0000000000 },
1040 { 0000000000, 0000000000 },
1041 { 0000000000, 0000000000 },
1042 { 0000000000, 0000000000 },
1043 { 0000000000, 0000000000 },
1044 { 0000000000, 0000000000 },
1045 { 0000000000, 0000000000 },
1046 { 0000000000, 0000000000 },
1047 { 0000000000, 0000000000 },
1048 { 0000000000, 0000000000 },
1049 { 0000000000, 0000000000 },
1050 { 0000000000, 0000000000 },
1051 { 0000000000, 0000000000 },
1052 { 0000000000, 0000000000 },
1053 { 0000000000, 0000000000 },
1054 { 0x000c2000, 0x00000004 },
1055 { 0x001d0018, 0x00000004 },
1056 { 0x001a0001, 0x00000004 },
1057 { 0x000000fb, 0x00000034 },
1058 { 0x0000004a, 0x00000008 },
1059 { 0x0500a04a, 0x00000008 },
1060 { 0000000000, 0000000000 },
1061 { 0000000000, 0000000000 },
1062 { 0000000000, 0000000000 },
1063 { 0000000000, 0000000000 },
1064};
1065
1066static const u32 RS600_cp_microcode[][2] = {
1067 { 0x4200e000, 0000000000 },
1068 { 0x4000e000, 0000000000 },
1069 { 0x000000a0, 0x00000008 },
1070 { 0x000000a4, 0x00000008 },
1071 { 0x4a554b4a, 0000000000 },
1072 { 0x4a4a4467, 0000000000 },
1073 { 0x55526f75, 0000000000 },
1074 { 0x4a7e7d65, 0000000000 },
1075 { 0x4ae74af6, 0000000000 },
1076 { 0x4ad34a4a, 0000000000 },
1077 { 0xd6898989, 0000000000 },
1078 { 0xcd4addcf, 0000000000 },
1079 { 0x8ebe4ae2, 0000000000 },
1080 { 0xc38a8a8a, 0000000000 },
1081 { 0x4a0f8cc8, 0000000000 },
1082 { 0x000ca000, 0x00000004 },
1083 { 0x000d0012, 0x00000038 },
1084 { 0x0000e8b4, 0x00000004 },
1085 { 0x000d0014, 0x00000038 },
1086 { 0x0000e8b6, 0x00000004 },
1087 { 0x000d0016, 0x00000038 },
1088 { 0x0000e854, 0x00000004 },
1089 { 0x000d0018, 0x00000038 },
1090 { 0x0000e855, 0x00000004 },
1091 { 0x000d001a, 0x00000038 },
1092 { 0x0000e856, 0x00000004 },
1093 { 0x000d001c, 0x00000038 },
1094 { 0x0000e857, 0x00000004 },
1095 { 0x000d001e, 0x00000038 },
1096 { 0x0000e824, 0x00000004 },
1097 { 0x000d0020, 0x00000038 },
1098 { 0x0000e825, 0x00000004 },
1099 { 0x000d0022, 0x00000038 },
1100 { 0x0000e830, 0x00000004 },
1101 { 0x000d0024, 0x00000038 },
1102 { 0x0000f0c0, 0x00000004 },
1103 { 0x000d0026, 0x00000038 },
1104 { 0x0000f0c1, 0x00000004 },
1105 { 0x000d0028, 0x00000038 },
1106 { 0x0000f041, 0x00000004 },
1107 { 0x000d002a, 0x00000038 },
1108 { 0x0000f184, 0x00000004 },
1109 { 0x000d002c, 0x00000038 },
1110 { 0x0000f185, 0x00000004 },
1111 { 0x000d002e, 0x00000038 },
1112 { 0x0000f186, 0x00000004 },
1113 { 0x000d0030, 0x00000038 },
1114 { 0x0000f187, 0x00000004 },
1115 { 0x000d0032, 0x00000038 },
1116 { 0x0000f180, 0x00000004 },
1117 { 0x000d0034, 0x00000038 },
1118 { 0x0000f393, 0x00000004 },
1119 { 0x000d0036, 0x00000038 },
1120 { 0x0000f38a, 0x00000004 },
1121 { 0x000d0038, 0x00000038 },
1122 { 0x0000f38e, 0x00000004 },
1123 { 0x0000e821, 0x00000004 },
1124 { 0x0140a000, 0x00000004 },
1125 { 0x00000043, 0x00000018 },
1126 { 0x00cce800, 0x00000004 },
1127 { 0x001b0001, 0x00000004 },
1128 { 0x08004800, 0x00000004 },
1129 { 0x001b0001, 0x00000004 },
1130 { 0x08004800, 0x00000004 },
1131 { 0x001b0001, 0x00000004 },
1132 { 0x08004800, 0x00000004 },
1133 { 0x0000003a, 0x00000008 },
1134 { 0x0000a000, 0000000000 },
1135 { 0x2000451d, 0x00000004 },
1136 { 0x0000e580, 0x00000004 },
1137 { 0x000ce581, 0x00000004 },
1138 { 0x08004580, 0x00000004 },
1139 { 0x000ce581, 0x00000004 },
1140 { 0x00000047, 0x00000008 },
1141 { 0x0000a000, 0000000000 },
1142 { 0x000c2000, 0x00000004 },
1143 { 0x0000e50e, 0x00000004 },
1144 { 0x00032000, 0x00000004 },
1145 { 0x00022051, 0x00000028 },
1146 { 0x00000051, 0x00000024 },
1147 { 0x0800450f, 0x00000004 },
1148 { 0x0000a04b, 0x00000008 },
1149 { 0x0000e565, 0x00000004 },
1150 { 0x0000e566, 0x00000004 },
1151 { 0x00000052, 0x00000008 },
1152 { 0x03cca5b4, 0x00000004 },
1153 { 0x05432000, 0x00000004 },
1154 { 0x00022000, 0x00000004 },
1155 { 0x4ccce05e, 0x00000030 },
1156 { 0x08274565, 0x00000004 },
1157 { 0x0000005e, 0x00000030 },
1158 { 0x08004564, 0x00000004 },
1159 { 0x0000e566, 0x00000004 },
1160 { 0x00000055, 0x00000008 },
1161 { 0x00802061, 0x00000010 },
1162 { 0x00202000, 0x00000004 },
1163 { 0x001b00ff, 0x00000004 },
1164 { 0x01000064, 0x00000010 },
1165 { 0x001f2000, 0x00000004 },
1166 { 0x001c00ff, 0x00000004 },
1167 { 0000000000, 0x0000000c },
1168 { 0x00000072, 0x00000030 },
1169 { 0x00000055, 0x00000008 },
1170 { 0x0000e576, 0x00000004 },
1171 { 0x0000e577, 0x00000004 },
1172 { 0x0000e50e, 0x00000004 },
1173 { 0x0000e50f, 0x00000004 },
1174 { 0x0140a000, 0x00000004 },
1175 { 0x00000069, 0x00000018 },
1176 { 0x00c0e5f9, 0x000000c2 },
1177 { 0x00000069, 0x00000008 },
1178 { 0x0014e50e, 0x00000004 },
1179 { 0x0040e50f, 0x00000004 },
1180 { 0x00c0006c, 0x00000008 },
1181 { 0x0000e570, 0x00000004 },
1182 { 0x0000e571, 0x00000004 },
1183 { 0x0000e572, 0x0000000c },
1184 { 0x0000a000, 0x00000004 },
1185 { 0x0140a000, 0x00000004 },
1186 { 0x0000e568, 0x00000004 },
1187 { 0x000c2000, 0x00000004 },
1188 { 0x00000076, 0x00000018 },
1189 { 0x000b0000, 0x00000004 },
1190 { 0x18c0e562, 0x00000004 },
1191 { 0x00000078, 0x00000008 },
1192 { 0x00c00077, 0x00000008 },
1193 { 0x000700d5, 0x00000004 },
1194 { 0x00000084, 0x00000038 },
1195 { 0x000ca086, 0x00000030 },
1196 { 0x080045bb, 0x00000004 },
1197 { 0x000c2087, 0x00000030 },
1198 { 0x0800e5bc, 0000000000 },
1199 { 0x0000e5bb, 0x00000004 },
1200 { 0x0000e5bc, 0000000000 },
1201 { 0x00120000, 0x0000000c },
1202 { 0x00120000, 0x00000004 },
1203 { 0x001b0002, 0x0000000c },
1204 { 0x0000a000, 0x00000004 },
1205 { 0x0000e821, 0x00000004 },
1206 { 0x0000e800, 0000000000 },
1207 { 0x0000e821, 0x00000004 },
1208 { 0x0000e82e, 0000000000 },
1209 { 0x02cca000, 0x00000004 },
1210 { 0x00140000, 0x00000004 },
1211 { 0x000ce1cc, 0x00000004 },
1212 { 0x050de1cd, 0x00000004 },
1213 { 0x00400000, 0x00000004 },
1214 { 0x00000096, 0x00000018 },
1215 { 0x00c0a000, 0x00000004 },
1216 { 0x00000093, 0x00000008 },
1217 { 0x00000098, 0x00000020 },
1218 { 0x4200e000, 0000000000 },
1219 { 0x0000009f, 0x00000038 },
1220 { 0x000ca000, 0x00000004 },
1221 { 0x00140000, 0x00000004 },
1222 { 0x000c2000, 0x00000004 },
1223 { 0x00160000, 0x00000004 },
1224 { 0x700ce000, 0x00000004 },
1225 { 0x0014009b, 0x00000008 },
1226 { 0x4000e000, 0000000000 },
1227 { 0x02400000, 0x00000004 },
1228 { 0x400ee000, 0x00000004 },
1229 { 0x02400000, 0x00000004 },
1230 { 0x4000e000, 0000000000 },
1231 { 0x000c2000, 0x00000004 },
1232 { 0x0240e51b, 0x00000004 },
1233 { 0x0080e50a, 0x00000005 },
1234 { 0x0080e50b, 0x00000005 },
1235 { 0x00220000, 0x00000004 },
1236 { 0x000700d5, 0x00000004 },
1237 { 0x000000b2, 0x00000038 },
1238 { 0x000c2087, 0x00000030 },
1239 { 0x0880e5bd, 0x00000005 },
1240 { 0x000c2086, 0x00000030 },
1241 { 0x0800e5bb, 0x00000005 },
1242 { 0x000c2087, 0x00000030 },
1243 { 0x0880e5bc, 0x00000005 },
1244 { 0x000000b5, 0x00000008 },
1245 { 0x0080e5bd, 0x00000005 },
1246 { 0x0000e5bb, 0x00000005 },
1247 { 0x0080e5bc, 0x00000005 },
1248 { 0x00210000, 0x00000004 },
1249 { 0x02800000, 0x00000004 },
1250 { 0x00c000b9, 0x00000018 },
1251 { 0x4180e000, 0x00000040 },
1252 { 0x000000bb, 0x00000024 },
1253 { 0x01000000, 0x0000000c },
1254 { 0x0100e51d, 0x0000000c },
1255 { 0x000045bb, 0x00000004 },
1256 { 0x000080b5, 0x00000008 },
1257 { 0x0000f3ce, 0x00000004 },
1258 { 0x0140a000, 0x00000004 },
1259 { 0x00cc2000, 0x00000004 },
1260 { 0x08c053cf, 0x00000040 },
1261 { 0x00008000, 0000000000 },
1262 { 0x0000f3d2, 0x00000004 },
1263 { 0x0140a000, 0x00000004 },
1264 { 0x00cc2000, 0x00000004 },
1265 { 0x08c053d3, 0x00000040 },
1266 { 0x00008000, 0000000000 },
1267 { 0x0000f39d, 0x00000004 },
1268 { 0x0140a000, 0x00000004 },
1269 { 0x00cc2000, 0x00000004 },
1270 { 0x08c0539e, 0x00000040 },
1271 { 0x00008000, 0000000000 },
1272 { 0x03c00830, 0x00000004 },
1273 { 0x4200e000, 0000000000 },
1274 { 0x0000a000, 0x00000004 },
1275 { 0x200045e0, 0x00000004 },
1276 { 0x0000e5e1, 0000000000 },
1277 { 0x00000001, 0000000000 },
1278 { 0x000700d2, 0x00000004 },
1279 { 0x0800e394, 0000000000 },
1280 { 0000000000, 0000000000 },
1281 { 0x0000e8c4, 0x00000004 },
1282 { 0x0000e8c5, 0x00000004 },
1283 { 0x0000e8c6, 0x00000004 },
1284 { 0x0000e928, 0x00000004 },
1285 { 0x0000e929, 0x00000004 },
1286 { 0x0000e92a, 0x00000004 },
1287 { 0x000000d6, 0x00000008 },
1288 { 0x0000e928, 0x00000004 },
1289 { 0x0000e929, 0x00000004 },
1290 { 0x0000e92a, 0x00000004 },
1291 { 0x000000dd, 0x00000008 },
1292 { 0x00e00116, 0000000000 },
1293 { 0x000700e1, 0x00000004 },
1294 { 0x0800401c, 0x00000004 },
1295 { 0x200050e7, 0x00000004 },
1296 { 0x0000e01d, 0x00000004 },
1297 { 0x000000e4, 0x00000008 },
1298 { 0x02c02000, 0x00000004 },
1299 { 0x00060000, 0x00000004 },
1300 { 0x000000eb, 0x00000034 },
1301 { 0x000000e8, 0x00000008 },
1302 { 0x00008000, 0x00000004 },
1303 { 0xc000e000, 0000000000 },
1304 { 0000000000, 0000000000 },
1305 { 0000000000, 0000000000 },
1306 { 0000000000, 0000000000 },
1307 { 0000000000, 0000000000 },
1308 { 0000000000, 0000000000 },
1309 { 0000000000, 0000000000 },
1310 { 0000000000, 0000000000 },
1311 { 0000000000, 0000000000 },
1312 { 0000000000, 0000000000 },
1313 { 0x000c2000, 0x00000004 },
1314 { 0x001d0018, 0x00000004 },
1315 { 0x001a0001, 0x00000004 },
1316 { 0x000000fb, 0x00000034 },
1317 { 0x0000004a, 0x00000008 },
1318 { 0x0500a04a, 0x00000008 },
1319 { 0000000000, 0000000000 },
1320 { 0000000000, 0000000000 },
1321 { 0000000000, 0000000000 },
1322 { 0000000000, 0000000000 },
1323};
1324
1325static const u32 RS690_cp_microcode[][2] = {
1326 { 0x000000dd, 0x00000008 },
1327 { 0x000000df, 0x00000008 },
1328 { 0x000000a0, 0x00000008 },
1329 { 0x000000a4, 0x00000008 },
1330 { 0x4a554b4a, 0000000000 },
1331 { 0x4a4a4467, 0000000000 },
1332 { 0x55526f75, 0000000000 },
1333 { 0x4a7e7d65, 0000000000 },
1334 { 0x4ad74af6, 0000000000 },
1335 { 0x4ac94a4a, 0000000000 },
1336 { 0xcc898989, 0000000000 },
1337 { 0xc34ad3c5, 0000000000 },
1338 { 0x8e4a4a4a, 0000000000 },
1339 { 0x4a8a8a8a, 0000000000 },
1340 { 0x4a0f8c4a, 0000000000 },
1341 { 0x000ca000, 0x00000004 },
1342 { 0x000d0012, 0x00000038 },
1343 { 0x0000e8b4, 0x00000004 },
1344 { 0x000d0014, 0x00000038 },
1345 { 0x0000e8b6, 0x00000004 },
1346 { 0x000d0016, 0x00000038 },
1347 { 0x0000e854, 0x00000004 },
1348 { 0x000d0018, 0x00000038 },
1349 { 0x0000e855, 0x00000004 },
1350 { 0x000d001a, 0x00000038 },
1351 { 0x0000e856, 0x00000004 },
1352 { 0x000d001c, 0x00000038 },
1353 { 0x0000e857, 0x00000004 },
1354 { 0x000d001e, 0x00000038 },
1355 { 0x0000e824, 0x00000004 },
1356 { 0x000d0020, 0x00000038 },
1357 { 0x0000e825, 0x00000004 },
1358 { 0x000d0022, 0x00000038 },
1359 { 0x0000e830, 0x00000004 },
1360 { 0x000d0024, 0x00000038 },
1361 { 0x0000f0c0, 0x00000004 },
1362 { 0x000d0026, 0x00000038 },
1363 { 0x0000f0c1, 0x00000004 },
1364 { 0x000d0028, 0x00000038 },
1365 { 0x0000f041, 0x00000004 },
1366 { 0x000d002a, 0x00000038 },
1367 { 0x0000f184, 0x00000004 },
1368 { 0x000d002c, 0x00000038 },
1369 { 0x0000f185, 0x00000004 },
1370 { 0x000d002e, 0x00000038 },
1371 { 0x0000f186, 0x00000004 },
1372 { 0x000d0030, 0x00000038 },
1373 { 0x0000f187, 0x00000004 },
1374 { 0x000d0032, 0x00000038 },
1375 { 0x0000f180, 0x00000004 },
1376 { 0x000d0034, 0x00000038 },
1377 { 0x0000f393, 0x00000004 },
1378 { 0x000d0036, 0x00000038 },
1379 { 0x0000f38a, 0x00000004 },
1380 { 0x000d0038, 0x00000038 },
1381 { 0x0000f38e, 0x00000004 },
1382 { 0x0000e821, 0x00000004 },
1383 { 0x0140a000, 0x00000004 },
1384 { 0x00000043, 0x00000018 },
1385 { 0x00cce800, 0x00000004 },
1386 { 0x001b0001, 0x00000004 },
1387 { 0x08004800, 0x00000004 },
1388 { 0x001b0001, 0x00000004 },
1389 { 0x08004800, 0x00000004 },
1390 { 0x001b0001, 0x00000004 },
1391 { 0x08004800, 0x00000004 },
1392 { 0x0000003a, 0x00000008 },
1393 { 0x0000a000, 0000000000 },
1394 { 0x2000451d, 0x00000004 },
1395 { 0x0000e580, 0x00000004 },
1396 { 0x000ce581, 0x00000004 },
1397 { 0x08004580, 0x00000004 },
1398 { 0x000ce581, 0x00000004 },
1399 { 0x00000047, 0x00000008 },
1400 { 0x0000a000, 0000000000 },
1401 { 0x000c2000, 0x00000004 },
1402 { 0x0000e50e, 0x00000004 },
1403 { 0x00032000, 0x00000004 },
1404 { 0x00022051, 0x00000028 },
1405 { 0x00000051, 0x00000024 },
1406 { 0x0800450f, 0x00000004 },
1407 { 0x0000a04b, 0x00000008 },
1408 { 0x0000e565, 0x00000004 },
1409 { 0x0000e566, 0x00000004 },
1410 { 0x00000052, 0x00000008 },
1411 { 0x03cca5b4, 0x00000004 },
1412 { 0x05432000, 0x00000004 },
1413 { 0x00022000, 0x00000004 },
1414 { 0x4ccce05e, 0x00000030 },
1415 { 0x08274565, 0x00000004 },
1416 { 0x0000005e, 0x00000030 },
1417 { 0x08004564, 0x00000004 },
1418 { 0x0000e566, 0x00000004 },
1419 { 0x00000055, 0x00000008 },
1420 { 0x00802061, 0x00000010 },
1421 { 0x00202000, 0x00000004 },
1422 { 0x001b00ff, 0x00000004 },
1423 { 0x01000064, 0x00000010 },
1424 { 0x001f2000, 0x00000004 },
1425 { 0x001c00ff, 0x00000004 },
1426 { 0000000000, 0x0000000c },
1427 { 0x00000072, 0x00000030 },
1428 { 0x00000055, 0x00000008 },
1429 { 0x0000e576, 0x00000004 },
1430 { 0x0000e577, 0x00000004 },
1431 { 0x0000e50e, 0x00000004 },
1432 { 0x0000e50f, 0x00000004 },
1433 { 0x0140a000, 0x00000004 },
1434 { 0x00000069, 0x00000018 },
1435 { 0x00c0e5f9, 0x000000c2 },
1436 { 0x00000069, 0x00000008 },
1437 { 0x0014e50e, 0x00000004 },
1438 { 0x0040e50f, 0x00000004 },
1439 { 0x00c0006c, 0x00000008 },
1440 { 0x0000e570, 0x00000004 },
1441 { 0x0000e571, 0x00000004 },
1442 { 0x0000e572, 0x0000000c },
1443 { 0x0000a000, 0x00000004 },
1444 { 0x0140a000, 0x00000004 },
1445 { 0x0000e568, 0x00000004 },
1446 { 0x000c2000, 0x00000004 },
1447 { 0x00000076, 0x00000018 },
1448 { 0x000b0000, 0x00000004 },
1449 { 0x18c0e562, 0x00000004 },
1450 { 0x00000078, 0x00000008 },
1451 { 0x00c00077, 0x00000008 },
1452 { 0x000700cb, 0x00000004 },
1453 { 0x00000084, 0x00000038 },
1454 { 0x000ca086, 0x00000030 },
1455 { 0x080045bb, 0x00000004 },
1456 { 0x000c2087, 0x00000030 },
1457 { 0x0800e5bc, 0000000000 },
1458 { 0x0000e5bb, 0x00000004 },
1459 { 0x0000e5bc, 0000000000 },
1460 { 0x00120000, 0x0000000c },
1461 { 0x00120000, 0x00000004 },
1462 { 0x001b0002, 0x0000000c },
1463 { 0x0000a000, 0x00000004 },
1464 { 0x0000e821, 0x00000004 },
1465 { 0x0000e800, 0000000000 },
1466 { 0x0000e821, 0x00000004 },
1467 { 0x0000e82e, 0000000000 },
1468 { 0x02cca000, 0x00000004 },
1469 { 0x00140000, 0x00000004 },
1470 { 0x000ce1cc, 0x00000004 },
1471 { 0x050de1cd, 0x00000004 },
1472 { 0x00400000, 0x00000004 },
1473 { 0x00000096, 0x00000018 },
1474 { 0x00c0a000, 0x00000004 },
1475 { 0x00000093, 0x00000008 },
1476 { 0x00000098, 0x00000020 },
1477 { 0x4200e000, 0000000000 },
1478 { 0x0000009f, 0x00000038 },
1479 { 0x000ca000, 0x00000004 },
1480 { 0x00140000, 0x00000004 },
1481 { 0x000c2000, 0x00000004 },
1482 { 0x00160000, 0x00000004 },
1483 { 0x700ce000, 0x00000004 },
1484 { 0x0014009b, 0x00000008 },
1485 { 0x4000e000, 0000000000 },
1486 { 0x02400000, 0x00000004 },
1487 { 0x400ee000, 0x00000004 },
1488 { 0x02400000, 0x00000004 },
1489 { 0x4000e000, 0000000000 },
1490 { 0x00100000, 0x0000002c },
1491 { 0x00004000, 0000000000 },
1492 { 0x080045c8, 0x00000004 },
1493 { 0x00240005, 0x00000004 },
1494 { 0x08004d0b, 0x00000004 },
1495 { 0x000c2000, 0x00000004 },
1496 { 0x0240e51b, 0x00000004 },
1497 { 0x0080e50a, 0x00000005 },
1498 { 0x0080e50b, 0x00000005 },
1499 { 0x00220000, 0x00000004 },
1500 { 0x000700cb, 0x00000004 },
1501 { 0x000000b7, 0x00000038 },
1502 { 0x000c2087, 0x00000030 },
1503 { 0x0880e5bd, 0x00000005 },
1504 { 0x000c2086, 0x00000030 },
1505 { 0x0800e5bb, 0x00000005 },
1506 { 0x000c2087, 0x00000030 },
1507 { 0x0880e5bc, 0x00000005 },
1508 { 0x000000ba, 0x00000008 },
1509 { 0x0080e5bd, 0x00000005 },
1510 { 0x0000e5bb, 0x00000005 },
1511 { 0x0080e5bc, 0x00000005 },
1512 { 0x00210000, 0x00000004 },
1513 { 0x02800000, 0x00000004 },
1514 { 0x00c000be, 0x00000018 },
1515 { 0x4180e000, 0x00000040 },
1516 { 0x000000c0, 0x00000024 },
1517 { 0x01000000, 0x0000000c },
1518 { 0x0100e51d, 0x0000000c },
1519 { 0x000045bb, 0x00000004 },
1520 { 0x000080ba, 0x00000008 },
1521 { 0x03c00830, 0x00000004 },
1522 { 0x4200e000, 0000000000 },
1523 { 0x0000a000, 0x00000004 },
1524 { 0x200045e0, 0x00000004 },
1525 { 0x0000e5e1, 0000000000 },
1526 { 0x00000001, 0000000000 },
1527 { 0x000700c8, 0x00000004 },
1528 { 0x0800e394, 0000000000 },
1529 { 0000000000, 0000000000 },
1530 { 0x0000e8c4, 0x00000004 },
1531 { 0x0000e8c5, 0x00000004 },
1532 { 0x0000e8c6, 0x00000004 },
1533 { 0x0000e928, 0x00000004 },
1534 { 0x0000e929, 0x00000004 },
1535 { 0x0000e92a, 0x00000004 },
1536 { 0x000000cc, 0x00000008 },
1537 { 0x0000e928, 0x00000004 },
1538 { 0x0000e929, 0x00000004 },
1539 { 0x0000e92a, 0x00000004 },
1540 { 0x000000d3, 0x00000008 },
1541 { 0x02c02000, 0x00000004 },
1542 { 0x00060000, 0x00000004 },
1543 { 0x000000db, 0x00000034 },
1544 { 0x000000d8, 0x00000008 },
1545 { 0x00008000, 0x00000004 },
1546 { 0xc000e000, 0000000000 },
1547 { 0x000000e1, 0x00000030 },
1548 { 0x4200e000, 0000000000 },
1549 { 0x000000e1, 0x00000030 },
1550 { 0x4000e000, 0000000000 },
1551 { 0x0025001b, 0x00000004 },
1552 { 0x00230000, 0x00000004 },
1553 { 0x00250005, 0x00000004 },
1554 { 0x000000e6, 0x00000034 },
1555 { 0000000000, 0x0000000c },
1556 { 0x00244000, 0x00000004 },
1557 { 0x080045c8, 0x00000004 },
1558 { 0x00240005, 0x00000004 },
1559 { 0x08004d0b, 0x0000000c },
1560 { 0000000000, 0000000000 },
1561 { 0000000000, 0000000000 },
1562 { 0000000000, 0000000000 },
1563 { 0000000000, 0000000000 },
1564 { 0000000000, 0000000000 },
1565 { 0000000000, 0000000000 },
1566 { 0000000000, 0000000000 },
1567 { 0000000000, 0000000000 },
1568 { 0000000000, 0000000000 },
1569 { 0000000000, 0000000000 },
1570 { 0000000000, 0000000000 },
1571 { 0000000000, 0000000000 },
1572 { 0x000c2000, 0x00000004 },
1573 { 0x001d0018, 0x00000004 },
1574 { 0x001a0001, 0x00000004 },
1575 { 0x000000fb, 0x00000034 },
1576 { 0x0000004a, 0x00000008 },
1577 { 0x0500a04a, 0x00000008 },
1578 { 0000000000, 0000000000 },
1579 { 0000000000, 0000000000 },
1580 { 0000000000, 0000000000 },
1581 { 0000000000, 0000000000 },
1582};
1583
1584static const u32 R520_cp_microcode[][2] = {
1585 { 0x4200e000, 0000000000 },
1586 { 0x4000e000, 0000000000 },
1587 { 0x00000099, 0x00000008 },
1588 { 0x0000009d, 0x00000008 },
1589 { 0x4a554b4a, 0000000000 },
1590 { 0x4a4a4467, 0000000000 },
1591 { 0x55526f75, 0000000000 },
1592 { 0x4a7e7d65, 0000000000 },
1593 { 0xe0dae6f6, 0000000000 },
1594 { 0x4ac54a4a, 0000000000 },
1595 { 0xc8828282, 0000000000 },
1596 { 0xbf4acfc1, 0000000000 },
1597 { 0x87b04ad5, 0000000000 },
1598 { 0xb5838383, 0000000000 },
1599 { 0x4a0f85ba, 0000000000 },
1600 { 0x000ca000, 0x00000004 },
1601 { 0x000d0012, 0x00000038 },
1602 { 0x0000e8b4, 0x00000004 },
1603 { 0x000d0014, 0x00000038 },
1604 { 0x0000e8b6, 0x00000004 },
1605 { 0x000d0016, 0x00000038 },
1606 { 0x0000e854, 0x00000004 },
1607 { 0x000d0018, 0x00000038 },
1608 { 0x0000e855, 0x00000004 },
1609 { 0x000d001a, 0x00000038 },
1610 { 0x0000e856, 0x00000004 },
1611 { 0x000d001c, 0x00000038 },
1612 { 0x0000e857, 0x00000004 },
1613 { 0x000d001e, 0x00000038 },
1614 { 0x0000e824, 0x00000004 },
1615 { 0x000d0020, 0x00000038 },
1616 { 0x0000e825, 0x00000004 },
1617 { 0x000d0022, 0x00000038 },
1618 { 0x0000e830, 0x00000004 },
1619 { 0x000d0024, 0x00000038 },
1620 { 0x0000f0c0, 0x00000004 },
1621 { 0x000d0026, 0x00000038 },
1622 { 0x0000f0c1, 0x00000004 },
1623 { 0x000d0028, 0x00000038 },
1624 { 0x0000e000, 0x00000004 },
1625 { 0x000d002a, 0x00000038 },
1626 { 0x0000e000, 0x00000004 },
1627 { 0x000d002c, 0x00000038 },
1628 { 0x0000e000, 0x00000004 },
1629 { 0x000d002e, 0x00000038 },
1630 { 0x0000e000, 0x00000004 },
1631 { 0x000d0030, 0x00000038 },
1632 { 0x0000e000, 0x00000004 },
1633 { 0x000d0032, 0x00000038 },
1634 { 0x0000f180, 0x00000004 },
1635 { 0x000d0034, 0x00000038 },
1636 { 0x0000f393, 0x00000004 },
1637 { 0x000d0036, 0x00000038 },
1638 { 0x0000f38a, 0x00000004 },
1639 { 0x000d0038, 0x00000038 },
1640 { 0x0000f38e, 0x00000004 },
1641 { 0x0000e821, 0x00000004 },
1642 { 0x0140a000, 0x00000004 },
1643 { 0x00000043, 0x00000018 },
1644 { 0x00cce800, 0x00000004 },
1645 { 0x001b0001, 0x00000004 },
1646 { 0x08004800, 0x00000004 },
1647 { 0x001b0001, 0x00000004 },
1648 { 0x08004800, 0x00000004 },
1649 { 0x001b0001, 0x00000004 },
1650 { 0x08004800, 0x00000004 },
1651 { 0x0000003a, 0x00000008 },
1652 { 0x0000a000, 0000000000 },
1653 { 0x2000451d, 0x00000004 },
1654 { 0x0000e580, 0x00000004 },
1655 { 0x000ce581, 0x00000004 },
1656 { 0x08004580, 0x00000004 },
1657 { 0x000ce581, 0x00000004 },
1658 { 0x00000047, 0x00000008 },
1659 { 0x0000a000, 0000000000 },
1660 { 0x000c2000, 0x00000004 },
1661 { 0x0000e50e, 0x00000004 },
1662 { 0x00032000, 0x00000004 },
1663 { 0x00022051, 0x00000028 },
1664 { 0x00000051, 0x00000024 },
1665 { 0x0800450f, 0x00000004 },
1666 { 0x0000a04b, 0x00000008 },
1667 { 0x0000e565, 0x00000004 },
1668 { 0x0000e566, 0x00000004 },
1669 { 0x00000052, 0x00000008 },
1670 { 0x03cca5b4, 0x00000004 },
1671 { 0x05432000, 0x00000004 },
1672 { 0x00022000, 0x00000004 },
1673 { 0x4ccce05e, 0x00000030 },
1674 { 0x08274565, 0x00000004 },
1675 { 0x0000005e, 0x00000030 },
1676 { 0x08004564, 0x00000004 },
1677 { 0x0000e566, 0x00000004 },
1678 { 0x00000055, 0x00000008 },
1679 { 0x00802061, 0x00000010 },
1680 { 0x00202000, 0x00000004 },
1681 { 0x001b00ff, 0x00000004 },
1682 { 0x01000064, 0x00000010 },
1683 { 0x001f2000, 0x00000004 },
1684 { 0x001c00ff, 0x00000004 },
1685 { 0000000000, 0x0000000c },
1686 { 0x00000072, 0x00000030 },
1687 { 0x00000055, 0x00000008 },
1688 { 0x0000e576, 0x00000004 },
1689 { 0x0000e577, 0x00000004 },
1690 { 0x0000e50e, 0x00000004 },
1691 { 0x0000e50f, 0x00000004 },
1692 { 0x0140a000, 0x00000004 },
1693 { 0x00000069, 0x00000018 },
1694 { 0x00c0e5f9, 0x000000c2 },
1695 { 0x00000069, 0x00000008 },
1696 { 0x0014e50e, 0x00000004 },
1697 { 0x0040e50f, 0x00000004 },
1698 { 0x00c0006c, 0x00000008 },
1699 { 0x0000e570, 0x00000004 },
1700 { 0x0000e571, 0x00000004 },
1701 { 0x0000e572, 0x0000000c },
1702 { 0x0000a000, 0x00000004 },
1703 { 0x0140a000, 0x00000004 },
1704 { 0x0000e568, 0x00000004 },
1705 { 0x000c2000, 0x00000004 },
1706 { 0x00000076, 0x00000018 },
1707 { 0x000b0000, 0x00000004 },
1708 { 0x18c0e562, 0x00000004 },
1709 { 0x00000078, 0x00000008 },
1710 { 0x00c00077, 0x00000008 },
1711 { 0x000700c7, 0x00000004 },
1712 { 0x00000080, 0x00000038 },
1713 { 0x0000e5bb, 0x00000004 },
1714 { 0x0000e5bc, 0000000000 },
1715 { 0x0000a000, 0x00000004 },
1716 { 0x0000e821, 0x00000004 },
1717 { 0x0000e800, 0000000000 },
1718 { 0x0000e821, 0x00000004 },
1719 { 0x0000e82e, 0000000000 },
1720 { 0x02cca000, 0x00000004 },
1721 { 0x00140000, 0x00000004 },
1722 { 0x000ce1cc, 0x00000004 },
1723 { 0x050de1cd, 0x00000004 },
1724 { 0x00400000, 0x00000004 },
1725 { 0x0000008f, 0x00000018 },
1726 { 0x00c0a000, 0x00000004 },
1727 { 0x0000008c, 0x00000008 },
1728 { 0x00000091, 0x00000020 },
1729 { 0x4200e000, 0000000000 },
1730 { 0x00000098, 0x00000038 },
1731 { 0x000ca000, 0x00000004 },
1732 { 0x00140000, 0x00000004 },
1733 { 0x000c2000, 0x00000004 },
1734 { 0x00160000, 0x00000004 },
1735 { 0x700ce000, 0x00000004 },
1736 { 0x00140094, 0x00000008 },
1737 { 0x4000e000, 0000000000 },
1738 { 0x02400000, 0x00000004 },
1739 { 0x400ee000, 0x00000004 },
1740 { 0x02400000, 0x00000004 },
1741 { 0x4000e000, 0000000000 },
1742 { 0x000c2000, 0x00000004 },
1743 { 0x0240e51b, 0x00000004 },
1744 { 0x0080e50a, 0x00000005 },
1745 { 0x0080e50b, 0x00000005 },
1746 { 0x00220000, 0x00000004 },
1747 { 0x000700c7, 0x00000004 },
1748 { 0x000000a4, 0x00000038 },
1749 { 0x0080e5bd, 0x00000005 },
1750 { 0x0000e5bb, 0x00000005 },
1751 { 0x0080e5bc, 0x00000005 },
1752 { 0x00210000, 0x00000004 },
1753 { 0x02800000, 0x00000004 },
1754 { 0x00c000ab, 0x00000018 },
1755 { 0x4180e000, 0x00000040 },
1756 { 0x000000ad, 0x00000024 },
1757 { 0x01000000, 0x0000000c },
1758 { 0x0100e51d, 0x0000000c },
1759 { 0x000045bb, 0x00000004 },
1760 { 0x000080a7, 0x00000008 },
1761 { 0x0000f3ce, 0x00000004 },
1762 { 0x0140a000, 0x00000004 },
1763 { 0x00cc2000, 0x00000004 },
1764 { 0x08c053cf, 0x00000040 },
1765 { 0x00008000, 0000000000 },
1766 { 0x0000f3d2, 0x00000004 },
1767 { 0x0140a000, 0x00000004 },
1768 { 0x00cc2000, 0x00000004 },
1769 { 0x08c053d3, 0x00000040 },
1770 { 0x00008000, 0000000000 },
1771 { 0x0000f39d, 0x00000004 },
1772 { 0x0140a000, 0x00000004 },
1773 { 0x00cc2000, 0x00000004 },
1774 { 0x08c0539e, 0x00000040 },
1775 { 0x00008000, 0000000000 },
1776 { 0x03c00830, 0x00000004 },
1777 { 0x4200e000, 0000000000 },
1778 { 0x0000a000, 0x00000004 },
1779 { 0x200045e0, 0x00000004 },
1780 { 0x0000e5e1, 0000000000 },
1781 { 0x00000001, 0000000000 },
1782 { 0x000700c4, 0x00000004 },
1783 { 0x0800e394, 0000000000 },
1784 { 0000000000, 0000000000 },
1785 { 0x0000e8c4, 0x00000004 },
1786 { 0x0000e8c5, 0x00000004 },
1787 { 0x0000e8c6, 0x00000004 },
1788 { 0x0000e928, 0x00000004 },
1789 { 0x0000e929, 0x00000004 },
1790 { 0x0000e92a, 0x00000004 },
1791 { 0x000000c8, 0x00000008 },
1792 { 0x0000e928, 0x00000004 },
1793 { 0x0000e929, 0x00000004 },
1794 { 0x0000e92a, 0x00000004 },
1795 { 0x000000cf, 0x00000008 },
1796 { 0xdeadbeef, 0000000000 },
1797 { 0x00000116, 0000000000 },
1798 { 0x000700d3, 0x00000004 },
1799 { 0x080050e7, 0x00000004 },
1800 { 0x000700d4, 0x00000004 },
1801 { 0x0800401c, 0x00000004 },
1802 { 0x0000e01d, 0000000000 },
1803 { 0x02c02000, 0x00000004 },
1804 { 0x00060000, 0x00000004 },
1805 { 0x000000de, 0x00000034 },
1806 { 0x000000db, 0x00000008 },
1807 { 0x00008000, 0x00000004 },
1808 { 0xc000e000, 0000000000 },
1809 { 0x0000e1cc, 0x00000004 },
1810 { 0x0500e1cd, 0x00000004 },
1811 { 0x000ca000, 0x00000004 },
1812 { 0x000000e5, 0x00000034 },
1813 { 0x000000e1, 0x00000008 },
1814 { 0x0000a000, 0000000000 },
1815 { 0x0019e1cc, 0x00000004 },
1816 { 0x001b0001, 0x00000004 },
1817 { 0x0500a000, 0x00000004 },
1818 { 0x080041cd, 0x00000004 },
1819 { 0x000ca000, 0x00000004 },
1820 { 0x000000fb, 0x00000034 },
1821 { 0x0000004a, 0x00000008 },
1822 { 0000000000, 0000000000 },
1823 { 0000000000, 0000000000 },
1824 { 0000000000, 0000000000 },
1825 { 0000000000, 0000000000 },
1826 { 0000000000, 0000000000 },
1827 { 0000000000, 0000000000 },
1828 { 0000000000, 0000000000 },
1829 { 0000000000, 0000000000 },
1830 { 0000000000, 0000000000 },
1831 { 0x000c2000, 0x00000004 },
1832 { 0x001d0018, 0x00000004 },
1833 { 0x001a0001, 0x00000004 },
1834 { 0x000000fb, 0x00000034 },
1835 { 0x0000004a, 0x00000008 },
1836 { 0x0500a04a, 0x00000008 },
1837 { 0000000000, 0000000000 },
1838 { 0000000000, 0000000000 },
1839 { 0000000000, 0000000000 },
1840 { 0000000000, 0000000000 },
1841};
1842
1843
1844#endif
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index 6f75512f591e..11c146b49211 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -1662,7 +1662,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1662 u32 height; 1662 u32 height;
1663 int i; 1663 int i;
1664 u32 texpitch, microtile; 1664 u32 texpitch, microtile;
1665 u32 offset; 1665 u32 offset, byte_offset;
1666 RING_LOCALS; 1666 RING_LOCALS;
1667 1667
1668 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) { 1668 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
@@ -1727,6 +1727,13 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1727 } else 1727 } else
1728 microtile = 0; 1728 microtile = 0;
1729 1729
1730 /* this might fail for zero-sized uploads - are those illegal? */
1731 if (!radeon_check_offset(dev_priv, tex->offset + image->height *
1732 blit_width - 1)) {
1733 DRM_ERROR("Invalid final destination offset\n");
1734 return -EINVAL;
1735 }
1736
1730 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width); 1737 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
1731 1738
1732 do { 1739 do {
@@ -1840,6 +1847,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1840 } 1847 }
1841 1848
1842#undef RADEON_COPY_MT 1849#undef RADEON_COPY_MT
1850 byte_offset = (image->y & ~2047) * blit_width;
1843 buf->file_priv = file_priv; 1851 buf->file_priv = file_priv;
1844 buf->used = size; 1852 buf->used = size;
1845 offset = dev_priv->gart_buffers_offset + buf->offset; 1853 offset = dev_priv->gart_buffers_offset + buf->offset;
@@ -1854,9 +1862,9 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1854 RADEON_DP_SRC_SOURCE_MEMORY | 1862 RADEON_DP_SRC_SOURCE_MEMORY |
1855 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); 1863 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1856 OUT_RING((spitch << 22) | (offset >> 10)); 1864 OUT_RING((spitch << 22) | (offset >> 10));
1857 OUT_RING((texpitch << 22) | (tex->offset >> 10)); 1865 OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
1858 OUT_RING(0); 1866 OUT_RING(0);
1859 OUT_RING((image->x << 16) | image->y); 1867 OUT_RING((image->x << 16) | (image->y % 2048));
1860 OUT_RING((image->width << 16) | height); 1868 OUT_RING((image->width << 16) | height);
1861 RADEON_WAIT_UNTIL_2D_IDLE(); 1869 RADEON_WAIT_UNTIL_2D_IDLE();
1862 ADVANCE_RING(); 1870 ADVANCE_RING();
@@ -3037,6 +3045,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
3037 case RADEON_PARAM_FB_LOCATION: 3045 case RADEON_PARAM_FB_LOCATION:
3038 value = radeon_read_fb_location(dev_priv); 3046 value = radeon_read_fb_location(dev_priv);
3039 break; 3047 break;
3048 case RADEON_PARAM_NUM_GB_PIPES:
3049 value = dev_priv->num_gb_pipes;
3050 break;
3040 default: 3051 default:
3041 DRM_DEBUG("Invalid parameter %d\n", param->param); 3052 DRM_DEBUG("Invalid parameter %d\n", param->param);
3042 return -EINVAL; 3053 return -EINVAL;
diff --git a/drivers/char/drm/via_drv.c b/drivers/char/drm/via_drv.c
index 37870a4a3dc7..80c01cdfa37d 100644
--- a/drivers/char/drm/via_drv.c
+++ b/drivers/char/drm/via_drv.c
@@ -40,13 +40,11 @@ static struct pci_device_id pciidlist[] = {
40static struct drm_driver driver = { 40static struct drm_driver driver = {
41 .driver_features = 41 .driver_features =
42 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | 42 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_IRQ |
43 DRIVER_IRQ_SHARED, 43 DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL,
44 .load = via_driver_load, 44 .load = via_driver_load,
45 .unload = via_driver_unload, 45 .unload = via_driver_unload,
46 .context_dtor = via_final_context, 46 .context_dtor = via_final_context,
47 .get_vblank_counter = via_get_vblank_counter, 47 .vblank_wait = via_driver_vblank_wait,
48 .enable_vblank = via_enable_vblank,
49 .disable_vblank = via_disable_vblank,
50 .irq_preinstall = via_driver_irq_preinstall, 48 .irq_preinstall = via_driver_irq_preinstall,
51 .irq_postinstall = via_driver_irq_postinstall, 49 .irq_postinstall = via_driver_irq_postinstall,
52 .irq_uninstall = via_driver_irq_uninstall, 50 .irq_uninstall = via_driver_irq_uninstall,
diff --git a/drivers/char/drm/via_drv.h b/drivers/char/drm/via_drv.h
index fe67030e39ac..2daae81874cd 100644
--- a/drivers/char/drm/via_drv.h
+++ b/drivers/char/drm/via_drv.h
@@ -75,7 +75,6 @@ typedef struct drm_via_private {
75 struct timeval last_vblank; 75 struct timeval last_vblank;
76 int last_vblank_valid; 76 int last_vblank_valid;
77 unsigned usec_per_vblank; 77 unsigned usec_per_vblank;
78 atomic_t vbl_received;
79 drm_via_state_t hc_state; 78 drm_via_state_t hc_state;
80 char pci_buf[VIA_PCI_BUF_SIZE]; 79 char pci_buf[VIA_PCI_BUF_SIZE];
81 const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE]; 80 const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE];
@@ -131,13 +130,11 @@ extern int via_init_context(struct drm_device * dev, int context);
131extern int via_final_context(struct drm_device * dev, int context); 130extern int via_final_context(struct drm_device * dev, int context);
132 131
133extern int via_do_cleanup_map(struct drm_device * dev); 132extern int via_do_cleanup_map(struct drm_device * dev);
134extern u32 via_get_vblank_counter(struct drm_device *dev, int crtc); 133extern int via_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence);
135extern int via_enable_vblank(struct drm_device *dev, int crtc);
136extern void via_disable_vblank(struct drm_device *dev, int crtc);
137 134
138extern irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS); 135extern irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS);
139extern void via_driver_irq_preinstall(struct drm_device * dev); 136extern void via_driver_irq_preinstall(struct drm_device * dev);
140extern int via_driver_irq_postinstall(struct drm_device * dev); 137extern void via_driver_irq_postinstall(struct drm_device * dev);
141extern void via_driver_irq_uninstall(struct drm_device * dev); 138extern void via_driver_irq_uninstall(struct drm_device * dev);
142 139
143extern int via_dma_cleanup(struct drm_device * dev); 140extern int via_dma_cleanup(struct drm_device * dev);
diff --git a/drivers/char/drm/via_irq.c b/drivers/char/drm/via_irq.c
index f1ab6fc7c07e..c6bb978a1106 100644
--- a/drivers/char/drm/via_irq.c
+++ b/drivers/char/drm/via_irq.c
@@ -92,17 +92,8 @@ static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
92static unsigned time_diff(struct timeval *now, struct timeval *then) 92static unsigned time_diff(struct timeval *now, struct timeval *then)
93{ 93{
94 return (now->tv_usec >= then->tv_usec) ? 94 return (now->tv_usec >= then->tv_usec) ?
95 now->tv_usec - then->tv_usec : 95 now->tv_usec - then->tv_usec :
96 1000000 - (then->tv_usec - now->tv_usec); 96 1000000 - (then->tv_usec - now->tv_usec);
97}
98
99u32 via_get_vblank_counter(struct drm_device *dev, int crtc)
100{
101 drm_via_private_t *dev_priv = dev->dev_private;
102 if (crtc != 0)
103 return 0;
104
105 return atomic_read(&dev_priv->vbl_received);
106} 97}
107 98
108irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS) 99irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
@@ -117,8 +108,8 @@ irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
117 108
118 status = VIA_READ(VIA_REG_INTERRUPT); 109 status = VIA_READ(VIA_REG_INTERRUPT);
119 if (status & VIA_IRQ_VBLANK_PENDING) { 110 if (status & VIA_IRQ_VBLANK_PENDING) {
120 atomic_inc(&dev_priv->vbl_received); 111 atomic_inc(&dev->vbl_received);
121 if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) { 112 if (!(atomic_read(&dev->vbl_received) & 0x0F)) {
122 do_gettimeofday(&cur_vblank); 113 do_gettimeofday(&cur_vblank);
123 if (dev_priv->last_vblank_valid) { 114 if (dev_priv->last_vblank_valid) {
124 dev_priv->usec_per_vblank = 115 dev_priv->usec_per_vblank =
@@ -128,11 +119,12 @@ irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
128 dev_priv->last_vblank = cur_vblank; 119 dev_priv->last_vblank = cur_vblank;
129 dev_priv->last_vblank_valid = 1; 120 dev_priv->last_vblank_valid = 1;
130 } 121 }
131 if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) { 122 if (!(atomic_read(&dev->vbl_received) & 0xFF)) {
132 DRM_DEBUG("US per vblank is: %u\n", 123 DRM_DEBUG("US per vblank is: %u\n",
133 dev_priv->usec_per_vblank); 124 dev_priv->usec_per_vblank);
134 } 125 }
135 drm_handle_vblank(dev, 0); 126 DRM_WAKEUP(&dev->vbl_queue);
127 drm_vbl_send_signals(dev);
136 handled = 1; 128 handled = 1;
137 } 129 }
138 130
@@ -171,34 +163,31 @@ static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv)
171 } 163 }
172} 164}
173 165
174int via_enable_vblank(struct drm_device *dev, int crtc) 166int via_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence)
175{ 167{
176 drm_via_private_t *dev_priv = dev->dev_private; 168 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
177 u32 status; 169 unsigned int cur_vblank;
170 int ret = 0;
178 171
179 if (crtc != 0) { 172 DRM_DEBUG("\n");
180 DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc); 173 if (!dev_priv) {
174 DRM_ERROR("called with no initialization\n");
181 return -EINVAL; 175 return -EINVAL;
182 } 176 }
183 177
184 status = VIA_READ(VIA_REG_INTERRUPT); 178 viadrv_acknowledge_irqs(dev_priv);
185 VIA_WRITE(VIA_REG_INTERRUPT, status & VIA_IRQ_VBLANK_ENABLE);
186 179
187 VIA_WRITE8(0x83d4, 0x11); 180 /* Assume that the user has missed the current sequence number
188 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30); 181 * by about a day rather than she wants to wait for years
182 * using vertical blanks...
183 */
189 184
190 return 0; 185 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
191} 186 (((cur_vblank = atomic_read(&dev->vbl_received)) -
187 *sequence) <= (1 << 23)));
192 188
193void via_disable_vblank(struct drm_device *dev, int crtc) 189 *sequence = cur_vblank;
194{ 190 return ret;
195 drm_via_private_t *dev_priv = dev->dev_private;
196
197 VIA_WRITE8(0x83d4, 0x11);
198 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
199
200 if (crtc != 0)
201 DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc);
202} 191}
203 192
204static int 193static int
@@ -303,25 +292,23 @@ void via_driver_irq_preinstall(struct drm_device * dev)
303 } 292 }
304} 293}
305 294
306int via_driver_irq_postinstall(struct drm_device * dev) 295void via_driver_irq_postinstall(struct drm_device * dev)
307{ 296{
308 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 297 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
309 u32 status; 298 u32 status;
310 299
311 DRM_DEBUG("via_driver_irq_postinstall\n"); 300 DRM_DEBUG("\n");
312 if (!dev_priv) 301 if (dev_priv) {
313 return -EINVAL; 302 status = VIA_READ(VIA_REG_INTERRUPT);
303 VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
304 | dev_priv->irq_enable_mask);
314 305
315 drm_vblank_init(dev, 1); 306 /* Some magic, oh for some data sheets ! */
316 status = VIA_READ(VIA_REG_INTERRUPT);
317 VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
318 | dev_priv->irq_enable_mask);
319 307
320 /* Some magic, oh for some data sheets ! */ 308 VIA_WRITE8(0x83d4, 0x11);
321 VIA_WRITE8(0x83d4, 0x11); 309 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
322 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
323 310
324 return 0; 311 }
325} 312}
326 313
327void via_driver_irq_uninstall(struct drm_device * dev) 314void via_driver_irq_uninstall(struct drm_device * dev)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 11:24:51 -0500