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path: root/drivers/char/drm/radeon_state.c
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Diffstat (limited to 'drivers/char/drm/radeon_state.c')
-rw-r--r--drivers/char/drm/radeon_state.c2473
1 files changed, 1257 insertions, 1216 deletions
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index 64a3e3a406ef..231ac1438c69 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -37,51 +37,58 @@
37 * Helper functions for client state checking and fixup 37 * Helper functions for client state checking and fixup
38 */ 38 */
39 39
40static __inline__ int radeon_check_and_fixup_offset( drm_radeon_private_t *dev_priv, 40static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
41 drm_file_t *filp_priv, 41 dev_priv,
42 u32 *offset ) { 42 drm_file_t * filp_priv,
43 u32 *offset)
44{
43 u32 off = *offset; 45 u32 off = *offset;
44 struct drm_radeon_driver_file_fields *radeon_priv; 46 struct drm_radeon_driver_file_fields *radeon_priv;
45 47
46 if ( off >= dev_priv->fb_location && 48 if (off >= dev_priv->fb_location &&
47 off < ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) 49 off < (dev_priv->gart_vm_start + dev_priv->gart_size))
48 return 0; 50 return 0;
49 51
50 radeon_priv = filp_priv->driver_priv; 52 radeon_priv = filp_priv->driver_priv;
51 off += radeon_priv->radeon_fb_delta; 53 off += radeon_priv->radeon_fb_delta;
52 54
53 DRM_DEBUG( "offset fixed up to 0x%x\n", off ); 55 DRM_DEBUG("offset fixed up to 0x%x\n", off);
54 56
55 if ( off < dev_priv->fb_location || 57 if (off < dev_priv->fb_location ||
56 off >= ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) 58 off >= (dev_priv->gart_vm_start + dev_priv->gart_size))
57 return DRM_ERR( EINVAL ); 59 return DRM_ERR(EINVAL);
58 60
59 *offset = off; 61 *offset = off;
60 62
61 return 0; 63 return 0;
62} 64}
63 65
64static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_priv, 66static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
65 drm_file_t *filp_priv, 67 dev_priv,
66 int id, 68 drm_file_t * filp_priv,
67 u32 __user *data ) { 69 int id, u32 *data)
68 switch ( id ) { 70{
71 switch (id) {
69 72
70 case RADEON_EMIT_PP_MISC: 73 case RADEON_EMIT_PP_MISC:
71 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 74 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
72 &data[( RADEON_RB3D_DEPTHOFFSET 75 &data[(RADEON_RB3D_DEPTHOFFSET
73 - RADEON_PP_MISC ) / 4] ) ) { 76 -
74 DRM_ERROR( "Invalid depth buffer offset\n" ); 77 RADEON_PP_MISC) /
75 return DRM_ERR( EINVAL ); 78 4])) {
79 DRM_ERROR("Invalid depth buffer offset\n");
80 return DRM_ERR(EINVAL);
76 } 81 }
77 break; 82 break;
78 83
79 case RADEON_EMIT_PP_CNTL: 84 case RADEON_EMIT_PP_CNTL:
80 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 85 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
81 &data[( RADEON_RB3D_COLOROFFSET 86 &data[(RADEON_RB3D_COLOROFFSET
82 - RADEON_PP_CNTL ) / 4] ) ) { 87 -
83 DRM_ERROR( "Invalid colour buffer offset\n" ); 88 RADEON_PP_CNTL) /
84 return DRM_ERR( EINVAL ); 89 4])) {
90 DRM_ERROR("Invalid colour buffer offset\n");
91 return DRM_ERR(EINVAL);
85 } 92 }
86 break; 93 break;
87 94
@@ -91,21 +98,23 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
91 case R200_EMIT_PP_TXOFFSET_3: 98 case R200_EMIT_PP_TXOFFSET_3:
92 case R200_EMIT_PP_TXOFFSET_4: 99 case R200_EMIT_PP_TXOFFSET_4:
93 case R200_EMIT_PP_TXOFFSET_5: 100 case R200_EMIT_PP_TXOFFSET_5:
94 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 101 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
95 &data[0] ) ) { 102 &data[0])) {
96 DRM_ERROR( "Invalid R200 texture offset\n" ); 103 DRM_ERROR("Invalid R200 texture offset\n");
97 return DRM_ERR( EINVAL ); 104 return DRM_ERR(EINVAL);
98 } 105 }
99 break; 106 break;
100 107
101 case RADEON_EMIT_PP_TXFILTER_0: 108 case RADEON_EMIT_PP_TXFILTER_0:
102 case RADEON_EMIT_PP_TXFILTER_1: 109 case RADEON_EMIT_PP_TXFILTER_1:
103 case RADEON_EMIT_PP_TXFILTER_2: 110 case RADEON_EMIT_PP_TXFILTER_2:
104 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 111 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
105 &data[( RADEON_PP_TXOFFSET_0 112 &data[(RADEON_PP_TXOFFSET_0
106 - RADEON_PP_TXFILTER_0 ) / 4] ) ) { 113 -
107 DRM_ERROR( "Invalid R100 texture offset\n" ); 114 RADEON_PP_TXFILTER_0) /
108 return DRM_ERR( EINVAL ); 115 4])) {
116 DRM_ERROR("Invalid R100 texture offset\n");
117 return DRM_ERR(EINVAL);
109 } 118 }
110 break; 119 break;
111 120
@@ -114,17 +123,18 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
114 case R200_EMIT_PP_CUBIC_OFFSETS_2: 123 case R200_EMIT_PP_CUBIC_OFFSETS_2:
115 case R200_EMIT_PP_CUBIC_OFFSETS_3: 124 case R200_EMIT_PP_CUBIC_OFFSETS_3:
116 case R200_EMIT_PP_CUBIC_OFFSETS_4: 125 case R200_EMIT_PP_CUBIC_OFFSETS_4:
117 case R200_EMIT_PP_CUBIC_OFFSETS_5: { 126 case R200_EMIT_PP_CUBIC_OFFSETS_5:{
118 int i; 127 int i;
119 for ( i = 0; i < 5; i++ ) { 128 for (i = 0; i < 5; i++) {
120 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 129 if (radeon_check_and_fixup_offset
121 &data[i] ) ) { 130 (dev_priv, filp_priv, &data[i])) {
122 DRM_ERROR( "Invalid R200 cubic texture offset\n" ); 131 DRM_ERROR
123 return DRM_ERR( EINVAL ); 132 ("Invalid R200 cubic texture offset\n");
133 return DRM_ERR(EINVAL);
134 }
124 } 135 }
136 break;
125 } 137 }
126 break;
127 }
128 138
129 case RADEON_EMIT_PP_CUBIC_OFFSETS_T0: 139 case RADEON_EMIT_PP_CUBIC_OFFSETS_T0:
130 case RADEON_EMIT_PP_CUBIC_OFFSETS_T1: 140 case RADEON_EMIT_PP_CUBIC_OFFSETS_T1:
@@ -207,247 +217,259 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
207 case RADEON_EMIT_PP_CUBIC_FACES_1: 217 case RADEON_EMIT_PP_CUBIC_FACES_1:
208 case RADEON_EMIT_PP_CUBIC_FACES_2: 218 case RADEON_EMIT_PP_CUBIC_FACES_2:
209 case R200_EMIT_PP_TRI_PERF_CNTL: 219 case R200_EMIT_PP_TRI_PERF_CNTL:
220 case R200_EMIT_PP_AFS_0:
221 case R200_EMIT_PP_AFS_1:
222 case R200_EMIT_ATF_TFACTOR:
223 case R200_EMIT_PP_TXCTLALL_0:
224 case R200_EMIT_PP_TXCTLALL_1:
225 case R200_EMIT_PP_TXCTLALL_2:
226 case R200_EMIT_PP_TXCTLALL_3:
227 case R200_EMIT_PP_TXCTLALL_4:
228 case R200_EMIT_PP_TXCTLALL_5:
210 /* These packets don't contain memory offsets */ 229 /* These packets don't contain memory offsets */
211 break; 230 break;
212 231
213 default: 232 default:
214 DRM_ERROR( "Unknown state packet ID %d\n", id ); 233 DRM_ERROR("Unknown state packet ID %d\n", id);
215 return DRM_ERR( EINVAL ); 234 return DRM_ERR(EINVAL);
216 } 235 }
217 236
218 return 0; 237 return 0;
219} 238}
220 239
221static __inline__ int radeon_check_and_fixup_packet3( drm_radeon_private_t *dev_priv, 240static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
222 drm_file_t *filp_priv, 241 dev_priv,
223 drm_radeon_cmd_buffer_t *cmdbuf, 242 drm_file_t * filp_priv,
224 unsigned int *cmdsz ) { 243 drm_radeon_kcmd_buffer_t *cmdbuf,
244 unsigned int *cmdsz)
245{
225 u32 *cmd = (u32 *) cmdbuf->buf; 246 u32 *cmd = (u32 *) cmdbuf->buf;
226 247
227 *cmdsz = 2 + ( ( cmd[0] & RADEON_CP_PACKET_COUNT_MASK ) >> 16 ); 248 *cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
228 249
229 if ( ( cmd[0] & 0xc0000000 ) != RADEON_CP_PACKET3 ) { 250 if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) {
230 DRM_ERROR( "Not a type 3 packet\n" ); 251 DRM_ERROR("Not a type 3 packet\n");
231 return DRM_ERR( EINVAL ); 252 return DRM_ERR(EINVAL);
232 } 253 }
233 254
234 if ( 4 * *cmdsz > cmdbuf->bufsz ) { 255 if (4 * *cmdsz > cmdbuf->bufsz) {
235 DRM_ERROR( "Packet size larger than size of data provided\n" ); 256 DRM_ERROR("Packet size larger than size of data provided\n");
236 return DRM_ERR( EINVAL ); 257 return DRM_ERR(EINVAL);
237 } 258 }
238 259
239 /* Check client state and fix it up if necessary */ 260 /* Check client state and fix it up if necessary */
240 if ( cmd[0] & 0x8000 ) { /* MSB of opcode: next DWORD GUI_CNTL */ 261 if (cmd[0] & 0x8000) { /* MSB of opcode: next DWORD GUI_CNTL */
241 u32 offset; 262 u32 offset;
242 263
243 if ( cmd[1] & ( RADEON_GMC_SRC_PITCH_OFFSET_CNTL 264 if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
244 | RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) { 265 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
245 offset = cmd[2] << 10; 266 offset = cmd[2] << 10;
246 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { 267 if (radeon_check_and_fixup_offset
247 DRM_ERROR( "Invalid first packet offset\n" ); 268 (dev_priv, filp_priv, &offset)) {
248 return DRM_ERR( EINVAL ); 269 DRM_ERROR("Invalid first packet offset\n");
270 return DRM_ERR(EINVAL);
249 } 271 }
250 cmd[2] = ( cmd[2] & 0xffc00000 ) | offset >> 10; 272 cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10;
251 } 273 }
252 274
253 if ( ( cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL ) && 275 if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
254 ( cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) { 276 (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
255 offset = cmd[3] << 10; 277 offset = cmd[3] << 10;
256 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { 278 if (radeon_check_and_fixup_offset
257 DRM_ERROR( "Invalid second packet offset\n" ); 279 (dev_priv, filp_priv, &offset)) {
258 return DRM_ERR( EINVAL ); 280 DRM_ERROR("Invalid second packet offset\n");
281 return DRM_ERR(EINVAL);
259 } 282 }
260 cmd[3] = ( cmd[3] & 0xffc00000 ) | offset >> 10; 283 cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10;
261 } 284 }
262 } 285 }
263 286
264 return 0; 287 return 0;
265} 288}
266 289
267
268/* ================================================================ 290/* ================================================================
269 * CP hardware state programming functions 291 * CP hardware state programming functions
270 */ 292 */
271 293
272static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv, 294static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
273 drm_clip_rect_t *box ) 295 drm_clip_rect_t * box)
274{ 296{
275 RING_LOCALS; 297 RING_LOCALS;
276 298
277 DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n", 299 DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n",
278 box->x1, box->y1, box->x2, box->y2 ); 300 box->x1, box->y1, box->x2, box->y2);
279 301
280 BEGIN_RING( 4 ); 302 BEGIN_RING(4);
281 OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) ); 303 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
282 OUT_RING( (box->y1 << 16) | box->x1 ); 304 OUT_RING((box->y1 << 16) | box->x1);
283 OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) ); 305 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
284 OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) ); 306 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
285 ADVANCE_RING(); 307 ADVANCE_RING();
286} 308}
287 309
288/* Emit 1.1 state 310/* Emit 1.1 state
289 */ 311 */
290static int radeon_emit_state( drm_radeon_private_t *dev_priv, 312static int radeon_emit_state(drm_radeon_private_t * dev_priv,
291 drm_file_t *filp_priv, 313 drm_file_t * filp_priv,
292 drm_radeon_context_regs_t *ctx, 314 drm_radeon_context_regs_t * ctx,
293 drm_radeon_texture_regs_t *tex, 315 drm_radeon_texture_regs_t * tex,
294 unsigned int dirty ) 316 unsigned int dirty)
295{ 317{
296 RING_LOCALS; 318 RING_LOCALS;
297 DRM_DEBUG( "dirty=0x%08x\n", dirty ); 319 DRM_DEBUG("dirty=0x%08x\n", dirty);
298 320
299 if ( dirty & RADEON_UPLOAD_CONTEXT ) { 321 if (dirty & RADEON_UPLOAD_CONTEXT) {
300 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 322 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
301 &ctx->rb3d_depthoffset ) ) { 323 &ctx->rb3d_depthoffset)) {
302 DRM_ERROR( "Invalid depth buffer offset\n" ); 324 DRM_ERROR("Invalid depth buffer offset\n");
303 return DRM_ERR( EINVAL ); 325 return DRM_ERR(EINVAL);
304 } 326 }
305 327
306 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 328 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
307 &ctx->rb3d_coloroffset ) ) { 329 &ctx->rb3d_coloroffset)) {
308 DRM_ERROR( "Invalid depth buffer offset\n" ); 330 DRM_ERROR("Invalid depth buffer offset\n");
309 return DRM_ERR( EINVAL ); 331 return DRM_ERR(EINVAL);
310 } 332 }
311 333
312 BEGIN_RING( 14 ); 334 BEGIN_RING(14);
313 OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) ); 335 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
314 OUT_RING( ctx->pp_misc ); 336 OUT_RING(ctx->pp_misc);
315 OUT_RING( ctx->pp_fog_color ); 337 OUT_RING(ctx->pp_fog_color);
316 OUT_RING( ctx->re_solid_color ); 338 OUT_RING(ctx->re_solid_color);
317 OUT_RING( ctx->rb3d_blendcntl ); 339 OUT_RING(ctx->rb3d_blendcntl);
318 OUT_RING( ctx->rb3d_depthoffset ); 340 OUT_RING(ctx->rb3d_depthoffset);
319 OUT_RING( ctx->rb3d_depthpitch ); 341 OUT_RING(ctx->rb3d_depthpitch);
320 OUT_RING( ctx->rb3d_zstencilcntl ); 342 OUT_RING(ctx->rb3d_zstencilcntl);
321 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) ); 343 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
322 OUT_RING( ctx->pp_cntl ); 344 OUT_RING(ctx->pp_cntl);
323 OUT_RING( ctx->rb3d_cntl ); 345 OUT_RING(ctx->rb3d_cntl);
324 OUT_RING( ctx->rb3d_coloroffset ); 346 OUT_RING(ctx->rb3d_coloroffset);
325 OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) ); 347 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
326 OUT_RING( ctx->rb3d_colorpitch ); 348 OUT_RING(ctx->rb3d_colorpitch);
327 ADVANCE_RING(); 349 ADVANCE_RING();
328 } 350 }
329 351
330 if ( dirty & RADEON_UPLOAD_VERTFMT ) { 352 if (dirty & RADEON_UPLOAD_VERTFMT) {
331 BEGIN_RING( 2 ); 353 BEGIN_RING(2);
332 OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) ); 354 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
333 OUT_RING( ctx->se_coord_fmt ); 355 OUT_RING(ctx->se_coord_fmt);
334 ADVANCE_RING(); 356 ADVANCE_RING();
335 } 357 }
336 358
337 if ( dirty & RADEON_UPLOAD_LINE ) { 359 if (dirty & RADEON_UPLOAD_LINE) {
338 BEGIN_RING( 5 ); 360 BEGIN_RING(5);
339 OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) ); 361 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
340 OUT_RING( ctx->re_line_pattern ); 362 OUT_RING(ctx->re_line_pattern);
341 OUT_RING( ctx->re_line_state ); 363 OUT_RING(ctx->re_line_state);
342 OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) ); 364 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
343 OUT_RING( ctx->se_line_width ); 365 OUT_RING(ctx->se_line_width);
344 ADVANCE_RING(); 366 ADVANCE_RING();
345 } 367 }
346 368
347 if ( dirty & RADEON_UPLOAD_BUMPMAP ) { 369 if (dirty & RADEON_UPLOAD_BUMPMAP) {
348 BEGIN_RING( 5 ); 370 BEGIN_RING(5);
349 OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) ); 371 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
350 OUT_RING( ctx->pp_lum_matrix ); 372 OUT_RING(ctx->pp_lum_matrix);
351 OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) ); 373 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1));
352 OUT_RING( ctx->pp_rot_matrix_0 ); 374 OUT_RING(ctx->pp_rot_matrix_0);
353 OUT_RING( ctx->pp_rot_matrix_1 ); 375 OUT_RING(ctx->pp_rot_matrix_1);
354 ADVANCE_RING(); 376 ADVANCE_RING();
355 } 377 }
356 378
357 if ( dirty & RADEON_UPLOAD_MASKS ) { 379 if (dirty & RADEON_UPLOAD_MASKS) {
358 BEGIN_RING( 4 ); 380 BEGIN_RING(4);
359 OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) ); 381 OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2));
360 OUT_RING( ctx->rb3d_stencilrefmask ); 382 OUT_RING(ctx->rb3d_stencilrefmask);
361 OUT_RING( ctx->rb3d_ropcntl ); 383 OUT_RING(ctx->rb3d_ropcntl);
362 OUT_RING( ctx->rb3d_planemask ); 384 OUT_RING(ctx->rb3d_planemask);
363 ADVANCE_RING(); 385 ADVANCE_RING();
364 } 386 }
365 387
366 if ( dirty & RADEON_UPLOAD_VIEWPORT ) { 388 if (dirty & RADEON_UPLOAD_VIEWPORT) {
367 BEGIN_RING( 7 ); 389 BEGIN_RING(7);
368 OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) ); 390 OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5));
369 OUT_RING( ctx->se_vport_xscale ); 391 OUT_RING(ctx->se_vport_xscale);
370 OUT_RING( ctx->se_vport_xoffset ); 392 OUT_RING(ctx->se_vport_xoffset);
371 OUT_RING( ctx->se_vport_yscale ); 393 OUT_RING(ctx->se_vport_yscale);
372 OUT_RING( ctx->se_vport_yoffset ); 394 OUT_RING(ctx->se_vport_yoffset);
373 OUT_RING( ctx->se_vport_zscale ); 395 OUT_RING(ctx->se_vport_zscale);
374 OUT_RING( ctx->se_vport_zoffset ); 396 OUT_RING(ctx->se_vport_zoffset);
375 ADVANCE_RING(); 397 ADVANCE_RING();
376 } 398 }
377 399
378 if ( dirty & RADEON_UPLOAD_SETUP ) { 400 if (dirty & RADEON_UPLOAD_SETUP) {
379 BEGIN_RING( 4 ); 401 BEGIN_RING(4);
380 OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) ); 402 OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0));
381 OUT_RING( ctx->se_cntl ); 403 OUT_RING(ctx->se_cntl);
382 OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) ); 404 OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0));
383 OUT_RING( ctx->se_cntl_status ); 405 OUT_RING(ctx->se_cntl_status);
384 ADVANCE_RING(); 406 ADVANCE_RING();
385 } 407 }
386 408
387 if ( dirty & RADEON_UPLOAD_MISC ) { 409 if (dirty & RADEON_UPLOAD_MISC) {
388 BEGIN_RING( 2 ); 410 BEGIN_RING(2);
389 OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) ); 411 OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0));
390 OUT_RING( ctx->re_misc ); 412 OUT_RING(ctx->re_misc);
391 ADVANCE_RING(); 413 ADVANCE_RING();
392 } 414 }
393 415
394 if ( dirty & RADEON_UPLOAD_TEX0 ) { 416 if (dirty & RADEON_UPLOAD_TEX0) {
395 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 417 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
396 &tex[0].pp_txoffset ) ) { 418 &tex[0].pp_txoffset)) {
397 DRM_ERROR( "Invalid texture offset for unit 0\n" ); 419 DRM_ERROR("Invalid texture offset for unit 0\n");
398 return DRM_ERR( EINVAL ); 420 return DRM_ERR(EINVAL);
399 } 421 }
400 422
401 BEGIN_RING( 9 ); 423 BEGIN_RING(9);
402 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) ); 424 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5));
403 OUT_RING( tex[0].pp_txfilter ); 425 OUT_RING(tex[0].pp_txfilter);
404 OUT_RING( tex[0].pp_txformat ); 426 OUT_RING(tex[0].pp_txformat);
405 OUT_RING( tex[0].pp_txoffset ); 427 OUT_RING(tex[0].pp_txoffset);
406 OUT_RING( tex[0].pp_txcblend ); 428 OUT_RING(tex[0].pp_txcblend);
407 OUT_RING( tex[0].pp_txablend ); 429 OUT_RING(tex[0].pp_txablend);
408 OUT_RING( tex[0].pp_tfactor ); 430 OUT_RING(tex[0].pp_tfactor);
409 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) ); 431 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0));
410 OUT_RING( tex[0].pp_border_color ); 432 OUT_RING(tex[0].pp_border_color);
411 ADVANCE_RING(); 433 ADVANCE_RING();
412 } 434 }
413 435
414 if ( dirty & RADEON_UPLOAD_TEX1 ) { 436 if (dirty & RADEON_UPLOAD_TEX1) {
415 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 437 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
416 &tex[1].pp_txoffset ) ) { 438 &tex[1].pp_txoffset)) {
417 DRM_ERROR( "Invalid texture offset for unit 1\n" ); 439 DRM_ERROR("Invalid texture offset for unit 1\n");
418 return DRM_ERR( EINVAL ); 440 return DRM_ERR(EINVAL);
419 } 441 }
420 442
421 BEGIN_RING( 9 ); 443 BEGIN_RING(9);
422 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) ); 444 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5));
423 OUT_RING( tex[1].pp_txfilter ); 445 OUT_RING(tex[1].pp_txfilter);
424 OUT_RING( tex[1].pp_txformat ); 446 OUT_RING(tex[1].pp_txformat);
425 OUT_RING( tex[1].pp_txoffset ); 447 OUT_RING(tex[1].pp_txoffset);
426 OUT_RING( tex[1].pp_txcblend ); 448 OUT_RING(tex[1].pp_txcblend);
427 OUT_RING( tex[1].pp_txablend ); 449 OUT_RING(tex[1].pp_txablend);
428 OUT_RING( tex[1].pp_tfactor ); 450 OUT_RING(tex[1].pp_tfactor);
429 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) ); 451 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0));
430 OUT_RING( tex[1].pp_border_color ); 452 OUT_RING(tex[1].pp_border_color);
431 ADVANCE_RING(); 453 ADVANCE_RING();
432 } 454 }
433 455
434 if ( dirty & RADEON_UPLOAD_TEX2 ) { 456 if (dirty & RADEON_UPLOAD_TEX2) {
435 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 457 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
436 &tex[2].pp_txoffset ) ) { 458 &tex[2].pp_txoffset)) {
437 DRM_ERROR( "Invalid texture offset for unit 2\n" ); 459 DRM_ERROR("Invalid texture offset for unit 2\n");
438 return DRM_ERR( EINVAL ); 460 return DRM_ERR(EINVAL);
439 } 461 }
440 462
441 BEGIN_RING( 9 ); 463 BEGIN_RING(9);
442 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) ); 464 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5));
443 OUT_RING( tex[2].pp_txfilter ); 465 OUT_RING(tex[2].pp_txfilter);
444 OUT_RING( tex[2].pp_txformat ); 466 OUT_RING(tex[2].pp_txformat);
445 OUT_RING( tex[2].pp_txoffset ); 467 OUT_RING(tex[2].pp_txoffset);
446 OUT_RING( tex[2].pp_txcblend ); 468 OUT_RING(tex[2].pp_txcblend);
447 OUT_RING( tex[2].pp_txablend ); 469 OUT_RING(tex[2].pp_txablend);
448 OUT_RING( tex[2].pp_tfactor ); 470 OUT_RING(tex[2].pp_tfactor);
449 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) ); 471 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0));
450 OUT_RING( tex[2].pp_border_color ); 472 OUT_RING(tex[2].pp_border_color);
451 ADVANCE_RING(); 473 ADVANCE_RING();
452 } 474 }
453 475
@@ -456,129 +478,137 @@ static int radeon_emit_state( drm_radeon_private_t *dev_priv,
456 478
457/* Emit 1.2 state 479/* Emit 1.2 state
458 */ 480 */
459static int radeon_emit_state2( drm_radeon_private_t *dev_priv, 481static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
460 drm_file_t *filp_priv, 482 drm_file_t * filp_priv,
461 drm_radeon_state_t *state ) 483 drm_radeon_state_t * state)
462{ 484{
463 RING_LOCALS; 485 RING_LOCALS;
464 486
465 if (state->dirty & RADEON_UPLOAD_ZBIAS) { 487 if (state->dirty & RADEON_UPLOAD_ZBIAS) {
466 BEGIN_RING( 3 ); 488 BEGIN_RING(3);
467 OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) ); 489 OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1));
468 OUT_RING( state->context2.se_zbias_factor ); 490 OUT_RING(state->context2.se_zbias_factor);
469 OUT_RING( state->context2.se_zbias_constant ); 491 OUT_RING(state->context2.se_zbias_constant);
470 ADVANCE_RING(); 492 ADVANCE_RING();
471 } 493 }
472 494
473 return radeon_emit_state( dev_priv, filp_priv, &state->context, 495 return radeon_emit_state(dev_priv, filp_priv, &state->context,
474 state->tex, state->dirty ); 496 state->tex, state->dirty);
475} 497}
476 498
477/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in 499/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
478 * 1.3 cmdbuffers allow all previous state to be updated as well as 500 * 1.3 cmdbuffers allow all previous state to be updated as well as
479 * the tcl scalar and vector areas. 501 * the tcl scalar and vector areas.
480 */ 502 */
481static struct { 503static struct {
482 int start; 504 int start;
483 int len; 505 int len;
484 const char *name; 506 const char *name;
485} packet[RADEON_MAX_STATE_PACKETS] = { 507} packet[RADEON_MAX_STATE_PACKETS] = {
486 { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, 508 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
487 { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" }, 509 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
488 { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" }, 510 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
489 { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" }, 511 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
490 { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" }, 512 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
491 { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" }, 513 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
492 { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" }, 514 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
493 { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" }, 515 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
494 { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" }, 516 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
495 { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" }, 517 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
496 { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" }, 518 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
497 { RADEON_RE_MISC,1,"RADEON_RE_MISC" }, 519 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
498 { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" }, 520 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
499 { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" }, 521 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
500 { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" }, 522 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
501 { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" }, 523 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
502 { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" }, 524 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
503 { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" }, 525 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
504 { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" }, 526 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
505 { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" }, 527 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
506 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" }, 528 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
507 { R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" }, 529 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
508 { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" }, 530 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
509 { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" }, 531 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
510 { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" }, 532 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
511 { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" }, 533 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
512 { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" }, 534 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
513 { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" }, 535 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
514 { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" }, 536 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
515 { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, 537 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
516 { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" }, 538 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
517 { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" }, 539 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
518 { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" }, 540 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
519 { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" }, 541 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
520 { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" }, 542 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
521 { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, 543 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
522 { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" }, 544 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
523 { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" }, 545 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
524 { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" }, 546 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
525 { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" }, 547 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
526 { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" }, 548 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
527 { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" }, 549 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
528 { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" }, 550 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
529 { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" }, 551 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
530 { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" }, 552 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
531 { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" }, 553 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
532 { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" }, 554 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
533 { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" }, 555 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
534 { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" }, 556 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
535 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, 557 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
536 { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" }, 558 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
537 { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, 559 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
538 { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, 560 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
539 { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, 561 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
540 { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, 562 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
541 { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, 563 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
542 { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, 564 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
543 { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, 565 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
544 { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, 566 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
545 { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, 567 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
546 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, 568 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
547 { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */ 569 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
548 { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */ 570 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
549 { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" }, 571 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
550 { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" }, 572 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
551 { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" }, 573 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
552 { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" }, 574 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
553 { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" }, 575 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
554 { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" }, 576 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
555 { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" }, 577 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
556 { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" }, 578 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
557 { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" }, 579 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
558 { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, 580 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
559 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, 581 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
560 { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, 582 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
561 { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, 583 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
562 { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, 584 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
563 { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" }, 585 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
564 { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, 586 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
565 { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, 587 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
566 { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, 588 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
567 { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, 589 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
568 { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, 590 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
569 { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, 591 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
570 { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, 592 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
593 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
594 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
595 {R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */
596 {R200_PP_AFS_1, 32, "R200_PP_AFS_1"},
597 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
598 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
599 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
600 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
601 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
602 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
603 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
571}; 604};
572 605
573
574
575/* ================================================================ 606/* ================================================================
576 * Performance monitoring functions 607 * Performance monitoring functions
577 */ 608 */
578 609
579static void radeon_clear_box( drm_radeon_private_t *dev_priv, 610static void radeon_clear_box(drm_radeon_private_t * dev_priv,
580 int x, int y, int w, int h, 611 int x, int y, int w, int h, int r, int g, int b)
581 int r, int g, int b )
582{ 612{
583 u32 color; 613 u32 color;
584 RING_LOCALS; 614 RING_LOCALS;
@@ -586,49 +616,47 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv,
586 x += dev_priv->sarea_priv->boxes[0].x1; 616 x += dev_priv->sarea_priv->boxes[0].x1;
587 y += dev_priv->sarea_priv->boxes[0].y1; 617 y += dev_priv->sarea_priv->boxes[0].y1;
588 618
589 switch ( dev_priv->color_fmt ) { 619 switch (dev_priv->color_fmt) {
590 case RADEON_COLOR_FORMAT_RGB565: 620 case RADEON_COLOR_FORMAT_RGB565:
591 color = (((r & 0xf8) << 8) | 621 color = (((r & 0xf8) << 8) |
592 ((g & 0xfc) << 3) | 622 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
593 ((b & 0xf8) >> 3));
594 break; 623 break;
595 case RADEON_COLOR_FORMAT_ARGB8888: 624 case RADEON_COLOR_FORMAT_ARGB8888:
596 default: 625 default:
597 color = (((0xff) << 24) | (r << 16) | (g << 8) | b); 626 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
598 break; 627 break;
599 } 628 }
600 629
601 BEGIN_RING( 4 ); 630 BEGIN_RING(4);
602 RADEON_WAIT_UNTIL_3D_IDLE(); 631 RADEON_WAIT_UNTIL_3D_IDLE();
603 OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); 632 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
604 OUT_RING( 0xffffffff ); 633 OUT_RING(0xffffffff);
605 ADVANCE_RING(); 634 ADVANCE_RING();
606 635
607 BEGIN_RING( 6 ); 636 BEGIN_RING(6);
608 637
609 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); 638 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
610 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | 639 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
611 RADEON_GMC_BRUSH_SOLID_COLOR | 640 RADEON_GMC_BRUSH_SOLID_COLOR |
612 (dev_priv->color_fmt << 8) | 641 (dev_priv->color_fmt << 8) |
613 RADEON_GMC_SRC_DATATYPE_COLOR | 642 RADEON_GMC_SRC_DATATYPE_COLOR |
614 RADEON_ROP3_P | 643 RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
615 RADEON_GMC_CLR_CMP_CNTL_DIS );
616 644
617 if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { 645 if (dev_priv->page_flipping && dev_priv->current_page == 1) {
618 OUT_RING( dev_priv->front_pitch_offset ); 646 OUT_RING(dev_priv->front_pitch_offset);
619 } else { 647 } else {
620 OUT_RING( dev_priv->back_pitch_offset ); 648 OUT_RING(dev_priv->back_pitch_offset);
621 } 649 }
622 650
623 OUT_RING( color ); 651 OUT_RING(color);
624 652
625 OUT_RING( (x << 16) | y ); 653 OUT_RING((x << 16) | y);
626 OUT_RING( (w << 16) | h ); 654 OUT_RING((w << 16) | h);
627 655
628 ADVANCE_RING(); 656 ADVANCE_RING();
629} 657}
630 658
631static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv ) 659static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
632{ 660{
633 /* Collapse various things into a wait flag -- trying to 661 /* Collapse various things into a wait flag -- trying to
634 * guess if userspase slept -- better just to have them tell us. 662 * guess if userspase slept -- better just to have them tell us.
@@ -644,50 +672,50 @@ static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
644 672
645 /* Purple box for page flipping 673 /* Purple box for page flipping
646 */ 674 */
647 if ( dev_priv->stats.boxes & RADEON_BOX_FLIP ) 675 if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
648 radeon_clear_box( dev_priv, 4, 4, 8, 8, 255, 0, 255 ); 676 radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255);
649 677
650 /* Red box if we have to wait for idle at any point 678 /* Red box if we have to wait for idle at any point
651 */ 679 */
652 if ( dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE ) 680 if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
653 radeon_clear_box( dev_priv, 16, 4, 8, 8, 255, 0, 0 ); 681 radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0);
654 682
655 /* Blue box: lost context? 683 /* Blue box: lost context?
656 */ 684 */
657 685
658 /* Yellow box for texture swaps 686 /* Yellow box for texture swaps
659 */ 687 */
660 if ( dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD ) 688 if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
661 radeon_clear_box( dev_priv, 40, 4, 8, 8, 255, 255, 0 ); 689 radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0);
662 690
663 /* Green box if hardware never idles (as far as we can tell) 691 /* Green box if hardware never idles (as far as we can tell)
664 */ 692 */
665 if ( !(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE) ) 693 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
666 radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); 694 radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
667
668 695
669 /* Draw bars indicating number of buffers allocated 696 /* Draw bars indicating number of buffers allocated
670 * (not a great measure, easily confused) 697 * (not a great measure, easily confused)
671 */ 698 */
672 if (dev_priv->stats.requested_bufs) { 699 if (dev_priv->stats.requested_bufs) {
673 if (dev_priv->stats.requested_bufs > 100) 700 if (dev_priv->stats.requested_bufs > 100)
674 dev_priv->stats.requested_bufs = 100; 701 dev_priv->stats.requested_bufs = 100;
675 702
676 radeon_clear_box( dev_priv, 4, 16, 703 radeon_clear_box(dev_priv, 4, 16,
677 dev_priv->stats.requested_bufs, 4, 704 dev_priv->stats.requested_bufs, 4,
678 196, 128, 128 ); 705 196, 128, 128);
679 } 706 }
680 707
681 memset( &dev_priv->stats, 0, sizeof(dev_priv->stats) ); 708 memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));
682 709
683} 710}
711
684/* ================================================================ 712/* ================================================================
685 * CP command dispatch functions 713 * CP command dispatch functions
686 */ 714 */
687 715
688static void radeon_cp_dispatch_clear( drm_device_t *dev, 716static void radeon_cp_dispatch_clear(drm_device_t * dev,
689 drm_radeon_clear_t *clear, 717 drm_radeon_clear_t * clear,
690 drm_radeon_clear_rect_t *depth_boxes ) 718 drm_radeon_clear_rect_t * depth_boxes)
691{ 719{
692 drm_radeon_private_t *dev_priv = dev->dev_private; 720 drm_radeon_private_t *dev_priv = dev->dev_private;
693 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 721 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -695,32 +723,34 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
695 int nbox = sarea_priv->nbox; 723 int nbox = sarea_priv->nbox;
696 drm_clip_rect_t *pbox = sarea_priv->boxes; 724 drm_clip_rect_t *pbox = sarea_priv->boxes;
697 unsigned int flags = clear->flags; 725 unsigned int flags = clear->flags;
698 u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0; 726 u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0;
699 int i; 727 int i;
700 RING_LOCALS; 728 RING_LOCALS;
701 DRM_DEBUG( "flags = 0x%x\n", flags ); 729 DRM_DEBUG("flags = 0x%x\n", flags);
702 730
703 dev_priv->stats.clears++; 731 dev_priv->stats.clears++;
704 732
705 if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { 733 if (dev_priv->page_flipping && dev_priv->current_page == 1) {
706 unsigned int tmp = flags; 734 unsigned int tmp = flags;
707 735
708 flags &= ~(RADEON_FRONT | RADEON_BACK); 736 flags &= ~(RADEON_FRONT | RADEON_BACK);
709 if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK; 737 if (tmp & RADEON_FRONT)
710 if ( tmp & RADEON_BACK ) flags |= RADEON_FRONT; 738 flags |= RADEON_BACK;
739 if (tmp & RADEON_BACK)
740 flags |= RADEON_FRONT;
711 } 741 }
712 742
713 if ( flags & (RADEON_FRONT | RADEON_BACK) ) { 743 if (flags & (RADEON_FRONT | RADEON_BACK)) {
714 744
715 BEGIN_RING( 4 ); 745 BEGIN_RING(4);
716 746
717 /* Ensure the 3D stream is idle before doing a 747 /* Ensure the 3D stream is idle before doing a
718 * 2D fill to clear the front or back buffer. 748 * 2D fill to clear the front or back buffer.
719 */ 749 */
720 RADEON_WAIT_UNTIL_3D_IDLE(); 750 RADEON_WAIT_UNTIL_3D_IDLE();
721 751
722 OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); 752 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
723 OUT_RING( clear->color_mask ); 753 OUT_RING(clear->color_mask);
724 754
725 ADVANCE_RING(); 755 ADVANCE_RING();
726 756
@@ -728,121 +758,130 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
728 */ 758 */
729 dev_priv->sarea_priv->ctx_owner = 0; 759 dev_priv->sarea_priv->ctx_owner = 0;
730 760
731 for ( i = 0 ; i < nbox ; i++ ) { 761 for (i = 0; i < nbox; i++) {
732 int x = pbox[i].x1; 762 int x = pbox[i].x1;
733 int y = pbox[i].y1; 763 int y = pbox[i].y1;
734 int w = pbox[i].x2 - x; 764 int w = pbox[i].x2 - x;
735 int h = pbox[i].y2 - y; 765 int h = pbox[i].y2 - y;
736 766
737 DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", 767 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
738 x, y, w, h, flags ); 768 x, y, w, h, flags);
739 769
740 if ( flags & RADEON_FRONT ) { 770 if (flags & RADEON_FRONT) {
741 BEGIN_RING( 6 ); 771 BEGIN_RING(6);
742 772
743 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); 773 OUT_RING(CP_PACKET3
744 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | 774 (RADEON_CNTL_PAINT_MULTI, 4));
745 RADEON_GMC_BRUSH_SOLID_COLOR | 775 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
746 (dev_priv->color_fmt << 8) | 776 RADEON_GMC_BRUSH_SOLID_COLOR |
747 RADEON_GMC_SRC_DATATYPE_COLOR | 777 (dev_priv->
748 RADEON_ROP3_P | 778 color_fmt << 8) |
749 RADEON_GMC_CLR_CMP_CNTL_DIS ); 779 RADEON_GMC_SRC_DATATYPE_COLOR |
750 780 RADEON_ROP3_P |
751 OUT_RING( dev_priv->front_pitch_offset ); 781 RADEON_GMC_CLR_CMP_CNTL_DIS);
752 OUT_RING( clear->clear_color ); 782
753 783 OUT_RING(dev_priv->front_pitch_offset);
754 OUT_RING( (x << 16) | y ); 784 OUT_RING(clear->clear_color);
755 OUT_RING( (w << 16) | h ); 785
756 786 OUT_RING((x << 16) | y);
787 OUT_RING((w << 16) | h);
788
757 ADVANCE_RING(); 789 ADVANCE_RING();
758 } 790 }
759 791
760 if ( flags & RADEON_BACK ) { 792 if (flags & RADEON_BACK) {
761 BEGIN_RING( 6 ); 793 BEGIN_RING(6);
762 794
763 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); 795 OUT_RING(CP_PACKET3
764 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | 796 (RADEON_CNTL_PAINT_MULTI, 4));
765 RADEON_GMC_BRUSH_SOLID_COLOR | 797 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
766 (dev_priv->color_fmt << 8) | 798 RADEON_GMC_BRUSH_SOLID_COLOR |
767 RADEON_GMC_SRC_DATATYPE_COLOR | 799 (dev_priv->
768 RADEON_ROP3_P | 800 color_fmt << 8) |
769 RADEON_GMC_CLR_CMP_CNTL_DIS ); 801 RADEON_GMC_SRC_DATATYPE_COLOR |
770 802 RADEON_ROP3_P |
771 OUT_RING( dev_priv->back_pitch_offset ); 803 RADEON_GMC_CLR_CMP_CNTL_DIS);
772 OUT_RING( clear->clear_color ); 804
773 805 OUT_RING(dev_priv->back_pitch_offset);
774 OUT_RING( (x << 16) | y ); 806 OUT_RING(clear->clear_color);
775 OUT_RING( (w << 16) | h ); 807
808 OUT_RING((x << 16) | y);
809 OUT_RING((w << 16) | h);
776 810
777 ADVANCE_RING(); 811 ADVANCE_RING();
778 } 812 }
779 } 813 }
780 } 814 }
781 815
782 /* hyper z clear */ 816 /* hyper z clear */
783 /* no docs available, based on reverse engeneering by Stephane Marchesin */ 817 /* no docs available, based on reverse engeneering by Stephane Marchesin */
784 if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) && (flags & RADEON_CLEAR_FASTZ)) { 818 if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
819 && (flags & RADEON_CLEAR_FASTZ)) {
785 820
786 int i; 821 int i;
787 int depthpixperline = dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z? 822 int depthpixperline =
788 (dev_priv->depth_pitch / 2): (dev_priv->depth_pitch / 4); 823 dev_priv->depth_fmt ==
789 824 RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
825 2) : (dev_priv->
826 depth_pitch / 4);
827
790 u32 clearmask; 828 u32 clearmask;
791 829
792 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth | 830 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
793 ((clear->depth_mask & 0xff) << 24); 831 ((clear->depth_mask & 0xff) << 24);
794 832
795
796 /* Make sure we restore the 3D state next time. 833 /* Make sure we restore the 3D state next time.
797 * we haven't touched any "normal" state - still need this? 834 * we haven't touched any "normal" state - still need this?
798 */ 835 */
799 dev_priv->sarea_priv->ctx_owner = 0; 836 dev_priv->sarea_priv->ctx_owner = 0;
800 837
801 if ((dev_priv->flags & CHIP_HAS_HIERZ) && (flags & RADEON_USE_HIERZ)) { 838 if ((dev_priv->flags & CHIP_HAS_HIERZ)
802 /* FIXME : reverse engineer that for Rx00 cards */ 839 && (flags & RADEON_USE_HIERZ)) {
803 /* FIXME : the mask supposedly contains low-res z values. So can't set 840 /* FIXME : reverse engineer that for Rx00 cards */
804 just to the max (0xff? or actually 0x3fff?), need to take z clear 841 /* FIXME : the mask supposedly contains low-res z values. So can't set
805 value into account? */ 842 just to the max (0xff? or actually 0x3fff?), need to take z clear
806 /* pattern seems to work for r100, though get slight 843 value into account? */
807 rendering errors with glxgears. If hierz is not enabled for r100, 844 /* pattern seems to work for r100, though get slight
808 only 4 bits which indicate clear (15,16,31,32, all zero) matter, the 845 rendering errors with glxgears. If hierz is not enabled for r100,
809 other ones are ignored, and the same clear mask can be used. That's 846 only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
810 very different behaviour than R200 which needs different clear mask 847 other ones are ignored, and the same clear mask can be used. That's
811 and different number of tiles to clear if hierz is enabled or not !?! 848 very different behaviour than R200 which needs different clear mask
812 */ 849 and different number of tiles to clear if hierz is enabled or not !?!
813 clearmask = (0xff<<22)|(0xff<<6)| 0x003f003f; 850 */
814 } 851 clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f;
815 else { 852 } else {
816 /* clear mask : chooses the clearing pattern. 853 /* clear mask : chooses the clearing pattern.
817 rv250: could be used to clear only parts of macrotiles 854 rv250: could be used to clear only parts of macrotiles
818 (but that would get really complicated...)? 855 (but that would get really complicated...)?
819 bit 0 and 1 (either or both of them ?!?!) are used to 856 bit 0 and 1 (either or both of them ?!?!) are used to
820 not clear tile (or maybe one of the bits indicates if the tile is 857 not clear tile (or maybe one of the bits indicates if the tile is
821 compressed or not), bit 2 and 3 to not clear tile 1,...,. 858 compressed or not), bit 2 and 3 to not clear tile 1,...,.
822 Pattern is as follows: 859 Pattern is as follows:
823 | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29| 860 | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
824 bits ------------------------------------------------- 861 bits -------------------------------------------------
825 | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31| 862 | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
826 rv100: clearmask covers 2x8 4x1 tiles, but one clear still 863 rv100: clearmask covers 2x8 4x1 tiles, but one clear still
827 covers 256 pixels ?!? 864 covers 256 pixels ?!?
828 */ 865 */
829 clearmask = 0x0; 866 clearmask = 0x0;
830 } 867 }
831 868
832 BEGIN_RING( 8 ); 869 BEGIN_RING(8);
833 RADEON_WAIT_UNTIL_2D_IDLE(); 870 RADEON_WAIT_UNTIL_2D_IDLE();
834 OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE, 871 OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE,
835 tempRB3D_DEPTHCLEARVALUE); 872 tempRB3D_DEPTHCLEARVALUE);
836 /* what offset is this exactly ? */ 873 /* what offset is this exactly ? */
837 OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET, 0 ); 874 OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0);
838 /* need ctlstat, otherwise get some strange black flickering */ 875 /* need ctlstat, otherwise get some strange black flickering */
839 OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT, RADEON_RB3D_ZC_FLUSH_ALL ); 876 OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT,
877 RADEON_RB3D_ZC_FLUSH_ALL);
840 ADVANCE_RING(); 878 ADVANCE_RING();
841 879
842 for (i = 0; i < nbox; i++) { 880 for (i = 0; i < nbox; i++) {
843 int tileoffset, nrtilesx, nrtilesy, j; 881 int tileoffset, nrtilesx, nrtilesy, j;
844 /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */ 882 /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
845 if ((dev_priv->flags&CHIP_HAS_HIERZ) && !(dev_priv->microcode_version==UCODE_R200)) { 883 if ((dev_priv->flags & CHIP_HAS_HIERZ)
884 && !(dev_priv->microcode_version == UCODE_R200)) {
846 /* FIXME : figure this out for r200 (when hierz is enabled). Or 885 /* FIXME : figure this out for r200 (when hierz is enabled). Or
847 maybe r200 actually doesn't need to put the low-res z value into 886 maybe r200 actually doesn't need to put the low-res z value into
848 the tile cache like r100, but just needs to clear the hi-level z-buffer? 887 the tile cache like r100, but just needs to clear the hi-level z-buffer?
@@ -850,59 +889,74 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
850 R100 seems to operate on 2x1 8x8 tiles, but... 889 R100 seems to operate on 2x1 8x8 tiles, but...
851 odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially 890 odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially
852 problematic with resolutions which are not 64 pix aligned? */ 891 problematic with resolutions which are not 64 pix aligned? */
853 tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 6; 892 tileoffset =
854 nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; 893 ((pbox[i].y1 >> 3) * depthpixperline +
855 nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); 894 pbox[i].x1) >> 6;
895 nrtilesx =
896 ((pbox[i].x2 & ~63) -
897 (pbox[i].x1 & ~63)) >> 4;
898 nrtilesy =
899 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
856 for (j = 0; j <= nrtilesy; j++) { 900 for (j = 0; j <= nrtilesy; j++) {
857 BEGIN_RING( 4 ); 901 BEGIN_RING(4);
858 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); 902 OUT_RING(CP_PACKET3
903 (RADEON_3D_CLEAR_ZMASK, 2));
859 /* first tile */ 904 /* first tile */
860 OUT_RING( tileoffset * 8 ); 905 OUT_RING(tileoffset * 8);
861 /* the number of tiles to clear */ 906 /* the number of tiles to clear */
862 OUT_RING( nrtilesx + 4 ); 907 OUT_RING(nrtilesx + 4);
863 /* clear mask : chooses the clearing pattern. */ 908 /* clear mask : chooses the clearing pattern. */
864 OUT_RING( clearmask ); 909 OUT_RING(clearmask);
865 ADVANCE_RING(); 910 ADVANCE_RING();
866 tileoffset += depthpixperline >> 6; 911 tileoffset += depthpixperline >> 6;
867 } 912 }
868 } 913 } else if (dev_priv->microcode_version == UCODE_R200) {
869 else if (dev_priv->microcode_version==UCODE_R200) {
870 /* works for rv250. */ 914 /* works for rv250. */
871 /* find first macro tile (8x2 4x4 z-pixels on rv250) */ 915 /* find first macro tile (8x2 4x4 z-pixels on rv250) */
872 tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 5; 916 tileoffset =
873 nrtilesx = (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5); 917 ((pbox[i].y1 >> 3) * depthpixperline +
874 nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); 918 pbox[i].x1) >> 5;
919 nrtilesx =
920 (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5);
921 nrtilesy =
922 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
875 for (j = 0; j <= nrtilesy; j++) { 923 for (j = 0; j <= nrtilesy; j++) {
876 BEGIN_RING( 4 ); 924 BEGIN_RING(4);
877 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); 925 OUT_RING(CP_PACKET3
926 (RADEON_3D_CLEAR_ZMASK, 2));
878 /* first tile */ 927 /* first tile */
879 /* judging by the first tile offset needed, could possibly 928 /* judging by the first tile offset needed, could possibly
880 directly address/clear 4x4 tiles instead of 8x2 * 4x4 929 directly address/clear 4x4 tiles instead of 8x2 * 4x4
881 macro tiles, though would still need clear mask for 930 macro tiles, though would still need clear mask for
882 right/bottom if truely 4x4 granularity is desired ? */ 931 right/bottom if truely 4x4 granularity is desired ? */
883 OUT_RING( tileoffset * 16 ); 932 OUT_RING(tileoffset * 16);
884 /* the number of tiles to clear */ 933 /* the number of tiles to clear */
885 OUT_RING( nrtilesx + 1 ); 934 OUT_RING(nrtilesx + 1);
886 /* clear mask : chooses the clearing pattern. */ 935 /* clear mask : chooses the clearing pattern. */
887 OUT_RING( clearmask ); 936 OUT_RING(clearmask);
888 ADVANCE_RING(); 937 ADVANCE_RING();
889 tileoffset += depthpixperline >> 5; 938 tileoffset += depthpixperline >> 5;
890 } 939 }
891 } 940 } else { /* rv 100 */
892 else { /* rv 100 */
893 /* rv100 might not need 64 pix alignment, who knows */ 941 /* rv100 might not need 64 pix alignment, who knows */
894 /* offsets are, hmm, weird */ 942 /* offsets are, hmm, weird */
895 tileoffset = ((pbox[i].y1 >> 4) * depthpixperline + pbox[i].x1) >> 6; 943 tileoffset =
896 nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; 944 ((pbox[i].y1 >> 4) * depthpixperline +
897 nrtilesy = (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4); 945 pbox[i].x1) >> 6;
946 nrtilesx =
947 ((pbox[i].x2 & ~63) -
948 (pbox[i].x1 & ~63)) >> 4;
949 nrtilesy =
950 (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4);
898 for (j = 0; j <= nrtilesy; j++) { 951 for (j = 0; j <= nrtilesy; j++) {
899 BEGIN_RING( 4 ); 952 BEGIN_RING(4);
900 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); 953 OUT_RING(CP_PACKET3
901 OUT_RING( tileoffset * 128 ); 954 (RADEON_3D_CLEAR_ZMASK, 2));
955 OUT_RING(tileoffset * 128);
902 /* the number of tiles to clear */ 956 /* the number of tiles to clear */
903 OUT_RING( nrtilesx + 4 ); 957 OUT_RING(nrtilesx + 4);
904 /* clear mask : chooses the clearing pattern. */ 958 /* clear mask : chooses the clearing pattern. */
905 OUT_RING( clearmask ); 959 OUT_RING(clearmask);
906 ADVANCE_RING(); 960 ADVANCE_RING();
907 tileoffset += depthpixperline >> 6; 961 tileoffset += depthpixperline >> 6;
908 } 962 }
@@ -910,18 +964,19 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
910 } 964 }
911 965
912 /* TODO don't always clear all hi-level z tiles */ 966 /* TODO don't always clear all hi-level z tiles */
913 if ((dev_priv->flags & CHIP_HAS_HIERZ) && (dev_priv->microcode_version==UCODE_R200) 967 if ((dev_priv->flags & CHIP_HAS_HIERZ)
914 && (flags & RADEON_USE_HIERZ)) 968 && (dev_priv->microcode_version == UCODE_R200)
915 /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */ 969 && (flags & RADEON_USE_HIERZ))
916 /* FIXME : the mask supposedly contains low-res z values. So can't set 970 /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
917 just to the max (0xff? or actually 0x3fff?), need to take z clear 971 /* FIXME : the mask supposedly contains low-res z values. So can't set
918 value into account? */ 972 just to the max (0xff? or actually 0x3fff?), need to take z clear
973 value into account? */
919 { 974 {
920 BEGIN_RING( 4 ); 975 BEGIN_RING(4);
921 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) ); 976 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2));
922 OUT_RING( 0x0 ); /* First tile */ 977 OUT_RING(0x0); /* First tile */
923 OUT_RING( 0x3cc0 ); 978 OUT_RING(0x3cc0);
924 OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f); 979 OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f);
925 ADVANCE_RING(); 980 ADVANCE_RING();
926 } 981 }
927 } 982 }
@@ -956,30 +1011,27 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
956 1011
957 tempSE_CNTL = depth_clear->se_cntl; 1012 tempSE_CNTL = depth_clear->se_cntl;
958 1013
959
960
961 /* Disable TCL */ 1014 /* Disable TCL */
962 1015
963 tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */ 1016 tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */
964 (0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT)); 1017 (0x9 <<
1018 SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
965 1019
966 tempRB3D_PLANEMASK = 0x0; 1020 tempRB3D_PLANEMASK = 0x0;
967 1021
968 tempRE_AUX_SCISSOR_CNTL = 0x0; 1022 tempRE_AUX_SCISSOR_CNTL = 0x0;
969 1023
970 tempSE_VTE_CNTL = 1024 tempSE_VTE_CNTL =
971 SE_VTE_CNTL__VTX_XY_FMT_MASK | 1025 SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK;
972 SE_VTE_CNTL__VTX_Z_FMT_MASK;
973 1026
974 /* Vertex format (X, Y, Z, W)*/ 1027 /* Vertex format (X, Y, Z, W) */
975 tempSE_VTX_FMT_0 = 1028 tempSE_VTX_FMT_0 =
976 SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK | 1029 SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
977 SE_VTX_FMT_0__VTX_W0_PRESENT_MASK; 1030 SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
978 tempSE_VTX_FMT_1 = 0x0; 1031 tempSE_VTX_FMT_1 = 0x0;
979 1032
980 1033 /*
981 /* 1034 * Depth buffer specific enables
982 * Depth buffer specific enables
983 */ 1035 */
984 if (flags & RADEON_DEPTH) { 1036 if (flags & RADEON_DEPTH) {
985 /* Enable depth buffer */ 1037 /* Enable depth buffer */
@@ -989,12 +1041,12 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
989 tempRB3D_CNTL &= ~RADEON_Z_ENABLE; 1041 tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
990 } 1042 }
991 1043
992 /* 1044 /*
993 * Stencil buffer specific enables 1045 * Stencil buffer specific enables
994 */ 1046 */
995 if ( flags & RADEON_STENCIL ) { 1047 if (flags & RADEON_STENCIL) {
996 tempRB3D_CNTL |= RADEON_STENCIL_ENABLE; 1048 tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
997 tempRB3D_STENCILREFMASK = clear->depth_mask; 1049 tempRB3D_STENCILREFMASK = clear->depth_mask;
998 } else { 1050 } else {
999 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE; 1051 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
1000 tempRB3D_STENCILREFMASK = 0x00000000; 1052 tempRB3D_STENCILREFMASK = 0x00000000;
@@ -1002,79 +1054,75 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
1002 1054
1003 if (flags & RADEON_USE_COMP_ZBUF) { 1055 if (flags & RADEON_USE_COMP_ZBUF) {
1004 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | 1056 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1005 RADEON_Z_DECOMPRESSION_ENABLE; 1057 RADEON_Z_DECOMPRESSION_ENABLE;
1006 } 1058 }
1007 if (flags & RADEON_USE_HIERZ) { 1059 if (flags & RADEON_USE_HIERZ) {
1008 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; 1060 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1009 } 1061 }
1010 1062
1011 BEGIN_RING( 26 ); 1063 BEGIN_RING(26);
1012 RADEON_WAIT_UNTIL_2D_IDLE(); 1064 RADEON_WAIT_UNTIL_2D_IDLE();
1013 1065
1014 OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL ); 1066 OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL);
1015 OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL ); 1067 OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL);
1016 OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL ); 1068 OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL);
1017 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, 1069 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1018 tempRB3D_ZSTENCILCNTL ); 1070 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK,
1019 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, 1071 tempRB3D_STENCILREFMASK);
1020 tempRB3D_STENCILREFMASK ); 1072 OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK);
1021 OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK ); 1073 OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL);
1022 OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL ); 1074 OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL);
1023 OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL ); 1075 OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0);
1024 OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 ); 1076 OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1);
1025 OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 ); 1077 OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL);
1026 OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL ); 1078 OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL);
1027 OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL,
1028 tempRE_AUX_SCISSOR_CNTL );
1029 ADVANCE_RING(); 1079 ADVANCE_RING();
1030 1080
1031 /* Make sure we restore the 3D state next time. 1081 /* Make sure we restore the 3D state next time.
1032 */ 1082 */
1033 dev_priv->sarea_priv->ctx_owner = 0; 1083 dev_priv->sarea_priv->ctx_owner = 0;
1034 1084
1035 for ( i = 0 ; i < nbox ; i++ ) { 1085 for (i = 0; i < nbox; i++) {
1036 1086
1037 /* Funny that this should be required -- 1087 /* Funny that this should be required --
1038 * sets top-left? 1088 * sets top-left?
1039 */ 1089 */
1040 radeon_emit_clip_rect( dev_priv, 1090 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1041 &sarea_priv->boxes[i] ); 1091
1042 1092 BEGIN_RING(14);
1043 BEGIN_RING( 14 ); 1093 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12));
1044 OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) ); 1094 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1045 OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | 1095 RADEON_PRIM_WALK_RING |
1046 RADEON_PRIM_WALK_RING | 1096 (3 << RADEON_NUM_VERTICES_SHIFT)));
1047 (3 << RADEON_NUM_VERTICES_SHIFT)) ); 1097 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1048 OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); 1098 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1049 OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); 1099 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1050 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1100 OUT_RING(0x3f800000);
1051 OUT_RING( 0x3f800000 ); 1101 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1052 OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); 1102 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1053 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); 1103 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1054 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1104 OUT_RING(0x3f800000);
1055 OUT_RING( 0x3f800000 ); 1105 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1056 OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); 1106 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1057 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); 1107 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1058 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1108 OUT_RING(0x3f800000);
1059 OUT_RING( 0x3f800000 );
1060 ADVANCE_RING(); 1109 ADVANCE_RING();
1061 } 1110 }
1062 } 1111 } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {
1063 else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
1064 1112
1065 int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; 1113 int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1066 1114
1067 rb3d_cntl = depth_clear->rb3d_cntl; 1115 rb3d_cntl = depth_clear->rb3d_cntl;
1068 1116
1069 if ( flags & RADEON_DEPTH ) { 1117 if (flags & RADEON_DEPTH) {
1070 rb3d_cntl |= RADEON_Z_ENABLE; 1118 rb3d_cntl |= RADEON_Z_ENABLE;
1071 } else { 1119 } else {
1072 rb3d_cntl &= ~RADEON_Z_ENABLE; 1120 rb3d_cntl &= ~RADEON_Z_ENABLE;
1073 } 1121 }
1074 1122
1075 if ( flags & RADEON_STENCIL ) { 1123 if (flags & RADEON_STENCIL) {
1076 rb3d_cntl |= RADEON_STENCIL_ENABLE; 1124 rb3d_cntl |= RADEON_STENCIL_ENABLE;
1077 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */ 1125 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
1078 } else { 1126 } else {
1079 rb3d_cntl &= ~RADEON_STENCIL_ENABLE; 1127 rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
1080 rb3d_stencilrefmask = 0x00000000; 1128 rb3d_stencilrefmask = 0x00000000;
@@ -1082,66 +1130,61 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
1082 1130
1083 if (flags & RADEON_USE_COMP_ZBUF) { 1131 if (flags & RADEON_USE_COMP_ZBUF) {
1084 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | 1132 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1085 RADEON_Z_DECOMPRESSION_ENABLE; 1133 RADEON_Z_DECOMPRESSION_ENABLE;
1086 } 1134 }
1087 if (flags & RADEON_USE_HIERZ) { 1135 if (flags & RADEON_USE_HIERZ) {
1088 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; 1136 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1089 } 1137 }
1090 1138
1091 BEGIN_RING( 13 ); 1139 BEGIN_RING(13);
1092 RADEON_WAIT_UNTIL_2D_IDLE(); 1140 RADEON_WAIT_UNTIL_2D_IDLE();
1093 1141
1094 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) ); 1142 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1));
1095 OUT_RING( 0x00000000 ); 1143 OUT_RING(0x00000000);
1096 OUT_RING( rb3d_cntl ); 1144 OUT_RING(rb3d_cntl);
1097 1145
1098 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL ); 1146 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1099 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, 1147 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask);
1100 rb3d_stencilrefmask ); 1148 OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000);
1101 OUT_RING_REG( RADEON_RB3D_PLANEMASK, 1149 OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl);
1102 0x00000000 );
1103 OUT_RING_REG( RADEON_SE_CNTL,
1104 depth_clear->se_cntl );
1105 ADVANCE_RING(); 1150 ADVANCE_RING();
1106 1151
1107 /* Make sure we restore the 3D state next time. 1152 /* Make sure we restore the 3D state next time.
1108 */ 1153 */
1109 dev_priv->sarea_priv->ctx_owner = 0; 1154 dev_priv->sarea_priv->ctx_owner = 0;
1110 1155
1111 for ( i = 0 ; i < nbox ; i++ ) { 1156 for (i = 0; i < nbox; i++) {
1112 1157
1113 /* Funny that this should be required -- 1158 /* Funny that this should be required --
1114 * sets top-left? 1159 * sets top-left?
1115 */ 1160 */
1116 radeon_emit_clip_rect( dev_priv, 1161 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1117 &sarea_priv->boxes[i] ); 1162
1118 1163 BEGIN_RING(15);
1119 BEGIN_RING( 15 ); 1164
1120 1165 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13));
1121 OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) ); 1166 OUT_RING(RADEON_VTX_Z_PRESENT |
1122 OUT_RING( RADEON_VTX_Z_PRESENT | 1167 RADEON_VTX_PKCOLOR_PRESENT);
1123 RADEON_VTX_PKCOLOR_PRESENT); 1168 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1124 OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | 1169 RADEON_PRIM_WALK_RING |
1125 RADEON_PRIM_WALK_RING | 1170 RADEON_MAOS_ENABLE |
1126 RADEON_MAOS_ENABLE | 1171 RADEON_VTX_FMT_RADEON_MODE |
1127 RADEON_VTX_FMT_RADEON_MODE | 1172 (3 << RADEON_NUM_VERTICES_SHIFT)));
1128 (3 << RADEON_NUM_VERTICES_SHIFT)) ); 1173
1129 1174 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1130 1175 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1131 OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); 1176 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1132 OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); 1177 OUT_RING(0x0);
1133 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1178
1134 OUT_RING( 0x0 ); 1179 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1135 1180 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1136 OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); 1181 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1137 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); 1182 OUT_RING(0x0);
1138 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1183
1139 OUT_RING( 0x0 ); 1184 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1140 1185 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1141 OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); 1186 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1142 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); 1187 OUT_RING(0x0);
1143 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
1144 OUT_RING( 0x0 );
1145 1188
1146 ADVANCE_RING(); 1189 ADVANCE_RING();
1147 } 1190 }
@@ -1153,15 +1196,15 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
1153 */ 1196 */
1154 dev_priv->sarea_priv->last_clear++; 1197 dev_priv->sarea_priv->last_clear++;
1155 1198
1156 BEGIN_RING( 4 ); 1199 BEGIN_RING(4);
1157 1200
1158 RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear ); 1201 RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
1159 RADEON_WAIT_UNTIL_IDLE(); 1202 RADEON_WAIT_UNTIL_IDLE();
1160 1203
1161 ADVANCE_RING(); 1204 ADVANCE_RING();
1162} 1205}
1163 1206
1164static void radeon_cp_dispatch_swap( drm_device_t *dev ) 1207static void radeon_cp_dispatch_swap(drm_device_t * dev)
1165{ 1208{
1166 drm_radeon_private_t *dev_priv = dev->dev_private; 1209 drm_radeon_private_t *dev_priv = dev->dev_private;
1167 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 1210 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1169,59 +1212,55 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
1169 drm_clip_rect_t *pbox = sarea_priv->boxes; 1212 drm_clip_rect_t *pbox = sarea_priv->boxes;
1170 int i; 1213 int i;
1171 RING_LOCALS; 1214 RING_LOCALS;
1172 DRM_DEBUG( "\n" ); 1215 DRM_DEBUG("\n");
1173 1216
1174 /* Do some trivial performance monitoring... 1217 /* Do some trivial performance monitoring...
1175 */ 1218 */
1176 if (dev_priv->do_boxes) 1219 if (dev_priv->do_boxes)
1177 radeon_cp_performance_boxes( dev_priv ); 1220 radeon_cp_performance_boxes(dev_priv);
1178
1179 1221
1180 /* Wait for the 3D stream to idle before dispatching the bitblt. 1222 /* Wait for the 3D stream to idle before dispatching the bitblt.
1181 * This will prevent data corruption between the two streams. 1223 * This will prevent data corruption between the two streams.
1182 */ 1224 */
1183 BEGIN_RING( 2 ); 1225 BEGIN_RING(2);
1184 1226
1185 RADEON_WAIT_UNTIL_3D_IDLE(); 1227 RADEON_WAIT_UNTIL_3D_IDLE();
1186 1228
1187 ADVANCE_RING(); 1229 ADVANCE_RING();
1188 1230
1189 for ( i = 0 ; i < nbox ; i++ ) { 1231 for (i = 0; i < nbox; i++) {
1190 int x = pbox[i].x1; 1232 int x = pbox[i].x1;
1191 int y = pbox[i].y1; 1233 int y = pbox[i].y1;
1192 int w = pbox[i].x2 - x; 1234 int w = pbox[i].x2 - x;
1193 int h = pbox[i].y2 - y; 1235 int h = pbox[i].y2 - y;
1194 1236
1195 DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n", 1237 DRM_DEBUG("dispatch swap %d,%d-%d,%d\n", x, y, w, h);
1196 x, y, w, h ); 1238
1197 1239 BEGIN_RING(7);
1198 BEGIN_RING( 7 ); 1240
1199 1241 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
1200 OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) ); 1242 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1201 OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 1243 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1202 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 1244 RADEON_GMC_BRUSH_NONE |
1203 RADEON_GMC_BRUSH_NONE | 1245 (dev_priv->color_fmt << 8) |
1204 (dev_priv->color_fmt << 8) | 1246 RADEON_GMC_SRC_DATATYPE_COLOR |
1205 RADEON_GMC_SRC_DATATYPE_COLOR | 1247 RADEON_ROP3_S |
1206 RADEON_ROP3_S | 1248 RADEON_DP_SRC_SOURCE_MEMORY |
1207 RADEON_DP_SRC_SOURCE_MEMORY | 1249 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1208 RADEON_GMC_CLR_CMP_CNTL_DIS | 1250
1209 RADEON_GMC_WR_MSK_DIS );
1210
1211 /* Make this work even if front & back are flipped: 1251 /* Make this work even if front & back are flipped:
1212 */ 1252 */
1213 if (dev_priv->current_page == 0) { 1253 if (dev_priv->current_page == 0) {
1214 OUT_RING( dev_priv->back_pitch_offset ); 1254 OUT_RING(dev_priv->back_pitch_offset);
1215 OUT_RING( dev_priv->front_pitch_offset ); 1255 OUT_RING(dev_priv->front_pitch_offset);
1216 } 1256 } else {
1217 else { 1257 OUT_RING(dev_priv->front_pitch_offset);
1218 OUT_RING( dev_priv->front_pitch_offset ); 1258 OUT_RING(dev_priv->back_pitch_offset);
1219 OUT_RING( dev_priv->back_pitch_offset );
1220 } 1259 }
1221 1260
1222 OUT_RING( (x << 16) | y ); 1261 OUT_RING((x << 16) | y);
1223 OUT_RING( (x << 16) | y ); 1262 OUT_RING((x << 16) | y);
1224 OUT_RING( (w << 16) | h ); 1263 OUT_RING((w << 16) | h);
1225 1264
1226 ADVANCE_RING(); 1265 ADVANCE_RING();
1227 } 1266 }
@@ -1232,44 +1271,43 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
1232 */ 1271 */
1233 dev_priv->sarea_priv->last_frame++; 1272 dev_priv->sarea_priv->last_frame++;
1234 1273
1235 BEGIN_RING( 4 ); 1274 BEGIN_RING(4);
1236 1275
1237 RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); 1276 RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1238 RADEON_WAIT_UNTIL_2D_IDLE(); 1277 RADEON_WAIT_UNTIL_2D_IDLE();
1239 1278
1240 ADVANCE_RING(); 1279 ADVANCE_RING();
1241} 1280}
1242 1281
1243static void radeon_cp_dispatch_flip( drm_device_t *dev ) 1282static void radeon_cp_dispatch_flip(drm_device_t * dev)
1244{ 1283{
1245 drm_radeon_private_t *dev_priv = dev->dev_private; 1284 drm_radeon_private_t *dev_priv = dev->dev_private;
1246 drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle; 1285 drm_sarea_t *sarea = (drm_sarea_t *) dev_priv->sarea->handle;
1247 int offset = (dev_priv->current_page == 1) 1286 int offset = (dev_priv->current_page == 1)
1248 ? dev_priv->front_offset : dev_priv->back_offset; 1287 ? dev_priv->front_offset : dev_priv->back_offset;
1249 RING_LOCALS; 1288 RING_LOCALS;
1250 DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", 1289 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
1251 __FUNCTION__, 1290 __FUNCTION__,
1252 dev_priv->current_page, 1291 dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
1253 dev_priv->sarea_priv->pfCurrentPage);
1254 1292
1255 /* Do some trivial performance monitoring... 1293 /* Do some trivial performance monitoring...
1256 */ 1294 */
1257 if (dev_priv->do_boxes) { 1295 if (dev_priv->do_boxes) {
1258 dev_priv->stats.boxes |= RADEON_BOX_FLIP; 1296 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
1259 radeon_cp_performance_boxes( dev_priv ); 1297 radeon_cp_performance_boxes(dev_priv);
1260 } 1298 }
1261 1299
1262 /* Update the frame offsets for both CRTCs 1300 /* Update the frame offsets for both CRTCs
1263 */ 1301 */
1264 BEGIN_RING( 6 ); 1302 BEGIN_RING(6);
1265 1303
1266 RADEON_WAIT_UNTIL_3D_IDLE(); 1304 RADEON_WAIT_UNTIL_3D_IDLE();
1267 OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch 1305 OUT_RING_REG(RADEON_CRTC_OFFSET,
1268 + sarea->frame.x 1306 ((sarea->frame.y * dev_priv->front_pitch +
1269 * ( dev_priv->color_fmt - 2 ) ) & ~7 ) 1307 sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
1270 + offset ); 1308 + offset);
1271 OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base 1309 OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
1272 + offset ); 1310 + offset);
1273 1311
1274 ADVANCE_RING(); 1312 ADVANCE_RING();
1275 1313
@@ -1279,16 +1317,16 @@ static void radeon_cp_dispatch_flip( drm_device_t *dev )
1279 */ 1317 */
1280 dev_priv->sarea_priv->last_frame++; 1318 dev_priv->sarea_priv->last_frame++;
1281 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = 1319 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
1282 1 - dev_priv->current_page; 1320 1 - dev_priv->current_page;
1283 1321
1284 BEGIN_RING( 2 ); 1322 BEGIN_RING(2);
1285 1323
1286 RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); 1324 RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1287 1325
1288 ADVANCE_RING(); 1326 ADVANCE_RING();
1289} 1327}
1290 1328
1291static int bad_prim_vertex_nr( int primitive, int nr ) 1329static int bad_prim_vertex_nr(int primitive, int nr)
1292{ 1330{
1293 switch (primitive & RADEON_PRIM_TYPE_MASK) { 1331 switch (primitive & RADEON_PRIM_TYPE_MASK) {
1294 case RADEON_PRIM_TYPE_NONE: 1332 case RADEON_PRIM_TYPE_NONE:
@@ -1308,24 +1346,21 @@ static int bad_prim_vertex_nr( int primitive, int nr )
1308 return nr < 3; 1346 return nr < 3;
1309 default: 1347 default:
1310 return 1; 1348 return 1;
1311 } 1349 }
1312} 1350}
1313 1351
1314
1315
1316typedef struct { 1352typedef struct {
1317 unsigned int start; 1353 unsigned int start;
1318 unsigned int finish; 1354 unsigned int finish;
1319 unsigned int prim; 1355 unsigned int prim;
1320 unsigned int numverts; 1356 unsigned int numverts;
1321 unsigned int offset; 1357 unsigned int offset;
1322 unsigned int vc_format; 1358 unsigned int vc_format;
1323} drm_radeon_tcl_prim_t; 1359} drm_radeon_tcl_prim_t;
1324 1360
1325static void radeon_cp_dispatch_vertex( drm_device_t *dev, 1361static void radeon_cp_dispatch_vertex(drm_device_t * dev,
1326 drm_buf_t *buf, 1362 drm_buf_t * buf,
1327 drm_radeon_tcl_prim_t *prim ) 1363 drm_radeon_tcl_prim_t * prim)
1328
1329{ 1364{
1330 drm_radeon_private_t *dev_priv = dev->dev_private; 1365 drm_radeon_private_t *dev_priv = dev->dev_private;
1331 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 1366 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1337,45 +1372,39 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
1337 1372
1338 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n", 1373 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
1339 prim->prim, 1374 prim->prim,
1340 prim->vc_format, 1375 prim->vc_format, prim->start, prim->finish, prim->numverts);
1341 prim->start,
1342 prim->finish,
1343 prim->numverts);
1344 1376
1345 if (bad_prim_vertex_nr( prim->prim, prim->numverts )) { 1377 if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
1346 DRM_ERROR( "bad prim %x numverts %d\n", 1378 DRM_ERROR("bad prim %x numverts %d\n",
1347 prim->prim, prim->numverts ); 1379 prim->prim, prim->numverts);
1348 return; 1380 return;
1349 } 1381 }
1350 1382
1351 do { 1383 do {
1352 /* Emit the next cliprect */ 1384 /* Emit the next cliprect */
1353 if ( i < nbox ) { 1385 if (i < nbox) {
1354 radeon_emit_clip_rect( dev_priv, 1386 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1355 &sarea_priv->boxes[i] );
1356 } 1387 }
1357 1388
1358 /* Emit the vertex buffer rendering commands */ 1389 /* Emit the vertex buffer rendering commands */
1359 BEGIN_RING( 5 ); 1390 BEGIN_RING(5);
1360 1391
1361 OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) ); 1392 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3));
1362 OUT_RING( offset ); 1393 OUT_RING(offset);
1363 OUT_RING( numverts ); 1394 OUT_RING(numverts);
1364 OUT_RING( prim->vc_format ); 1395 OUT_RING(prim->vc_format);
1365 OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST | 1396 OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
1366 RADEON_COLOR_ORDER_RGBA | 1397 RADEON_COLOR_ORDER_RGBA |
1367 RADEON_VTX_FMT_RADEON_MODE | 1398 RADEON_VTX_FMT_RADEON_MODE |
1368 (numverts << RADEON_NUM_VERTICES_SHIFT) ); 1399 (numverts << RADEON_NUM_VERTICES_SHIFT));
1369 1400
1370 ADVANCE_RING(); 1401 ADVANCE_RING();
1371 1402
1372 i++; 1403 i++;
1373 } while ( i < nbox ); 1404 } while (i < nbox);
1374} 1405}
1375 1406
1376 1407static void radeon_cp_discard_buffer(drm_device_t * dev, drm_buf_t * buf)
1377
1378static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
1379{ 1408{
1380 drm_radeon_private_t *dev_priv = dev->dev_private; 1409 drm_radeon_private_t *dev_priv = dev->dev_private;
1381 drm_radeon_buf_priv_t *buf_priv = buf->dev_private; 1410 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
@@ -1384,24 +1413,22 @@ static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
1384 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; 1413 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
1385 1414
1386 /* Emit the vertex buffer age */ 1415 /* Emit the vertex buffer age */
1387 BEGIN_RING( 2 ); 1416 BEGIN_RING(2);
1388 RADEON_DISPATCH_AGE( buf_priv->age ); 1417 RADEON_DISPATCH_AGE(buf_priv->age);
1389 ADVANCE_RING(); 1418 ADVANCE_RING();
1390 1419
1391 buf->pending = 1; 1420 buf->pending = 1;
1392 buf->used = 0; 1421 buf->used = 0;
1393} 1422}
1394 1423
1395static void radeon_cp_dispatch_indirect( drm_device_t *dev, 1424static void radeon_cp_dispatch_indirect(drm_device_t * dev,
1396 drm_buf_t *buf, 1425 drm_buf_t * buf, int start, int end)
1397 int start, int end )
1398{ 1426{
1399 drm_radeon_private_t *dev_priv = dev->dev_private; 1427 drm_radeon_private_t *dev_priv = dev->dev_private;
1400 RING_LOCALS; 1428 RING_LOCALS;
1401 DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", 1429 DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
1402 buf->idx, start, end );
1403 1430
1404 if ( start != end ) { 1431 if (start != end) {
1405 int offset = (dev_priv->gart_buffers_offset 1432 int offset = (dev_priv->gart_buffers_offset
1406 + buf->offset + start); 1433 + buf->offset + start);
1407 int dwords = (end - start + 3) / sizeof(u32); 1434 int dwords = (end - start + 3) / sizeof(u32);
@@ -1410,28 +1437,27 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
1410 * dwords, so if we've been given an odd number we must 1437 * dwords, so if we've been given an odd number we must
1411 * pad the data with a Type-2 CP packet. 1438 * pad the data with a Type-2 CP packet.
1412 */ 1439 */
1413 if ( dwords & 1 ) { 1440 if (dwords & 1) {
1414 u32 *data = (u32 *) 1441 u32 *data = (u32 *)
1415 ((char *)dev->agp_buffer_map->handle 1442 ((char *)dev->agp_buffer_map->handle
1416 + buf->offset + start); 1443 + buf->offset + start);
1417 data[dwords++] = RADEON_CP_PACKET2; 1444 data[dwords++] = RADEON_CP_PACKET2;
1418 } 1445 }
1419 1446
1420 /* Fire off the indirect buffer */ 1447 /* Fire off the indirect buffer */
1421 BEGIN_RING( 3 ); 1448 BEGIN_RING(3);
1422 1449
1423 OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) ); 1450 OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
1424 OUT_RING( offset ); 1451 OUT_RING(offset);
1425 OUT_RING( dwords ); 1452 OUT_RING(dwords);
1426 1453
1427 ADVANCE_RING(); 1454 ADVANCE_RING();
1428 } 1455 }
1429} 1456}
1430 1457
1431 1458static void radeon_cp_dispatch_indices(drm_device_t * dev,
1432static void radeon_cp_dispatch_indices( drm_device_t *dev, 1459 drm_buf_t * elt_buf,
1433 drm_buf_t *elt_buf, 1460 drm_radeon_tcl_prim_t * prim)
1434 drm_radeon_tcl_prim_t *prim )
1435{ 1461{
1436 drm_radeon_private_t *dev_priv = dev->dev_private; 1462 drm_radeon_private_t *dev_priv = dev->dev_private;
1437 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 1463 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1446,30 +1472,24 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
1446 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", 1472 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
1447 prim->prim, 1473 prim->prim,
1448 prim->vc_format, 1474 prim->vc_format,
1449 prim->start, 1475 prim->start, prim->finish, prim->offset, prim->numverts);
1450 prim->finish, 1476
1451 prim->offset, 1477 if (bad_prim_vertex_nr(prim->prim, count)) {
1452 prim->numverts); 1478 DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
1453
1454 if (bad_prim_vertex_nr( prim->prim, count )) {
1455 DRM_ERROR( "bad prim %x count %d\n",
1456 prim->prim, count );
1457 return; 1479 return;
1458 } 1480 }
1459 1481
1460 1482 if (start >= prim->finish || (prim->start & 0x7)) {
1461 if ( start >= prim->finish || 1483 DRM_ERROR("buffer prim %d\n", prim->prim);
1462 (prim->start & 0x7) ) {
1463 DRM_ERROR( "buffer prim %d\n", prim->prim );
1464 return; 1484 return;
1465 } 1485 }
1466 1486
1467 dwords = (prim->finish - prim->start + 3) / sizeof(u32); 1487 dwords = (prim->finish - prim->start + 3) / sizeof(u32);
1468 1488
1469 data = (u32 *)((char *)dev->agp_buffer_map->handle + 1489 data = (u32 *) ((char *)dev->agp_buffer_map->handle +
1470 elt_buf->offset + prim->start); 1490 elt_buf->offset + prim->start);
1471 1491
1472 data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 ); 1492 data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2);
1473 data[1] = offset; 1493 data[1] = offset;
1474 data[2] = prim->numverts; 1494 data[2] = prim->numverts;
1475 data[3] = prim->vc_format; 1495 data[3] = prim->vc_format;
@@ -1477,28 +1497,26 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
1477 RADEON_PRIM_WALK_IND | 1497 RADEON_PRIM_WALK_IND |
1478 RADEON_COLOR_ORDER_RGBA | 1498 RADEON_COLOR_ORDER_RGBA |
1479 RADEON_VTX_FMT_RADEON_MODE | 1499 RADEON_VTX_FMT_RADEON_MODE |
1480 (count << RADEON_NUM_VERTICES_SHIFT) ); 1500 (count << RADEON_NUM_VERTICES_SHIFT));
1481 1501
1482 do { 1502 do {
1483 if ( i < nbox ) 1503 if (i < nbox)
1484 radeon_emit_clip_rect( dev_priv, 1504 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1485 &sarea_priv->boxes[i] );
1486 1505
1487 radeon_cp_dispatch_indirect( dev, elt_buf, 1506 radeon_cp_dispatch_indirect(dev, elt_buf,
1488 prim->start, 1507 prim->start, prim->finish);
1489 prim->finish );
1490 1508
1491 i++; 1509 i++;
1492 } while ( i < nbox ); 1510 } while (i < nbox);
1493 1511
1494} 1512}
1495 1513
1496#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE 1514#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE
1497 1515
1498static int radeon_cp_dispatch_texture( DRMFILE filp, 1516static int radeon_cp_dispatch_texture(DRMFILE filp,
1499 drm_device_t *dev, 1517 drm_device_t * dev,
1500 drm_radeon_texture_t *tex, 1518 drm_radeon_texture_t * tex,
1501 drm_radeon_tex_image_t *image ) 1519 drm_radeon_tex_image_t * image)
1502{ 1520{
1503 drm_radeon_private_t *dev_priv = dev->dev_private; 1521 drm_radeon_private_t *dev_priv = dev->dev_private;
1504 drm_file_t *filp_priv; 1522 drm_file_t *filp_priv;
@@ -1513,11 +1531,11 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1513 u32 offset; 1531 u32 offset;
1514 RING_LOCALS; 1532 RING_LOCALS;
1515 1533
1516 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 1534 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
1517 1535
1518 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &tex->offset ) ) { 1536 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) {
1519 DRM_ERROR( "Invalid destination offset\n" ); 1537 DRM_ERROR("Invalid destination offset\n");
1520 return DRM_ERR( EINVAL ); 1538 return DRM_ERR(EINVAL);
1521 } 1539 }
1522 1540
1523 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; 1541 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
@@ -1526,7 +1544,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1526 * up with the texture data from the host data blit, otherwise 1544 * up with the texture data from the host data blit, otherwise
1527 * part of the texture image may be corrupted. 1545 * part of the texture image may be corrupted.
1528 */ 1546 */
1529 BEGIN_RING( 4 ); 1547 BEGIN_RING(4);
1530 RADEON_FLUSH_CACHE(); 1548 RADEON_FLUSH_CACHE();
1531 RADEON_WAIT_UNTIL_IDLE(); 1549 RADEON_WAIT_UNTIL_IDLE();
1532 ADVANCE_RING(); 1550 ADVANCE_RING();
@@ -1535,7 +1553,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1535 * even if the only legal values are powers of two. Thus, we'll 1553 * even if the only legal values are powers of two. Thus, we'll
1536 * use a shift instead. 1554 * use a shift instead.
1537 */ 1555 */
1538 switch ( tex->format ) { 1556 switch (tex->format) {
1539 case RADEON_TXFORMAT_ARGB8888: 1557 case RADEON_TXFORMAT_ARGB8888:
1540 case RADEON_TXFORMAT_RGBA8888: 1558 case RADEON_TXFORMAT_RGBA8888:
1541 format = RADEON_COLOR_FORMAT_ARGB8888; 1559 format = RADEON_COLOR_FORMAT_ARGB8888;
@@ -1559,7 +1577,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1559 blit_width = image->width * 1; 1577 blit_width = image->width * 1;
1560 break; 1578 break;
1561 default: 1579 default:
1562 DRM_ERROR( "invalid texture format %d\n", tex->format ); 1580 DRM_ERROR("invalid texture format %d\n", tex->format);
1563 return DRM_ERR(EINVAL); 1581 return DRM_ERR(EINVAL);
1564 } 1582 }
1565 spitch = blit_width >> 6; 1583 spitch = blit_width >> 6;
@@ -1574,49 +1592,49 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1574 /* we got tiled coordinates, untile them */ 1592 /* we got tiled coordinates, untile them */
1575 image->x *= 2; 1593 image->x *= 2;
1576 } 1594 }
1577 } 1595 } else
1578 else microtile = 0; 1596 microtile = 0;
1579 1597
1580 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width ); 1598 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
1581 1599
1582 do { 1600 do {
1583 DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", 1601 DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
1584 tex->offset >> 10, tex->pitch, tex->format, 1602 tex->offset >> 10, tex->pitch, tex->format,
1585 image->x, image->y, image->width, image->height ); 1603 image->x, image->y, image->width, image->height);
1586 1604
1587 /* Make a copy of some parameters in case we have to 1605 /* Make a copy of some parameters in case we have to
1588 * update them for a multi-pass texture blit. 1606 * update them for a multi-pass texture blit.
1589 */ 1607 */
1590 height = image->height; 1608 height = image->height;
1591 data = (const u8 __user *)image->data; 1609 data = (const u8 __user *)image->data;
1592 1610
1593 size = height * blit_width; 1611 size = height * blit_width;
1594 1612
1595 if ( size > RADEON_MAX_TEXTURE_SIZE ) { 1613 if (size > RADEON_MAX_TEXTURE_SIZE) {
1596 height = RADEON_MAX_TEXTURE_SIZE / blit_width; 1614 height = RADEON_MAX_TEXTURE_SIZE / blit_width;
1597 size = height * blit_width; 1615 size = height * blit_width;
1598 } else if ( size < 4 && size > 0 ) { 1616 } else if (size < 4 && size > 0) {
1599 size = 4; 1617 size = 4;
1600 } else if ( size == 0 ) { 1618 } else if (size == 0) {
1601 return 0; 1619 return 0;
1602 } 1620 }
1603 1621
1604 buf = radeon_freelist_get( dev ); 1622 buf = radeon_freelist_get(dev);
1605 if ( 0 && !buf ) { 1623 if (0 && !buf) {
1606 radeon_do_cp_idle( dev_priv ); 1624 radeon_do_cp_idle(dev_priv);
1607 buf = radeon_freelist_get( dev ); 1625 buf = radeon_freelist_get(dev);
1608 } 1626 }
1609 if ( !buf ) { 1627 if (!buf) {
1610 DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n"); 1628 DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n");
1611 if (DRM_COPY_TO_USER( tex->image, image, sizeof(*image) )) 1629 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
1612 return DRM_ERR(EFAULT); 1630 return DRM_ERR(EFAULT);
1613 return DRM_ERR(EAGAIN); 1631 return DRM_ERR(EAGAIN);
1614 } 1632 }
1615 1633
1616
1617 /* Dispatch the indirect buffer. 1634 /* Dispatch the indirect buffer.
1618 */ 1635 */
1619 buffer = (u32*)((char*)dev->agp_buffer_map->handle + buf->offset); 1636 buffer =
1637 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
1620 dwords = size / 4; 1638 dwords = size / 4;
1621 1639
1622 if (microtile) { 1640 if (microtile) {
@@ -1631,20 +1649,26 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1631 if (tex->height == 1) { 1649 if (tex->height == 1) {
1632 if (tex_width >= 64 || tex_width <= 16) { 1650 if (tex_width >= 64 || tex_width <= 16) {
1633 if (DRM_COPY_FROM_USER(buffer, data, 1651 if (DRM_COPY_FROM_USER(buffer, data,
1634 tex_width * sizeof(u32))) { 1652 tex_width *
1635 DRM_ERROR("EFAULT on pad, %d bytes\n", 1653 sizeof(u32))) {
1636 tex_width); 1654 DRM_ERROR
1655 ("EFAULT on pad, %d bytes\n",
1656 tex_width);
1637 return DRM_ERR(EFAULT); 1657 return DRM_ERR(EFAULT);
1638 } 1658 }
1639 } else if (tex_width == 32) { 1659 } else if (tex_width == 32) {
1640 if (DRM_COPY_FROM_USER(buffer, data, 16)) { 1660 if (DRM_COPY_FROM_USER
1641 DRM_ERROR("EFAULT on pad, %d bytes\n", 1661 (buffer, data, 16)) {
1642 tex_width); 1662 DRM_ERROR
1663 ("EFAULT on pad, %d bytes\n",
1664 tex_width);
1643 return DRM_ERR(EFAULT); 1665 return DRM_ERR(EFAULT);
1644 } 1666 }
1645 if (DRM_COPY_FROM_USER(buffer + 8, data + 16, 16)) { 1667 if (DRM_COPY_FROM_USER
1646 DRM_ERROR("EFAULT on pad, %d bytes\n", 1668 (buffer + 8, data + 16, 16)) {
1647 tex_width); 1669 DRM_ERROR
1670 ("EFAULT on pad, %d bytes\n",
1671 tex_width);
1648 return DRM_ERR(EFAULT); 1672 return DRM_ERR(EFAULT);
1649 } 1673 }
1650 } 1674 }
@@ -1657,9 +1681,11 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1657 } 1681 }
1658 } else if (tex_width < 16) { 1682 } else if (tex_width < 16) {
1659 for (i = 0; i < tex->height; i++) { 1683 for (i = 0; i < tex->height; i++) {
1660 if (DRM_COPY_FROM_USER(buffer, data, tex_width)) { 1684 if (DRM_COPY_FROM_USER
1661 DRM_ERROR("EFAULT on pad, %d bytes\n", 1685 (buffer, data, tex_width)) {
1662 tex_width); 1686 DRM_ERROR
1687 ("EFAULT on pad, %d bytes\n",
1688 tex_width);
1663 return DRM_ERR(EFAULT); 1689 return DRM_ERR(EFAULT);
1664 } 1690 }
1665 buffer += 4; 1691 buffer += 4;
@@ -1669,35 +1695,42 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1669 /* TODO: make sure this works when not fitting in one buffer 1695 /* TODO: make sure this works when not fitting in one buffer
1670 (i.e. 32bytes x 2048...) */ 1696 (i.e. 32bytes x 2048...) */
1671 for (i = 0; i < tex->height; i += 2) { 1697 for (i = 0; i < tex->height; i += 2) {
1672 if (DRM_COPY_FROM_USER(buffer, data, 16)) { 1698 if (DRM_COPY_FROM_USER
1673 DRM_ERROR("EFAULT on pad, %d bytes\n", 1699 (buffer, data, 16)) {
1674 tex_width); 1700 DRM_ERROR
1701 ("EFAULT on pad, %d bytes\n",
1702 tex_width);
1675 return DRM_ERR(EFAULT); 1703 return DRM_ERR(EFAULT);
1676 } 1704 }
1677 data += 16; 1705 data += 16;
1678 if (DRM_COPY_FROM_USER(buffer + 8, data, 16)) { 1706 if (DRM_COPY_FROM_USER
1679 DRM_ERROR("EFAULT on pad, %d bytes\n", 1707 (buffer + 8, data, 16)) {
1680 tex_width); 1708 DRM_ERROR
1709 ("EFAULT on pad, %d bytes\n",
1710 tex_width);
1681 return DRM_ERR(EFAULT); 1711 return DRM_ERR(EFAULT);
1682 } 1712 }
1683 data += 16; 1713 data += 16;
1684 if (DRM_COPY_FROM_USER(buffer + 4, data, 16)) { 1714 if (DRM_COPY_FROM_USER
1685 DRM_ERROR("EFAULT on pad, %d bytes\n", 1715 (buffer + 4, data, 16)) {
1686 tex_width); 1716 DRM_ERROR
1717 ("EFAULT on pad, %d bytes\n",
1718 tex_width);
1687 return DRM_ERR(EFAULT); 1719 return DRM_ERR(EFAULT);
1688 } 1720 }
1689 data += 16; 1721 data += 16;
1690 if (DRM_COPY_FROM_USER(buffer + 12, data, 16)) { 1722 if (DRM_COPY_FROM_USER
1691 DRM_ERROR("EFAULT on pad, %d bytes\n", 1723 (buffer + 12, data, 16)) {
1692 tex_width); 1724 DRM_ERROR
1725 ("EFAULT on pad, %d bytes\n",
1726 tex_width);
1693 return DRM_ERR(EFAULT); 1727 return DRM_ERR(EFAULT);
1694 } 1728 }
1695 data += 16; 1729 data += 16;
1696 buffer += 16; 1730 buffer += 16;
1697 } 1731 }
1698 } 1732 }
1699 } 1733 } else {
1700 else {
1701 if (tex_width >= 32) { 1734 if (tex_width >= 32) {
1702 /* Texture image width is larger than the minimum, so we 1735 /* Texture image width is larger than the minimum, so we
1703 * can upload it directly. 1736 * can upload it directly.
@@ -1713,9 +1746,12 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1713 * need to pad out each image scanline to the minimum 1746 * need to pad out each image scanline to the minimum
1714 * width. 1747 * width.
1715 */ 1748 */
1716 for (i = 0 ; i < tex->height ; i++) { 1749 for (i = 0; i < tex->height; i++) {
1717 if (DRM_COPY_FROM_USER(buffer, data, tex_width )) { 1750 if (DRM_COPY_FROM_USER
1718 DRM_ERROR("EFAULT on pad, %d bytes\n", tex_width); 1751 (buffer, data, tex_width)) {
1752 DRM_ERROR
1753 ("EFAULT on pad, %d bytes\n",
1754 tex_width);
1719 return DRM_ERR(EFAULT); 1755 return DRM_ERR(EFAULT);
1720 } 1756 }
1721 buffer += 8; 1757 buffer += 8;
@@ -1736,8 +1772,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1736 RADEON_GMC_SRC_DATATYPE_COLOR | 1772 RADEON_GMC_SRC_DATATYPE_COLOR |
1737 RADEON_ROP3_S | 1773 RADEON_ROP3_S |
1738 RADEON_DP_SRC_SOURCE_MEMORY | 1774 RADEON_DP_SRC_SOURCE_MEMORY |
1739 RADEON_GMC_CLR_CMP_CNTL_DIS | 1775 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1740 RADEON_GMC_WR_MSK_DIS );
1741 OUT_RING((spitch << 22) | (offset >> 10)); 1776 OUT_RING((spitch << 22) | (offset >> 10));
1742 OUT_RING((texpitch << 22) | (tex->offset >> 10)); 1777 OUT_RING((texpitch << 22) | (tex->offset >> 10));
1743 OUT_RING(0); 1778 OUT_RING(0);
@@ -1758,62 +1793,62 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1758 * the texture data is written out to memory before rendering 1793 * the texture data is written out to memory before rendering
1759 * continues. 1794 * continues.
1760 */ 1795 */
1761 BEGIN_RING( 4 ); 1796 BEGIN_RING(4);
1762 RADEON_FLUSH_CACHE(); 1797 RADEON_FLUSH_CACHE();
1763 RADEON_WAIT_UNTIL_2D_IDLE(); 1798 RADEON_WAIT_UNTIL_2D_IDLE();
1764 ADVANCE_RING(); 1799 ADVANCE_RING();
1765 return 0; 1800 return 0;
1766} 1801}
1767 1802
1768 1803static void radeon_cp_dispatch_stipple(drm_device_t * dev, u32 * stipple)
1769static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
1770{ 1804{
1771 drm_radeon_private_t *dev_priv = dev->dev_private; 1805 drm_radeon_private_t *dev_priv = dev->dev_private;
1772 int i; 1806 int i;
1773 RING_LOCALS; 1807 RING_LOCALS;
1774 DRM_DEBUG( "\n" ); 1808 DRM_DEBUG("\n");
1775 1809
1776 BEGIN_RING( 35 ); 1810 BEGIN_RING(35);
1777 1811
1778 OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) ); 1812 OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));
1779 OUT_RING( 0x00000000 ); 1813 OUT_RING(0x00000000);
1780 1814
1781 OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) ); 1815 OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
1782 for ( i = 0 ; i < 32 ; i++ ) { 1816 for (i = 0; i < 32; i++) {
1783 OUT_RING( stipple[i] ); 1817 OUT_RING(stipple[i]);
1784 } 1818 }
1785 1819
1786 ADVANCE_RING(); 1820 ADVANCE_RING();
1787} 1821}
1788 1822
1789static void radeon_apply_surface_regs(int surf_index, drm_radeon_private_t *dev_priv) 1823static void radeon_apply_surface_regs(int surf_index,
1824 drm_radeon_private_t * dev_priv)
1790{ 1825{
1791 if (!dev_priv->mmio) 1826 if (!dev_priv->mmio)
1792 return; 1827 return;
1793 1828
1794 radeon_do_cp_idle(dev_priv); 1829 radeon_do_cp_idle(dev_priv);
1795 1830
1796 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*surf_index, 1831 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
1797 dev_priv->surfaces[surf_index].flags); 1832 dev_priv->surfaces[surf_index].flags);
1798 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*surf_index, 1833 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
1799 dev_priv->surfaces[surf_index].lower); 1834 dev_priv->surfaces[surf_index].lower);
1800 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*surf_index, 1835 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
1801 dev_priv->surfaces[surf_index].upper); 1836 dev_priv->surfaces[surf_index].upper);
1802} 1837}
1803 1838
1804
1805/* Allocates a virtual surface 1839/* Allocates a virtual surface
1806 * doesn't always allocate a real surface, will stretch an existing 1840 * doesn't always allocate a real surface, will stretch an existing
1807 * surface when possible. 1841 * surface when possible.
1808 * 1842 *
1809 * Note that refcount can be at most 2, since during a free refcount=3 1843 * Note that refcount can be at most 2, since during a free refcount=3
1810 * might mean we have to allocate a new surface which might not always 1844 * might mean we have to allocate a new surface which might not always
1811 * be available. 1845 * be available.
1812 * For example : we allocate three contigous surfaces ABC. If B is 1846 * For example : we allocate three contigous surfaces ABC. If B is
1813 * freed, we suddenly need two surfaces to store A and C, which might 1847 * freed, we suddenly need two surfaces to store A and C, which might
1814 * not always be available. 1848 * not always be available.
1815 */ 1849 */
1816static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *dev_priv, DRMFILE filp) 1850static int alloc_surface(drm_radeon_surface_alloc_t * new,
1851 drm_radeon_private_t * dev_priv, DRMFILE filp)
1817{ 1852{
1818 struct radeon_virt_surface *s; 1853 struct radeon_virt_surface *s;
1819 int i; 1854 int i;
@@ -1825,34 +1860,37 @@ static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *
1825 1860
1826 /* sanity check */ 1861 /* sanity check */
1827 if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) || 1862 if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) ||
1828 ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) != RADEON_SURF_ADDRESS_FIXED_MASK) || 1863 ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) !=
1829 ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0)) 1864 RADEON_SURF_ADDRESS_FIXED_MASK)
1865 || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0))
1830 return -1; 1866 return -1;
1831 1867
1832 /* make sure there is no overlap with existing surfaces */ 1868 /* make sure there is no overlap with existing surfaces */
1833 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1869 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1834 if ((dev_priv->surfaces[i].refcount != 0) && 1870 if ((dev_priv->surfaces[i].refcount != 0) &&
1835 (( (new_lower >= dev_priv->surfaces[i].lower) && 1871 (((new_lower >= dev_priv->surfaces[i].lower) &&
1836 (new_lower < dev_priv->surfaces[i].upper) ) || 1872 (new_lower < dev_priv->surfaces[i].upper)) ||
1837 ( (new_lower < dev_priv->surfaces[i].lower) && 1873 ((new_lower < dev_priv->surfaces[i].lower) &&
1838 (new_upper > dev_priv->surfaces[i].lower) )) ){ 1874 (new_upper > dev_priv->surfaces[i].lower)))) {
1839 return -1;} 1875 return -1;
1876 }
1840 } 1877 }
1841 1878
1842 /* find a virtual surface */ 1879 /* find a virtual surface */
1843 for (i = 0; i < 2*RADEON_MAX_SURFACES; i++) 1880 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
1844 if (dev_priv->virt_surfaces[i].filp == 0) 1881 if (dev_priv->virt_surfaces[i].filp == 0)
1845 break; 1882 break;
1846 if (i == 2*RADEON_MAX_SURFACES) { 1883 if (i == 2 * RADEON_MAX_SURFACES) {
1847 return -1;} 1884 return -1;
1885 }
1848 virt_surface_index = i; 1886 virt_surface_index = i;
1849 1887
1850 /* try to reuse an existing surface */ 1888 /* try to reuse an existing surface */
1851 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1889 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1852 /* extend before */ 1890 /* extend before */
1853 if ((dev_priv->surfaces[i].refcount == 1) && 1891 if ((dev_priv->surfaces[i].refcount == 1) &&
1854 (new->flags == dev_priv->surfaces[i].flags) && 1892 (new->flags == dev_priv->surfaces[i].flags) &&
1855 (new_upper + 1 == dev_priv->surfaces[i].lower)) { 1893 (new_upper + 1 == dev_priv->surfaces[i].lower)) {
1856 s = &(dev_priv->virt_surfaces[virt_surface_index]); 1894 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1857 s->surface_index = i; 1895 s->surface_index = i;
1858 s->lower = new_lower; 1896 s->lower = new_lower;
@@ -1867,8 +1905,8 @@ static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *
1867 1905
1868 /* extend after */ 1906 /* extend after */
1869 if ((dev_priv->surfaces[i].refcount == 1) && 1907 if ((dev_priv->surfaces[i].refcount == 1) &&
1870 (new->flags == dev_priv->surfaces[i].flags) && 1908 (new->flags == dev_priv->surfaces[i].flags) &&
1871 (new_lower == dev_priv->surfaces[i].upper + 1)) { 1909 (new_lower == dev_priv->surfaces[i].upper + 1)) {
1872 s = &(dev_priv->virt_surfaces[virt_surface_index]); 1910 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1873 s->surface_index = i; 1911 s->surface_index = i;
1874 s->lower = new_lower; 1912 s->lower = new_lower;
@@ -1904,26 +1942,34 @@ static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *
1904 return -1; 1942 return -1;
1905} 1943}
1906 1944
1907static int free_surface(DRMFILE filp, drm_radeon_private_t *dev_priv, int lower) 1945static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv,
1946 int lower)
1908{ 1947{
1909 struct radeon_virt_surface *s; 1948 struct radeon_virt_surface *s;
1910 int i; 1949 int i;
1911 /* find the virtual surface */ 1950 /* find the virtual surface */
1912 for(i = 0; i < 2*RADEON_MAX_SURFACES; i++) { 1951 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
1913 s = &(dev_priv->virt_surfaces[i]); 1952 s = &(dev_priv->virt_surfaces[i]);
1914 if (s->filp) { 1953 if (s->filp) {
1915 if ((lower == s->lower) && (filp == s->filp)) { 1954 if ((lower == s->lower) && (filp == s->filp)) {
1916 if (dev_priv->surfaces[s->surface_index].lower == s->lower) 1955 if (dev_priv->surfaces[s->surface_index].
1917 dev_priv->surfaces[s->surface_index].lower = s->upper; 1956 lower == s->lower)
1957 dev_priv->surfaces[s->surface_index].
1958 lower = s->upper;
1918 1959
1919 if (dev_priv->surfaces[s->surface_index].upper == s->upper) 1960 if (dev_priv->surfaces[s->surface_index].
1920 dev_priv->surfaces[s->surface_index].upper = s->lower; 1961 upper == s->upper)
1962 dev_priv->surfaces[s->surface_index].
1963 upper = s->lower;
1921 1964
1922 dev_priv->surfaces[s->surface_index].refcount--; 1965 dev_priv->surfaces[s->surface_index].refcount--;
1923 if (dev_priv->surfaces[s->surface_index].refcount == 0) 1966 if (dev_priv->surfaces[s->surface_index].
1924 dev_priv->surfaces[s->surface_index].flags = 0; 1967 refcount == 0)
1968 dev_priv->surfaces[s->surface_index].
1969 flags = 0;
1925 s->filp = NULL; 1970 s->filp = NULL;
1926 radeon_apply_surface_regs(s->surface_index, dev_priv); 1971 radeon_apply_surface_regs(s->surface_index,
1972 dev_priv);
1927 return 0; 1973 return 0;
1928 } 1974 }
1929 } 1975 }
@@ -1931,13 +1977,14 @@ static int free_surface(DRMFILE filp, drm_radeon_private_t *dev_priv, int lower)
1931 return 1; 1977 return 1;
1932} 1978}
1933 1979
1934static void radeon_surfaces_release(DRMFILE filp, drm_radeon_private_t *dev_priv) 1980static void radeon_surfaces_release(DRMFILE filp,
1981 drm_radeon_private_t * dev_priv)
1935{ 1982{
1936 int i; 1983 int i;
1937 for( i = 0; i < 2*RADEON_MAX_SURFACES; i++) 1984 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
1938 {
1939 if (dev_priv->virt_surfaces[i].filp == filp) 1985 if (dev_priv->virt_surfaces[i].filp == filp)
1940 free_surface(filp, dev_priv, dev_priv->virt_surfaces[i].lower); 1986 free_surface(filp, dev_priv,
1987 dev_priv->virt_surfaces[i].lower);
1941 } 1988 }
1942} 1989}
1943 1990
@@ -1951,12 +1998,13 @@ static int radeon_surface_alloc(DRM_IOCTL_ARGS)
1951 drm_radeon_surface_alloc_t alloc; 1998 drm_radeon_surface_alloc_t alloc;
1952 1999
1953 if (!dev_priv) { 2000 if (!dev_priv) {
1954 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2001 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1955 return DRM_ERR(EINVAL); 2002 return DRM_ERR(EINVAL);
1956 } 2003 }
1957 2004
1958 DRM_COPY_FROM_USER_IOCTL(alloc, (drm_radeon_surface_alloc_t __user *)data, 2005 DRM_COPY_FROM_USER_IOCTL(alloc,
1959 sizeof(alloc)); 2006 (drm_radeon_surface_alloc_t __user *) data,
2007 sizeof(alloc));
1960 2008
1961 if (alloc_surface(&alloc, dev_priv, filp) == -1) 2009 if (alloc_surface(&alloc, dev_priv, filp) == -1)
1962 return DRM_ERR(EINVAL); 2010 return DRM_ERR(EINVAL);
@@ -1971,12 +2019,12 @@ static int radeon_surface_free(DRM_IOCTL_ARGS)
1971 drm_radeon_surface_free_t memfree; 2019 drm_radeon_surface_free_t memfree;
1972 2020
1973 if (!dev_priv) { 2021 if (!dev_priv) {
1974 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2022 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1975 return DRM_ERR(EINVAL); 2023 return DRM_ERR(EINVAL);
1976 } 2024 }
1977 2025
1978 DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *)data, 2026 DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *) data,
1979 sizeof(memfree) ); 2027 sizeof(memfree));
1980 2028
1981 if (free_surface(filp, dev_priv, memfree.address)) 2029 if (free_surface(filp, dev_priv, memfree.address))
1982 return DRM_ERR(EINVAL); 2030 return DRM_ERR(EINVAL);
@@ -1984,51 +2032,52 @@ static int radeon_surface_free(DRM_IOCTL_ARGS)
1984 return 0; 2032 return 0;
1985} 2033}
1986 2034
1987static int radeon_cp_clear( DRM_IOCTL_ARGS ) 2035static int radeon_cp_clear(DRM_IOCTL_ARGS)
1988{ 2036{
1989 DRM_DEVICE; 2037 DRM_DEVICE;
1990 drm_radeon_private_t *dev_priv = dev->dev_private; 2038 drm_radeon_private_t *dev_priv = dev->dev_private;
1991 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 2039 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1992 drm_radeon_clear_t clear; 2040 drm_radeon_clear_t clear;
1993 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; 2041 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
1994 DRM_DEBUG( "\n" ); 2042 DRM_DEBUG("\n");
1995 2043
1996 LOCK_TEST_WITH_RETURN( dev, filp ); 2044 LOCK_TEST_WITH_RETURN(dev, filp);
1997 2045
1998 DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t __user *)data, 2046 DRM_COPY_FROM_USER_IOCTL(clear, (drm_radeon_clear_t __user *) data,
1999 sizeof(clear) ); 2047 sizeof(clear));
2000 2048
2001 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2049 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2002 2050
2003 if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) 2051 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2004 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; 2052 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2005 2053
2006 if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes, 2054 if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes,
2007 sarea_priv->nbox * sizeof(depth_boxes[0]) ) ) 2055 sarea_priv->nbox * sizeof(depth_boxes[0])))
2008 return DRM_ERR(EFAULT); 2056 return DRM_ERR(EFAULT);
2009 2057
2010 radeon_cp_dispatch_clear( dev, &clear, depth_boxes ); 2058 radeon_cp_dispatch_clear(dev, &clear, depth_boxes);
2011 2059
2012 COMMIT_RING(); 2060 COMMIT_RING();
2013 return 0; 2061 return 0;
2014} 2062}
2015 2063
2016
2017/* Not sure why this isn't set all the time: 2064/* Not sure why this isn't set all the time:
2018 */ 2065 */
2019static int radeon_do_init_pageflip( drm_device_t *dev ) 2066static int radeon_do_init_pageflip(drm_device_t * dev)
2020{ 2067{
2021 drm_radeon_private_t *dev_priv = dev->dev_private; 2068 drm_radeon_private_t *dev_priv = dev->dev_private;
2022 RING_LOCALS; 2069 RING_LOCALS;
2023 2070
2024 DRM_DEBUG( "\n" ); 2071 DRM_DEBUG("\n");
2025 2072
2026 BEGIN_RING( 6 ); 2073 BEGIN_RING(6);
2027 RADEON_WAIT_UNTIL_3D_IDLE(); 2074 RADEON_WAIT_UNTIL_3D_IDLE();
2028 OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) ); 2075 OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0));
2029 OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); 2076 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
2030 OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) ); 2077 RADEON_CRTC_OFFSET_FLIP_CNTL);
2031 OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); 2078 OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0));
2079 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
2080 RADEON_CRTC_OFFSET_FLIP_CNTL);
2032 ADVANCE_RING(); 2081 ADVANCE_RING();
2033 2082
2034 dev_priv->page_flipping = 1; 2083 dev_priv->page_flipping = 1;
@@ -2041,62 +2090,62 @@ static int radeon_do_init_pageflip( drm_device_t *dev )
2041/* Called whenever a client dies, from drm_release. 2090/* Called whenever a client dies, from drm_release.
2042 * NOTE: Lock isn't necessarily held when this is called! 2091 * NOTE: Lock isn't necessarily held when this is called!
2043 */ 2092 */
2044static int radeon_do_cleanup_pageflip( drm_device_t *dev ) 2093static int radeon_do_cleanup_pageflip(drm_device_t * dev)
2045{ 2094{
2046 drm_radeon_private_t *dev_priv = dev->dev_private; 2095 drm_radeon_private_t *dev_priv = dev->dev_private;
2047 DRM_DEBUG( "\n" ); 2096 DRM_DEBUG("\n");
2048 2097
2049 if (dev_priv->current_page != 0) 2098 if (dev_priv->current_page != 0)
2050 radeon_cp_dispatch_flip( dev ); 2099 radeon_cp_dispatch_flip(dev);
2051 2100
2052 dev_priv->page_flipping = 0; 2101 dev_priv->page_flipping = 0;
2053 return 0; 2102 return 0;
2054} 2103}
2055 2104
2056/* Swapping and flipping are different operations, need different ioctls. 2105/* Swapping and flipping are different operations, need different ioctls.
2057 * They can & should be intermixed to support multiple 3d windows. 2106 * They can & should be intermixed to support multiple 3d windows.
2058 */ 2107 */
2059static int radeon_cp_flip( DRM_IOCTL_ARGS ) 2108static int radeon_cp_flip(DRM_IOCTL_ARGS)
2060{ 2109{
2061 DRM_DEVICE; 2110 DRM_DEVICE;
2062 drm_radeon_private_t *dev_priv = dev->dev_private; 2111 drm_radeon_private_t *dev_priv = dev->dev_private;
2063 DRM_DEBUG( "\n" ); 2112 DRM_DEBUG("\n");
2113
2114 LOCK_TEST_WITH_RETURN(dev, filp);
2064 2115
2065 LOCK_TEST_WITH_RETURN( dev, filp ); 2116 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2066 2117
2067 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2118 if (!dev_priv->page_flipping)
2119 radeon_do_init_pageflip(dev);
2068 2120
2069 if (!dev_priv->page_flipping) 2121 radeon_cp_dispatch_flip(dev);
2070 radeon_do_init_pageflip( dev );
2071
2072 radeon_cp_dispatch_flip( dev );
2073 2122
2074 COMMIT_RING(); 2123 COMMIT_RING();
2075 return 0; 2124 return 0;
2076} 2125}
2077 2126
2078static int radeon_cp_swap( DRM_IOCTL_ARGS ) 2127static int radeon_cp_swap(DRM_IOCTL_ARGS)
2079{ 2128{
2080 DRM_DEVICE; 2129 DRM_DEVICE;
2081 drm_radeon_private_t *dev_priv = dev->dev_private; 2130 drm_radeon_private_t *dev_priv = dev->dev_private;
2082 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 2131 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2083 DRM_DEBUG( "\n" ); 2132 DRM_DEBUG("\n");
2084 2133
2085 LOCK_TEST_WITH_RETURN( dev, filp ); 2134 LOCK_TEST_WITH_RETURN(dev, filp);
2086 2135
2087 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2136 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2088 2137
2089 if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) 2138 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2090 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; 2139 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2091 2140
2092 radeon_cp_dispatch_swap( dev ); 2141 radeon_cp_dispatch_swap(dev);
2093 dev_priv->sarea_priv->ctx_owner = 0; 2142 dev_priv->sarea_priv->ctx_owner = 0;
2094 2143
2095 COMMIT_RING(); 2144 COMMIT_RING();
2096 return 0; 2145 return 0;
2097} 2146}
2098 2147
2099static int radeon_cp_vertex( DRM_IOCTL_ARGS ) 2148static int radeon_cp_vertex(DRM_IOCTL_ARGS)
2100{ 2149{
2101 DRM_DEVICE; 2150 DRM_DEVICE;
2102 drm_radeon_private_t *dev_priv = dev->dev_private; 2151 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2107,55 +2156,53 @@ static int radeon_cp_vertex( DRM_IOCTL_ARGS )
2107 drm_radeon_vertex_t vertex; 2156 drm_radeon_vertex_t vertex;
2108 drm_radeon_tcl_prim_t prim; 2157 drm_radeon_tcl_prim_t prim;
2109 2158
2110 LOCK_TEST_WITH_RETURN( dev, filp ); 2159 LOCK_TEST_WITH_RETURN(dev, filp);
2111 2160
2112 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 2161 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2113 2162
2114 DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t __user *)data, 2163 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data,
2115 sizeof(vertex) ); 2164 sizeof(vertex));
2116 2165
2117 DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", 2166 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
2118 DRM_CURRENTPID, 2167 DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard);
2119 vertex.idx, vertex.count, vertex.discard );
2120 2168
2121 if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { 2169 if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
2122 DRM_ERROR( "buffer index %d (of %d max)\n", 2170 DRM_ERROR("buffer index %d (of %d max)\n",
2123 vertex.idx, dma->buf_count - 1 ); 2171 vertex.idx, dma->buf_count - 1);
2124 return DRM_ERR(EINVAL); 2172 return DRM_ERR(EINVAL);
2125 } 2173 }
2126 if ( vertex.prim < 0 || 2174 if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2127 vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { 2175 DRM_ERROR("buffer prim %d\n", vertex.prim);
2128 DRM_ERROR( "buffer prim %d\n", vertex.prim );
2129 return DRM_ERR(EINVAL); 2176 return DRM_ERR(EINVAL);
2130 } 2177 }
2131 2178
2132 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2179 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2133 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2180 VB_AGE_TEST_WITH_RETURN(dev_priv);
2134 2181
2135 buf = dma->buflist[vertex.idx]; 2182 buf = dma->buflist[vertex.idx];
2136 2183
2137 if ( buf->filp != filp ) { 2184 if (buf->filp != filp) {
2138 DRM_ERROR( "process %d using buffer owned by %p\n", 2185 DRM_ERROR("process %d using buffer owned by %p\n",
2139 DRM_CURRENTPID, buf->filp ); 2186 DRM_CURRENTPID, buf->filp);
2140 return DRM_ERR(EINVAL); 2187 return DRM_ERR(EINVAL);
2141 } 2188 }
2142 if ( buf->pending ) { 2189 if (buf->pending) {
2143 DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); 2190 DRM_ERROR("sending pending buffer %d\n", vertex.idx);
2144 return DRM_ERR(EINVAL); 2191 return DRM_ERR(EINVAL);
2145 } 2192 }
2146 2193
2147 /* Build up a prim_t record: 2194 /* Build up a prim_t record:
2148 */ 2195 */
2149 if (vertex.count) { 2196 if (vertex.count) {
2150 buf->used = vertex.count; /* not used? */ 2197 buf->used = vertex.count; /* not used? */
2151 2198
2152 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { 2199 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2153 if ( radeon_emit_state( dev_priv, filp_priv, 2200 if (radeon_emit_state(dev_priv, filp_priv,
2154 &sarea_priv->context_state, 2201 &sarea_priv->context_state,
2155 sarea_priv->tex_state, 2202 sarea_priv->tex_state,
2156 sarea_priv->dirty ) ) { 2203 sarea_priv->dirty)) {
2157 DRM_ERROR( "radeon_emit_state failed\n" ); 2204 DRM_ERROR("radeon_emit_state failed\n");
2158 return DRM_ERR( EINVAL ); 2205 return DRM_ERR(EINVAL);
2159 } 2206 }
2160 2207
2161 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | 2208 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
@@ -2165,23 +2212,23 @@ static int radeon_cp_vertex( DRM_IOCTL_ARGS )
2165 } 2212 }
2166 2213
2167 prim.start = 0; 2214 prim.start = 0;
2168 prim.finish = vertex.count; /* unused */ 2215 prim.finish = vertex.count; /* unused */
2169 prim.prim = vertex.prim; 2216 prim.prim = vertex.prim;
2170 prim.numverts = vertex.count; 2217 prim.numverts = vertex.count;
2171 prim.vc_format = dev_priv->sarea_priv->vc_format; 2218 prim.vc_format = dev_priv->sarea_priv->vc_format;
2172 2219
2173 radeon_cp_dispatch_vertex( dev, buf, &prim ); 2220 radeon_cp_dispatch_vertex(dev, buf, &prim);
2174 } 2221 }
2175 2222
2176 if (vertex.discard) { 2223 if (vertex.discard) {
2177 radeon_cp_discard_buffer( dev, buf ); 2224 radeon_cp_discard_buffer(dev, buf);
2178 } 2225 }
2179 2226
2180 COMMIT_RING(); 2227 COMMIT_RING();
2181 return 0; 2228 return 0;
2182} 2229}
2183 2230
2184static int radeon_cp_indices( DRM_IOCTL_ARGS ) 2231static int radeon_cp_indices(DRM_IOCTL_ARGS)
2185{ 2232{
2186 DRM_DEVICE; 2233 DRM_DEVICE;
2187 drm_radeon_private_t *dev_priv = dev->dev_private; 2234 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2193,69 +2240,67 @@ static int radeon_cp_indices( DRM_IOCTL_ARGS )
2193 drm_radeon_tcl_prim_t prim; 2240 drm_radeon_tcl_prim_t prim;
2194 int count; 2241 int count;
2195 2242
2196 LOCK_TEST_WITH_RETURN( dev, filp ); 2243 LOCK_TEST_WITH_RETURN(dev, filp);
2197 2244
2198 if ( !dev_priv ) { 2245 if (!dev_priv) {
2199 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2246 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2200 return DRM_ERR(EINVAL); 2247 return DRM_ERR(EINVAL);
2201 } 2248 }
2202 2249
2203 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 2250 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2204 2251
2205 DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t __user *)data, 2252 DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data,
2206 sizeof(elts) ); 2253 sizeof(elts));
2207 2254
2208 DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n", 2255 DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
2209 DRM_CURRENTPID, 2256 DRM_CURRENTPID, elts.idx, elts.start, elts.end, elts.discard);
2210 elts.idx, elts.start, elts.end, elts.discard );
2211 2257
2212 if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { 2258 if (elts.idx < 0 || elts.idx >= dma->buf_count) {
2213 DRM_ERROR( "buffer index %d (of %d max)\n", 2259 DRM_ERROR("buffer index %d (of %d max)\n",
2214 elts.idx, dma->buf_count - 1 ); 2260 elts.idx, dma->buf_count - 1);
2215 return DRM_ERR(EINVAL); 2261 return DRM_ERR(EINVAL);
2216 } 2262 }
2217 if ( elts.prim < 0 || 2263 if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2218 elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { 2264 DRM_ERROR("buffer prim %d\n", elts.prim);
2219 DRM_ERROR( "buffer prim %d\n", elts.prim );
2220 return DRM_ERR(EINVAL); 2265 return DRM_ERR(EINVAL);
2221 } 2266 }
2222 2267
2223 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2268 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2224 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2269 VB_AGE_TEST_WITH_RETURN(dev_priv);
2225 2270
2226 buf = dma->buflist[elts.idx]; 2271 buf = dma->buflist[elts.idx];
2227 2272
2228 if ( buf->filp != filp ) { 2273 if (buf->filp != filp) {
2229 DRM_ERROR( "process %d using buffer owned by %p\n", 2274 DRM_ERROR("process %d using buffer owned by %p\n",
2230 DRM_CURRENTPID, buf->filp ); 2275 DRM_CURRENTPID, buf->filp);
2231 return DRM_ERR(EINVAL); 2276 return DRM_ERR(EINVAL);
2232 } 2277 }
2233 if ( buf->pending ) { 2278 if (buf->pending) {
2234 DRM_ERROR( "sending pending buffer %d\n", elts.idx ); 2279 DRM_ERROR("sending pending buffer %d\n", elts.idx);
2235 return DRM_ERR(EINVAL); 2280 return DRM_ERR(EINVAL);
2236 } 2281 }
2237 2282
2238 count = (elts.end - elts.start) / sizeof(u16); 2283 count = (elts.end - elts.start) / sizeof(u16);
2239 elts.start -= RADEON_INDEX_PRIM_OFFSET; 2284 elts.start -= RADEON_INDEX_PRIM_OFFSET;
2240 2285
2241 if ( elts.start & 0x7 ) { 2286 if (elts.start & 0x7) {
2242 DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); 2287 DRM_ERROR("misaligned buffer 0x%x\n", elts.start);
2243 return DRM_ERR(EINVAL); 2288 return DRM_ERR(EINVAL);
2244 } 2289 }
2245 if ( elts.start < buf->used ) { 2290 if (elts.start < buf->used) {
2246 DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); 2291 DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used);
2247 return DRM_ERR(EINVAL); 2292 return DRM_ERR(EINVAL);
2248 } 2293 }
2249 2294
2250 buf->used = elts.end; 2295 buf->used = elts.end;
2251 2296
2252 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { 2297 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2253 if ( radeon_emit_state( dev_priv, filp_priv, 2298 if (radeon_emit_state(dev_priv, filp_priv,
2254 &sarea_priv->context_state, 2299 &sarea_priv->context_state,
2255 sarea_priv->tex_state, 2300 sarea_priv->tex_state,
2256 sarea_priv->dirty ) ) { 2301 sarea_priv->dirty)) {
2257 DRM_ERROR( "radeon_emit_state failed\n" ); 2302 DRM_ERROR("radeon_emit_state failed\n");
2258 return DRM_ERR( EINVAL ); 2303 return DRM_ERR(EINVAL);
2259 } 2304 }
2260 2305
2261 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | 2306 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
@@ -2264,26 +2309,25 @@ static int radeon_cp_indices( DRM_IOCTL_ARGS )
2264 RADEON_REQUIRE_QUIESCENCE); 2309 RADEON_REQUIRE_QUIESCENCE);
2265 } 2310 }
2266 2311
2267
2268 /* Build up a prim_t record: 2312 /* Build up a prim_t record:
2269 */ 2313 */
2270 prim.start = elts.start; 2314 prim.start = elts.start;
2271 prim.finish = elts.end; 2315 prim.finish = elts.end;
2272 prim.prim = elts.prim; 2316 prim.prim = elts.prim;
2273 prim.offset = 0; /* offset from start of dma buffers */ 2317 prim.offset = 0; /* offset from start of dma buffers */
2274 prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ 2318 prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2275 prim.vc_format = dev_priv->sarea_priv->vc_format; 2319 prim.vc_format = dev_priv->sarea_priv->vc_format;
2276 2320
2277 radeon_cp_dispatch_indices( dev, buf, &prim ); 2321 radeon_cp_dispatch_indices(dev, buf, &prim);
2278 if (elts.discard) { 2322 if (elts.discard) {
2279 radeon_cp_discard_buffer( dev, buf ); 2323 radeon_cp_discard_buffer(dev, buf);
2280 } 2324 }
2281 2325
2282 COMMIT_RING(); 2326 COMMIT_RING();
2283 return 0; 2327 return 0;
2284} 2328}
2285 2329
2286static int radeon_cp_texture( DRM_IOCTL_ARGS ) 2330static int radeon_cp_texture(DRM_IOCTL_ARGS)
2287{ 2331{
2288 DRM_DEVICE; 2332 DRM_DEVICE;
2289 drm_radeon_private_t *dev_priv = dev->dev_private; 2333 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2291,53 +2335,54 @@ static int radeon_cp_texture( DRM_IOCTL_ARGS )
2291 drm_radeon_tex_image_t image; 2335 drm_radeon_tex_image_t image;
2292 int ret; 2336 int ret;
2293 2337
2294 LOCK_TEST_WITH_RETURN( dev, filp ); 2338 LOCK_TEST_WITH_RETURN(dev, filp);
2295 2339
2296 DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t __user *)data, sizeof(tex) ); 2340 DRM_COPY_FROM_USER_IOCTL(tex, (drm_radeon_texture_t __user *) data,
2341 sizeof(tex));
2297 2342
2298 if ( tex.image == NULL ) { 2343 if (tex.image == NULL) {
2299 DRM_ERROR( "null texture image!\n" ); 2344 DRM_ERROR("null texture image!\n");
2300 return DRM_ERR(EINVAL); 2345 return DRM_ERR(EINVAL);
2301 } 2346 }
2302 2347
2303 if ( DRM_COPY_FROM_USER( &image, 2348 if (DRM_COPY_FROM_USER(&image,
2304 (drm_radeon_tex_image_t __user *)tex.image, 2349 (drm_radeon_tex_image_t __user *) tex.image,
2305 sizeof(image) ) ) 2350 sizeof(image)))
2306 return DRM_ERR(EFAULT); 2351 return DRM_ERR(EFAULT);
2307 2352
2308 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2353 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2309 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2354 VB_AGE_TEST_WITH_RETURN(dev_priv);
2310 2355
2311 ret = radeon_cp_dispatch_texture( filp, dev, &tex, &image ); 2356 ret = radeon_cp_dispatch_texture(filp, dev, &tex, &image);
2312 2357
2313 COMMIT_RING(); 2358 COMMIT_RING();
2314 return ret; 2359 return ret;
2315} 2360}
2316 2361
2317static int radeon_cp_stipple( DRM_IOCTL_ARGS ) 2362static int radeon_cp_stipple(DRM_IOCTL_ARGS)
2318{ 2363{
2319 DRM_DEVICE; 2364 DRM_DEVICE;
2320 drm_radeon_private_t *dev_priv = dev->dev_private; 2365 drm_radeon_private_t *dev_priv = dev->dev_private;
2321 drm_radeon_stipple_t stipple; 2366 drm_radeon_stipple_t stipple;
2322 u32 mask[32]; 2367 u32 mask[32];
2323 2368
2324 LOCK_TEST_WITH_RETURN( dev, filp ); 2369 LOCK_TEST_WITH_RETURN(dev, filp);
2325 2370
2326 DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t __user *)data, 2371 DRM_COPY_FROM_USER_IOCTL(stipple, (drm_radeon_stipple_t __user *) data,
2327 sizeof(stipple) ); 2372 sizeof(stipple));
2328 2373
2329 if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) ) 2374 if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32)))
2330 return DRM_ERR(EFAULT); 2375 return DRM_ERR(EFAULT);
2331 2376
2332 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2377 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2333 2378
2334 radeon_cp_dispatch_stipple( dev, mask ); 2379 radeon_cp_dispatch_stipple(dev, mask);
2335 2380
2336 COMMIT_RING(); 2381 COMMIT_RING();
2337 return 0; 2382 return 0;
2338} 2383}
2339 2384
2340static int radeon_cp_indirect( DRM_IOCTL_ARGS ) 2385static int radeon_cp_indirect(DRM_IOCTL_ARGS)
2341{ 2386{
2342 DRM_DEVICE; 2387 DRM_DEVICE;
2343 drm_radeon_private_t *dev_priv = dev->dev_private; 2388 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2346,53 +2391,53 @@ static int radeon_cp_indirect( DRM_IOCTL_ARGS )
2346 drm_radeon_indirect_t indirect; 2391 drm_radeon_indirect_t indirect;
2347 RING_LOCALS; 2392 RING_LOCALS;
2348 2393
2349 LOCK_TEST_WITH_RETURN( dev, filp ); 2394 LOCK_TEST_WITH_RETURN(dev, filp);
2350 2395
2351 if ( !dev_priv ) { 2396 if (!dev_priv) {
2352 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2397 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2353 return DRM_ERR(EINVAL); 2398 return DRM_ERR(EINVAL);
2354 } 2399 }
2355 2400
2356 DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t __user *)data, 2401 DRM_COPY_FROM_USER_IOCTL(indirect,
2357 sizeof(indirect) ); 2402 (drm_radeon_indirect_t __user *) data,
2403 sizeof(indirect));
2358 2404
2359 DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", 2405 DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n",
2360 indirect.idx, indirect.start, 2406 indirect.idx, indirect.start, indirect.end, indirect.discard);
2361 indirect.end, indirect.discard );
2362 2407
2363 if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { 2408 if (indirect.idx < 0 || indirect.idx >= dma->buf_count) {
2364 DRM_ERROR( "buffer index %d (of %d max)\n", 2409 DRM_ERROR("buffer index %d (of %d max)\n",
2365 indirect.idx, dma->buf_count - 1 ); 2410 indirect.idx, dma->buf_count - 1);
2366 return DRM_ERR(EINVAL); 2411 return DRM_ERR(EINVAL);
2367 } 2412 }
2368 2413
2369 buf = dma->buflist[indirect.idx]; 2414 buf = dma->buflist[indirect.idx];
2370 2415
2371 if ( buf->filp != filp ) { 2416 if (buf->filp != filp) {
2372 DRM_ERROR( "process %d using buffer owned by %p\n", 2417 DRM_ERROR("process %d using buffer owned by %p\n",
2373 DRM_CURRENTPID, buf->filp ); 2418 DRM_CURRENTPID, buf->filp);
2374 return DRM_ERR(EINVAL); 2419 return DRM_ERR(EINVAL);
2375 } 2420 }
2376 if ( buf->pending ) { 2421 if (buf->pending) {
2377 DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); 2422 DRM_ERROR("sending pending buffer %d\n", indirect.idx);
2378 return DRM_ERR(EINVAL); 2423 return DRM_ERR(EINVAL);
2379 } 2424 }
2380 2425
2381 if ( indirect.start < buf->used ) { 2426 if (indirect.start < buf->used) {
2382 DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", 2427 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
2383 indirect.start, buf->used ); 2428 indirect.start, buf->used);
2384 return DRM_ERR(EINVAL); 2429 return DRM_ERR(EINVAL);
2385 } 2430 }
2386 2431
2387 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2432 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2388 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2433 VB_AGE_TEST_WITH_RETURN(dev_priv);
2389 2434
2390 buf->used = indirect.end; 2435 buf->used = indirect.end;
2391 2436
2392 /* Wait for the 3D stream to idle before the indirect buffer 2437 /* Wait for the 3D stream to idle before the indirect buffer
2393 * containing 2D acceleration commands is processed. 2438 * containing 2D acceleration commands is processed.
2394 */ 2439 */
2395 BEGIN_RING( 2 ); 2440 BEGIN_RING(2);
2396 2441
2397 RADEON_WAIT_UNTIL_3D_IDLE(); 2442 RADEON_WAIT_UNTIL_3D_IDLE();
2398 2443
@@ -2402,17 +2447,16 @@ static int radeon_cp_indirect( DRM_IOCTL_ARGS )
2402 * X server. This is insecure and is thus only available to 2447 * X server. This is insecure and is thus only available to
2403 * privileged clients. 2448 * privileged clients.
2404 */ 2449 */
2405 radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end ); 2450 radeon_cp_dispatch_indirect(dev, buf, indirect.start, indirect.end);
2406 if (indirect.discard) { 2451 if (indirect.discard) {
2407 radeon_cp_discard_buffer( dev, buf ); 2452 radeon_cp_discard_buffer(dev, buf);
2408 } 2453 }
2409 2454
2410
2411 COMMIT_RING(); 2455 COMMIT_RING();
2412 return 0; 2456 return 0;
2413} 2457}
2414 2458
2415static int radeon_cp_vertex2( DRM_IOCTL_ARGS ) 2459static int radeon_cp_vertex2(DRM_IOCTL_ARGS)
2416{ 2460{
2417 DRM_DEVICE; 2461 DRM_DEVICE;
2418 drm_radeon_private_t *dev_priv = dev->dev_private; 2462 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2424,65 +2468,64 @@ static int radeon_cp_vertex2( DRM_IOCTL_ARGS )
2424 int i; 2468 int i;
2425 unsigned char laststate; 2469 unsigned char laststate;
2426 2470
2427 LOCK_TEST_WITH_RETURN( dev, filp ); 2471 LOCK_TEST_WITH_RETURN(dev, filp);
2428 2472
2429 if ( !dev_priv ) { 2473 if (!dev_priv) {
2430 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2474 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2431 return DRM_ERR(EINVAL); 2475 return DRM_ERR(EINVAL);
2432 } 2476 }
2433 2477
2434 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 2478 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2435 2479
2436 DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t __user *)data, 2480 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data,
2437 sizeof(vertex) ); 2481 sizeof(vertex));
2438 2482
2439 DRM_DEBUG( "pid=%d index=%d discard=%d\n", 2483 DRM_DEBUG("pid=%d index=%d discard=%d\n",
2440 DRM_CURRENTPID, 2484 DRM_CURRENTPID, vertex.idx, vertex.discard);
2441 vertex.idx, vertex.discard );
2442 2485
2443 if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { 2486 if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
2444 DRM_ERROR( "buffer index %d (of %d max)\n", 2487 DRM_ERROR("buffer index %d (of %d max)\n",
2445 vertex.idx, dma->buf_count - 1 ); 2488 vertex.idx, dma->buf_count - 1);
2446 return DRM_ERR(EINVAL); 2489 return DRM_ERR(EINVAL);
2447 } 2490 }
2448 2491
2449 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2492 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2450 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2493 VB_AGE_TEST_WITH_RETURN(dev_priv);
2451 2494
2452 buf = dma->buflist[vertex.idx]; 2495 buf = dma->buflist[vertex.idx];
2453 2496
2454 if ( buf->filp != filp ) { 2497 if (buf->filp != filp) {
2455 DRM_ERROR( "process %d using buffer owned by %p\n", 2498 DRM_ERROR("process %d using buffer owned by %p\n",
2456 DRM_CURRENTPID, buf->filp ); 2499 DRM_CURRENTPID, buf->filp);
2457 return DRM_ERR(EINVAL); 2500 return DRM_ERR(EINVAL);
2458 } 2501 }
2459 2502
2460 if ( buf->pending ) { 2503 if (buf->pending) {
2461 DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); 2504 DRM_ERROR("sending pending buffer %d\n", vertex.idx);
2462 return DRM_ERR(EINVAL); 2505 return DRM_ERR(EINVAL);
2463 } 2506 }
2464 2507
2465 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) 2508 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2466 return DRM_ERR(EINVAL); 2509 return DRM_ERR(EINVAL);
2467 2510
2468 for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) { 2511 for (laststate = 0xff, i = 0; i < vertex.nr_prims; i++) {
2469 drm_radeon_prim_t prim; 2512 drm_radeon_prim_t prim;
2470 drm_radeon_tcl_prim_t tclprim; 2513 drm_radeon_tcl_prim_t tclprim;
2471 2514
2472 if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) ) 2515 if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof(prim)))
2473 return DRM_ERR(EFAULT); 2516 return DRM_ERR(EFAULT);
2474 2517
2475 if ( prim.stateidx != laststate ) { 2518 if (prim.stateidx != laststate) {
2476 drm_radeon_state_t state; 2519 drm_radeon_state_t state;
2477 2520
2478 if ( DRM_COPY_FROM_USER( &state, 2521 if (DRM_COPY_FROM_USER(&state,
2479 &vertex.state[prim.stateidx], 2522 &vertex.state[prim.stateidx],
2480 sizeof(state) ) ) 2523 sizeof(state)))
2481 return DRM_ERR(EFAULT); 2524 return DRM_ERR(EFAULT);
2482 2525
2483 if ( radeon_emit_state2( dev_priv, filp_priv, &state ) ) { 2526 if (radeon_emit_state2(dev_priv, filp_priv, &state)) {
2484 DRM_ERROR( "radeon_emit_state2 failed\n" ); 2527 DRM_ERROR("radeon_emit_state2 failed\n");
2485 return DRM_ERR( EINVAL ); 2528 return DRM_ERR(EINVAL);
2486 } 2529 }
2487 2530
2488 laststate = prim.stateidx; 2531 laststate = prim.stateidx;
@@ -2493,42 +2536,40 @@ static int radeon_cp_vertex2( DRM_IOCTL_ARGS )
2493 tclprim.prim = prim.prim; 2536 tclprim.prim = prim.prim;
2494 tclprim.vc_format = prim.vc_format; 2537 tclprim.vc_format = prim.vc_format;
2495 2538
2496 if ( prim.prim & RADEON_PRIM_WALK_IND ) { 2539 if (prim.prim & RADEON_PRIM_WALK_IND) {
2497 tclprim.offset = prim.numverts * 64; 2540 tclprim.offset = prim.numverts * 64;
2498 tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ 2541 tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2499 2542
2500 radeon_cp_dispatch_indices( dev, buf, &tclprim ); 2543 radeon_cp_dispatch_indices(dev, buf, &tclprim);
2501 } else { 2544 } else {
2502 tclprim.numverts = prim.numverts; 2545 tclprim.numverts = prim.numverts;
2503 tclprim.offset = 0; /* not used */ 2546 tclprim.offset = 0; /* not used */
2504 2547
2505 radeon_cp_dispatch_vertex( dev, buf, &tclprim ); 2548 radeon_cp_dispatch_vertex(dev, buf, &tclprim);
2506 } 2549 }
2507 2550
2508 if (sarea_priv->nbox == 1) 2551 if (sarea_priv->nbox == 1)
2509 sarea_priv->nbox = 0; 2552 sarea_priv->nbox = 0;
2510 } 2553 }
2511 2554
2512 if ( vertex.discard ) { 2555 if (vertex.discard) {
2513 radeon_cp_discard_buffer( dev, buf ); 2556 radeon_cp_discard_buffer(dev, buf);
2514 } 2557 }
2515 2558
2516 COMMIT_RING(); 2559 COMMIT_RING();
2517 return 0; 2560 return 0;
2518} 2561}
2519 2562
2520 2563static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
2521static int radeon_emit_packets( 2564 drm_file_t * filp_priv,
2522 drm_radeon_private_t *dev_priv, 2565 drm_radeon_cmd_header_t header,
2523 drm_file_t *filp_priv, 2566 drm_radeon_kcmd_buffer_t *cmdbuf)
2524 drm_radeon_cmd_header_t header,
2525 drm_radeon_cmd_buffer_t *cmdbuf )
2526{ 2567{
2527 int id = (int)header.packet.packet_id; 2568 int id = (int)header.packet.packet_id;
2528 int sz, reg; 2569 int sz, reg;
2529 int *data = (int *)cmdbuf->buf; 2570 int *data = (int *)cmdbuf->buf;
2530 RING_LOCALS; 2571 RING_LOCALS;
2531 2572
2532 if (id >= RADEON_MAX_STATE_PACKETS) 2573 if (id >= RADEON_MAX_STATE_PACKETS)
2533 return DRM_ERR(EINVAL); 2574 return DRM_ERR(EINVAL);
2534 2575
@@ -2536,18 +2577,18 @@ static int radeon_emit_packets(
2536 reg = packet[id].start; 2577 reg = packet[id].start;
2537 2578
2538 if (sz * sizeof(int) > cmdbuf->bufsz) { 2579 if (sz * sizeof(int) > cmdbuf->bufsz) {
2539 DRM_ERROR( "Packet size provided larger than data provided\n" ); 2580 DRM_ERROR("Packet size provided larger than data provided\n");
2540 return DRM_ERR(EINVAL); 2581 return DRM_ERR(EINVAL);
2541 } 2582 }
2542 2583
2543 if ( radeon_check_and_fixup_packets( dev_priv, filp_priv, id, data ) ) { 2584 if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) {
2544 DRM_ERROR( "Packet verification failed\n" ); 2585 DRM_ERROR("Packet verification failed\n");
2545 return DRM_ERR( EINVAL ); 2586 return DRM_ERR(EINVAL);
2546 } 2587 }
2547 2588
2548 BEGIN_RING(sz+1); 2589 BEGIN_RING(sz + 1);
2549 OUT_RING( CP_PACKET0( reg, (sz-1) ) ); 2590 OUT_RING(CP_PACKET0(reg, (sz - 1)));
2550 OUT_RING_TABLE( data, sz ); 2591 OUT_RING_TABLE(data, sz);
2551 ADVANCE_RING(); 2592 ADVANCE_RING();
2552 2593
2553 cmdbuf->buf += sz * sizeof(int); 2594 cmdbuf->buf += sz * sizeof(int);
@@ -2555,21 +2596,20 @@ static int radeon_emit_packets(
2555 return 0; 2596 return 0;
2556} 2597}
2557 2598
2558static __inline__ int radeon_emit_scalars( 2599static __inline__ int radeon_emit_scalars(drm_radeon_private_t * dev_priv,
2559 drm_radeon_private_t *dev_priv, 2600 drm_radeon_cmd_header_t header,
2560 drm_radeon_cmd_header_t header, 2601 drm_radeon_kcmd_buffer_t * cmdbuf)
2561 drm_radeon_cmd_buffer_t *cmdbuf )
2562{ 2602{
2563 int sz = header.scalars.count; 2603 int sz = header.scalars.count;
2564 int start = header.scalars.offset; 2604 int start = header.scalars.offset;
2565 int stride = header.scalars.stride; 2605 int stride = header.scalars.stride;
2566 RING_LOCALS; 2606 RING_LOCALS;
2567 2607
2568 BEGIN_RING( 3+sz ); 2608 BEGIN_RING(3 + sz);
2569 OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); 2609 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2570 OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); 2610 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2571 OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); 2611 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2572 OUT_RING_TABLE( cmdbuf->buf, sz ); 2612 OUT_RING_TABLE(cmdbuf->buf, sz);
2573 ADVANCE_RING(); 2613 ADVANCE_RING();
2574 cmdbuf->buf += sz * sizeof(int); 2614 cmdbuf->buf += sz * sizeof(int);
2575 cmdbuf->bufsz -= sz * sizeof(int); 2615 cmdbuf->bufsz -= sz * sizeof(int);
@@ -2578,42 +2618,40 @@ static __inline__ int radeon_emit_scalars(
2578 2618
2579/* God this is ugly 2619/* God this is ugly
2580 */ 2620 */
2581static __inline__ int radeon_emit_scalars2( 2621static __inline__ int radeon_emit_scalars2(drm_radeon_private_t * dev_priv,
2582 drm_radeon_private_t *dev_priv, 2622 drm_radeon_cmd_header_t header,
2583 drm_radeon_cmd_header_t header, 2623 drm_radeon_kcmd_buffer_t * cmdbuf)
2584 drm_radeon_cmd_buffer_t *cmdbuf )
2585{ 2624{
2586 int sz = header.scalars.count; 2625 int sz = header.scalars.count;
2587 int start = ((unsigned int)header.scalars.offset) + 0x100; 2626 int start = ((unsigned int)header.scalars.offset) + 0x100;
2588 int stride = header.scalars.stride; 2627 int stride = header.scalars.stride;
2589 RING_LOCALS; 2628 RING_LOCALS;
2590 2629
2591 BEGIN_RING( 3+sz ); 2630 BEGIN_RING(3 + sz);
2592 OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); 2631 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2593 OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); 2632 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2594 OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); 2633 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2595 OUT_RING_TABLE( cmdbuf->buf, sz ); 2634 OUT_RING_TABLE(cmdbuf->buf, sz);
2596 ADVANCE_RING(); 2635 ADVANCE_RING();
2597 cmdbuf->buf += sz * sizeof(int); 2636 cmdbuf->buf += sz * sizeof(int);
2598 cmdbuf->bufsz -= sz * sizeof(int); 2637 cmdbuf->bufsz -= sz * sizeof(int);
2599 return 0; 2638 return 0;
2600} 2639}
2601 2640
2602static __inline__ int radeon_emit_vectors( 2641static __inline__ int radeon_emit_vectors(drm_radeon_private_t * dev_priv,
2603 drm_radeon_private_t *dev_priv, 2642 drm_radeon_cmd_header_t header,
2604 drm_radeon_cmd_header_t header, 2643 drm_radeon_kcmd_buffer_t * cmdbuf)
2605 drm_radeon_cmd_buffer_t *cmdbuf )
2606{ 2644{
2607 int sz = header.vectors.count; 2645 int sz = header.vectors.count;
2608 int start = header.vectors.offset; 2646 int start = header.vectors.offset;
2609 int stride = header.vectors.stride; 2647 int stride = header.vectors.stride;
2610 RING_LOCALS; 2648 RING_LOCALS;
2611 2649
2612 BEGIN_RING( 3+sz ); 2650 BEGIN_RING(3 + sz);
2613 OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) ); 2651 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2614 OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); 2652 OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2615 OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) ); 2653 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
2616 OUT_RING_TABLE( cmdbuf->buf, sz ); 2654 OUT_RING_TABLE(cmdbuf->buf, sz);
2617 ADVANCE_RING(); 2655 ADVANCE_RING();
2618 2656
2619 cmdbuf->buf += sz * sizeof(int); 2657 cmdbuf->buf += sz * sizeof(int);
@@ -2621,10 +2659,9 @@ static __inline__ int radeon_emit_vectors(
2621 return 0; 2659 return 0;
2622} 2660}
2623 2661
2624 2662static int radeon_emit_packet3(drm_device_t * dev,
2625static int radeon_emit_packet3( drm_device_t *dev, 2663 drm_file_t * filp_priv,
2626 drm_file_t *filp_priv, 2664 drm_radeon_kcmd_buffer_t *cmdbuf)
2627 drm_radeon_cmd_buffer_t *cmdbuf )
2628{ 2665{
2629 drm_radeon_private_t *dev_priv = dev->dev_private; 2666 drm_radeon_private_t *dev_priv = dev->dev_private;
2630 unsigned int cmdsz; 2667 unsigned int cmdsz;
@@ -2633,14 +2670,14 @@ static int radeon_emit_packet3( drm_device_t *dev,
2633 2670
2634 DRM_DEBUG("\n"); 2671 DRM_DEBUG("\n");
2635 2672
2636 if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, 2673 if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv,
2637 cmdbuf, &cmdsz ) ) ) { 2674 cmdbuf, &cmdsz))) {
2638 DRM_ERROR( "Packet verification failed\n" ); 2675 DRM_ERROR("Packet verification failed\n");
2639 return ret; 2676 return ret;
2640 } 2677 }
2641 2678
2642 BEGIN_RING( cmdsz ); 2679 BEGIN_RING(cmdsz);
2643 OUT_RING_TABLE( cmdbuf->buf, cmdsz ); 2680 OUT_RING_TABLE(cmdbuf->buf, cmdsz);
2644 ADVANCE_RING(); 2681 ADVANCE_RING();
2645 2682
2646 cmdbuf->buf += cmdsz * 4; 2683 cmdbuf->buf += cmdsz * 4;
@@ -2648,11 +2685,10 @@ static int radeon_emit_packet3( drm_device_t *dev,
2648 return 0; 2685 return 0;
2649} 2686}
2650 2687
2651 2688static int radeon_emit_packet3_cliprect(drm_device_t * dev,
2652static int radeon_emit_packet3_cliprect( drm_device_t *dev, 2689 drm_file_t * filp_priv,
2653 drm_file_t *filp_priv, 2690 drm_radeon_kcmd_buffer_t *cmdbuf,
2654 drm_radeon_cmd_buffer_t *cmdbuf, 2691 int orig_nbox)
2655 int orig_nbox )
2656{ 2692{
2657 drm_radeon_private_t *dev_priv = dev->dev_private; 2693 drm_radeon_private_t *dev_priv = dev->dev_private;
2658 drm_clip_rect_t box; 2694 drm_clip_rect_t box;
@@ -2664,9 +2700,9 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
2664 2700
2665 DRM_DEBUG("\n"); 2701 DRM_DEBUG("\n");
2666 2702
2667 if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, 2703 if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv,
2668 cmdbuf, &cmdsz ) ) ) { 2704 cmdbuf, &cmdsz))) {
2669 DRM_ERROR( "Packet verification failed\n" ); 2705 DRM_ERROR("Packet verification failed\n");
2670 return ret; 2706 return ret;
2671 } 2707 }
2672 2708
@@ -2674,8 +2710,8 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
2674 goto out; 2710 goto out;
2675 2711
2676 do { 2712 do {
2677 if ( i < cmdbuf->nbox ) { 2713 if (i < cmdbuf->nbox) {
2678 if (DRM_COPY_FROM_USER( &box, &boxes[i], sizeof(box) )) 2714 if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box)))
2679 return DRM_ERR(EFAULT); 2715 return DRM_ERR(EFAULT);
2680 /* FIXME The second and subsequent times round 2716 /* FIXME The second and subsequent times round
2681 * this loop, send a WAIT_UNTIL_3D_IDLE before 2717 * this loop, send a WAIT_UNTIL_3D_IDLE before
@@ -2689,30 +2725,29 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
2689 * the correct place to fix it but this works 2725 * the correct place to fix it but this works
2690 * around it until I can figure that out - Tim 2726 * around it until I can figure that out - Tim
2691 * Smith */ 2727 * Smith */
2692 if ( i ) { 2728 if (i) {
2693 BEGIN_RING( 2 ); 2729 BEGIN_RING(2);
2694 RADEON_WAIT_UNTIL_3D_IDLE(); 2730 RADEON_WAIT_UNTIL_3D_IDLE();
2695 ADVANCE_RING(); 2731 ADVANCE_RING();
2696 } 2732 }
2697 radeon_emit_clip_rect( dev_priv, &box ); 2733 radeon_emit_clip_rect(dev_priv, &box);
2698 } 2734 }
2699 2735
2700 BEGIN_RING( cmdsz ); 2736 BEGIN_RING(cmdsz);
2701 OUT_RING_TABLE( cmdbuf->buf, cmdsz ); 2737 OUT_RING_TABLE(cmdbuf->buf, cmdsz);
2702 ADVANCE_RING(); 2738 ADVANCE_RING();
2703 2739
2704 } while ( ++i < cmdbuf->nbox ); 2740 } while (++i < cmdbuf->nbox);
2705 if (cmdbuf->nbox == 1) 2741 if (cmdbuf->nbox == 1)
2706 cmdbuf->nbox = 0; 2742 cmdbuf->nbox = 0;
2707 2743
2708 out: 2744 out:
2709 cmdbuf->buf += cmdsz * 4; 2745 cmdbuf->buf += cmdsz * 4;
2710 cmdbuf->bufsz -= cmdsz * 4; 2746 cmdbuf->bufsz -= cmdsz * 4;
2711 return 0; 2747 return 0;
2712} 2748}
2713 2749
2714 2750static int radeon_emit_wait(drm_device_t * dev, int flags)
2715static int radeon_emit_wait( drm_device_t *dev, int flags )
2716{ 2751{
2717 drm_radeon_private_t *dev_priv = dev->dev_private; 2752 drm_radeon_private_t *dev_priv = dev->dev_private;
2718 RING_LOCALS; 2753 RING_LOCALS;
@@ -2720,18 +2755,18 @@ static int radeon_emit_wait( drm_device_t *dev, int flags )
2720 DRM_DEBUG("%s: %x\n", __FUNCTION__, flags); 2755 DRM_DEBUG("%s: %x\n", __FUNCTION__, flags);
2721 switch (flags) { 2756 switch (flags) {
2722 case RADEON_WAIT_2D: 2757 case RADEON_WAIT_2D:
2723 BEGIN_RING( 2 ); 2758 BEGIN_RING(2);
2724 RADEON_WAIT_UNTIL_2D_IDLE(); 2759 RADEON_WAIT_UNTIL_2D_IDLE();
2725 ADVANCE_RING(); 2760 ADVANCE_RING();
2726 break; 2761 break;
2727 case RADEON_WAIT_3D: 2762 case RADEON_WAIT_3D:
2728 BEGIN_RING( 2 ); 2763 BEGIN_RING(2);
2729 RADEON_WAIT_UNTIL_3D_IDLE(); 2764 RADEON_WAIT_UNTIL_3D_IDLE();
2730 ADVANCE_RING(); 2765 ADVANCE_RING();
2731 break; 2766 break;
2732 case RADEON_WAIT_2D|RADEON_WAIT_3D: 2767 case RADEON_WAIT_2D | RADEON_WAIT_3D:
2733 BEGIN_RING( 2 ); 2768 BEGIN_RING(2);
2734 RADEON_WAIT_UNTIL_IDLE(); 2769 RADEON_WAIT_UNTIL_IDLE();
2735 ADVANCE_RING(); 2770 ADVANCE_RING();
2736 break; 2771 break;
2737 default: 2772 default:
@@ -2741,7 +2776,7 @@ static int radeon_emit_wait( drm_device_t *dev, int flags )
2741 return 0; 2776 return 0;
2742} 2777}
2743 2778
2744static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) 2779static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2745{ 2780{
2746 DRM_DEVICE; 2781 DRM_DEVICE;
2747 drm_radeon_private_t *dev_priv = dev->dev_private; 2782 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2749,27 +2784,28 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2749 drm_device_dma_t *dma = dev->dma; 2784 drm_device_dma_t *dma = dev->dma;
2750 drm_buf_t *buf = NULL; 2785 drm_buf_t *buf = NULL;
2751 int idx; 2786 int idx;
2752 drm_radeon_cmd_buffer_t cmdbuf; 2787 drm_radeon_kcmd_buffer_t cmdbuf;
2753 drm_radeon_cmd_header_t header; 2788 drm_radeon_cmd_header_t header;
2754 int orig_nbox, orig_bufsz; 2789 int orig_nbox, orig_bufsz;
2755 char *kbuf=NULL; 2790 char *kbuf = NULL;
2756 2791
2757 LOCK_TEST_WITH_RETURN( dev, filp ); 2792 LOCK_TEST_WITH_RETURN(dev, filp);
2758 2793
2759 if ( !dev_priv ) { 2794 if (!dev_priv) {
2760 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2795 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2761 return DRM_ERR(EINVAL); 2796 return DRM_ERR(EINVAL);
2762 } 2797 }
2763 2798
2764 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 2799 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2765 2800
2766 DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t __user *)data, 2801 DRM_COPY_FROM_USER_IOCTL(cmdbuf,
2767 sizeof(cmdbuf) ); 2802 (drm_radeon_cmd_buffer_t __user *) data,
2803 sizeof(cmdbuf));
2768 2804
2769 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2805 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2770 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2806 VB_AGE_TEST_WITH_RETURN(dev_priv);
2771 2807
2772 if (cmdbuf.bufsz > 64*1024 || cmdbuf.bufsz<0) { 2808 if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) {
2773 return DRM_ERR(EINVAL); 2809 return DRM_ERR(EINVAL);
2774 } 2810 }
2775 2811
@@ -2782,7 +2818,7 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2782 kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER); 2818 kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER);
2783 if (kbuf == NULL) 2819 if (kbuf == NULL)
2784 return DRM_ERR(ENOMEM); 2820 return DRM_ERR(ENOMEM);
2785 if (DRM_COPY_FROM_USER(kbuf, cmdbuf.buf, cmdbuf.bufsz)) { 2821 if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf.buf, cmdbuf.bufsz)) {
2786 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); 2822 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2787 return DRM_ERR(EFAULT); 2823 return DRM_ERR(EFAULT);
2788 } 2824 }
@@ -2791,27 +2827,28 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2791 2827
2792 orig_nbox = cmdbuf.nbox; 2828 orig_nbox = cmdbuf.nbox;
2793 2829
2794 if(dev_priv->microcode_version == UCODE_R300) { 2830 if (dev_priv->microcode_version == UCODE_R300) {
2795 int temp; 2831 int temp;
2796 temp=r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf); 2832 temp = r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf);
2797 2833
2798 if (orig_bufsz != 0) 2834 if (orig_bufsz != 0)
2799 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); 2835 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2800 2836
2801 return temp; 2837 return temp;
2802 } 2838 }
2803 2839
2804 /* microcode_version != r300 */ 2840 /* microcode_version != r300 */
2805 while ( cmdbuf.bufsz >= sizeof(header) ) { 2841 while (cmdbuf.bufsz >= sizeof(header)) {
2806 2842
2807 header.i = *(int *)cmdbuf.buf; 2843 header.i = *(int *)cmdbuf.buf;
2808 cmdbuf.buf += sizeof(header); 2844 cmdbuf.buf += sizeof(header);
2809 cmdbuf.bufsz -= sizeof(header); 2845 cmdbuf.bufsz -= sizeof(header);
2810 2846
2811 switch (header.header.cmd_type) { 2847 switch (header.header.cmd_type) {
2812 case RADEON_CMD_PACKET: 2848 case RADEON_CMD_PACKET:
2813 DRM_DEBUG("RADEON_CMD_PACKET\n"); 2849 DRM_DEBUG("RADEON_CMD_PACKET\n");
2814 if (radeon_emit_packets( dev_priv, filp_priv, header, &cmdbuf )) { 2850 if (radeon_emit_packets
2851 (dev_priv, filp_priv, header, &cmdbuf)) {
2815 DRM_ERROR("radeon_emit_packets failed\n"); 2852 DRM_ERROR("radeon_emit_packets failed\n");
2816 goto err; 2853 goto err;
2817 } 2854 }
@@ -2819,7 +2856,7 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2819 2856
2820 case RADEON_CMD_SCALARS: 2857 case RADEON_CMD_SCALARS:
2821 DRM_DEBUG("RADEON_CMD_SCALARS\n"); 2858 DRM_DEBUG("RADEON_CMD_SCALARS\n");
2822 if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) { 2859 if (radeon_emit_scalars(dev_priv, header, &cmdbuf)) {
2823 DRM_ERROR("radeon_emit_scalars failed\n"); 2860 DRM_ERROR("radeon_emit_scalars failed\n");
2824 goto err; 2861 goto err;
2825 } 2862 }
@@ -2827,7 +2864,7 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2827 2864
2828 case RADEON_CMD_VECTORS: 2865 case RADEON_CMD_VECTORS:
2829 DRM_DEBUG("RADEON_CMD_VECTORS\n"); 2866 DRM_DEBUG("RADEON_CMD_VECTORS\n");
2830 if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) { 2867 if (radeon_emit_vectors(dev_priv, header, &cmdbuf)) {
2831 DRM_ERROR("radeon_emit_vectors failed\n"); 2868 DRM_ERROR("radeon_emit_vectors failed\n");
2832 goto err; 2869 goto err;
2833 } 2870 }
@@ -2836,25 +2873,25 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2836 case RADEON_CMD_DMA_DISCARD: 2873 case RADEON_CMD_DMA_DISCARD:
2837 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); 2874 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
2838 idx = header.dma.buf_idx; 2875 idx = header.dma.buf_idx;
2839 if ( idx < 0 || idx >= dma->buf_count ) { 2876 if (idx < 0 || idx >= dma->buf_count) {
2840 DRM_ERROR( "buffer index %d (of %d max)\n", 2877 DRM_ERROR("buffer index %d (of %d max)\n",
2841 idx, dma->buf_count - 1 ); 2878 idx, dma->buf_count - 1);
2842 goto err; 2879 goto err;
2843 } 2880 }
2844 2881
2845 buf = dma->buflist[idx]; 2882 buf = dma->buflist[idx];
2846 if ( buf->filp != filp || buf->pending ) { 2883 if (buf->filp != filp || buf->pending) {
2847 DRM_ERROR( "bad buffer %p %p %d\n", 2884 DRM_ERROR("bad buffer %p %p %d\n",
2848 buf->filp, filp, buf->pending); 2885 buf->filp, filp, buf->pending);
2849 goto err; 2886 goto err;
2850 } 2887 }
2851 2888
2852 radeon_cp_discard_buffer( dev, buf ); 2889 radeon_cp_discard_buffer(dev, buf);
2853 break; 2890 break;
2854 2891
2855 case RADEON_CMD_PACKET3: 2892 case RADEON_CMD_PACKET3:
2856 DRM_DEBUG("RADEON_CMD_PACKET3\n"); 2893 DRM_DEBUG("RADEON_CMD_PACKET3\n");
2857 if (radeon_emit_packet3( dev, filp_priv, &cmdbuf )) { 2894 if (radeon_emit_packet3(dev, filp_priv, &cmdbuf)) {
2858 DRM_ERROR("radeon_emit_packet3 failed\n"); 2895 DRM_ERROR("radeon_emit_packet3 failed\n");
2859 goto err; 2896 goto err;
2860 } 2897 }
@@ -2862,7 +2899,8 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2862 2899
2863 case RADEON_CMD_PACKET3_CLIP: 2900 case RADEON_CMD_PACKET3_CLIP:
2864 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); 2901 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
2865 if (radeon_emit_packet3_cliprect( dev, filp_priv, &cmdbuf, orig_nbox )) { 2902 if (radeon_emit_packet3_cliprect
2903 (dev, filp_priv, &cmdbuf, orig_nbox)) {
2866 DRM_ERROR("radeon_emit_packet3_clip failed\n"); 2904 DRM_ERROR("radeon_emit_packet3_clip failed\n");
2867 goto err; 2905 goto err;
2868 } 2906 }
@@ -2870,7 +2908,7 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2870 2908
2871 case RADEON_CMD_SCALARS2: 2909 case RADEON_CMD_SCALARS2:
2872 DRM_DEBUG("RADEON_CMD_SCALARS2\n"); 2910 DRM_DEBUG("RADEON_CMD_SCALARS2\n");
2873 if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) { 2911 if (radeon_emit_scalars2(dev_priv, header, &cmdbuf)) {
2874 DRM_ERROR("radeon_emit_scalars2 failed\n"); 2912 DRM_ERROR("radeon_emit_scalars2 failed\n");
2875 goto err; 2913 goto err;
2876 } 2914 }
@@ -2878,13 +2916,13 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2878 2916
2879 case RADEON_CMD_WAIT: 2917 case RADEON_CMD_WAIT:
2880 DRM_DEBUG("RADEON_CMD_WAIT\n"); 2918 DRM_DEBUG("RADEON_CMD_WAIT\n");
2881 if (radeon_emit_wait( dev, header.wait.flags )) { 2919 if (radeon_emit_wait(dev, header.wait.flags)) {
2882 DRM_ERROR("radeon_emit_wait failed\n"); 2920 DRM_ERROR("radeon_emit_wait failed\n");
2883 goto err; 2921 goto err;
2884 } 2922 }
2885 break; 2923 break;
2886 default: 2924 default:
2887 DRM_ERROR("bad cmd_type %d at %p\n", 2925 DRM_ERROR("bad cmd_type %d at %p\n",
2888 header.header.cmd_type, 2926 header.header.cmd_type,
2889 cmdbuf.buf - sizeof(header)); 2927 cmdbuf.buf - sizeof(header));
2890 goto err; 2928 goto err;
@@ -2898,45 +2936,43 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2898 COMMIT_RING(); 2936 COMMIT_RING();
2899 return 0; 2937 return 0;
2900 2938
2901err: 2939 err:
2902 if (orig_bufsz != 0) 2940 if (orig_bufsz != 0)
2903 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); 2941 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2904 return DRM_ERR(EINVAL); 2942 return DRM_ERR(EINVAL);
2905} 2943}
2906 2944
2907 2945static int radeon_cp_getparam(DRM_IOCTL_ARGS)
2908
2909static int radeon_cp_getparam( DRM_IOCTL_ARGS )
2910{ 2946{
2911 DRM_DEVICE; 2947 DRM_DEVICE;
2912 drm_radeon_private_t *dev_priv = dev->dev_private; 2948 drm_radeon_private_t *dev_priv = dev->dev_private;
2913 drm_radeon_getparam_t param; 2949 drm_radeon_getparam_t param;
2914 int value; 2950 int value;
2915 2951
2916 if ( !dev_priv ) { 2952 if (!dev_priv) {
2917 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2953 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2918 return DRM_ERR(EINVAL); 2954 return DRM_ERR(EINVAL);
2919 } 2955 }
2920 2956
2921 DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t __user *)data, 2957 DRM_COPY_FROM_USER_IOCTL(param, (drm_radeon_getparam_t __user *) data,
2922 sizeof(param) ); 2958 sizeof(param));
2923 2959
2924 DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); 2960 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
2925 2961
2926 switch( param.param ) { 2962 switch (param.param) {
2927 case RADEON_PARAM_GART_BUFFER_OFFSET: 2963 case RADEON_PARAM_GART_BUFFER_OFFSET:
2928 value = dev_priv->gart_buffers_offset; 2964 value = dev_priv->gart_buffers_offset;
2929 break; 2965 break;
2930 case RADEON_PARAM_LAST_FRAME: 2966 case RADEON_PARAM_LAST_FRAME:
2931 dev_priv->stats.last_frame_reads++; 2967 dev_priv->stats.last_frame_reads++;
2932 value = GET_SCRATCH( 0 ); 2968 value = GET_SCRATCH(0);
2933 break; 2969 break;
2934 case RADEON_PARAM_LAST_DISPATCH: 2970 case RADEON_PARAM_LAST_DISPATCH:
2935 value = GET_SCRATCH( 1 ); 2971 value = GET_SCRATCH(1);
2936 break; 2972 break;
2937 case RADEON_PARAM_LAST_CLEAR: 2973 case RADEON_PARAM_LAST_CLEAR:
2938 dev_priv->stats.last_clear_reads++; 2974 dev_priv->stats.last_clear_reads++;
2939 value = GET_SCRATCH( 2 ); 2975 value = GET_SCRATCH(2);
2940 break; 2976 break;
2941 case RADEON_PARAM_IRQ_NR: 2977 case RADEON_PARAM_IRQ_NR:
2942 value = dev->irq; 2978 value = dev->irq;
@@ -2951,15 +2987,15 @@ static int radeon_cp_getparam( DRM_IOCTL_ARGS )
2951 value = dev_priv->ring_rptr_offset; 2987 value = dev_priv->ring_rptr_offset;
2952 break; 2988 break;
2953#if BITS_PER_LONG == 32 2989#if BITS_PER_LONG == 32
2954 /* 2990 /*
2955 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a 2991 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
2956 * pointer which can't fit into an int-sized variable. According to 2992 * pointer which can't fit into an int-sized variable. According to
2957 * Michel Dänzer, the ioctl() is only used on embedded platforms, so 2993 * Michel Dänzer, the ioctl() is only used on embedded platforms, so
2958 * not supporting it shouldn't be a problem. If the same functionality 2994 * not supporting it shouldn't be a problem. If the same functionality
2959 * is needed on 64-bit platforms, a new ioctl() would have to be added, 2995 * is needed on 64-bit platforms, a new ioctl() would have to be added,
2960 * so backwards-compatibility for the embedded platforms can be 2996 * so backwards-compatibility for the embedded platforms can be
2961 * maintained. --davidm 4-Feb-2004. 2997 * maintained. --davidm 4-Feb-2004.
2962 */ 2998 */
2963 case RADEON_PARAM_SAREA_HANDLE: 2999 case RADEON_PARAM_SAREA_HANDLE:
2964 /* The lock is the first dword in the sarea. */ 3000 /* The lock is the first dword in the sarea. */
2965 value = (long)dev->lock.hw_lock; 3001 value = (long)dev->lock.hw_lock;
@@ -2972,53 +3008,56 @@ static int radeon_cp_getparam( DRM_IOCTL_ARGS )
2972 return DRM_ERR(EINVAL); 3008 return DRM_ERR(EINVAL);
2973 } 3009 }
2974 3010
2975 if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { 3011 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
2976 DRM_ERROR( "copy_to_user\n" ); 3012 DRM_ERROR("copy_to_user\n");
2977 return DRM_ERR(EFAULT); 3013 return DRM_ERR(EFAULT);
2978 } 3014 }
2979 3015
2980 return 0; 3016 return 0;
2981} 3017}
2982 3018
2983static int radeon_cp_setparam( DRM_IOCTL_ARGS ) { 3019static int radeon_cp_setparam(DRM_IOCTL_ARGS)
3020{
2984 DRM_DEVICE; 3021 DRM_DEVICE;
2985 drm_radeon_private_t *dev_priv = dev->dev_private; 3022 drm_radeon_private_t *dev_priv = dev->dev_private;
2986 drm_file_t *filp_priv; 3023 drm_file_t *filp_priv;
2987 drm_radeon_setparam_t sp; 3024 drm_radeon_setparam_t sp;
2988 struct drm_radeon_driver_file_fields *radeon_priv; 3025 struct drm_radeon_driver_file_fields *radeon_priv;
2989 3026
2990 if ( !dev_priv ) { 3027 if (!dev_priv) {
2991 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 3028 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2992 return DRM_ERR( EINVAL ); 3029 return DRM_ERR(EINVAL);
2993 } 3030 }
2994 3031
2995 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 3032 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2996 3033
2997 DRM_COPY_FROM_USER_IOCTL( sp, ( drm_radeon_setparam_t __user * )data, 3034 DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data,
2998 sizeof( sp ) ); 3035 sizeof(sp));
2999 3036
3000 switch( sp.param ) { 3037 switch (sp.param) {
3001 case RADEON_SETPARAM_FB_LOCATION: 3038 case RADEON_SETPARAM_FB_LOCATION:
3002 radeon_priv = filp_priv->driver_priv; 3039 radeon_priv = filp_priv->driver_priv;
3003 radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value; 3040 radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value;
3004 break; 3041 break;
3005 case RADEON_SETPARAM_SWITCH_TILING: 3042 case RADEON_SETPARAM_SWITCH_TILING:
3006 if (sp.value == 0) { 3043 if (sp.value == 0) {
3007 DRM_DEBUG( "color tiling disabled\n" ); 3044 DRM_DEBUG("color tiling disabled\n");
3008 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO; 3045 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3009 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO; 3046 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3010 dev_priv->sarea_priv->tiling_enabled = 0; 3047 dev_priv->sarea_priv->tiling_enabled = 0;
3011 } 3048 } else if (sp.value == 1) {
3012 else if (sp.value == 1) { 3049 DRM_DEBUG("color tiling enabled\n");
3013 DRM_DEBUG( "color tiling enabled\n" );
3014 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO; 3050 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
3015 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO; 3051 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
3016 dev_priv->sarea_priv->tiling_enabled = 1; 3052 dev_priv->sarea_priv->tiling_enabled = 1;
3017 } 3053 }
3018 break; 3054 break;
3055 case RADEON_SETPARAM_PCIGART_LOCATION:
3056 dev_priv->pcigart_offset = sp.value;
3057 break;
3019 default: 3058 default:
3020 DRM_DEBUG( "Invalid parameter %d\n", sp.param ); 3059 DRM_DEBUG("Invalid parameter %d\n", sp.param);
3021 return DRM_ERR( EINVAL ); 3060 return DRM_ERR(EINVAL);
3022 } 3061 }
3023 3062
3024 return 0; 3063 return 0;
@@ -3030,78 +3069,80 @@ static int radeon_cp_setparam( DRM_IOCTL_ARGS ) {
3030 * 3069 *
3031 * DRM infrastructure takes care of reclaiming dma buffers. 3070 * DRM infrastructure takes care of reclaiming dma buffers.
3032 */ 3071 */
3033void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp) 3072void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp)
3034{ 3073{
3035 if ( dev->dev_private ) { 3074 if (dev->dev_private) {
3036 drm_radeon_private_t *dev_priv = dev->dev_private; 3075 drm_radeon_private_t *dev_priv = dev->dev_private;
3037 if ( dev_priv->page_flipping ) { 3076 if (dev_priv->page_flipping) {
3038 radeon_do_cleanup_pageflip( dev ); 3077 radeon_do_cleanup_pageflip(dev);
3039 } 3078 }
3040 radeon_mem_release( filp, dev_priv->gart_heap ); 3079 radeon_mem_release(filp, dev_priv->gart_heap);
3041 radeon_mem_release( filp, dev_priv->fb_heap ); 3080 radeon_mem_release(filp, dev_priv->fb_heap);
3042 radeon_surfaces_release(filp, dev_priv); 3081 radeon_surfaces_release(filp, dev_priv);
3043 } 3082 }
3044} 3083}
3045 3084
3046void radeon_driver_pretakedown(drm_device_t *dev) 3085void radeon_driver_pretakedown(drm_device_t * dev)
3047{ 3086{
3048 radeon_do_release(dev); 3087 radeon_do_release(dev);
3049} 3088}
3050 3089
3051int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv) 3090int radeon_driver_open_helper(drm_device_t * dev, drm_file_t * filp_priv)
3052{ 3091{
3053 drm_radeon_private_t *dev_priv = dev->dev_private; 3092 drm_radeon_private_t *dev_priv = dev->dev_private;
3054 struct drm_radeon_driver_file_fields *radeon_priv; 3093 struct drm_radeon_driver_file_fields *radeon_priv;
3055 3094
3056 radeon_priv = (struct drm_radeon_driver_file_fields *)drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES); 3095 radeon_priv =
3057 3096 (struct drm_radeon_driver_file_fields *)
3097 drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES);
3098
3058 if (!radeon_priv) 3099 if (!radeon_priv)
3059 return -ENOMEM; 3100 return -ENOMEM;
3060 3101
3061 filp_priv->driver_priv = radeon_priv; 3102 filp_priv->driver_priv = radeon_priv;
3062 if ( dev_priv ) 3103 if (dev_priv)
3063 radeon_priv->radeon_fb_delta = dev_priv->fb_location; 3104 radeon_priv->radeon_fb_delta = dev_priv->fb_location;
3064 else 3105 else
3065 radeon_priv->radeon_fb_delta = 0; 3106 radeon_priv->radeon_fb_delta = 0;
3066 return 0; 3107 return 0;
3067} 3108}
3068 3109
3069 3110void radeon_driver_free_filp_priv(drm_device_t * dev, drm_file_t * filp_priv)
3070void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv)
3071{ 3111{
3072 struct drm_radeon_driver_file_fields *radeon_priv = filp_priv->driver_priv; 3112 struct drm_radeon_driver_file_fields *radeon_priv =
3073 3113 filp_priv->driver_priv;
3074 drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); 3114
3115 drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES);
3075} 3116}
3076 3117
3077drm_ioctl_desc_t radeon_ioctls[] = { 3118drm_ioctl_desc_t radeon_ioctls[] = {
3078 [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 }, 3119 [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, 1, 1},
3079 [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = { radeon_cp_start, 1, 1 }, 3120 [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, 1, 1},
3080 [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 }, 3121 [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, 1, 1},
3081 [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 }, 3122 [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = {radeon_cp_reset, 1, 1},
3082 [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 }, 3123 [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = {radeon_cp_idle, 1, 0},
3083 [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = { radeon_cp_resume, 1, 0 }, 3124 [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = {radeon_cp_resume, 1, 0},
3084 [DRM_IOCTL_NR(DRM_RADEON_RESET)] = { radeon_engine_reset, 1, 0 }, 3125 [DRM_IOCTL_NR(DRM_RADEON_RESET)] = {radeon_engine_reset, 1, 0},
3085 [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = { radeon_fullscreen, 1, 0 }, 3126 [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = {radeon_fullscreen, 1, 0},
3086 [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 }, 3127 [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = {radeon_cp_swap, 1, 0},
3087 [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = { radeon_cp_clear, 1, 0 }, 3128 [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = {radeon_cp_clear, 1, 0},
3088 [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = { radeon_cp_vertex, 1, 0 }, 3129 [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = {radeon_cp_vertex, 1, 0},
3089 [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = { radeon_cp_indices, 1, 0 }, 3130 [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = {radeon_cp_indices, 1, 0},
3090 [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = { radeon_cp_texture, 1, 0 }, 3131 [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = {radeon_cp_texture, 1, 0},
3091 [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = { radeon_cp_stipple, 1, 0 }, 3132 [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = {radeon_cp_stipple, 1, 0},
3092 [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = { radeon_cp_indirect, 1, 1 }, 3133 [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = {radeon_cp_indirect, 1, 1},
3093 [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = { radeon_cp_vertex2, 1, 0 }, 3134 [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = {radeon_cp_vertex2, 1, 0},
3094 [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = { radeon_cp_cmdbuf, 1, 0 }, 3135 [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = {radeon_cp_cmdbuf, 1, 0},
3095 [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = { radeon_cp_getparam, 1, 0 }, 3136 [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = {radeon_cp_getparam, 1, 0},
3096 [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = { radeon_cp_flip, 1, 0 }, 3137 [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = {radeon_cp_flip, 1, 0},
3097 [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = { radeon_mem_alloc, 1, 0 }, 3138 [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = {radeon_mem_alloc, 1, 0},
3098 [DRM_IOCTL_NR(DRM_RADEON_FREE)] = { radeon_mem_free, 1, 0 }, 3139 [DRM_IOCTL_NR(DRM_RADEON_FREE)] = {radeon_mem_free, 1, 0},
3099 [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = { radeon_mem_init_heap,1, 1 }, 3140 [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = {radeon_mem_init_heap, 1, 1},
3100 [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = { radeon_irq_emit, 1, 0 }, 3141 [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = {radeon_irq_emit, 1, 0},
3101 [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = { radeon_irq_wait, 1, 0 }, 3142 [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = {radeon_irq_wait, 1, 0},
3102 [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = { radeon_cp_setparam, 1, 0 }, 3143 [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = {radeon_cp_setparam, 1, 0},
3103 [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = { radeon_surface_alloc,1, 0 }, 3144 [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = {radeon_surface_alloc, 1, 0},
3104 [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = { radeon_surface_free, 1, 0 } 3145 [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = {radeon_surface_free, 1, 0}
3105}; 3146};
3106 3147
3107int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); 3148int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 15:01:45 -0500