1 files changed, 38 insertions, 0 deletions

diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 4434332c79bc..173ae620223a 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -123,6 +123,7 @@ enum radeon_family {
         CHIP_R420,
         CHIP_RV410,
         CHIP_RS400,
+        CHIP_RS690,
         CHIP_RV515,
         CHIP_R520,
         CHIP_RV530,
@@ -467,6 +468,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #define RADEON_IGPGART_ENABLE           0x38
 #define RADEON_IGPGART_UNK_39           0x39
 
+#define RS690_MC_INDEX                  0x78
+#   define RS690_MC_INDEX_MASK          0x1ff
+#   define RS690_MC_INDEX_WR_EN         (1 << 9)
+#   define RS690_MC_INDEX_WR_ACK        0x7f
+#define RS690_MC_DATA                   0x7c
+
+#define RS690_MC_MISC_CNTL              0x18
+#define RS690_MC_GART_FEATURE_ID        0x2b
+#define RS690_MC_GART_BASE              0x2c
+#define RS690_MC_GART_CACHE_CNTL        0x2e
+#   define RS690_MC_GART_CC_NO_CHANGE   0x0
+#   define RS690_MC_GART_CC_CLEAR       0x1
+#   define RS690_MC_GART_CLEAR_STATUS   (1 << 1)
+#       define RS690_MC_GART_CLEAR_DONE     (0 << 1)
+#       define RS690_MC_GART_CLEAR_PENDING  (1 << 1)
+#define RS690_MC_AGP_SIZE               0x38
+#   define RS690_MC_GART_DIS            0x0
+#   define RS690_MC_GART_EN             0x1
+#   define RS690_MC_AGP_SIZE_32MB       (0 << 1)
+#   define RS690_MC_AGP_SIZE_64MB       (1 << 1)
+#   define RS690_MC_AGP_SIZE_128MB      (2 << 1)
+#   define RS690_MC_AGP_SIZE_256MB      (3 << 1)
+#   define RS690_MC_AGP_SIZE_512MB      (4 << 1)
+#   define RS690_MC_AGP_SIZE_1GB        (5 << 1)
+#   define RS690_MC_AGP_SIZE_2GB        (6 << 1)
+#define RS690_MC_AGP_MODE_CONTROL       0x39
+#define RS690_MC_FB_LOCATION            0x100
+#define RS690_MC_AGP_LOCATION           0x101
+#define RS690_MC_AGP_BASE               0x102
+
 #define R520_MC_IND_INDEX 0x70
 #define R520_MC_IND_WR_EN (1<<24)
 #define R520_MC_IND_DATA  0x74
@@ -1076,6 +1107,13 @@ do {									\
                 RADEON_WRITE(R520_MC_IND_INDEX, 0);     \
         } while (0)
 
+#define RS690_WRITE_MCIND( addr, val )                                  \
+do {                                                            \
+        RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK));    \
+        RADEON_WRITE(RS690_MC_DATA, val);                       \
+        RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);    \
+} while (0)
+
 #define CP_PACKET0( reg, n )                                            \
         (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
 #define CP_PACKET0_TABLE( reg, n )                                      \