diff options
Diffstat (limited to 'drivers/char/drm/radeon_drv.h')
-rw-r--r-- | drivers/char/drm/radeon_drv.h | 45 |
1 files changed, 28 insertions, 17 deletions
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index 54f49ef4bef0..3b3d9357201c 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h | |||
@@ -97,9 +97,10 @@ | |||
97 | * new packet type) | 97 | * new packet type) |
98 | * 1.26- Add support for variable size PCI(E) gart aperture | 98 | * 1.26- Add support for variable size PCI(E) gart aperture |
99 | * 1.27- Add support for IGP GART | 99 | * 1.27- Add support for IGP GART |
100 | * 1.28- Add support for VBL on CRTC2 | ||
100 | */ | 101 | */ |
101 | #define DRIVER_MAJOR 1 | 102 | #define DRIVER_MAJOR 1 |
102 | #define DRIVER_MINOR 27 | 103 | #define DRIVER_MINOR 28 |
103 | #define DRIVER_PATCHLEVEL 0 | 104 | #define DRIVER_PATCHLEVEL 0 |
104 | 105 | ||
105 | /* | 106 | /* |
@@ -154,7 +155,7 @@ enum radeon_chip_flags { | |||
154 | 155 | ||
155 | typedef struct drm_radeon_freelist { | 156 | typedef struct drm_radeon_freelist { |
156 | unsigned int age; | 157 | unsigned int age; |
157 | drm_buf_t *buf; | 158 | struct drm_buf *buf; |
158 | struct drm_radeon_freelist *next; | 159 | struct drm_radeon_freelist *next; |
159 | struct drm_radeon_freelist *prev; | 160 | struct drm_radeon_freelist *prev; |
160 | } drm_radeon_freelist_t; | 161 | } drm_radeon_freelist_t; |
@@ -277,13 +278,16 @@ typedef struct drm_radeon_private { | |||
277 | /* SW interrupt */ | 278 | /* SW interrupt */ |
278 | wait_queue_head_t swi_queue; | 279 | wait_queue_head_t swi_queue; |
279 | atomic_t swi_emitted; | 280 | atomic_t swi_emitted; |
281 | int vblank_crtc; | ||
282 | uint32_t irq_enable_reg; | ||
283 | int irq_enabled; | ||
280 | 284 | ||
281 | struct radeon_surface surfaces[RADEON_MAX_SURFACES]; | 285 | struct radeon_surface surfaces[RADEON_MAX_SURFACES]; |
282 | struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; | 286 | struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; |
283 | 287 | ||
284 | unsigned long pcigart_offset; | 288 | unsigned long pcigart_offset; |
285 | unsigned int pcigart_offset_set; | 289 | unsigned int pcigart_offset_set; |
286 | drm_ati_pcigart_info gart_info; | 290 | struct drm_ati_pcigart_info gart_info; |
287 | 291 | ||
288 | u32 scratch_ages[5]; | 292 | u32 scratch_ages[5]; |
289 | 293 | ||
@@ -299,7 +303,7 @@ typedef struct drm_radeon_kcmd_buffer { | |||
299 | int bufsz; | 303 | int bufsz; |
300 | char *buf; | 304 | char *buf; |
301 | int nbox; | 305 | int nbox; |
302 | drm_clip_rect_t __user *boxes; | 306 | struct drm_clip_rect __user *boxes; |
303 | } drm_radeon_kcmd_buffer_t; | 307 | } drm_radeon_kcmd_buffer_t; |
304 | 308 | ||
305 | extern int radeon_no_wb; | 309 | extern int radeon_no_wb; |
@@ -332,8 +336,8 @@ extern int radeon_engine_reset(DRM_IOCTL_ARGS); | |||
332 | extern int radeon_fullscreen(DRM_IOCTL_ARGS); | 336 | extern int radeon_fullscreen(DRM_IOCTL_ARGS); |
333 | extern int radeon_cp_buffers(DRM_IOCTL_ARGS); | 337 | extern int radeon_cp_buffers(DRM_IOCTL_ARGS); |
334 | 338 | ||
335 | extern void radeon_freelist_reset(drm_device_t * dev); | 339 | extern void radeon_freelist_reset(struct drm_device * dev); |
336 | extern drm_buf_t *radeon_freelist_get(drm_device_t * dev); | 340 | extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); |
337 | 341 | ||
338 | extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); | 342 | extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); |
339 | 343 | ||
@@ -353,29 +357,33 @@ extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap); | |||
353 | extern int radeon_irq_emit(DRM_IOCTL_ARGS); | 357 | extern int radeon_irq_emit(DRM_IOCTL_ARGS); |
354 | extern int radeon_irq_wait(DRM_IOCTL_ARGS); | 358 | extern int radeon_irq_wait(DRM_IOCTL_ARGS); |
355 | 359 | ||
356 | extern void radeon_do_release(drm_device_t * dev); | 360 | extern void radeon_do_release(struct drm_device * dev); |
357 | extern int radeon_driver_vblank_wait(drm_device_t * dev, | 361 | extern int radeon_driver_vblank_wait(struct drm_device * dev, |
358 | unsigned int *sequence); | 362 | unsigned int *sequence); |
363 | extern int radeon_driver_vblank_wait2(struct drm_device * dev, | ||
364 | unsigned int *sequence); | ||
359 | extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); | 365 | extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); |
360 | extern void radeon_driver_irq_preinstall(drm_device_t * dev); | 366 | extern void radeon_driver_irq_preinstall(struct drm_device * dev); |
361 | extern void radeon_driver_irq_postinstall(drm_device_t * dev); | 367 | extern void radeon_driver_irq_postinstall(struct drm_device * dev); |
362 | extern void radeon_driver_irq_uninstall(drm_device_t * dev); | 368 | extern void radeon_driver_irq_uninstall(struct drm_device * dev); |
369 | extern int radeon_vblank_crtc_get(struct drm_device *dev); | ||
370 | extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); | ||
363 | 371 | ||
364 | extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); | 372 | extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); |
365 | extern int radeon_driver_unload(struct drm_device *dev); | 373 | extern int radeon_driver_unload(struct drm_device *dev); |
366 | extern int radeon_driver_firstopen(struct drm_device *dev); | 374 | extern int radeon_driver_firstopen(struct drm_device *dev); |
367 | extern void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp); | 375 | extern void radeon_driver_preclose(struct drm_device * dev, DRMFILE filp); |
368 | extern void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp); | 376 | extern void radeon_driver_postclose(struct drm_device * dev, struct drm_file * filp); |
369 | extern void radeon_driver_lastclose(drm_device_t * dev); | 377 | extern void radeon_driver_lastclose(struct drm_device * dev); |
370 | extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv); | 378 | extern int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv); |
371 | extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, | 379 | extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, |
372 | unsigned long arg); | 380 | unsigned long arg); |
373 | 381 | ||
374 | /* r300_cmdbuf.c */ | 382 | /* r300_cmdbuf.c */ |
375 | extern void r300_init_reg_flags(void); | 383 | extern void r300_init_reg_flags(void); |
376 | 384 | ||
377 | extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp, | 385 | extern int r300_do_cp_cmdbuf(struct drm_device * dev, DRMFILE filp, |
378 | drm_file_t * filp_priv, | 386 | struct drm_file * filp_priv, |
379 | drm_radeon_kcmd_buffer_t * cmdbuf); | 387 | drm_radeon_kcmd_buffer_t * cmdbuf); |
380 | 388 | ||
381 | /* Flags for stats.boxes | 389 | /* Flags for stats.boxes |
@@ -496,12 +504,15 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp, | |||
496 | 504 | ||
497 | #define RADEON_GEN_INT_CNTL 0x0040 | 505 | #define RADEON_GEN_INT_CNTL 0x0040 |
498 | # define RADEON_CRTC_VBLANK_MASK (1 << 0) | 506 | # define RADEON_CRTC_VBLANK_MASK (1 << 0) |
507 | # define RADEON_CRTC2_VBLANK_MASK (1 << 9) | ||
499 | # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) | 508 | # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) |
500 | # define RADEON_SW_INT_ENABLE (1 << 25) | 509 | # define RADEON_SW_INT_ENABLE (1 << 25) |
501 | 510 | ||
502 | #define RADEON_GEN_INT_STATUS 0x0044 | 511 | #define RADEON_GEN_INT_STATUS 0x0044 |
503 | # define RADEON_CRTC_VBLANK_STAT (1 << 0) | 512 | # define RADEON_CRTC_VBLANK_STAT (1 << 0) |
504 | # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) | 513 | # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) |
514 | # define RADEON_CRTC2_VBLANK_STAT (1 << 9) | ||
515 | # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) | ||
505 | # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) | 516 | # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) |
506 | # define RADEON_SW_INT_TEST (1 << 25) | 517 | # define RADEON_SW_INT_TEST (1 << 25) |
507 | # define RADEON_SW_INT_TEST_ACK (1 << 25) | 518 | # define RADEON_SW_INT_TEST_ACK (1 << 25) |