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path: root/drivers/char/drm/radeon_drv.h
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-rw-r--r--drivers/char/drm/radeon_drv.h50
1 files changed, 49 insertions, 1 deletions
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 8ce4940aba75..443a8952eced 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -166,6 +166,12 @@ typedef struct drm_radeon_ring_buffer {
166 int size; 166 int size;
167 int size_l2qw; 167 int size_l2qw;
168 168
169 int rptr_update; /* Double Words */
170 int rptr_update_l2qw; /* log2 Quad Words */
171
172 int fetch_size; /* Double Words */
173 int fetch_size_l2ow; /* log2 Oct Words */
174
169 u32 tail; 175 u32 tail;
170 u32 tail_mask; 176 u32 tail_mask;
171 int space; 177 int space;
@@ -615,9 +621,51 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
615# define RADEON_SOFT_RESET_E2 (1 << 5) 621# define RADEON_SOFT_RESET_E2 (1 << 5)
616# define RADEON_SOFT_RESET_RB (1 << 6) 622# define RADEON_SOFT_RESET_RB (1 << 6)
617# define RADEON_SOFT_RESET_HDP (1 << 7) 623# define RADEON_SOFT_RESET_HDP (1 << 7)
624/*
625 * 6:0 Available slots in the FIFO
626 * 8 Host Interface active
627 * 9 CP request active
628 * 10 FIFO request active
629 * 11 Host Interface retry active
630 * 12 CP retry active
631 * 13 FIFO retry active
632 * 14 FIFO pipeline busy
633 * 15 Event engine busy
634 * 16 CP command stream busy
635 * 17 2D engine busy
636 * 18 2D portion of render backend busy
637 * 20 3D setup engine busy
638 * 26 GA engine busy
639 * 27 CBA 2D engine busy
640 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
641 * command stream queue not empty or Ring Buffer not empty
642 */
618#define RADEON_RBBM_STATUS 0x0e40 643#define RADEON_RBBM_STATUS 0x0e40
644/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
645/* #define RADEON_RBBM_STATUS 0x1740 */
646/* bits 6:0 are dword slots available in the cmd fifo */
619# define RADEON_RBBM_FIFOCNT_MASK 0x007f 647# define RADEON_RBBM_FIFOCNT_MASK 0x007f
620# define RADEON_RBBM_ACTIVE (1 << 31) 648# define RADEON_HIRQ_ON_RBB (1 << 8)
649# define RADEON_CPRQ_ON_RBB (1 << 9)
650# define RADEON_CFRQ_ON_RBB (1 << 10)
651# define RADEON_HIRQ_IN_RTBUF (1 << 11)
652# define RADEON_CPRQ_IN_RTBUF (1 << 12)
653# define RADEON_CFRQ_IN_RTBUF (1 << 13)
654# define RADEON_PIPE_BUSY (1 << 14)
655# define RADEON_ENG_EV_BUSY (1 << 15)
656# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
657# define RADEON_E2_BUSY (1 << 17)
658# define RADEON_RB2D_BUSY (1 << 18)
659# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
660# define RADEON_VAP_BUSY (1 << 20)
661# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
662# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
663# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
664# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
665# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
666# define RADEON_GA_BUSY (1 << 26)
667# define RADEON_CBA2D_BUSY (1 << 27)
668# define RADEON_RBBM_ACTIVE (1 << 31)
621#define RADEON_RE_LINE_PATTERN 0x1cd0 669#define RADEON_RE_LINE_PATTERN 0x1cd0
622#define RADEON_RE_MISC 0x26c4 670#define RADEON_RE_MISC 0x26c4
623#define RADEON_RE_TOP_LEFT 0x26c0 671#define RADEON_RE_TOP_LEFT 0x26c0