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path: root/drivers/char/drm/radeon_drv.h
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Diffstat (limited to 'drivers/char/drm/radeon_drv.h')
-rw-r--r--drivers/char/drm/radeon_drv.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 78345cee8f8e..e5a256f5429c 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -38,7 +38,7 @@
38 38
39#define DRIVER_NAME "radeon" 39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon" 40#define DRIVER_DESC "ATI Radeon"
41#define DRIVER_DATE "20060225" 41#define DRIVER_DATE "20060524"
42 42
43/* Interface history: 43/* Interface history:
44 * 44 *
@@ -93,9 +93,11 @@
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh 94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
96 */ 98 */
97#define DRIVER_MAJOR 1 99#define DRIVER_MAJOR 1
98#define DRIVER_MINOR 24 100#define DRIVER_MINOR 25
99#define DRIVER_PATCHLEVEL 0 101#define DRIVER_PATCHLEVEL 0
100 102
101/* 103/*
@@ -884,6 +886,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
884#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 886#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
885#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 887#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
886 888
889#define RADEON_SE_TCL_STATE_FLUSH 0x2284
890
887#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 891#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
888#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 892#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
889#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 893#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
@@ -905,6 +909,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
905#define R200_PP_AFS_0 0x2f80 909#define R200_PP_AFS_0 0x2f80
906#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 910#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
907 911
912#define R200_VAP_PVS_CNTL_1 0x22D0
913
908/* Constants */ 914/* Constants */
909#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 915#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
910 916