aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/char/drm/radeon_drv.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/char/drm/radeon_drv.h')
-rw-r--r--drivers/char/drm/radeon_drv.h270
1 files changed, 184 insertions, 86 deletions
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index b791420bd3d9..3f0eca957aa7 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -38,7 +38,7 @@
38 38
39#define DRIVER_NAME "radeon" 39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon" 40#define DRIVER_DESC "ATI Radeon"
41#define DRIVER_DATE "20060524" 41#define DRIVER_DATE "20080528"
42 42
43/* Interface history: 43/* Interface history:
44 * 44 *
@@ -98,9 +98,10 @@
98 * 1.26- Add support for variable size PCI(E) gart aperture 98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART 99 * 1.27- Add support for IGP GART
100 * 1.28- Add support for VBL on CRTC2 100 * 1.28- Add support for VBL on CRTC2
101 * 1.29- R500 3D cmd buffer support
101 */ 102 */
102#define DRIVER_MAJOR 1 103#define DRIVER_MAJOR 1
103#define DRIVER_MINOR 28 104#define DRIVER_MINOR 29
104#define DRIVER_PATCHLEVEL 0 105#define DRIVER_PATCHLEVEL 0
105 106
106/* 107/*
@@ -122,7 +123,7 @@ enum radeon_family {
122 CHIP_RV380, 123 CHIP_RV380,
123 CHIP_R420, 124 CHIP_R420,
124 CHIP_RV410, 125 CHIP_RV410,
125 CHIP_RS400, 126 CHIP_RS480,
126 CHIP_RS690, 127 CHIP_RS690,
127 CHIP_RV515, 128 CHIP_RV515,
128 CHIP_R520, 129 CHIP_R520,
@@ -294,6 +295,7 @@ typedef struct drm_radeon_private {
294 int vblank_crtc; 295 int vblank_crtc;
295 uint32_t irq_enable_reg; 296 uint32_t irq_enable_reg;
296 int irq_enabled; 297 int irq_enabled;
298 uint32_t r500_disp_irq_reg;
297 299
298 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 300 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
299 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 301 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
@@ -304,12 +306,11 @@ typedef struct drm_radeon_private {
304 306
305 u32 scratch_ages[5]; 307 u32 scratch_ages[5];
306 308
307 unsigned int crtc_last_cnt;
308 unsigned int crtc2_last_cnt;
309
310 /* starting from here on, data is preserved accross an open */ 309 /* starting from here on, data is preserved accross an open */
311 uint32_t flags; /* see radeon_chip_flags */ 310 uint32_t flags; /* see radeon_chip_flags */
312 unsigned long fb_aper_offset; 311 unsigned long fb_aper_offset;
312
313 int num_gb_pipes;
313} drm_radeon_private_t; 314} drm_radeon_private_t;
314 315
315typedef struct drm_radeon_buf_priv { 316typedef struct drm_radeon_buf_priv {
@@ -377,14 +378,15 @@ extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *
377extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 378extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
378 379
379extern void radeon_do_release(struct drm_device * dev); 380extern void radeon_do_release(struct drm_device * dev);
380extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 381extern int radeon_driver_vblank_wait(struct drm_device * dev,
381extern int radeon_enable_vblank(struct drm_device *dev, int crtc); 382 unsigned int *sequence);
382extern void radeon_disable_vblank(struct drm_device *dev, int crtc); 383extern int radeon_driver_vblank_wait2(struct drm_device * dev,
383extern void radeon_do_release(struct drm_device * dev); 384 unsigned int *sequence);
384extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 385extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
385extern void radeon_driver_irq_preinstall(struct drm_device * dev); 386extern void radeon_driver_irq_preinstall(struct drm_device * dev);
386extern int radeon_driver_irq_postinstall(struct drm_device * dev); 387extern void radeon_driver_irq_postinstall(struct drm_device * dev);
387extern void radeon_driver_irq_uninstall(struct drm_device * dev); 388extern void radeon_driver_irq_uninstall(struct drm_device * dev);
389extern void radeon_enable_interrupt(struct drm_device *dev);
388extern int radeon_vblank_crtc_get(struct drm_device *dev); 390extern int radeon_vblank_crtc_get(struct drm_device *dev);
389extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 391extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
390 392
@@ -447,13 +449,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
447#define RADEON_PCIE_DATA 0x0034 449#define RADEON_PCIE_DATA 0x0034
448#define RADEON_PCIE_TX_GART_CNTL 0x10 450#define RADEON_PCIE_TX_GART_CNTL 0x10
449# define RADEON_PCIE_TX_GART_EN (1 << 0) 451# define RADEON_PCIE_TX_GART_EN (1 << 0)
450# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) 452# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
451# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) 453# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
452# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) 454# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
453# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3) 455# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
454# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3) 456# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
455# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5) 457# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
456# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) 458# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
457#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 459#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
458#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 460#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
459#define RADEON_PCIE_TX_GART_BASE 0x13 461#define RADEON_PCIE_TX_GART_BASE 0x13
@@ -462,14 +464,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
462#define RADEON_PCIE_TX_GART_END_LO 0x16 464#define RADEON_PCIE_TX_GART_END_LO 0x16
463#define RADEON_PCIE_TX_GART_END_HI 0x17 465#define RADEON_PCIE_TX_GART_END_HI 0x17
464 466
465#define RADEON_IGPGART_INDEX 0x168 467#define RS480_NB_MC_INDEX 0x168
466#define RADEON_IGPGART_DATA 0x16c 468# define RS480_NB_MC_IND_WR_EN (1 << 8)
467#define RADEON_IGPGART_UNK_18 0x18 469#define RS480_NB_MC_DATA 0x16c
468#define RADEON_IGPGART_CTRL 0x2b
469#define RADEON_IGPGART_BASE_ADDR 0x2c
470#define RADEON_IGPGART_FLUSH 0x2e
471#define RADEON_IGPGART_ENABLE 0x38
472#define RADEON_IGPGART_UNK_39 0x39
473 470
474#define RS690_MC_INDEX 0x78 471#define RS690_MC_INDEX 0x78
475# define RS690_MC_INDEX_MASK 0x1ff 472# define RS690_MC_INDEX_MASK 0x1ff
@@ -477,45 +474,91 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
477# define RS690_MC_INDEX_WR_ACK 0x7f 474# define RS690_MC_INDEX_WR_ACK 0x7f
478#define RS690_MC_DATA 0x7c 475#define RS690_MC_DATA 0x7c
479 476
480#define RS690_MC_MISC_CNTL 0x18 477/* MC indirect registers */
481#define RS690_MC_GART_FEATURE_ID 0x2b 478#define RS480_MC_MISC_CNTL 0x18
482#define RS690_MC_GART_BASE 0x2c 479# define RS480_DISABLE_GTW (1 << 1)
483#define RS690_MC_GART_CACHE_CNTL 0x2e 480/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
484# define RS690_MC_GART_CC_NO_CHANGE 0x0 481# define RS480_GART_INDEX_REG_EN (1 << 12)
485# define RS690_MC_GART_CC_CLEAR 0x1 482# define RS690_BLOCK_GFX_D3_EN (1 << 14)
486# define RS690_MC_GART_CLEAR_STATUS (1 << 1) 483#define RS480_K8_FB_LOCATION 0x1e
487# define RS690_MC_GART_CLEAR_DONE (0 << 1) 484#define RS480_GART_FEATURE_ID 0x2b
488# define RS690_MC_GART_CLEAR_PENDING (1 << 1) 485# define RS480_HANG_EN (1 << 11)
489#define RS690_MC_AGP_SIZE 0x38 486# define RS480_TLB_ENABLE (1 << 18)
490# define RS690_MC_GART_DIS 0x0 487# define RS480_P2P_ENABLE (1 << 19)
491# define RS690_MC_GART_EN 0x1 488# define RS480_GTW_LAC_EN (1 << 25)
492# define RS690_MC_AGP_SIZE_32MB (0 << 1) 489# define RS480_2LEVEL_GART (0 << 30)
493# define RS690_MC_AGP_SIZE_64MB (1 << 1) 490# define RS480_1LEVEL_GART (1 << 30)
494# define RS690_MC_AGP_SIZE_128MB (2 << 1) 491# define RS480_PDC_EN (1 << 31)
495# define RS690_MC_AGP_SIZE_256MB (3 << 1) 492#define RS480_GART_BASE 0x2c
496# define RS690_MC_AGP_SIZE_512MB (4 << 1) 493#define RS480_GART_CACHE_CNTRL 0x2e
497# define RS690_MC_AGP_SIZE_1GB (5 << 1) 494# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
498# define RS690_MC_AGP_SIZE_2GB (6 << 1) 495#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
499#define RS690_MC_AGP_MODE_CONTROL 0x39 496# define RS480_GART_EN (1 << 0)
497# define RS480_VA_SIZE_32MB (0 << 1)
498# define RS480_VA_SIZE_64MB (1 << 1)
499# define RS480_VA_SIZE_128MB (2 << 1)
500# define RS480_VA_SIZE_256MB (3 << 1)
501# define RS480_VA_SIZE_512MB (4 << 1)
502# define RS480_VA_SIZE_1GB (5 << 1)
503# define RS480_VA_SIZE_2GB (6 << 1)
504#define RS480_AGP_MODE_CNTL 0x39
505# define RS480_POST_GART_Q_SIZE (1 << 18)
506# define RS480_NONGART_SNOOP (1 << 19)
507# define RS480_AGP_RD_BUF_SIZE (1 << 20)
508# define RS480_REQ_TYPE_SNOOP_SHIFT 22
509# define RS480_REQ_TYPE_SNOOP_MASK 0x3
510# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
511#define RS480_MC_MISC_UMA_CNTL 0x5f
512#define RS480_MC_MCLK_CNTL 0x7a
513#define RS480_MC_UMA_DUALCH_CNTL 0x86
514
500#define RS690_MC_FB_LOCATION 0x100 515#define RS690_MC_FB_LOCATION 0x100
501#define RS690_MC_AGP_LOCATION 0x101 516#define RS690_MC_AGP_LOCATION 0x101
502#define RS690_MC_AGP_BASE 0x102 517#define RS690_MC_AGP_BASE 0x102
518#define RS690_MC_AGP_BASE_2 0x103
503 519
504#define R520_MC_IND_INDEX 0x70 520#define R520_MC_IND_INDEX 0x70
505#define R520_MC_IND_WR_EN (1<<24) 521#define R520_MC_IND_WR_EN (1 << 24)
506#define R520_MC_IND_DATA 0x74 522#define R520_MC_IND_DATA 0x74
507 523
508#define RV515_MC_FB_LOCATION 0x01 524#define RV515_MC_FB_LOCATION 0x01
509#define RV515_MC_AGP_LOCATION 0x02 525#define RV515_MC_AGP_LOCATION 0x02
526#define RV515_MC_AGP_BASE 0x03
527#define RV515_MC_AGP_BASE_2 0x04
510 528
511#define R520_MC_FB_LOCATION 0x04 529#define R520_MC_FB_LOCATION 0x04
512#define R520_MC_AGP_LOCATION 0x05 530#define R520_MC_AGP_LOCATION 0x05
531#define R520_MC_AGP_BASE 0x06
532#define R520_MC_AGP_BASE_2 0x07
513 533
514#define RADEON_MPP_TB_CONFIG 0x01c0 534#define RADEON_MPP_TB_CONFIG 0x01c0
515#define RADEON_MEM_CNTL 0x0140 535#define RADEON_MEM_CNTL 0x0140
516#define RADEON_MEM_SDRAM_MODE_REG 0x0158 536#define RADEON_MEM_SDRAM_MODE_REG 0x0158
537#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
538#define RS480_AGP_BASE_2 0x0164
517#define RADEON_AGP_BASE 0x0170 539#define RADEON_AGP_BASE 0x0170
518 540
541/* pipe config regs */
542#define R400_GB_PIPE_SELECT 0x402c
543#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
544#define R500_SU_REG_DEST 0x42c8
545#define R300_GB_TILE_CONFIG 0x4018
546# define R300_ENABLE_TILING (1 << 0)
547# define R300_PIPE_COUNT_RV350 (0 << 1)
548# define R300_PIPE_COUNT_R300 (3 << 1)
549# define R300_PIPE_COUNT_R420_3P (6 << 1)
550# define R300_PIPE_COUNT_R420 (7 << 1)
551# define R300_TILE_SIZE_8 (0 << 4)
552# define R300_TILE_SIZE_16 (1 << 4)
553# define R300_TILE_SIZE_32 (2 << 4)
554# define R300_SUBPIXEL_1_12 (0 << 16)
555# define R300_SUBPIXEL_1_16 (1 << 16)
556#define R300_DST_PIPE_CONFIG 0x170c
557# define R300_PIPE_AUTO_CONFIG (1 << 31)
558#define R300_RB2D_DSTCACHE_MODE 0x3428
559# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
560# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
561
519#define RADEON_RB3D_COLOROFFSET 0x1c40 562#define RADEON_RB3D_COLOROFFSET 0x1c40
520#define RADEON_RB3D_COLORPITCH 0x1c48 563#define RADEON_RB3D_COLORPITCH 0x1c48
521 564
@@ -561,12 +604,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
561 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 604 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
562 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 605 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
563 606
564#define RADEON_CRTC_CRNT_FRAME 0x0214
565#define RADEON_CRTC2_CRNT_FRAME 0x0314
566
567#define RADEON_CRTC_STATUS 0x005c
568#define RADEON_CRTC2_STATUS 0x03fc
569
570#define RADEON_GEN_INT_CNTL 0x0040 607#define RADEON_GEN_INT_CNTL 0x0040
571# define RADEON_CRTC_VBLANK_MASK (1 << 0) 608# define RADEON_CRTC_VBLANK_MASK (1 << 0)
572# define RADEON_CRTC2_VBLANK_MASK (1 << 9) 609# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
@@ -625,11 +662,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
625#define RADEON_PP_TXFILTER_1 0x1c6c 662#define RADEON_PP_TXFILTER_1 0x1c6c
626#define RADEON_PP_TXFILTER_2 0x1c84 663#define RADEON_PP_TXFILTER_2 0x1c84
627 664
628#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 665#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
629# define RADEON_RB2D_DC_FLUSH (3 << 0) 666#define R300_DSTCACHE_CTLSTAT 0x1714
630# define RADEON_RB2D_DC_FREE (3 << 2) 667# define R300_RB2D_DC_FLUSH (3 << 0)
631# define RADEON_RB2D_DC_FLUSH_ALL 0xf 668# define R300_RB2D_DC_FREE (3 << 2)
632# define RADEON_RB2D_DC_BUSY (1 << 31) 669# define R300_RB2D_DC_FLUSH_ALL 0xf
670# define R300_RB2D_DC_BUSY (1 << 31)
633#define RADEON_RB3D_CNTL 0x1c3c 671#define RADEON_RB3D_CNTL 0x1c3c
634# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 672# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
635# define RADEON_PLANE_MASK_ENABLE (1 << 1) 673# define RADEON_PLANE_MASK_ENABLE (1 << 1)
@@ -652,11 +690,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
652# define RADEON_RB3D_ZC_FREE (1 << 2) 690# define RADEON_RB3D_ZC_FREE (1 << 2)
653# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 691# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
654# define RADEON_RB3D_ZC_BUSY (1 << 31) 692# define RADEON_RB3D_ZC_BUSY (1 << 31)
693#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
694# define R300_ZC_FLUSH (1 << 0)
695# define R300_ZC_FREE (1 << 1)
696# define R300_ZC_FLUSH_ALL 0x3
697# define R300_ZC_BUSY (1 << 31)
655#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 698#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
656# define RADEON_RB3D_DC_FLUSH (3 << 0) 699# define RADEON_RB3D_DC_FLUSH (3 << 0)
657# define RADEON_RB3D_DC_FREE (3 << 2) 700# define RADEON_RB3D_DC_FREE (3 << 2)
658# define RADEON_RB3D_DC_FLUSH_ALL 0xf 701# define RADEON_RB3D_DC_FLUSH_ALL 0xf
659# define RADEON_RB3D_DC_BUSY (1 << 31) 702# define RADEON_RB3D_DC_BUSY (1 << 31)
703#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
704# define R300_RB3D_DC_FINISH (1 << 4)
660#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 705#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
661# define RADEON_Z_TEST_MASK (7 << 4) 706# define RADEON_Z_TEST_MASK (7 << 4)
662# define RADEON_Z_TEST_ALWAYS (7 << 4) 707# define RADEON_Z_TEST_ALWAYS (7 << 4)
@@ -1066,6 +1111,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
1066 1111
1067#define R200_VAP_PVS_CNTL_1 0x22D0 1112#define R200_VAP_PVS_CNTL_1 0x22D0
1068 1113
1114#define R500_D1CRTC_STATUS 0x609c
1115#define R500_D2CRTC_STATUS 0x689c
1116#define R500_CRTC_V_BLANK (1<<0)
1117
1118#define R500_D1CRTC_FRAME_COUNT 0x60a4
1119#define R500_D2CRTC_FRAME_COUNT 0x68a4
1120
1121#define R500_D1MODE_V_COUNTER 0x6530
1122#define R500_D2MODE_V_COUNTER 0x6d30
1123
1124#define R500_D1MODE_VBLANK_STATUS 0x6534
1125#define R500_D2MODE_VBLANK_STATUS 0x6d34
1126#define R500_VBLANK_OCCURED (1<<0)
1127#define R500_VBLANK_ACK (1<<4)
1128#define R500_VBLANK_STAT (1<<12)
1129#define R500_VBLANK_INT (1<<16)
1130
1131#define R500_DxMODE_INT_MASK 0x6540
1132#define R500_D1MODE_INT_MASK (1<<0)
1133#define R500_D2MODE_INT_MASK (1<<8)
1134
1135#define R500_DISP_INTERRUPT_STATUS 0x7edc
1136#define R500_D1_VBLANK_INTERRUPT (1 << 4)
1137#define R500_D2_VBLANK_INTERRUPT (1 << 5)
1138
1069/* Constants */ 1139/* Constants */
1070#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1140#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1071 1141
@@ -1087,42 +1157,50 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
1087#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1157#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1088#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1158#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1089 1159
1090#define RADEON_WRITE_PLL( addr, val ) \ 1160#define RADEON_WRITE_PLL(addr, val) \
1091do { \ 1161do { \
1092 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 1162 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1093 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1163 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1094 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 1164 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1095} while (0) 1165} while (0)
1096 1166
1097#define RADEON_WRITE_IGPGART( addr, val ) \ 1167#define RADEON_WRITE_PCIE(addr, val) \
1098do { \ 1168do { \
1099 RADEON_WRITE( RADEON_IGPGART_INDEX, \ 1169 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1100 ((addr) & 0x7f) | (1 << 8)); \ 1170 ((addr) & 0xff)); \
1101 RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \ 1171 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1102 RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
1103} while (0) 1172} while (0)
1104 1173
1105#define RADEON_WRITE_PCIE( addr, val ) \ 1174#define R500_WRITE_MCIND(addr, val) \
1106do { \ 1175do { \
1107 RADEON_WRITE8( RADEON_PCIE_INDEX, \ 1176 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1108 ((addr) & 0xff)); \ 1177 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1109 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 1178 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1110} while (0) 1179} while (0)
1111 1180
1112#define RADEON_WRITE_MCIND( addr, val ) \ 1181#define RS480_WRITE_MCIND(addr, val) \
1113 do { \ 1182do { \
1114 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1183 RADEON_WRITE(RS480_NB_MC_INDEX, \
1115 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1184 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1116 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1185 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1117 } while (0) 1186 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1187} while (0)
1118 1188
1119#define RS690_WRITE_MCIND( addr, val ) \ 1189#define RS690_WRITE_MCIND(addr, val) \
1120do { \ 1190do { \
1121 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1191 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1122 RADEON_WRITE(RS690_MC_DATA, val); \ 1192 RADEON_WRITE(RS690_MC_DATA, val); \
1123 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1193 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1124} while (0) 1194} while (0)
1125 1195
1196#define IGP_WRITE_MCIND(addr, val) \
1197do { \
1198 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
1199 RS690_WRITE_MCIND(addr, val); \
1200 else \
1201 RS480_WRITE_MCIND(addr, val); \
1202} while (0)
1203
1126#define CP_PACKET0( reg, n ) \ 1204#define CP_PACKET0( reg, n ) \
1127 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1205 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1128#define CP_PACKET0_TABLE( reg, n ) \ 1206#define CP_PACKET0_TABLE( reg, n ) \
@@ -1163,23 +1241,43 @@ do { \
1163} while (0) 1241} while (0)
1164 1242
1165#define RADEON_FLUSH_CACHE() do { \ 1243#define RADEON_FLUSH_CACHE() do { \
1166 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ 1244 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1167 OUT_RING( RADEON_RB3D_DC_FLUSH ); \ 1245 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1246 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1247 } else { \
1248 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1249 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1250 } \
1168} while (0) 1251} while (0)
1169 1252
1170#define RADEON_PURGE_CACHE() do { \ 1253#define RADEON_PURGE_CACHE() do { \
1171 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ 1254 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1172 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \ 1255 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1256 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1257 } else { \
1258 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1259 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1260 } \
1173} while (0) 1261} while (0)
1174 1262
1175#define RADEON_FLUSH_ZCACHE() do { \ 1263#define RADEON_FLUSH_ZCACHE() do { \
1176 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1264 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1177 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 1265 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1266 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1267 } else { \
1268 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1269 OUT_RING(R300_ZC_FLUSH); \
1270 } \
1178} while (0) 1271} while (0)
1179 1272
1180#define RADEON_PURGE_ZCACHE() do { \ 1273#define RADEON_PURGE_ZCACHE() do { \
1181 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1274 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1182 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 1275 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1276 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
1277 } else { \
1278 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1279 OUT_RING(R300_ZC_FLUSH_ALL); \
1280 } \
1183} while (0) 1281} while (0)
1184 1282
1185/* ================================================================ 1283/* ================================================================
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 12:15:34 -0500