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-rw-r--r--drivers/char/drm/radeon_drv.h24
1 files changed, 13 insertions, 11 deletions
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index c37f2ea20783..498b19b1d641 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -38,7 +38,7 @@
38 38
39#define DRIVER_NAME "radeon" 39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon" 40#define DRIVER_DESC "ATI Radeon"
41#define DRIVER_DATE "20050911" 41#define DRIVER_DATE "20051229"
42 42
43/* Interface history: 43/* Interface history:
44 * 44 *
@@ -73,7 +73,7 @@
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200 74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading) 76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl. 78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling 79 * 1.14- Add support for color tiling
@@ -88,14 +88,13 @@
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300 90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
91 */ 93 */
92#define DRIVER_MAJOR 1 94#define DRIVER_MAJOR 1
93#define DRIVER_MINOR 19 95#define DRIVER_MINOR 21
94#define DRIVER_PATCHLEVEL 0 96#define DRIVER_PATCHLEVEL 0
95 97
96#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
97#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
98
99/* 98/*
100 * Radeon chip families 99 * Radeon chip families
101 */ 100 */
@@ -138,6 +137,9 @@ enum radeon_chip_flags {
138 CHIP_IS_PCIE = 0x00200000UL, 137 CHIP_IS_PCIE = 0x00200000UL,
139}; 138};
140 139
140#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
141#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
142
141typedef struct drm_radeon_freelist { 143typedef struct drm_radeon_freelist {
142 unsigned int age; 144 unsigned int age;
143 drm_buf_t *buf; 145 drm_buf_t *buf;
@@ -214,8 +216,6 @@ typedef struct drm_radeon_private {
214 216
215 int microcode_version; 217 int microcode_version;
216 218
217 int is_pci;
218
219 struct { 219 struct {
220 u32 boxes; 220 u32 boxes;
221 int freelist_timeouts; 221 int freelist_timeouts;
@@ -247,8 +247,6 @@ typedef struct drm_radeon_private {
247 247
248 drm_radeon_depth_clear_t depth_clear; 248 drm_radeon_depth_clear_t depth_clear;
249 249
250 unsigned long fb_offset;
251 unsigned long mmio_offset;
252 unsigned long ring_offset; 250 unsigned long ring_offset;
253 unsigned long ring_rptr_offset; 251 unsigned long ring_rptr_offset;
254 unsigned long buffers_offset; 252 unsigned long buffers_offset;
@@ -362,6 +360,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
362 */ 360 */
363 361
364#define RADEON_AGP_COMMAND 0x0f60 362#define RADEON_AGP_COMMAND 0x0f60
363#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
364# define RADEON_AGP_ENABLE (1<<8)
365#define RADEON_AUX_SCISSOR_CNTL 0x26f0 365#define RADEON_AUX_SCISSOR_CNTL 0x26f0
366# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 366# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
367# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 367# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
@@ -377,6 +377,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
377# define RADEON_PLL_WR_EN (1 << 7) 377# define RADEON_PLL_WR_EN (1 << 7)
378#define RADEON_CLOCK_CNTL_INDEX 0x0008 378#define RADEON_CLOCK_CNTL_INDEX 0x0008
379#define RADEON_CONFIG_APER_SIZE 0x0108 379#define RADEON_CONFIG_APER_SIZE 0x0108
380#define RADEON_CONFIG_MEMSIZE 0x00f8
380#define RADEON_CRTC_OFFSET 0x0224 381#define RADEON_CRTC_OFFSET 0x0224
381#define RADEON_CRTC_OFFSET_CNTL 0x0228 382#define RADEON_CRTC_OFFSET_CNTL 0x0228
382# define RADEON_CRTC_TILE_EN (1 << 15) 383# define RADEON_CRTC_TILE_EN (1 << 15)
@@ -648,6 +649,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
648 649
649#define RADEON_WAIT_UNTIL 0x1720 650#define RADEON_WAIT_UNTIL 0x1720
650# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 651# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
652# define RADEON_WAIT_2D_IDLE (1 << 14)
653# define RADEON_WAIT_3D_IDLE (1 << 15)
651# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 654# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
652# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 655# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
653# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 656# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
@@ -1102,7 +1105,6 @@ do { \
1102 write = 0; \ 1105 write = 0; \
1103 _tab += _i; \ 1106 _tab += _i; \
1104 } \ 1107 } \
1105 \
1106 while (_size > 0) { \ 1108 while (_size > 0) { \
1107 *(ring + write) = *_tab++; \ 1109 *(ring + write) = *_tab++; \
1108 write++; \ 1110 write++; \