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path: root/drivers/char/drm/radeon_drv.h
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Diffstat (limited to 'drivers/char/drm/radeon_drv.h')
-rw-r--r--drivers/char/drm/radeon_drv.h91
1 files changed, 81 insertions, 10 deletions
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index bfbb60a9298c..4434332c79bc 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -123,6 +123,12 @@ enum radeon_family {
123 CHIP_R420, 123 CHIP_R420,
124 CHIP_RV410, 124 CHIP_RV410,
125 CHIP_RS400, 125 CHIP_RS400,
126 CHIP_RV515,
127 CHIP_R520,
128 CHIP_RV530,
129 CHIP_RV560,
130 CHIP_RV570,
131 CHIP_R580,
126 CHIP_LAST, 132 CHIP_LAST,
127}; 133};
128 134
@@ -166,6 +172,12 @@ typedef struct drm_radeon_ring_buffer {
166 int size; 172 int size;
167 int size_l2qw; 173 int size_l2qw;
168 174
175 int rptr_update; /* Double Words */
176 int rptr_update_l2qw; /* log2 Quad Words */
177
178 int fetch_size; /* Double Words */
179 int fetch_size_l2ow; /* log2 Oct Words */
180
169 u32 tail; 181 u32 tail;
170 u32 tail_mask; 182 u32 tail_mask;
171 int space; 183 int space;
@@ -336,6 +348,7 @@ extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file
336extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 348extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
337extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 349extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
338extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 350extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
351extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
339 352
340extern void radeon_freelist_reset(struct drm_device * dev); 353extern void radeon_freelist_reset(struct drm_device * dev);
341extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 354extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
@@ -382,7 +395,7 @@ extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
382 unsigned long arg); 395 unsigned long arg);
383 396
384/* r300_cmdbuf.c */ 397/* r300_cmdbuf.c */
385extern void r300_init_reg_flags(void); 398extern void r300_init_reg_flags(struct drm_device *dev);
386 399
387extern int r300_do_cp_cmdbuf(struct drm_device * dev, 400extern int r300_do_cp_cmdbuf(struct drm_device * dev,
388 struct drm_file *file_priv, 401 struct drm_file *file_priv,
@@ -429,7 +442,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
429#define RADEON_PCIE_INDEX 0x0030 442#define RADEON_PCIE_INDEX 0x0030
430#define RADEON_PCIE_DATA 0x0034 443#define RADEON_PCIE_DATA 0x0034
431#define RADEON_PCIE_TX_GART_CNTL 0x10 444#define RADEON_PCIE_TX_GART_CNTL 0x10
432# define RADEON_PCIE_TX_GART_EN (1 << 0) 445# define RADEON_PCIE_TX_GART_EN (1 << 0)
433# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) 446# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
434# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) 447# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
435# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) 448# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
@@ -439,7 +452,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
439# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) 452# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
440#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 453#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
441#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 454#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
442#define RADEON_PCIE_TX_GART_BASE 0x13 455#define RADEON_PCIE_TX_GART_BASE 0x13
443#define RADEON_PCIE_TX_GART_START_LO 0x14 456#define RADEON_PCIE_TX_GART_START_LO 0x14
444#define RADEON_PCIE_TX_GART_START_HI 0x15 457#define RADEON_PCIE_TX_GART_START_HI 0x15
445#define RADEON_PCIE_TX_GART_END_LO 0x16 458#define RADEON_PCIE_TX_GART_END_LO 0x16
@@ -454,6 +467,16 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
454#define RADEON_IGPGART_ENABLE 0x38 467#define RADEON_IGPGART_ENABLE 0x38
455#define RADEON_IGPGART_UNK_39 0x39 468#define RADEON_IGPGART_UNK_39 0x39
456 469
470#define R520_MC_IND_INDEX 0x70
471#define R520_MC_IND_WR_EN (1<<24)
472#define R520_MC_IND_DATA 0x74
473
474#define RV515_MC_FB_LOCATION 0x01
475#define RV515_MC_AGP_LOCATION 0x02
476
477#define R520_MC_FB_LOCATION 0x04
478#define R520_MC_AGP_LOCATION 0x05
479
457#define RADEON_MPP_TB_CONFIG 0x01c0 480#define RADEON_MPP_TB_CONFIG 0x01c0
458#define RADEON_MEM_CNTL 0x0140 481#define RADEON_MEM_CNTL 0x0140
459#define RADEON_MEM_SDRAM_MODE_REG 0x0158 482#define RADEON_MEM_SDRAM_MODE_REG 0x0158
@@ -512,12 +535,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
512 535
513#define RADEON_GEN_INT_STATUS 0x0044 536#define RADEON_GEN_INT_STATUS 0x0044
514# define RADEON_CRTC_VBLANK_STAT (1 << 0) 537# define RADEON_CRTC_VBLANK_STAT (1 << 0)
515# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 538# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
516# define RADEON_CRTC2_VBLANK_STAT (1 << 9) 539# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
517# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 540# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
518# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 541# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
519# define RADEON_SW_INT_TEST (1 << 25) 542# define RADEON_SW_INT_TEST (1 << 25)
520# define RADEON_SW_INT_TEST_ACK (1 << 25) 543# define RADEON_SW_INT_TEST_ACK (1 << 25)
521# define RADEON_SW_INT_FIRE (1 << 26) 544# define RADEON_SW_INT_FIRE (1 << 26)
522 545
523#define RADEON_HOST_PATH_CNTL 0x0130 546#define RADEON_HOST_PATH_CNTL 0x0130
@@ -615,9 +638,51 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
615# define RADEON_SOFT_RESET_E2 (1 << 5) 638# define RADEON_SOFT_RESET_E2 (1 << 5)
616# define RADEON_SOFT_RESET_RB (1 << 6) 639# define RADEON_SOFT_RESET_RB (1 << 6)
617# define RADEON_SOFT_RESET_HDP (1 << 7) 640# define RADEON_SOFT_RESET_HDP (1 << 7)
641/*
642 * 6:0 Available slots in the FIFO
643 * 8 Host Interface active
644 * 9 CP request active
645 * 10 FIFO request active
646 * 11 Host Interface retry active
647 * 12 CP retry active
648 * 13 FIFO retry active
649 * 14 FIFO pipeline busy
650 * 15 Event engine busy
651 * 16 CP command stream busy
652 * 17 2D engine busy
653 * 18 2D portion of render backend busy
654 * 20 3D setup engine busy
655 * 26 GA engine busy
656 * 27 CBA 2D engine busy
657 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
658 * command stream queue not empty or Ring Buffer not empty
659 */
618#define RADEON_RBBM_STATUS 0x0e40 660#define RADEON_RBBM_STATUS 0x0e40
661/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
662/* #define RADEON_RBBM_STATUS 0x1740 */
663/* bits 6:0 are dword slots available in the cmd fifo */
619# define RADEON_RBBM_FIFOCNT_MASK 0x007f 664# define RADEON_RBBM_FIFOCNT_MASK 0x007f
620# define RADEON_RBBM_ACTIVE (1 << 31) 665# define RADEON_HIRQ_ON_RBB (1 << 8)
666# define RADEON_CPRQ_ON_RBB (1 << 9)
667# define RADEON_CFRQ_ON_RBB (1 << 10)
668# define RADEON_HIRQ_IN_RTBUF (1 << 11)
669# define RADEON_CPRQ_IN_RTBUF (1 << 12)
670# define RADEON_CFRQ_IN_RTBUF (1 << 13)
671# define RADEON_PIPE_BUSY (1 << 14)
672# define RADEON_ENG_EV_BUSY (1 << 15)
673# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
674# define RADEON_E2_BUSY (1 << 17)
675# define RADEON_RB2D_BUSY (1 << 18)
676# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
677# define RADEON_VAP_BUSY (1 << 20)
678# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
679# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
680# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
681# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
682# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
683# define RADEON_GA_BUSY (1 << 26)
684# define RADEON_CBA2D_BUSY (1 << 27)
685# define RADEON_RBBM_ACTIVE (1 << 31)
621#define RADEON_RE_LINE_PATTERN 0x1cd0 686#define RADEON_RE_LINE_PATTERN 0x1cd0
622#define RADEON_RE_MISC 0x26c4 687#define RADEON_RE_MISC 0x26c4
623#define RADEON_RE_TOP_LEFT 0x26c0 688#define RADEON_RE_TOP_LEFT 0x26c0
@@ -1004,6 +1069,13 @@ do { \
1004 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 1069 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
1005} while (0) 1070} while (0)
1006 1071
1072#define RADEON_WRITE_MCIND( addr, val ) \
1073 do { \
1074 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1075 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1076 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1077 } while (0)
1078
1007#define CP_PACKET0( reg, n ) \ 1079#define CP_PACKET0( reg, n ) \
1008 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1080 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1009#define CP_PACKET0_TABLE( reg, n ) \ 1081#define CP_PACKET0_TABLE( reg, n ) \
@@ -1114,8 +1186,7 @@ do { \
1114 1186
1115#define BEGIN_RING( n ) do { \ 1187#define BEGIN_RING( n ) do { \
1116 if ( RADEON_VERBOSE ) { \ 1188 if ( RADEON_VERBOSE ) { \
1117 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ 1189 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1118 n, __FUNCTION__ ); \
1119 } \ 1190 } \
1120 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 1191 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1121 COMMIT_RING(); \ 1192 COMMIT_RING(); \
@@ -1133,7 +1204,7 @@ do { \
1133 write, dev_priv->ring.tail ); \ 1204 write, dev_priv->ring.tail ); \
1134 } \ 1205 } \
1135 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 1206 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1136 DRM_ERROR( \ 1207 DRM_ERROR( \
1137 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 1208 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1138 ((dev_priv->ring.tail + _nr) & mask), \ 1209 ((dev_priv->ring.tail + _nr) & mask), \
1139 write, __LINE__); \ 1210 write, __LINE__); \
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-28 08:36:48 -0500