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-rw-r--r--drivers/char/drm/radeon_drm.h286
1 files changed, 144 insertions, 142 deletions
diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h
index 3792798270a4..1cd81a671a36 100644
--- a/drivers/char/drm/radeon_drm.h
+++ b/drivers/char/drm/radeon_drm.h
@@ -57,78 +57,77 @@
57#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 57#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
58#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 58#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
59#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 59#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
60#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ 60#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
61#define RADEON_REQUIRE_QUIESCENCE 0x00010000 61#define RADEON_REQUIRE_QUIESCENCE 0x00010000
62#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ 62#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
63#define RADEON_UPLOAD_ALL 0x003effff 63#define RADEON_UPLOAD_ALL 0x003effff
64#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 64#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
65 65
66
67/* New style per-packet identifiers for use in cmd_buffer ioctl with 66/* New style per-packet identifiers for use in cmd_buffer ioctl with
68 * the RADEON_EMIT_PACKET command. Comments relate new packets to old 67 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
69 * state bits and the packet size: 68 * state bits and the packet size:
70 */ 69 */
71#define RADEON_EMIT_PP_MISC 0 /* context/7 */ 70#define RADEON_EMIT_PP_MISC 0 /* context/7 */
72#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ 71#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
73#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ 72#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
74#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ 73#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
75#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ 74#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
76#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ 75#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
77#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ 76#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
78#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ 77#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
79#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ 78#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
80#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ 79#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
81#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ 80#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
82#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ 81#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
83#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ 82#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
84#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ 83#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
85#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ 84#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
86#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ 85#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
87#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ 86#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
88#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ 87#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
89#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ 88#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
90#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ 89#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
91#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ 90#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
92#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ 91#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
93#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ 92#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
94#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ 93#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
95#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ 94#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
96#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ 95#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
97#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ 96#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
98#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ 97#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
99#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ 98#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
100#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ 99#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
101#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ 100#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
102#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ 101#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
103#define R200_EMIT_VAP_CTL 32 /* vap/1 */ 102#define R200_EMIT_VAP_CTL 32 /* vap/1 */
104#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ 103#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
105#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ 104#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
106#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ 105#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
107#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ 106#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
108#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ 107#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
109#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ 108#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
110#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ 109#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
111#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ 110#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
112#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ 111#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
113#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ 112#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
114#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ 113#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
115#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ 114#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
116#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ 115#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
117#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ 116#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
118#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ 117#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
119#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ 118#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
120#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ 119#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
121#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ 120#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
122#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ 121#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
123#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ 122#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
124#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ 123#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
125#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ 124#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
126#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ 125#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
127#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ 126#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
128#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ 127#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
129#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ 128#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
130#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ 129#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
131#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ 130#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
132#define R200_EMIT_PP_CUBIC_FACES_0 61 131#define R200_EMIT_PP_CUBIC_FACES_0 61
133#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 132#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
134#define R200_EMIT_PP_CUBIC_FACES_1 63 133#define R200_EMIT_PP_CUBIC_FACES_1 63
@@ -153,42 +152,50 @@
153#define RADEON_EMIT_PP_CUBIC_FACES_2 82 152#define RADEON_EMIT_PP_CUBIC_FACES_2 82
154#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 153#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
155#define R200_EMIT_PP_TRI_PERF_CNTL 84 154#define R200_EMIT_PP_TRI_PERF_CNTL 84
156#define RADEON_MAX_STATE_PACKETS 85 155#define R200_EMIT_PP_AFS_0 85
156#define R200_EMIT_PP_AFS_1 86
157#define R200_EMIT_ATF_TFACTOR 87
158#define R200_EMIT_PP_TXCTLALL_0 88
159#define R200_EMIT_PP_TXCTLALL_1 89
160#define R200_EMIT_PP_TXCTLALL_2 90
161#define R200_EMIT_PP_TXCTLALL_3 91
162#define R200_EMIT_PP_TXCTLALL_4 92
163#define R200_EMIT_PP_TXCTLALL_5 93
164#define RADEON_MAX_STATE_PACKETS 94
157 165
158/* Commands understood by cmd_buffer ioctl. More can be added but 166/* Commands understood by cmd_buffer ioctl. More can be added but
159 * obviously these can't be removed or changed: 167 * obviously these can't be removed or changed:
160 */ 168 */
161#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ 169#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
162#define RADEON_CMD_SCALARS 2 /* emit scalar data */ 170#define RADEON_CMD_SCALARS 2 /* emit scalar data */
163#define RADEON_CMD_VECTORS 3 /* emit vector data */ 171#define RADEON_CMD_VECTORS 3 /* emit vector data */
164#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ 172#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
165#define RADEON_CMD_PACKET3 5 /* emit hw packet */ 173#define RADEON_CMD_PACKET3 5 /* emit hw packet */
166#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ 174#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
167#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ 175#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
168#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: 176#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
169 * doesn't make the cpu wait, just 177 * doesn't make the cpu wait, just
170 * the graphics hardware */ 178 * the graphics hardware */
171
172 179
173typedef union { 180typedef union {
174 int i; 181 int i;
175 struct { 182 struct {
176 unsigned char cmd_type, pad0, pad1, pad2; 183 unsigned char cmd_type, pad0, pad1, pad2;
177 } header; 184 } header;
178 struct { 185 struct {
179 unsigned char cmd_type, packet_id, pad0, pad1; 186 unsigned char cmd_type, packet_id, pad0, pad1;
180 } packet; 187 } packet;
181 struct { 188 struct {
182 unsigned char cmd_type, offset, stride, count; 189 unsigned char cmd_type, offset, stride, count;
183 } scalars; 190 } scalars;
184 struct { 191 struct {
185 unsigned char cmd_type, offset, stride, count; 192 unsigned char cmd_type, offset, stride, count;
186 } vectors; 193 } vectors;
187 struct { 194 struct {
188 unsigned char cmd_type, buf_idx, pad0, pad1; 195 unsigned char cmd_type, buf_idx, pad0, pad1;
189 } dma; 196 } dma;
190 struct { 197 struct {
191 unsigned char cmd_type, flags, pad0, pad1; 198 unsigned char cmd_type, flags, pad0, pad1;
192 } wait; 199 } wait;
193} drm_radeon_cmd_header_t; 200} drm_radeon_cmd_header_t;
194 201
@@ -204,10 +211,10 @@ typedef union {
204 * The interface has not been stabilized, so some of these may be removed 211 * The interface has not been stabilized, so some of these may be removed
205 * and eventually reordered before stabilization. 212 * and eventually reordered before stabilization.
206 */ 213 */
207#define R300_CMD_PACKET0 1 214#define R300_CMD_PACKET0 1
208#define R300_CMD_VPU 2 /* emit vertex program upload */ 215#define R300_CMD_VPU 2 /* emit vertex program upload */
209#define R300_CMD_PACKET3 3 /* emit a packet3 */ 216#define R300_CMD_PACKET3 3 /* emit a packet3 */
210#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ 217#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
211#define R300_CMD_CP_DELAY 5 218#define R300_CMD_CP_DELAY 5
212#define R300_CMD_DMA_DISCARD 6 219#define R300_CMD_DMA_DISCARD 6
213#define R300_CMD_WAIT 7 220#define R300_CMD_WAIT 7
@@ -232,13 +239,13 @@ typedef union {
232 } packet3; 239 } packet3;
233 struct { 240 struct {
234 unsigned char cmd_type, packet; 241 unsigned char cmd_type, packet;
235 unsigned short count; /* amount of packet2 to emit */ 242 unsigned short count; /* amount of packet2 to emit */
236 } delay; 243 } delay;
237 struct { 244 struct {
238 unsigned char cmd_type, buf_idx, pad0, pad1; 245 unsigned char cmd_type, buf_idx, pad0, pad1;
239 } dma; 246 } dma;
240 struct { 247 struct {
241 unsigned char cmd_type, flags, pad0, pad1; 248 unsigned char cmd_type, flags, pad0, pad1;
242 } wait; 249 } wait;
243} drm_r300_cmd_header_t; 250} drm_r300_cmd_header_t;
244 251
@@ -292,7 +299,7 @@ typedef union {
292#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 299#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
293#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 300#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
294 301
295#endif /* __RADEON_SAREA_DEFINES__ */ 302#endif /* __RADEON_SAREA_DEFINES__ */
296 303
297typedef struct { 304typedef struct {
298 unsigned int red; 305 unsigned int red;
@@ -303,7 +310,7 @@ typedef struct {
303 310
304typedef struct { 311typedef struct {
305 /* Context state */ 312 /* Context state */
306 unsigned int pp_misc; /* 0x1c14 */ 313 unsigned int pp_misc; /* 0x1c14 */
307 unsigned int pp_fog_color; 314 unsigned int pp_fog_color;
308 unsigned int re_solid_color; 315 unsigned int re_solid_color;
309 unsigned int rb3d_blendcntl; 316 unsigned int rb3d_blendcntl;
@@ -311,7 +318,7 @@ typedef struct {
311 unsigned int rb3d_depthpitch; 318 unsigned int rb3d_depthpitch;
312 unsigned int rb3d_zstencilcntl; 319 unsigned int rb3d_zstencilcntl;
313 320
314 unsigned int pp_cntl; /* 0x1c38 */ 321 unsigned int pp_cntl; /* 0x1c38 */
315 unsigned int rb3d_cntl; 322 unsigned int rb3d_cntl;
316 unsigned int rb3d_coloroffset; 323 unsigned int rb3d_coloroffset;
317 unsigned int re_width_height; 324 unsigned int re_width_height;
@@ -319,27 +326,27 @@ typedef struct {
319 unsigned int se_cntl; 326 unsigned int se_cntl;
320 327
321 /* Vertex format state */ 328 /* Vertex format state */
322 unsigned int se_coord_fmt; /* 0x1c50 */ 329 unsigned int se_coord_fmt; /* 0x1c50 */
323 330
324 /* Line state */ 331 /* Line state */
325 unsigned int re_line_pattern; /* 0x1cd0 */ 332 unsigned int re_line_pattern; /* 0x1cd0 */
326 unsigned int re_line_state; 333 unsigned int re_line_state;
327 334
328 unsigned int se_line_width; /* 0x1db8 */ 335 unsigned int se_line_width; /* 0x1db8 */
329 336
330 /* Bumpmap state */ 337 /* Bumpmap state */
331 unsigned int pp_lum_matrix; /* 0x1d00 */ 338 unsigned int pp_lum_matrix; /* 0x1d00 */
332 339
333 unsigned int pp_rot_matrix_0; /* 0x1d58 */ 340 unsigned int pp_rot_matrix_0; /* 0x1d58 */
334 unsigned int pp_rot_matrix_1; 341 unsigned int pp_rot_matrix_1;
335 342
336 /* Mask state */ 343 /* Mask state */
337 unsigned int rb3d_stencilrefmask; /* 0x1d7c */ 344 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
338 unsigned int rb3d_ropcntl; 345 unsigned int rb3d_ropcntl;
339 unsigned int rb3d_planemask; 346 unsigned int rb3d_planemask;
340 347
341 /* Viewport state */ 348 /* Viewport state */
342 unsigned int se_vport_xscale; /* 0x1d98 */ 349 unsigned int se_vport_xscale; /* 0x1d98 */
343 unsigned int se_vport_xoffset; 350 unsigned int se_vport_xoffset;
344 unsigned int se_vport_yscale; 351 unsigned int se_vport_yscale;
345 unsigned int se_vport_yoffset; 352 unsigned int se_vport_yoffset;
@@ -347,20 +354,19 @@ typedef struct {
347 unsigned int se_vport_zoffset; 354 unsigned int se_vport_zoffset;
348 355
349 /* Setup state */ 356 /* Setup state */
350 unsigned int se_cntl_status; /* 0x2140 */ 357 unsigned int se_cntl_status; /* 0x2140 */
351 358
352 /* Misc state */ 359 /* Misc state */
353 unsigned int re_top_left; /* 0x26c0 */ 360 unsigned int re_top_left; /* 0x26c0 */
354 unsigned int re_misc; 361 unsigned int re_misc;
355} drm_radeon_context_regs_t; 362} drm_radeon_context_regs_t;
356 363
357typedef struct { 364typedef struct {
358 /* Zbias state */ 365 /* Zbias state */
359 unsigned int se_zbias_factor; /* 0x1dac */ 366 unsigned int se_zbias_factor; /* 0x1dac */
360 unsigned int se_zbias_constant; 367 unsigned int se_zbias_constant;
361} drm_radeon_context2_regs_t; 368} drm_radeon_context2_regs_t;
362 369
363
364/* Setup registers for each texture unit 370/* Setup registers for each texture unit
365 */ 371 */
366typedef struct { 372typedef struct {
@@ -378,11 +384,10 @@ typedef struct {
378 unsigned int finish; 384 unsigned int finish;
379 unsigned int prim:8; 385 unsigned int prim:8;
380 unsigned int stateidx:8; 386 unsigned int stateidx:8;
381 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ 387 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
382 unsigned int vc_format; /* vertex format */ 388 unsigned int vc_format; /* vertex format */
383} drm_radeon_prim_t; 389} drm_radeon_prim_t;
384 390
385
386typedef struct { 391typedef struct {
387 drm_radeon_context_regs_t context; 392 drm_radeon_context_regs_t context;
388 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 393 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
@@ -390,7 +395,6 @@ typedef struct {
390 unsigned int dirty; 395 unsigned int dirty;
391} drm_radeon_state_t; 396} drm_radeon_state_t;
392 397
393
394typedef struct { 398typedef struct {
395 /* The channel for communication of state information to the 399 /* The channel for communication of state information to the
396 * kernel on firing a vertex buffer with either of the 400 * kernel on firing a vertex buffer with either of the
@@ -413,16 +417,16 @@ typedef struct {
413 unsigned int last_dispatch; 417 unsigned int last_dispatch;
414 unsigned int last_clear; 418 unsigned int last_clear;
415 419
416 drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1]; 420 drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
421 1];
417 unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 422 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
418 int ctx_owner; 423 int ctx_owner;
419 int pfState; /* number of 3d windows (0,1,2ormore) */ 424 int pfState; /* number of 3d windows (0,1,2ormore) */
420 int pfCurrentPage; /* which buffer is being displayed? */ 425 int pfCurrentPage; /* which buffer is being displayed? */
421 int crtc2_base; /* CRTC2 frame offset */ 426 int crtc2_base; /* CRTC2 frame offset */
422 int tiling_enabled; /* set by drm, read by 2d + 3d clients */ 427 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
423} drm_radeon_sarea_t; 428} drm_radeon_sarea_t;
424 429
425
426/* WARNING: If you change any of these defines, make sure to change the 430/* WARNING: If you change any of these defines, make sure to change the
427 * defines in the Xserver file (xf86drmRadeon.h) 431 * defines in the Xserver file (xf86drmRadeon.h)
428 * 432 *
@@ -432,15 +436,15 @@ typedef struct {
432/* Radeon specific ioctls 436/* Radeon specific ioctls
433 * The device specific ioctl range is 0x40 to 0x79. 437 * The device specific ioctl range is 0x40 to 0x79.
434 */ 438 */
435#define DRM_RADEON_CP_INIT 0x00 439#define DRM_RADEON_CP_INIT 0x00
436#define DRM_RADEON_CP_START 0x01 440#define DRM_RADEON_CP_START 0x01
437#define DRM_RADEON_CP_STOP 0x02 441#define DRM_RADEON_CP_STOP 0x02
438#define DRM_RADEON_CP_RESET 0x03 442#define DRM_RADEON_CP_RESET 0x03
439#define DRM_RADEON_CP_IDLE 0x04 443#define DRM_RADEON_CP_IDLE 0x04
440#define DRM_RADEON_RESET 0x05 444#define DRM_RADEON_RESET 0x05
441#define DRM_RADEON_FULLSCREEN 0x06 445#define DRM_RADEON_FULLSCREEN 0x06
442#define DRM_RADEON_SWAP 0x07 446#define DRM_RADEON_SWAP 0x07
443#define DRM_RADEON_CLEAR 0x08 447#define DRM_RADEON_CLEAR 0x08
444#define DRM_RADEON_VERTEX 0x09 448#define DRM_RADEON_VERTEX 0x09
445#define DRM_RADEON_INDICES 0x0A 449#define DRM_RADEON_INDICES 0x0A
446#define DRM_RADEON_NOT_USED 450#define DRM_RADEON_NOT_USED
@@ -491,7 +495,7 @@ typedef struct {
491 495
492typedef struct drm_radeon_init { 496typedef struct drm_radeon_init {
493 enum { 497 enum {
494 RADEON_INIT_CP = 0x01, 498 RADEON_INIT_CP = 0x01,
495 RADEON_CLEANUP_CP = 0x02, 499 RADEON_CLEANUP_CP = 0x02,
496 RADEON_INIT_R200_CP = 0x03, 500 RADEON_INIT_R200_CP = 0x03,
497 RADEON_INIT_R300_CP = 0x04 501 RADEON_INIT_R300_CP = 0x04
@@ -524,7 +528,7 @@ typedef struct drm_radeon_cp_stop {
524 528
525typedef struct drm_radeon_fullscreen { 529typedef struct drm_radeon_fullscreen {
526 enum { 530 enum {
527 RADEON_INIT_FULLSCREEN = 0x01, 531 RADEON_INIT_FULLSCREEN = 0x01,
528 RADEON_CLEANUP_FULLSCREEN = 0x02 532 RADEON_CLEANUP_FULLSCREEN = 0x02
529 } func; 533 } func;
530} drm_radeon_fullscreen_t; 534} drm_radeon_fullscreen_t;
@@ -545,15 +549,15 @@ typedef struct drm_radeon_clear {
545 unsigned int clear_color; 549 unsigned int clear_color;
546 unsigned int clear_depth; 550 unsigned int clear_depth;
547 unsigned int color_mask; 551 unsigned int color_mask;
548 unsigned int depth_mask; /* misnamed field: should be stencil */ 552 unsigned int depth_mask; /* misnamed field: should be stencil */
549 drm_radeon_clear_rect_t __user *depth_boxes; 553 drm_radeon_clear_rect_t __user *depth_boxes;
550} drm_radeon_clear_t; 554} drm_radeon_clear_t;
551 555
552typedef struct drm_radeon_vertex { 556typedef struct drm_radeon_vertex {
553 int prim; 557 int prim;
554 int idx; /* Index of vertex buffer */ 558 int idx; /* Index of vertex buffer */
555 int count; /* Number of vertices in buffer */ 559 int count; /* Number of vertices in buffer */
556 int discard; /* Client finished with buffer? */ 560 int discard; /* Client finished with buffer? */
557} drm_radeon_vertex_t; 561} drm_radeon_vertex_t;
558 562
559typedef struct drm_radeon_indices { 563typedef struct drm_radeon_indices {
@@ -561,7 +565,7 @@ typedef struct drm_radeon_indices {
561 int idx; 565 int idx;
562 int start; 566 int start;
563 int end; 567 int end;
564 int discard; /* Client finished with buffer? */ 568 int discard; /* Client finished with buffer? */
565} drm_radeon_indices_t; 569} drm_radeon_indices_t;
566 570
567/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices 571/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
@@ -569,8 +573,8 @@ typedef struct drm_radeon_indices {
569 * - supports driver change to emit native primitives 573 * - supports driver change to emit native primitives
570 */ 574 */
571typedef struct drm_radeon_vertex2 { 575typedef struct drm_radeon_vertex2 {
572 int idx; /* Index of vertex buffer */ 576 int idx; /* Index of vertex buffer */
573 int discard; /* Client finished with buffer? */ 577 int discard; /* Client finished with buffer? */
574 int nr_states; 578 int nr_states;
575 drm_radeon_state_t __user *state; 579 drm_radeon_state_t __user *state;
576 int nr_prims; 580 int nr_prims;
@@ -578,10 +582,10 @@ typedef struct drm_radeon_vertex2 {
578} drm_radeon_vertex2_t; 582} drm_radeon_vertex2_t;
579 583
580/* v1.3 - obsoletes drm_radeon_vertex2 584/* v1.3 - obsoletes drm_radeon_vertex2
581 * - allows arbitarily large cliprect list 585 * - allows arbitarily large cliprect list
582 * - allows updating of tcl packet, vector and scalar state 586 * - allows updating of tcl packet, vector and scalar state
583 * - allows memory-efficient description of state updates 587 * - allows memory-efficient description of state updates
584 * - allows state to be emitted without a primitive 588 * - allows state to be emitted without a primitive
585 * (for clears, ctx switches) 589 * (for clears, ctx switches)
586 * - allows more than one dma buffer to be referenced per ioctl 590 * - allows more than one dma buffer to be referenced per ioctl
587 * - supports tcl driver 591 * - supports tcl driver
@@ -595,7 +599,7 @@ typedef struct drm_radeon_cmd_buffer {
595} drm_radeon_cmd_buffer_t; 599} drm_radeon_cmd_buffer_t;
596 600
597typedef struct drm_radeon_tex_image { 601typedef struct drm_radeon_tex_image {
598 unsigned int x, y; /* Blit coordinates */ 602 unsigned int x, y; /* Blit coordinates */
599 unsigned int width, height; 603 unsigned int width, height;
600 const void __user *data; 604 const void __user *data;
601} drm_radeon_tex_image_t; 605} drm_radeon_tex_image_t;
@@ -604,7 +608,7 @@ typedef struct drm_radeon_texture {
604 unsigned int offset; 608 unsigned int offset;
605 int pitch; 609 int pitch;
606 int format; 610 int format;
607 int width; /* Texture image coordinates */ 611 int width; /* Texture image coordinates */
608 int height; 612 int height;
609 drm_radeon_tex_image_t __user *image; 613 drm_radeon_tex_image_t __user *image;
610} drm_radeon_texture_t; 614} drm_radeon_texture_t;
@@ -620,19 +624,18 @@ typedef struct drm_radeon_indirect {
620 int discard; 624 int discard;
621} drm_radeon_indirect_t; 625} drm_radeon_indirect_t;
622 626
623
624/* 1.3: An ioctl to get parameters that aren't available to the 3d 627/* 1.3: An ioctl to get parameters that aren't available to the 3d
625 * client any other way. 628 * client any other way.
626 */ 629 */
627#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ 630#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
628#define RADEON_PARAM_LAST_FRAME 2 631#define RADEON_PARAM_LAST_FRAME 2
629#define RADEON_PARAM_LAST_DISPATCH 3 632#define RADEON_PARAM_LAST_DISPATCH 3
630#define RADEON_PARAM_LAST_CLEAR 4 633#define RADEON_PARAM_LAST_CLEAR 4
631/* Added with DRM version 1.6. */ 634/* Added with DRM version 1.6. */
632#define RADEON_PARAM_IRQ_NR 5 635#define RADEON_PARAM_IRQ_NR 5
633#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ 636#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
634/* Added with DRM version 1.8. */ 637/* Added with DRM version 1.8. */
635#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ 638#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
636#define RADEON_PARAM_STATUS_HANDLE 8 639#define RADEON_PARAM_STATUS_HANDLE 8
637#define RADEON_PARAM_SAREA_HANDLE 9 640#define RADEON_PARAM_SAREA_HANDLE 9
638#define RADEON_PARAM_GART_TEX_HANDLE 10 641#define RADEON_PARAM_GART_TEX_HANDLE 10
@@ -663,10 +666,9 @@ typedef struct drm_radeon_mem_free {
663typedef struct drm_radeon_mem_init_heap { 666typedef struct drm_radeon_mem_init_heap {
664 int region; 667 int region;
665 int size; 668 int size;
666 int start; 669 int start;
667} drm_radeon_mem_init_heap_t; 670} drm_radeon_mem_init_heap_t;
668 671
669
670/* 1.6: Userspace can request & wait on irq's: 672/* 1.6: Userspace can request & wait on irq's:
671 */ 673 */
672typedef struct drm_radeon_irq_emit { 674typedef struct drm_radeon_irq_emit {
@@ -677,18 +679,18 @@ typedef struct drm_radeon_irq_wait {
677 int irq_seq; 679 int irq_seq;
678} drm_radeon_irq_wait_t; 680} drm_radeon_irq_wait_t;
679 681
680
681/* 1.10: Clients tell the DRM where they think the framebuffer is located in 682/* 1.10: Clients tell the DRM where they think the framebuffer is located in
682 * the card's address space, via a new generic ioctl to set parameters 683 * the card's address space, via a new generic ioctl to set parameters
683 */ 684 */
684 685
685typedef struct drm_radeon_setparam { 686typedef struct drm_radeon_setparam {
686 unsigned int param; 687 unsigned int param;
687 int64_t value; 688 int64_t value;
688} drm_radeon_setparam_t; 689} drm_radeon_setparam_t;
689 690
690#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ 691#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
691#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ 692#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
693#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
692 694
693/* 1.14: Clients can allocate/free a surface 695/* 1.14: Clients can allocate/free a surface
694 */ 696 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 15:02:02 -0500