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path: root/drivers/char/drm/radeon_cp.c
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Diffstat (limited to 'drivers/char/drm/radeon_cp.c')
-rw-r--r--drivers/char/drm/radeon_cp.c2480
1 files changed, 1244 insertions, 1236 deletions
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index 6dff5e43f713..447bfbe0da8a 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -36,788 +36,787 @@
36 36
37#define RADEON_FIFO_DEBUG 0 37#define RADEON_FIFO_DEBUG 0
38 38
39static int radeon_do_cleanup_cp( drm_device_t *dev ); 39static int radeon_do_cleanup_cp(drm_device_t * dev);
40 40
41/* CP microcode (from ATI) */ 41/* CP microcode (from ATI) */
42static u32 R200_cp_microcode[][2] = { 42static u32 R200_cp_microcode[][2] = {
43 { 0x21007000, 0000000000 }, 43 {0x21007000, 0000000000},
44 { 0x20007000, 0000000000 }, 44 {0x20007000, 0000000000},
45 { 0x000000ab, 0x00000004 }, 45 {0x000000ab, 0x00000004},
46 { 0x000000af, 0x00000004 }, 46 {0x000000af, 0x00000004},
47 { 0x66544a49, 0000000000 }, 47 {0x66544a49, 0000000000},
48 { 0x49494174, 0000000000 }, 48 {0x49494174, 0000000000},
49 { 0x54517d83, 0000000000 }, 49 {0x54517d83, 0000000000},
50 { 0x498d8b64, 0000000000 }, 50 {0x498d8b64, 0000000000},
51 { 0x49494949, 0000000000 }, 51 {0x49494949, 0000000000},
52 { 0x49da493c, 0000000000 }, 52 {0x49da493c, 0000000000},
53 { 0x49989898, 0000000000 }, 53 {0x49989898, 0000000000},
54 { 0xd34949d5, 0000000000 }, 54 {0xd34949d5, 0000000000},
55 { 0x9dc90e11, 0000000000 }, 55 {0x9dc90e11, 0000000000},
56 { 0xce9b9b9b, 0000000000 }, 56 {0xce9b9b9b, 0000000000},
57 { 0x000f0000, 0x00000016 }, 57 {0x000f0000, 0x00000016},
58 { 0x352e232c, 0000000000 }, 58 {0x352e232c, 0000000000},
59 { 0x00000013, 0x00000004 }, 59 {0x00000013, 0x00000004},
60 { 0x000f0000, 0x00000016 }, 60 {0x000f0000, 0x00000016},
61 { 0x352e272c, 0000000000 }, 61 {0x352e272c, 0000000000},
62 { 0x000f0001, 0x00000016 }, 62 {0x000f0001, 0x00000016},
63 { 0x3239362f, 0000000000 }, 63 {0x3239362f, 0000000000},
64 { 0x000077ef, 0x00000002 }, 64 {0x000077ef, 0x00000002},
65 { 0x00061000, 0x00000002 }, 65 {0x00061000, 0x00000002},
66 { 0x00000020, 0x0000001a }, 66 {0x00000020, 0x0000001a},
67 { 0x00004000, 0x0000001e }, 67 {0x00004000, 0x0000001e},
68 { 0x00061000, 0x00000002 }, 68 {0x00061000, 0x00000002},
69 { 0x00000020, 0x0000001a }, 69 {0x00000020, 0x0000001a},
70 { 0x00004000, 0x0000001e }, 70 {0x00004000, 0x0000001e},
71 { 0x00061000, 0x00000002 }, 71 {0x00061000, 0x00000002},
72 { 0x00000020, 0x0000001a }, 72 {0x00000020, 0x0000001a},
73 { 0x00004000, 0x0000001e }, 73 {0x00004000, 0x0000001e},
74 { 0x00000016, 0x00000004 }, 74 {0x00000016, 0x00000004},
75 { 0x0003802a, 0x00000002 }, 75 {0x0003802a, 0x00000002},
76 { 0x040067e0, 0x00000002 }, 76 {0x040067e0, 0x00000002},
77 { 0x00000016, 0x00000004 }, 77 {0x00000016, 0x00000004},
78 { 0x000077e0, 0x00000002 }, 78 {0x000077e0, 0x00000002},
79 { 0x00065000, 0x00000002 }, 79 {0x00065000, 0x00000002},
80 { 0x000037e1, 0x00000002 }, 80 {0x000037e1, 0x00000002},
81 { 0x040067e1, 0x00000006 }, 81 {0x040067e1, 0x00000006},
82 { 0x000077e0, 0x00000002 }, 82 {0x000077e0, 0x00000002},
83 { 0x000077e1, 0x00000002 }, 83 {0x000077e1, 0x00000002},
84 { 0x000077e1, 0x00000006 }, 84 {0x000077e1, 0x00000006},
85 { 0xffffffff, 0000000000 }, 85 {0xffffffff, 0000000000},
86 { 0x10000000, 0000000000 }, 86 {0x10000000, 0000000000},
87 { 0x0003802a, 0x00000002 }, 87 {0x0003802a, 0x00000002},
88 { 0x040067e0, 0x00000006 }, 88 {0x040067e0, 0x00000006},
89 { 0x00007675, 0x00000002 }, 89 {0x00007675, 0x00000002},
90 { 0x00007676, 0x00000002 }, 90 {0x00007676, 0x00000002},
91 { 0x00007677, 0x00000002 }, 91 {0x00007677, 0x00000002},
92 { 0x00007678, 0x00000006 }, 92 {0x00007678, 0x00000006},
93 { 0x0003802b, 0x00000002 }, 93 {0x0003802b, 0x00000002},
94 { 0x04002676, 0x00000002 }, 94 {0x04002676, 0x00000002},
95 { 0x00007677, 0x00000002 }, 95 {0x00007677, 0x00000002},
96 { 0x00007678, 0x00000006 }, 96 {0x00007678, 0x00000006},
97 { 0x0000002e, 0x00000018 }, 97 {0x0000002e, 0x00000018},
98 { 0x0000002e, 0x00000018 }, 98 {0x0000002e, 0x00000018},
99 { 0000000000, 0x00000006 }, 99 {0000000000, 0x00000006},
100 { 0x0000002f, 0x00000018 }, 100 {0x0000002f, 0x00000018},
101 { 0x0000002f, 0x00000018 }, 101 {0x0000002f, 0x00000018},
102 { 0000000000, 0x00000006 }, 102 {0000000000, 0x00000006},
103 { 0x01605000, 0x00000002 }, 103 {0x01605000, 0x00000002},
104 { 0x00065000, 0x00000002 }, 104 {0x00065000, 0x00000002},
105 { 0x00098000, 0x00000002 }, 105 {0x00098000, 0x00000002},
106 { 0x00061000, 0x00000002 }, 106 {0x00061000, 0x00000002},
107 { 0x64c0603d, 0x00000004 }, 107 {0x64c0603d, 0x00000004},
108 { 0x00080000, 0x00000016 }, 108 {0x00080000, 0x00000016},
109 { 0000000000, 0000000000 }, 109 {0000000000, 0000000000},
110 { 0x0400251d, 0x00000002 }, 110 {0x0400251d, 0x00000002},
111 { 0x00007580, 0x00000002 }, 111 {0x00007580, 0x00000002},
112 { 0x00067581, 0x00000002 }, 112 {0x00067581, 0x00000002},
113 { 0x04002580, 0x00000002 }, 113 {0x04002580, 0x00000002},
114 { 0x00067581, 0x00000002 }, 114 {0x00067581, 0x00000002},
115 { 0x00000046, 0x00000004 }, 115 {0x00000046, 0x00000004},
116 { 0x00005000, 0000000000 }, 116 {0x00005000, 0000000000},
117 { 0x00061000, 0x00000002 }, 117 {0x00061000, 0x00000002},
118 { 0x0000750e, 0x00000002 }, 118 {0x0000750e, 0x00000002},
119 { 0x00019000, 0x00000002 }, 119 {0x00019000, 0x00000002},
120 { 0x00011055, 0x00000014 }, 120 {0x00011055, 0x00000014},
121 { 0x00000055, 0x00000012 }, 121 {0x00000055, 0x00000012},
122 { 0x0400250f, 0x00000002 }, 122 {0x0400250f, 0x00000002},
123 { 0x0000504a, 0x00000004 }, 123 {0x0000504a, 0x00000004},
124 { 0x00007565, 0x00000002 }, 124 {0x00007565, 0x00000002},
125 { 0x00007566, 0x00000002 }, 125 {0x00007566, 0x00000002},
126 { 0x00000051, 0x00000004 }, 126 {0x00000051, 0x00000004},
127 { 0x01e655b4, 0x00000002 }, 127 {0x01e655b4, 0x00000002},
128 { 0x4401b0dc, 0x00000002 }, 128 {0x4401b0dc, 0x00000002},
129 { 0x01c110dc, 0x00000002 }, 129 {0x01c110dc, 0x00000002},
130 { 0x2666705d, 0x00000018 }, 130 {0x2666705d, 0x00000018},
131 { 0x040c2565, 0x00000002 }, 131 {0x040c2565, 0x00000002},
132 { 0x0000005d, 0x00000018 }, 132 {0x0000005d, 0x00000018},
133 { 0x04002564, 0x00000002 }, 133 {0x04002564, 0x00000002},
134 { 0x00007566, 0x00000002 }, 134 {0x00007566, 0x00000002},
135 { 0x00000054, 0x00000004 }, 135 {0x00000054, 0x00000004},
136 { 0x00401060, 0x00000008 }, 136 {0x00401060, 0x00000008},
137 { 0x00101000, 0x00000002 }, 137 {0x00101000, 0x00000002},
138 { 0x000d80ff, 0x00000002 }, 138 {0x000d80ff, 0x00000002},
139 { 0x00800063, 0x00000008 }, 139 {0x00800063, 0x00000008},
140 { 0x000f9000, 0x00000002 }, 140 {0x000f9000, 0x00000002},
141 { 0x000e00ff, 0x00000002 }, 141 {0x000e00ff, 0x00000002},
142 { 0000000000, 0x00000006 }, 142 {0000000000, 0x00000006},
143 { 0x00000080, 0x00000018 }, 143 {0x00000080, 0x00000018},
144 { 0x00000054, 0x00000004 }, 144 {0x00000054, 0x00000004},
145 { 0x00007576, 0x00000002 }, 145 {0x00007576, 0x00000002},
146 { 0x00065000, 0x00000002 }, 146 {0x00065000, 0x00000002},
147 { 0x00009000, 0x00000002 }, 147 {0x00009000, 0x00000002},
148 { 0x00041000, 0x00000002 }, 148 {0x00041000, 0x00000002},
149 { 0x0c00350e, 0x00000002 }, 149 {0x0c00350e, 0x00000002},
150 { 0x00049000, 0x00000002 }, 150 {0x00049000, 0x00000002},
151 { 0x00051000, 0x00000002 }, 151 {0x00051000, 0x00000002},
152 { 0x01e785f8, 0x00000002 }, 152 {0x01e785f8, 0x00000002},
153 { 0x00200000, 0x00000002 }, 153 {0x00200000, 0x00000002},
154 { 0x00600073, 0x0000000c }, 154 {0x00600073, 0x0000000c},
155 { 0x00007563, 0x00000002 }, 155 {0x00007563, 0x00000002},
156 { 0x006075f0, 0x00000021 }, 156 {0x006075f0, 0x00000021},
157 { 0x20007068, 0x00000004 }, 157 {0x20007068, 0x00000004},
158 { 0x00005068, 0x00000004 }, 158 {0x00005068, 0x00000004},
159 { 0x00007576, 0x00000002 }, 159 {0x00007576, 0x00000002},
160 { 0x00007577, 0x00000002 }, 160 {0x00007577, 0x00000002},
161 { 0x0000750e, 0x00000002 }, 161 {0x0000750e, 0x00000002},
162 { 0x0000750f, 0x00000002 }, 162 {0x0000750f, 0x00000002},
163 { 0x00a05000, 0x00000002 }, 163 {0x00a05000, 0x00000002},
164 { 0x00600076, 0x0000000c }, 164 {0x00600076, 0x0000000c},
165 { 0x006075f0, 0x00000021 }, 165 {0x006075f0, 0x00000021},
166 { 0x000075f8, 0x00000002 }, 166 {0x000075f8, 0x00000002},
167 { 0x00000076, 0x00000004 }, 167 {0x00000076, 0x00000004},
168 { 0x000a750e, 0x00000002 }, 168 {0x000a750e, 0x00000002},
169 { 0x0020750f, 0x00000002 }, 169 {0x0020750f, 0x00000002},
170 { 0x00600079, 0x00000004 }, 170 {0x00600079, 0x00000004},
171 { 0x00007570, 0x00000002 }, 171 {0x00007570, 0x00000002},
172 { 0x00007571, 0x00000002 }, 172 {0x00007571, 0x00000002},
173 { 0x00007572, 0x00000006 }, 173 {0x00007572, 0x00000006},
174 { 0x00005000, 0x00000002 }, 174 {0x00005000, 0x00000002},
175 { 0x00a05000, 0x00000002 }, 175 {0x00a05000, 0x00000002},
176 { 0x00007568, 0x00000002 }, 176 {0x00007568, 0x00000002},
177 { 0x00061000, 0x00000002 }, 177 {0x00061000, 0x00000002},
178 { 0x00000084, 0x0000000c }, 178 {0x00000084, 0x0000000c},
179 { 0x00058000, 0x00000002 }, 179 {0x00058000, 0x00000002},
180 { 0x0c607562, 0x00000002 }, 180 {0x0c607562, 0x00000002},
181 { 0x00000086, 0x00000004 }, 181 {0x00000086, 0x00000004},
182 { 0x00600085, 0x00000004 }, 182 {0x00600085, 0x00000004},
183 { 0x400070dd, 0000000000 }, 183 {0x400070dd, 0000000000},
184 { 0x000380dd, 0x00000002 }, 184 {0x000380dd, 0x00000002},
185 { 0x00000093, 0x0000001c }, 185 {0x00000093, 0x0000001c},
186 { 0x00065095, 0x00000018 }, 186 {0x00065095, 0x00000018},
187 { 0x040025bb, 0x00000002 }, 187 {0x040025bb, 0x00000002},
188 { 0x00061096, 0x00000018 }, 188 {0x00061096, 0x00000018},
189 { 0x040075bc, 0000000000 }, 189 {0x040075bc, 0000000000},
190 { 0x000075bb, 0x00000002 }, 190 {0x000075bb, 0x00000002},
191 { 0x000075bc, 0000000000 }, 191 {0x000075bc, 0000000000},
192 { 0x00090000, 0x00000006 }, 192 {0x00090000, 0x00000006},
193 { 0x00090000, 0x00000002 }, 193 {0x00090000, 0x00000002},
194 { 0x000d8002, 0x00000006 }, 194 {0x000d8002, 0x00000006},
195 { 0x00005000, 0x00000002 }, 195 {0x00005000, 0x00000002},
196 { 0x00007821, 0x00000002 }, 196 {0x00007821, 0x00000002},
197 { 0x00007800, 0000000000 }, 197 {0x00007800, 0000000000},
198 { 0x00007821, 0x00000002 }, 198 {0x00007821, 0x00000002},
199 { 0x00007800, 0000000000 }, 199 {0x00007800, 0000000000},
200 { 0x01665000, 0x00000002 }, 200 {0x01665000, 0x00000002},
201 { 0x000a0000, 0x00000002 }, 201 {0x000a0000, 0x00000002},
202 { 0x000671cc, 0x00000002 }, 202 {0x000671cc, 0x00000002},
203 { 0x0286f1cd, 0x00000002 }, 203 {0x0286f1cd, 0x00000002},
204 { 0x000000a3, 0x00000010 }, 204 {0x000000a3, 0x00000010},
205 { 0x21007000, 0000000000 }, 205 {0x21007000, 0000000000},
206 { 0x000000aa, 0x0000001c }, 206 {0x000000aa, 0x0000001c},
207 { 0x00065000, 0x00000002 }, 207 {0x00065000, 0x00000002},
208 { 0x000a0000, 0x00000002 }, 208 {0x000a0000, 0x00000002},
209 { 0x00061000, 0x00000002 }, 209 {0x00061000, 0x00000002},
210 { 0x000b0000, 0x00000002 }, 210 {0x000b0000, 0x00000002},
211 { 0x38067000, 0x00000002 }, 211 {0x38067000, 0x00000002},
212 { 0x000a00a6, 0x00000004 }, 212 {0x000a00a6, 0x00000004},
213 { 0x20007000, 0000000000 }, 213 {0x20007000, 0000000000},
214 { 0x01200000, 0x00000002 }, 214 {0x01200000, 0x00000002},
215 { 0x20077000, 0x00000002 }, 215 {0x20077000, 0x00000002},
216 { 0x01200000, 0x00000002 }, 216 {0x01200000, 0x00000002},
217 { 0x20007000, 0000000000 }, 217 {0x20007000, 0000000000},
218 { 0x00061000, 0x00000002 }, 218 {0x00061000, 0x00000002},
219 { 0x0120751b, 0x00000002 }, 219 {0x0120751b, 0x00000002},
220 { 0x8040750a, 0x00000002 }, 220 {0x8040750a, 0x00000002},
221 { 0x8040750b, 0x00000002 }, 221 {0x8040750b, 0x00000002},
222 { 0x00110000, 0x00000002 }, 222 {0x00110000, 0x00000002},
223 { 0x000380dd, 0x00000002 }, 223 {0x000380dd, 0x00000002},
224 { 0x000000bd, 0x0000001c }, 224 {0x000000bd, 0x0000001c},
225 { 0x00061096, 0x00000018 }, 225 {0x00061096, 0x00000018},
226 { 0x844075bd, 0x00000002 }, 226 {0x844075bd, 0x00000002},
227 { 0x00061095, 0x00000018 }, 227 {0x00061095, 0x00000018},
228 { 0x840075bb, 0x00000002 }, 228 {0x840075bb, 0x00000002},
229 { 0x00061096, 0x00000018 }, 229 {0x00061096, 0x00000018},
230 { 0x844075bc, 0x00000002 }, 230 {0x844075bc, 0x00000002},
231 { 0x000000c0, 0x00000004 }, 231 {0x000000c0, 0x00000004},
232 { 0x804075bd, 0x00000002 }, 232 {0x804075bd, 0x00000002},
233 { 0x800075bb, 0x00000002 }, 233 {0x800075bb, 0x00000002},
234 { 0x804075bc, 0x00000002 }, 234 {0x804075bc, 0x00000002},
235 { 0x00108000, 0x00000002 }, 235 {0x00108000, 0x00000002},
236 { 0x01400000, 0x00000002 }, 236 {0x01400000, 0x00000002},
237 { 0x006000c4, 0x0000000c }, 237 {0x006000c4, 0x0000000c},
238 { 0x20c07000, 0x00000020 }, 238 {0x20c07000, 0x00000020},
239 { 0x000000c6, 0x00000012 }, 239 {0x000000c6, 0x00000012},
240 { 0x00800000, 0x00000006 }, 240 {0x00800000, 0x00000006},
241 { 0x0080751d, 0x00000006 }, 241 {0x0080751d, 0x00000006},
242 { 0x000025bb, 0x00000002 }, 242 {0x000025bb, 0x00000002},
243 { 0x000040c0, 0x00000004 }, 243 {0x000040c0, 0x00000004},
244 { 0x0000775c, 0x00000002 }, 244 {0x0000775c, 0x00000002},
245 { 0x00a05000, 0x00000002 }, 245 {0x00a05000, 0x00000002},
246 { 0x00661000, 0x00000002 }, 246 {0x00661000, 0x00000002},
247 { 0x0460275d, 0x00000020 }, 247 {0x0460275d, 0x00000020},
248 { 0x00004000, 0000000000 }, 248 {0x00004000, 0000000000},
249 { 0x00007999, 0x00000002 }, 249 {0x00007999, 0x00000002},
250 { 0x00a05000, 0x00000002 }, 250 {0x00a05000, 0x00000002},
251 { 0x00661000, 0x00000002 }, 251 {0x00661000, 0x00000002},
252 { 0x0460299b, 0x00000020 }, 252 {0x0460299b, 0x00000020},
253 { 0x00004000, 0000000000 }, 253 {0x00004000, 0000000000},
254 { 0x01e00830, 0x00000002 }, 254 {0x01e00830, 0x00000002},
255 { 0x21007000, 0000000000 }, 255 {0x21007000, 0000000000},
256 { 0x00005000, 0x00000002 }, 256 {0x00005000, 0x00000002},
257 { 0x00038042, 0x00000002 }, 257 {0x00038042, 0x00000002},
258 { 0x040025e0, 0x00000002 }, 258 {0x040025e0, 0x00000002},
259 { 0x000075e1, 0000000000 }, 259 {0x000075e1, 0000000000},
260 { 0x00000001, 0000000000 }, 260 {0x00000001, 0000000000},
261 { 0x000380d9, 0x00000002 }, 261 {0x000380d9, 0x00000002},
262 { 0x04007394, 0000000000 }, 262 {0x04007394, 0000000000},
263 { 0000000000, 0000000000 }, 263 {0000000000, 0000000000},
264 { 0000000000, 0000000000 }, 264 {0000000000, 0000000000},
265 { 0000000000, 0000000000 }, 265 {0000000000, 0000000000},
266 { 0000000000, 0000000000 }, 266 {0000000000, 0000000000},
267 { 0000000000, 0000000000 }, 267 {0000000000, 0000000000},
268 { 0000000000, 0000000000 }, 268 {0000000000, 0000000000},
269 { 0000000000, 0000000000 }, 269 {0000000000, 0000000000},
270 { 0000000000, 0000000000 }, 270 {0000000000, 0000000000},
271 { 0000000000, 0000000000 }, 271 {0000000000, 0000000000},
272 { 0000000000, 0000000000 }, 272 {0000000000, 0000000000},
273 { 0000000000, 0000000000 }, 273 {0000000000, 0000000000},
274 { 0000000000, 0000000000 }, 274 {0000000000, 0000000000},
275 { 0000000000, 0000000000 }, 275 {0000000000, 0000000000},
276 { 0000000000, 0000000000 }, 276 {0000000000, 0000000000},
277 { 0000000000, 0000000000 }, 277 {0000000000, 0000000000},
278 { 0000000000, 0000000000 }, 278 {0000000000, 0000000000},
279 { 0000000000, 0000000000 }, 279 {0000000000, 0000000000},
280 { 0000000000, 0000000000 }, 280 {0000000000, 0000000000},
281 { 0000000000, 0000000000 }, 281 {0000000000, 0000000000},
282 { 0000000000, 0000000000 }, 282 {0000000000, 0000000000},
283 { 0000000000, 0000000000 }, 283 {0000000000, 0000000000},
284 { 0000000000, 0000000000 }, 284 {0000000000, 0000000000},
285 { 0000000000, 0000000000 }, 285 {0000000000, 0000000000},
286 { 0000000000, 0000000000 }, 286 {0000000000, 0000000000},
287 { 0000000000, 0000000000 }, 287 {0000000000, 0000000000},
288 { 0000000000, 0000000000 }, 288 {0000000000, 0000000000},
289 { 0000000000, 0000000000 }, 289 {0000000000, 0000000000},
290 { 0000000000, 0000000000 }, 290 {0000000000, 0000000000},
291 { 0000000000, 0000000000 }, 291 {0000000000, 0000000000},
292 { 0000000000, 0000000000 }, 292 {0000000000, 0000000000},
293 { 0000000000, 0000000000 }, 293 {0000000000, 0000000000},
294 { 0000000000, 0000000000 }, 294 {0000000000, 0000000000},
295 { 0000000000, 0000000000 }, 295 {0000000000, 0000000000},
296 { 0000000000, 0000000000 }, 296 {0000000000, 0000000000},
297 { 0000000000, 0000000000 }, 297 {0000000000, 0000000000},
298 { 0000000000, 0000000000 }, 298 {0000000000, 0000000000},
299}; 299};
300 300
301
302static u32 radeon_cp_microcode[][2] = { 301static u32 radeon_cp_microcode[][2] = {
303 { 0x21007000, 0000000000 }, 302 {0x21007000, 0000000000},
304 { 0x20007000, 0000000000 }, 303 {0x20007000, 0000000000},
305 { 0x000000b4, 0x00000004 }, 304 {0x000000b4, 0x00000004},
306 { 0x000000b8, 0x00000004 }, 305 {0x000000b8, 0x00000004},
307 { 0x6f5b4d4c, 0000000000 }, 306 {0x6f5b4d4c, 0000000000},
308 { 0x4c4c427f, 0000000000 }, 307 {0x4c4c427f, 0000000000},
309 { 0x5b568a92, 0000000000 }, 308 {0x5b568a92, 0000000000},
310 { 0x4ca09c6d, 0000000000 }, 309 {0x4ca09c6d, 0000000000},
311 { 0xad4c4c4c, 0000000000 }, 310 {0xad4c4c4c, 0000000000},
312 { 0x4ce1af3d, 0000000000 }, 311 {0x4ce1af3d, 0000000000},
313 { 0xd8afafaf, 0000000000 }, 312 {0xd8afafaf, 0000000000},
314 { 0xd64c4cdc, 0000000000 }, 313 {0xd64c4cdc, 0000000000},
315 { 0x4cd10d10, 0000000000 }, 314 {0x4cd10d10, 0000000000},
316 { 0x000f0000, 0x00000016 }, 315 {0x000f0000, 0x00000016},
317 { 0x362f242d, 0000000000 }, 316 {0x362f242d, 0000000000},
318 { 0x00000012, 0x00000004 }, 317 {0x00000012, 0x00000004},
319 { 0x000f0000, 0x00000016 }, 318 {0x000f0000, 0x00000016},
320 { 0x362f282d, 0000000000 }, 319 {0x362f282d, 0000000000},
321 { 0x000380e7, 0x00000002 }, 320 {0x000380e7, 0x00000002},
322 { 0x04002c97, 0x00000002 }, 321 {0x04002c97, 0x00000002},
323 { 0x000f0001, 0x00000016 }, 322 {0x000f0001, 0x00000016},
324 { 0x333a3730, 0000000000 }, 323 {0x333a3730, 0000000000},
325 { 0x000077ef, 0x00000002 }, 324 {0x000077ef, 0x00000002},
326 { 0x00061000, 0x00000002 }, 325 {0x00061000, 0x00000002},
327 { 0x00000021, 0x0000001a }, 326 {0x00000021, 0x0000001a},
328 { 0x00004000, 0x0000001e }, 327 {0x00004000, 0x0000001e},
329 { 0x00061000, 0x00000002 }, 328 {0x00061000, 0x00000002},
330 { 0x00000021, 0x0000001a }, 329 {0x00000021, 0x0000001a},
331 { 0x00004000, 0x0000001e }, 330 {0x00004000, 0x0000001e},
332 { 0x00061000, 0x00000002 }, 331 {0x00061000, 0x00000002},
333 { 0x00000021, 0x0000001a }, 332 {0x00000021, 0x0000001a},
334 { 0x00004000, 0x0000001e }, 333 {0x00004000, 0x0000001e},
335 { 0x00000017, 0x00000004 }, 334 {0x00000017, 0x00000004},
336 { 0x0003802b, 0x00000002 }, 335 {0x0003802b, 0x00000002},
337 { 0x040067e0, 0x00000002 }, 336 {0x040067e0, 0x00000002},
338 { 0x00000017, 0x00000004 }, 337 {0x00000017, 0x00000004},
339 { 0x000077e0, 0x00000002 }, 338 {0x000077e0, 0x00000002},
340 { 0x00065000, 0x00000002 }, 339 {0x00065000, 0x00000002},
341 { 0x000037e1, 0x00000002 }, 340 {0x000037e1, 0x00000002},
342 { 0x040067e1, 0x00000006 }, 341 {0x040067e1, 0x00000006},
343 { 0x000077e0, 0x00000002 }, 342 {0x000077e0, 0x00000002},
344 { 0x000077e1, 0x00000002 }, 343 {0x000077e1, 0x00000002},
345 { 0x000077e1, 0x00000006 }, 344 {0x000077e1, 0x00000006},
346 { 0xffffffff, 0000000000 }, 345 {0xffffffff, 0000000000},
347 { 0x10000000, 0000000000 }, 346 {0x10000000, 0000000000},
348 { 0x0003802b, 0x00000002 }, 347 {0x0003802b, 0x00000002},
349 { 0x040067e0, 0x00000006 }, 348 {0x040067e0, 0x00000006},
350 { 0x00007675, 0x00000002 }, 349 {0x00007675, 0x00000002},
351 { 0x00007676, 0x00000002 }, 350 {0x00007676, 0x00000002},
352 { 0x00007677, 0x00000002 }, 351 {0x00007677, 0x00000002},
353 { 0x00007678, 0x00000006 }, 352 {0x00007678, 0x00000006},
354 { 0x0003802c, 0x00000002 }, 353 {0x0003802c, 0x00000002},
355 { 0x04002676, 0x00000002 }, 354 {0x04002676, 0x00000002},
356 { 0x00007677, 0x00000002 }, 355 {0x00007677, 0x00000002},
357 { 0x00007678, 0x00000006 }, 356 {0x00007678, 0x00000006},
358 { 0x0000002f, 0x00000018 }, 357 {0x0000002f, 0x00000018},
359 { 0x0000002f, 0x00000018 }, 358 {0x0000002f, 0x00000018},
360 { 0000000000, 0x00000006 }, 359 {0000000000, 0x00000006},
361 { 0x00000030, 0x00000018 }, 360 {0x00000030, 0x00000018},
362 { 0x00000030, 0x00000018 }, 361 {0x00000030, 0x00000018},
363 { 0000000000, 0x00000006 }, 362 {0000000000, 0x00000006},
364 { 0x01605000, 0x00000002 }, 363 {0x01605000, 0x00000002},
365 { 0x00065000, 0x00000002 }, 364 {0x00065000, 0x00000002},
366 { 0x00098000, 0x00000002 }, 365 {0x00098000, 0x00000002},
367 { 0x00061000, 0x00000002 }, 366 {0x00061000, 0x00000002},
368 { 0x64c0603e, 0x00000004 }, 367 {0x64c0603e, 0x00000004},
369 { 0x000380e6, 0x00000002 }, 368 {0x000380e6, 0x00000002},
370 { 0x040025c5, 0x00000002 }, 369 {0x040025c5, 0x00000002},
371 { 0x00080000, 0x00000016 }, 370 {0x00080000, 0x00000016},
372 { 0000000000, 0000000000 }, 371 {0000000000, 0000000000},
373 { 0x0400251d, 0x00000002 }, 372 {0x0400251d, 0x00000002},
374 { 0x00007580, 0x00000002 }, 373 {0x00007580, 0x00000002},
375 { 0x00067581, 0x00000002 }, 374 {0x00067581, 0x00000002},
376 { 0x04002580, 0x00000002 }, 375 {0x04002580, 0x00000002},
377 { 0x00067581, 0x00000002 }, 376 {0x00067581, 0x00000002},
378 { 0x00000049, 0x00000004 }, 377 {0x00000049, 0x00000004},
379 { 0x00005000, 0000000000 }, 378 {0x00005000, 0000000000},
380 { 0x000380e6, 0x00000002 }, 379 {0x000380e6, 0x00000002},
381 { 0x040025c5, 0x00000002 }, 380 {0x040025c5, 0x00000002},
382 { 0x00061000, 0x00000002 }, 381 {0x00061000, 0x00000002},
383 { 0x0000750e, 0x00000002 }, 382 {0x0000750e, 0x00000002},
384 { 0x00019000, 0x00000002 }, 383 {0x00019000, 0x00000002},
385 { 0x00011055, 0x00000014 }, 384 {0x00011055, 0x00000014},
386 { 0x00000055, 0x00000012 }, 385 {0x00000055, 0x00000012},
387 { 0x0400250f, 0x00000002 }, 386 {0x0400250f, 0x00000002},
388 { 0x0000504f, 0x00000004 }, 387 {0x0000504f, 0x00000004},
389 { 0x000380e6, 0x00000002 }, 388 {0x000380e6, 0x00000002},
390 { 0x040025c5, 0x00000002 }, 389 {0x040025c5, 0x00000002},
391 { 0x00007565, 0x00000002 }, 390 {0x00007565, 0x00000002},
392 { 0x00007566, 0x00000002 }, 391 {0x00007566, 0x00000002},
393 { 0x00000058, 0x00000004 }, 392 {0x00000058, 0x00000004},
394 { 0x000380e6, 0x00000002 }, 393 {0x000380e6, 0x00000002},
395 { 0x040025c5, 0x00000002 }, 394 {0x040025c5, 0x00000002},
396 { 0x01e655b4, 0x00000002 }, 395 {0x01e655b4, 0x00000002},
397 { 0x4401b0e4, 0x00000002 }, 396 {0x4401b0e4, 0x00000002},
398 { 0x01c110e4, 0x00000002 }, 397 {0x01c110e4, 0x00000002},
399 { 0x26667066, 0x00000018 }, 398 {0x26667066, 0x00000018},
400 { 0x040c2565, 0x00000002 }, 399 {0x040c2565, 0x00000002},
401 { 0x00000066, 0x00000018 }, 400 {0x00000066, 0x00000018},
402 { 0x04002564, 0x00000002 }, 401 {0x04002564, 0x00000002},
403 { 0x00007566, 0x00000002 }, 402 {0x00007566, 0x00000002},
404 { 0x0000005d, 0x00000004 }, 403 {0x0000005d, 0x00000004},
405 { 0x00401069, 0x00000008 }, 404 {0x00401069, 0x00000008},
406 { 0x00101000, 0x00000002 }, 405 {0x00101000, 0x00000002},
407 { 0x000d80ff, 0x00000002 }, 406 {0x000d80ff, 0x00000002},
408 { 0x0080006c, 0x00000008 }, 407 {0x0080006c, 0x00000008},
409 { 0x000f9000, 0x00000002 }, 408 {0x000f9000, 0x00000002},
410 { 0x000e00ff, 0x00000002 }, 409 {0x000e00ff, 0x00000002},
411 { 0000000000, 0x00000006 }, 410 {0000000000, 0x00000006},
412 { 0x0000008f, 0x00000018 }, 411 {0x0000008f, 0x00000018},
413 { 0x0000005b, 0x00000004 }, 412 {0x0000005b, 0x00000004},
414 { 0x000380e6, 0x00000002 }, 413 {0x000380e6, 0x00000002},
415 { 0x040025c5, 0x00000002 }, 414 {0x040025c5, 0x00000002},
416 { 0x00007576, 0x00000002 }, 415 {0x00007576, 0x00000002},
417 { 0x00065000, 0x00000002 }, 416 {0x00065000, 0x00000002},
418 { 0x00009000, 0x00000002 }, 417 {0x00009000, 0x00000002},
419 { 0x00041000, 0x00000002 }, 418 {0x00041000, 0x00000002},
420 { 0x0c00350e, 0x00000002 }, 419 {0x0c00350e, 0x00000002},
421 { 0x00049000, 0x00000002 }, 420 {0x00049000, 0x00000002},
422 { 0x00051000, 0x00000002 }, 421 {0x00051000, 0x00000002},
423 { 0x01e785f8, 0x00000002 }, 422 {0x01e785f8, 0x00000002},
424 { 0x00200000, 0x00000002 }, 423 {0x00200000, 0x00000002},
425 { 0x0060007e, 0x0000000c }, 424 {0x0060007e, 0x0000000c},
426 { 0x00007563, 0x00000002 }, 425 {0x00007563, 0x00000002},
427 { 0x006075f0, 0x00000021 }, 426 {0x006075f0, 0x00000021},
428 { 0x20007073, 0x00000004 }, 427 {0x20007073, 0x00000004},
429 { 0x00005073, 0x00000004 }, 428 {0x00005073, 0x00000004},
430 { 0x000380e6, 0x00000002 }, 429 {0x000380e6, 0x00000002},
431 { 0x040025c5, 0x00000002 }, 430 {0x040025c5, 0x00000002},
432 { 0x00007576, 0x00000002 }, 431 {0x00007576, 0x00000002},
433 { 0x00007577, 0x00000002 }, 432 {0x00007577, 0x00000002},
434 { 0x0000750e, 0x00000002 }, 433 {0x0000750e, 0x00000002},
435 { 0x0000750f, 0x00000002 }, 434 {0x0000750f, 0x00000002},
436 { 0x00a05000, 0x00000002 }, 435 {0x00a05000, 0x00000002},
437 { 0x00600083, 0x0000000c }, 436 {0x00600083, 0x0000000c},
438 { 0x006075f0, 0x00000021 }, 437 {0x006075f0, 0x00000021},
439 { 0x000075f8, 0x00000002 }, 438 {0x000075f8, 0x00000002},
440 { 0x00000083, 0x00000004 }, 439 {0x00000083, 0x00000004},
441 { 0x000a750e, 0x00000002 }, 440 {0x000a750e, 0x00000002},
442 { 0x000380e6, 0x00000002 }, 441 {0x000380e6, 0x00000002},
443 { 0x040025c5, 0x00000002 }, 442 {0x040025c5, 0x00000002},
444 { 0x0020750f, 0x00000002 }, 443 {0x0020750f, 0x00000002},
445 { 0x00600086, 0x00000004 }, 444 {0x00600086, 0x00000004},
446 { 0x00007570, 0x00000002 }, 445 {0x00007570, 0x00000002},
447 { 0x00007571, 0x00000002 }, 446 {0x00007571, 0x00000002},
448 { 0x00007572, 0x00000006 }, 447 {0x00007572, 0x00000006},
449 { 0x000380e6, 0x00000002 }, 448 {0x000380e6, 0x00000002},
450 { 0x040025c5, 0x00000002 }, 449 {0x040025c5, 0x00000002},
451 { 0x00005000, 0x00000002 }, 450 {0x00005000, 0x00000002},
452 { 0x00a05000, 0x00000002 }, 451 {0x00a05000, 0x00000002},
453 { 0x00007568, 0x00000002 }, 452 {0x00007568, 0x00000002},
454 { 0x00061000, 0x00000002 }, 453 {0x00061000, 0x00000002},
455 { 0x00000095, 0x0000000c }, 454 {0x00000095, 0x0000000c},
456 { 0x00058000, 0x00000002 }, 455 {0x00058000, 0x00000002},
457 { 0x0c607562, 0x00000002 }, 456 {0x0c607562, 0x00000002},
458 { 0x00000097, 0x00000004 }, 457 {0x00000097, 0x00000004},
459 { 0x000380e6, 0x00000002 }, 458 {0x000380e6, 0x00000002},
460 { 0x040025c5, 0x00000002 }, 459 {0x040025c5, 0x00000002},
461 { 0x00600096, 0x00000004 }, 460 {0x00600096, 0x00000004},
462 { 0x400070e5, 0000000000 }, 461 {0x400070e5, 0000000000},
463 { 0x000380e6, 0x00000002 }, 462 {0x000380e6, 0x00000002},
464 { 0x040025c5, 0x00000002 }, 463 {0x040025c5, 0x00000002},
465 { 0x000380e5, 0x00000002 }, 464 {0x000380e5, 0x00000002},
466 { 0x000000a8, 0x0000001c }, 465 {0x000000a8, 0x0000001c},
467 { 0x000650aa, 0x00000018 }, 466 {0x000650aa, 0x00000018},
468 { 0x040025bb, 0x00000002 }, 467 {0x040025bb, 0x00000002},
469 { 0x000610ab, 0x00000018 }, 468 {0x000610ab, 0x00000018},
470 { 0x040075bc, 0000000000 }, 469 {0x040075bc, 0000000000},
471 { 0x000075bb, 0x00000002 }, 470 {0x000075bb, 0x00000002},
472 { 0x000075bc, 0000000000 }, 471 {0x000075bc, 0000000000},
473 { 0x00090000, 0x00000006 }, 472 {0x00090000, 0x00000006},
474 { 0x00090000, 0x00000002 }, 473 {0x00090000, 0x00000002},
475 { 0x000d8002, 0x00000006 }, 474 {0x000d8002, 0x00000006},
476 { 0x00007832, 0x00000002 }, 475 {0x00007832, 0x00000002},
477 { 0x00005000, 0x00000002 }, 476 {0x00005000, 0x00000002},
478 { 0x000380e7, 0x00000002 }, 477 {0x000380e7, 0x00000002},
479 { 0x04002c97, 0x00000002 }, 478 {0x04002c97, 0x00000002},
480 { 0x00007820, 0x00000002 }, 479 {0x00007820, 0x00000002},
481 { 0x00007821, 0x00000002 }, 480 {0x00007821, 0x00000002},
482 { 0x00007800, 0000000000 }, 481 {0x00007800, 0000000000},
483 { 0x01200000, 0x00000002 }, 482 {0x01200000, 0x00000002},
484 { 0x20077000, 0x00000002 }, 483 {0x20077000, 0x00000002},
485 { 0x01200000, 0x00000002 }, 484 {0x01200000, 0x00000002},
486 { 0x20007000, 0x00000002 }, 485 {0x20007000, 0x00000002},
487 { 0x00061000, 0x00000002 }, 486 {0x00061000, 0x00000002},
488 { 0x0120751b, 0x00000002 }, 487 {0x0120751b, 0x00000002},
489 { 0x8040750a, 0x00000002 }, 488 {0x8040750a, 0x00000002},
490 { 0x8040750b, 0x00000002 }, 489 {0x8040750b, 0x00000002},
491 { 0x00110000, 0x00000002 }, 490 {0x00110000, 0x00000002},
492 { 0x000380e5, 0x00000002 }, 491 {0x000380e5, 0x00000002},
493 { 0x000000c6, 0x0000001c }, 492 {0x000000c6, 0x0000001c},
494 { 0x000610ab, 0x00000018 }, 493 {0x000610ab, 0x00000018},
495 { 0x844075bd, 0x00000002 }, 494 {0x844075bd, 0x00000002},
496 { 0x000610aa, 0x00000018 }, 495 {0x000610aa, 0x00000018},
497 { 0x840075bb, 0x00000002 }, 496 {0x840075bb, 0x00000002},
498 { 0x000610ab, 0x00000018 }, 497 {0x000610ab, 0x00000018},
499 { 0x844075bc, 0x00000002 }, 498 {0x844075bc, 0x00000002},
500 { 0x000000c9, 0x00000004 }, 499 {0x000000c9, 0x00000004},
501 { 0x804075bd, 0x00000002 }, 500 {0x804075bd, 0x00000002},
502 { 0x800075bb, 0x00000002 }, 501 {0x800075bb, 0x00000002},
503 { 0x804075bc, 0x00000002 }, 502 {0x804075bc, 0x00000002},
504 { 0x00108000, 0x00000002 }, 503 {0x00108000, 0x00000002},
505 { 0x01400000, 0x00000002 }, 504 {0x01400000, 0x00000002},
506 { 0x006000cd, 0x0000000c }, 505 {0x006000cd, 0x0000000c},
507 { 0x20c07000, 0x00000020 }, 506 {0x20c07000, 0x00000020},
508 { 0x000000cf, 0x00000012 }, 507 {0x000000cf, 0x00000012},
509 { 0x00800000, 0x00000006 }, 508 {0x00800000, 0x00000006},
510 { 0x0080751d, 0x00000006 }, 509 {0x0080751d, 0x00000006},
511 { 0000000000, 0000000000 }, 510 {0000000000, 0000000000},
512 { 0x0000775c, 0x00000002 }, 511 {0x0000775c, 0x00000002},
513 { 0x00a05000, 0x00000002 }, 512 {0x00a05000, 0x00000002},
514 { 0x00661000, 0x00000002 }, 513 {0x00661000, 0x00000002},
515 { 0x0460275d, 0x00000020 }, 514 {0x0460275d, 0x00000020},
516 { 0x00004000, 0000000000 }, 515 {0x00004000, 0000000000},
517 { 0x01e00830, 0x00000002 }, 516 {0x01e00830, 0x00000002},
518 { 0x21007000, 0000000000 }, 517 {0x21007000, 0000000000},
519 { 0x6464614d, 0000000000 }, 518 {0x6464614d, 0000000000},
520 { 0x69687420, 0000000000 }, 519 {0x69687420, 0000000000},
521 { 0x00000073, 0000000000 }, 520 {0x00000073, 0000000000},
522 { 0000000000, 0000000000 }, 521 {0000000000, 0000000000},
523 { 0x00005000, 0x00000002 }, 522 {0x00005000, 0x00000002},
524 { 0x000380d0, 0x00000002 }, 523 {0x000380d0, 0x00000002},
525 { 0x040025e0, 0x00000002 }, 524 {0x040025e0, 0x00000002},
526 { 0x000075e1, 0000000000 }, 525 {0x000075e1, 0000000000},
527 { 0x00000001, 0000000000 }, 526 {0x00000001, 0000000000},
528 { 0x000380e0, 0x00000002 }, 527 {0x000380e0, 0x00000002},
529 { 0x04002394, 0x00000002 }, 528 {0x04002394, 0x00000002},
530 { 0x00005000, 0000000000 }, 529 {0x00005000, 0000000000},
531 { 0000000000, 0000000000 }, 530 {0000000000, 0000000000},
532 { 0000000000, 0000000000 }, 531 {0000000000, 0000000000},
533 { 0x00000008, 0000000000 }, 532 {0x00000008, 0000000000},
534 { 0x00000004, 0000000000 }, 533 {0x00000004, 0000000000},
535 { 0000000000, 0000000000 }, 534 {0000000000, 0000000000},
536 { 0000000000, 0000000000 }, 535 {0000000000, 0000000000},
537 { 0000000000, 0000000000 }, 536 {0000000000, 0000000000},
538 { 0000000000, 0000000000 }, 537 {0000000000, 0000000000},
539 { 0000000000, 0000000000 }, 538 {0000000000, 0000000000},
540 { 0000000000, 0000000000 }, 539 {0000000000, 0000000000},
541 { 0000000000, 0000000000 }, 540 {0000000000, 0000000000},
542 { 0000000000, 0000000000 }, 541 {0000000000, 0000000000},
543 { 0000000000, 0000000000 }, 542 {0000000000, 0000000000},
544 { 0000000000, 0000000000 }, 543 {0000000000, 0000000000},
545 { 0000000000, 0000000000 }, 544 {0000000000, 0000000000},
546 { 0000000000, 0000000000 }, 545 {0000000000, 0000000000},
547 { 0000000000, 0000000000 }, 546 {0000000000, 0000000000},
548 { 0000000000, 0000000000 }, 547 {0000000000, 0000000000},
549 { 0000000000, 0000000000 }, 548 {0000000000, 0000000000},
550 { 0000000000, 0000000000 }, 549 {0000000000, 0000000000},
551 { 0000000000, 0000000000 }, 550 {0000000000, 0000000000},
552 { 0000000000, 0000000000 }, 551 {0000000000, 0000000000},
553 { 0000000000, 0000000000 }, 552 {0000000000, 0000000000},
554 { 0000000000, 0000000000 }, 553 {0000000000, 0000000000},
555 { 0000000000, 0000000000 }, 554 {0000000000, 0000000000},
556 { 0000000000, 0000000000 }, 555 {0000000000, 0000000000},
557 { 0000000000, 0000000000 }, 556 {0000000000, 0000000000},
558 { 0000000000, 0000000000 }, 557 {0000000000, 0000000000},
559}; 558};
560 559
561static u32 R300_cp_microcode[][2] = { 560static u32 R300_cp_microcode[][2] = {
562 { 0x4200e000, 0000000000 }, 561 {0x4200e000, 0000000000},
563 { 0x4000e000, 0000000000 }, 562 {0x4000e000, 0000000000},
564 { 0x000000af, 0x00000008 }, 563 {0x000000af, 0x00000008},
565 { 0x000000b3, 0x00000008 }, 564 {0x000000b3, 0x00000008},
566 { 0x6c5a504f, 0000000000 }, 565 {0x6c5a504f, 0000000000},
567 { 0x4f4f497a, 0000000000 }, 566 {0x4f4f497a, 0000000000},
568 { 0x5a578288, 0000000000 }, 567 {0x5a578288, 0000000000},
569 { 0x4f91906a, 0000000000 }, 568 {0x4f91906a, 0000000000},
570 { 0x4f4f4f4f, 0000000000 }, 569 {0x4f4f4f4f, 0000000000},
571 { 0x4fe24f44, 0000000000 }, 570 {0x4fe24f44, 0000000000},
572 { 0x4f9c9c9c, 0000000000 }, 571 {0x4f9c9c9c, 0000000000},
573 { 0xdc4f4fde, 0000000000 }, 572 {0xdc4f4fde, 0000000000},
574 { 0xa1cd4f4f, 0000000000 }, 573 {0xa1cd4f4f, 0000000000},
575 { 0xd29d9d9d, 0000000000 }, 574 {0xd29d9d9d, 0000000000},
576 { 0x4f0f9fd7, 0000000000 }, 575 {0x4f0f9fd7, 0000000000},
577 { 0x000ca000, 0x00000004 }, 576 {0x000ca000, 0x00000004},
578 { 0x000d0012, 0x00000038 }, 577 {0x000d0012, 0x00000038},
579 { 0x0000e8b4, 0x00000004 }, 578 {0x0000e8b4, 0x00000004},
580 { 0x000d0014, 0x00000038 }, 579 {0x000d0014, 0x00000038},
581 { 0x0000e8b6, 0x00000004 }, 580 {0x0000e8b6, 0x00000004},
582 { 0x000d0016, 0x00000038 }, 581 {0x000d0016, 0x00000038},
583 { 0x0000e854, 0x00000004 }, 582 {0x0000e854, 0x00000004},
584 { 0x000d0018, 0x00000038 }, 583 {0x000d0018, 0x00000038},
585 { 0x0000e855, 0x00000004 }, 584 {0x0000e855, 0x00000004},
586 { 0x000d001a, 0x00000038 }, 585 {0x000d001a, 0x00000038},
587 { 0x0000e856, 0x00000004 }, 586 {0x0000e856, 0x00000004},
588 { 0x000d001c, 0x00000038 }, 587 {0x000d001c, 0x00000038},
589 { 0x0000e857, 0x00000004 }, 588 {0x0000e857, 0x00000004},
590 { 0x000d001e, 0x00000038 }, 589 {0x000d001e, 0x00000038},
591 { 0x0000e824, 0x00000004 }, 590 {0x0000e824, 0x00000004},
592 { 0x000d0020, 0x00000038 }, 591 {0x000d0020, 0x00000038},
593 { 0x0000e825, 0x00000004 }, 592 {0x0000e825, 0x00000004},
594 { 0x000d0022, 0x00000038 }, 593 {0x000d0022, 0x00000038},
595 { 0x0000e830, 0x00000004 }, 594 {0x0000e830, 0x00000004},
596 { 0x000d0024, 0x00000038 }, 595 {0x000d0024, 0x00000038},
597 { 0x0000f0c0, 0x00000004 }, 596 {0x0000f0c0, 0x00000004},
598 { 0x000d0026, 0x00000038 }, 597 {0x000d0026, 0x00000038},
599 { 0x0000f0c1, 0x00000004 }, 598 {0x0000f0c1, 0x00000004},
600 { 0x000d0028, 0x00000038 }, 599 {0x000d0028, 0x00000038},
601 { 0x0000f041, 0x00000004 }, 600 {0x0000f041, 0x00000004},
602 { 0x000d002a, 0x00000038 }, 601 {0x000d002a, 0x00000038},
603 { 0x0000f184, 0x00000004 }, 602 {0x0000f184, 0x00000004},
604 { 0x000d002c, 0x00000038 }, 603 {0x000d002c, 0x00000038},
605 { 0x0000f185, 0x00000004 }, 604 {0x0000f185, 0x00000004},
606 { 0x000d002e, 0x00000038 }, 605 {0x000d002e, 0x00000038},
607 { 0x0000f186, 0x00000004 }, 606 {0x0000f186, 0x00000004},
608 { 0x000d0030, 0x00000038 }, 607 {0x000d0030, 0x00000038},
609 { 0x0000f187, 0x00000004 }, 608 {0x0000f187, 0x00000004},
610 { 0x000d0032, 0x00000038 }, 609 {0x000d0032, 0x00000038},
611 { 0x0000f180, 0x00000004 }, 610 {0x0000f180, 0x00000004},
612 { 0x000d0034, 0x00000038 }, 611 {0x000d0034, 0x00000038},
613 { 0x0000f393, 0x00000004 }, 612 {0x0000f393, 0x00000004},
614 { 0x000d0036, 0x00000038 }, 613 {0x000d0036, 0x00000038},
615 { 0x0000f38a, 0x00000004 }, 614 {0x0000f38a, 0x00000004},
616 { 0x000d0038, 0x00000038 }, 615 {0x000d0038, 0x00000038},
617 { 0x0000f38e, 0x00000004 }, 616 {0x0000f38e, 0x00000004},
618 { 0x0000e821, 0x00000004 }, 617 {0x0000e821, 0x00000004},
619 { 0x0140a000, 0x00000004 }, 618 {0x0140a000, 0x00000004},
620 { 0x00000043, 0x00000018 }, 619 {0x00000043, 0x00000018},
621 { 0x00cce800, 0x00000004 }, 620 {0x00cce800, 0x00000004},
622 { 0x001b0001, 0x00000004 }, 621 {0x001b0001, 0x00000004},
623 { 0x08004800, 0x00000004 }, 622 {0x08004800, 0x00000004},
624 { 0x001b0001, 0x00000004 }, 623 {0x001b0001, 0x00000004},
625 { 0x08004800, 0x00000004 }, 624 {0x08004800, 0x00000004},
626 { 0x001b0001, 0x00000004 }, 625 {0x001b0001, 0x00000004},
627 { 0x08004800, 0x00000004 }, 626 {0x08004800, 0x00000004},
628 { 0x0000003a, 0x00000008 }, 627 {0x0000003a, 0x00000008},
629 { 0x0000a000, 0000000000 }, 628 {0x0000a000, 0000000000},
630 { 0x02c0a000, 0x00000004 }, 629 {0x02c0a000, 0x00000004},
631 { 0x000ca000, 0x00000004 }, 630 {0x000ca000, 0x00000004},
632 { 0x00130000, 0x00000004 }, 631 {0x00130000, 0x00000004},
633 { 0x000c2000, 0x00000004 }, 632 {0x000c2000, 0x00000004},
634 { 0xc980c045, 0x00000008 }, 633 {0xc980c045, 0x00000008},
635 { 0x2000451d, 0x00000004 }, 634 {0x2000451d, 0x00000004},
636 { 0x0000e580, 0x00000004 }, 635 {0x0000e580, 0x00000004},
637 { 0x000ce581, 0x00000004 }, 636 {0x000ce581, 0x00000004},
638 { 0x08004580, 0x00000004 }, 637 {0x08004580, 0x00000004},
639 { 0x000ce581, 0x00000004 }, 638 {0x000ce581, 0x00000004},
640 { 0x0000004c, 0x00000008 }, 639 {0x0000004c, 0x00000008},
641 { 0x0000a000, 0000000000 }, 640 {0x0000a000, 0000000000},
642 { 0x000c2000, 0x00000004 }, 641 {0x000c2000, 0x00000004},
643 { 0x0000e50e, 0x00000004 }, 642 {0x0000e50e, 0x00000004},
644 { 0x00032000, 0x00000004 }, 643 {0x00032000, 0x00000004},
645 { 0x00022056, 0x00000028 }, 644 {0x00022056, 0x00000028},
646 { 0x00000056, 0x00000024 }, 645 {0x00000056, 0x00000024},
647 { 0x0800450f, 0x00000004 }, 646 {0x0800450f, 0x00000004},
648 { 0x0000a050, 0x00000008 }, 647 {0x0000a050, 0x00000008},
649 { 0x0000e565, 0x00000004 }, 648 {0x0000e565, 0x00000004},
650 { 0x0000e566, 0x00000004 }, 649 {0x0000e566, 0x00000004},
651 { 0x00000057, 0x00000008 }, 650 {0x00000057, 0x00000008},
652 { 0x03cca5b4, 0x00000004 }, 651 {0x03cca5b4, 0x00000004},
653 { 0x05432000, 0x00000004 }, 652 {0x05432000, 0x00000004},
654 { 0x00022000, 0x00000004 }, 653 {0x00022000, 0x00000004},
655 { 0x4ccce063, 0x00000030 }, 654 {0x4ccce063, 0x00000030},
656 { 0x08274565, 0x00000004 }, 655 {0x08274565, 0x00000004},
657 { 0x00000063, 0x00000030 }, 656 {0x00000063, 0x00000030},
658 { 0x08004564, 0x00000004 }, 657 {0x08004564, 0x00000004},
659 { 0x0000e566, 0x00000004 }, 658 {0x0000e566, 0x00000004},
660 { 0x0000005a, 0x00000008 }, 659 {0x0000005a, 0x00000008},
661 { 0x00802066, 0x00000010 }, 660 {0x00802066, 0x00000010},
662 { 0x00202000, 0x00000004 }, 661 {0x00202000, 0x00000004},
663 { 0x001b00ff, 0x00000004 }, 662 {0x001b00ff, 0x00000004},
664 { 0x01000069, 0x00000010 }, 663 {0x01000069, 0x00000010},
665 { 0x001f2000, 0x00000004 }, 664 {0x001f2000, 0x00000004},
666 { 0x001c00ff, 0x00000004 }, 665 {0x001c00ff, 0x00000004},
667 { 0000000000, 0x0000000c }, 666 {0000000000, 0x0000000c},
668 { 0x00000085, 0x00000030 }, 667 {0x00000085, 0x00000030},
669 { 0x0000005a, 0x00000008 }, 668 {0x0000005a, 0x00000008},
670 { 0x0000e576, 0x00000004 }, 669 {0x0000e576, 0x00000004},
671 { 0x000ca000, 0x00000004 }, 670 {0x000ca000, 0x00000004},
672 { 0x00012000, 0x00000004 }, 671 {0x00012000, 0x00000004},
673 { 0x00082000, 0x00000004 }, 672 {0x00082000, 0x00000004},
674 { 0x1800650e, 0x00000004 }, 673 {0x1800650e, 0x00000004},
675 { 0x00092000, 0x00000004 }, 674 {0x00092000, 0x00000004},
676 { 0x000a2000, 0x00000004 }, 675 {0x000a2000, 0x00000004},
677 { 0x000f0000, 0x00000004 }, 676 {0x000f0000, 0x00000004},
678 { 0x00400000, 0x00000004 }, 677 {0x00400000, 0x00000004},
679 { 0x00000079, 0x00000018 }, 678 {0x00000079, 0x00000018},
680 { 0x0000e563, 0x00000004 }, 679 {0x0000e563, 0x00000004},
681 { 0x00c0e5f9, 0x000000c2 }, 680 {0x00c0e5f9, 0x000000c2},
682 { 0x0000006e, 0x00000008 }, 681 {0x0000006e, 0x00000008},
683 { 0x0000a06e, 0x00000008 }, 682 {0x0000a06e, 0x00000008},
684 { 0x0000e576, 0x00000004 }, 683 {0x0000e576, 0x00000004},
685 { 0x0000e577, 0x00000004 }, 684 {0x0000e577, 0x00000004},
686 { 0x0000e50e, 0x00000004 }, 685 {0x0000e50e, 0x00000004},
687 { 0x0000e50f, 0x00000004 }, 686 {0x0000e50f, 0x00000004},
688 { 0x0140a000, 0x00000004 }, 687 {0x0140a000, 0x00000004},
689 { 0x0000007c, 0x00000018 }, 688 {0x0000007c, 0x00000018},
690 { 0x00c0e5f9, 0x000000c2 }, 689 {0x00c0e5f9, 0x000000c2},
691 { 0x0000007c, 0x00000008 }, 690 {0x0000007c, 0x00000008},
692 { 0x0014e50e, 0x00000004 }, 691 {0x0014e50e, 0x00000004},
693 { 0x0040e50f, 0x00000004 }, 692 {0x0040e50f, 0x00000004},
694 { 0x00c0007f, 0x00000008 }, 693 {0x00c0007f, 0x00000008},
695 { 0x0000e570, 0x00000004 }, 694 {0x0000e570, 0x00000004},
696 { 0x0000e571, 0x00000004 }, 695 {0x0000e571, 0x00000004},
697 { 0x0000e572, 0x0000000c }, 696 {0x0000e572, 0x0000000c},
698 { 0x0000a000, 0x00000004 }, 697 {0x0000a000, 0x00000004},
699 { 0x0140a000, 0x00000004 }, 698 {0x0140a000, 0x00000004},
700 { 0x0000e568, 0x00000004 }, 699 {0x0000e568, 0x00000004},
701 { 0x000c2000, 0x00000004 }, 700 {0x000c2000, 0x00000004},
702 { 0x00000089, 0x00000018 }, 701 {0x00000089, 0x00000018},
703 { 0x000b0000, 0x00000004 }, 702 {0x000b0000, 0x00000004},
704 { 0x18c0e562, 0x00000004 }, 703 {0x18c0e562, 0x00000004},
705 { 0x0000008b, 0x00000008 }, 704 {0x0000008b, 0x00000008},
706 { 0x00c0008a, 0x00000008 }, 705 {0x00c0008a, 0x00000008},
707 { 0x000700e4, 0x00000004 }, 706 {0x000700e4, 0x00000004},
708 { 0x00000097, 0x00000038 }, 707 {0x00000097, 0x00000038},
709 { 0x000ca099, 0x00000030 }, 708 {0x000ca099, 0x00000030},
710 { 0x080045bb, 0x00000004 }, 709 {0x080045bb, 0x00000004},
711 { 0x000c209a, 0x00000030 }, 710 {0x000c209a, 0x00000030},
712 { 0x0800e5bc, 0000000000 }, 711 {0x0800e5bc, 0000000000},
713 { 0x0000e5bb, 0x00000004 }, 712 {0x0000e5bb, 0x00000004},
714 { 0x0000e5bc, 0000000000 }, 713 {0x0000e5bc, 0000000000},
715 { 0x00120000, 0x0000000c }, 714 {0x00120000, 0x0000000c},
716 { 0x00120000, 0x00000004 }, 715 {0x00120000, 0x00000004},
717 { 0x001b0002, 0x0000000c }, 716 {0x001b0002, 0x0000000c},
718 { 0x0000a000, 0x00000004 }, 717 {0x0000a000, 0x00000004},
719 { 0x0000e821, 0x00000004 }, 718 {0x0000e821, 0x00000004},
720 { 0x0000e800, 0000000000 }, 719 {0x0000e800, 0000000000},
721 { 0x0000e821, 0x00000004 }, 720 {0x0000e821, 0x00000004},
722 { 0x0000e82e, 0000000000 }, 721 {0x0000e82e, 0000000000},
723 { 0x02cca000, 0x00000004 }, 722 {0x02cca000, 0x00000004},
724 { 0x00140000, 0x00000004 }, 723 {0x00140000, 0x00000004},
725 { 0x000ce1cc, 0x00000004 }, 724 {0x000ce1cc, 0x00000004},
726 { 0x050de1cd, 0x00000004 }, 725 {0x050de1cd, 0x00000004},
727 { 0x000000a7, 0x00000020 }, 726 {0x000000a7, 0x00000020},
728 { 0x4200e000, 0000000000 }, 727 {0x4200e000, 0000000000},
729 { 0x000000ae, 0x00000038 }, 728 {0x000000ae, 0x00000038},
730 { 0x000ca000, 0x00000004 }, 729 {0x000ca000, 0x00000004},
731 { 0x00140000, 0x00000004 }, 730 {0x00140000, 0x00000004},
732 { 0x000c2000, 0x00000004 }, 731 {0x000c2000, 0x00000004},
733 { 0x00160000, 0x00000004 }, 732 {0x00160000, 0x00000004},
734 { 0x700ce000, 0x00000004 }, 733 {0x700ce000, 0x00000004},
735 { 0x001400aa, 0x00000008 }, 734 {0x001400aa, 0x00000008},
736 { 0x4000e000, 0000000000 }, 735 {0x4000e000, 0000000000},
737 { 0x02400000, 0x00000004 }, 736 {0x02400000, 0x00000004},
738 { 0x400ee000, 0x00000004 }, 737 {0x400ee000, 0x00000004},
739 { 0x02400000, 0x00000004 }, 738 {0x02400000, 0x00000004},
740 { 0x4000e000, 0000000000 }, 739 {0x4000e000, 0000000000},
741 { 0x000c2000, 0x00000004 }, 740 {0x000c2000, 0x00000004},
742 { 0x0240e51b, 0x00000004 }, 741 {0x0240e51b, 0x00000004},
743 { 0x0080e50a, 0x00000005 }, 742 {0x0080e50a, 0x00000005},
744 { 0x0080e50b, 0x00000005 }, 743 {0x0080e50b, 0x00000005},
745 { 0x00220000, 0x00000004 }, 744 {0x00220000, 0x00000004},
746 { 0x000700e4, 0x00000004 }, 745 {0x000700e4, 0x00000004},
747 { 0x000000c1, 0x00000038 }, 746 {0x000000c1, 0x00000038},
748 { 0x000c209a, 0x00000030 }, 747 {0x000c209a, 0x00000030},
749 { 0x0880e5bd, 0x00000005 }, 748 {0x0880e5bd, 0x00000005},
750 { 0x000c2099, 0x00000030 }, 749 {0x000c2099, 0x00000030},
751 { 0x0800e5bb, 0x00000005 }, 750 {0x0800e5bb, 0x00000005},
752 { 0x000c209a, 0x00000030 }, 751 {0x000c209a, 0x00000030},
753 { 0x0880e5bc, 0x00000005 }, 752 {0x0880e5bc, 0x00000005},
754 { 0x000000c4, 0x00000008 }, 753 {0x000000c4, 0x00000008},
755 { 0x0080e5bd, 0x00000005 }, 754 {0x0080e5bd, 0x00000005},
756 { 0x0000e5bb, 0x00000005 }, 755 {0x0000e5bb, 0x00000005},
757 { 0x0080e5bc, 0x00000005 }, 756 {0x0080e5bc, 0x00000005},
758 { 0x00210000, 0x00000004 }, 757 {0x00210000, 0x00000004},
759 { 0x02800000, 0x00000004 }, 758 {0x02800000, 0x00000004},
760 { 0x00c000c8, 0x00000018 }, 759 {0x00c000c8, 0x00000018},
761 { 0x4180e000, 0x00000040 }, 760 {0x4180e000, 0x00000040},
762 { 0x000000ca, 0x00000024 }, 761 {0x000000ca, 0x00000024},
763 { 0x01000000, 0x0000000c }, 762 {0x01000000, 0x0000000c},
764 { 0x0100e51d, 0x0000000c }, 763 {0x0100e51d, 0x0000000c},
765 { 0x000045bb, 0x00000004 }, 764 {0x000045bb, 0x00000004},
766 { 0x000080c4, 0x00000008 }, 765 {0x000080c4, 0x00000008},
767 { 0x0000f3ce, 0x00000004 }, 766 {0x0000f3ce, 0x00000004},
768 { 0x0140a000, 0x00000004 }, 767 {0x0140a000, 0x00000004},
769 { 0x00cc2000, 0x00000004 }, 768 {0x00cc2000, 0x00000004},
770 { 0x08c053cf, 0x00000040 }, 769 {0x08c053cf, 0x00000040},
771 { 0x00008000, 0000000000 }, 770 {0x00008000, 0000000000},
772 { 0x0000f3d2, 0x00000004 }, 771 {0x0000f3d2, 0x00000004},
773 { 0x0140a000, 0x00000004 }, 772 {0x0140a000, 0x00000004},
774 { 0x00cc2000, 0x00000004 }, 773 {0x00cc2000, 0x00000004},
775 { 0x08c053d3, 0x00000040 }, 774 {0x08c053d3, 0x00000040},
776 { 0x00008000, 0000000000 }, 775 {0x00008000, 0000000000},
777 { 0x0000f39d, 0x00000004 }, 776 {0x0000f39d, 0x00000004},
778 { 0x0140a000, 0x00000004 }, 777 {0x0140a000, 0x00000004},
779 { 0x00cc2000, 0x00000004 }, 778 {0x00cc2000, 0x00000004},
780 { 0x08c0539e, 0x00000040 }, 779 {0x08c0539e, 0x00000040},
781 { 0x00008000, 0000000000 }, 780 {0x00008000, 0000000000},
782 { 0x03c00830, 0x00000004 }, 781 {0x03c00830, 0x00000004},
783 { 0x4200e000, 0000000000 }, 782 {0x4200e000, 0000000000},
784 { 0x0000a000, 0x00000004 }, 783 {0x0000a000, 0x00000004},
785 { 0x200045e0, 0x00000004 }, 784 {0x200045e0, 0x00000004},
786 { 0x0000e5e1, 0000000000 }, 785 {0x0000e5e1, 0000000000},
787 { 0x00000001, 0000000000 }, 786 {0x00000001, 0000000000},
788 { 0x000700e1, 0x00000004 }, 787 {0x000700e1, 0x00000004},
789 { 0x0800e394, 0000000000 }, 788 {0x0800e394, 0000000000},
790 { 0000000000, 0000000000 }, 789 {0000000000, 0000000000},
791 { 0000000000, 0000000000 }, 790 {0000000000, 0000000000},
792 { 0000000000, 0000000000 }, 791 {0000000000, 0000000000},
793 { 0000000000, 0000000000 }, 792 {0000000000, 0000000000},
794 { 0000000000, 0000000000 }, 793 {0000000000, 0000000000},
795 { 0000000000, 0000000000 }, 794 {0000000000, 0000000000},
796 { 0000000000, 0000000000 }, 795 {0000000000, 0000000000},
797 { 0000000000, 0000000000 }, 796 {0000000000, 0000000000},
798 { 0000000000, 0000000000 }, 797 {0000000000, 0000000000},
799 { 0000000000, 0000000000 }, 798 {0000000000, 0000000000},
800 { 0000000000, 0000000000 }, 799 {0000000000, 0000000000},
801 { 0000000000, 0000000000 }, 800 {0000000000, 0000000000},
802 { 0000000000, 0000000000 }, 801 {0000000000, 0000000000},
803 { 0000000000, 0000000000 }, 802 {0000000000, 0000000000},
804 { 0000000000, 0000000000 }, 803 {0000000000, 0000000000},
805 { 0000000000, 0000000000 }, 804 {0000000000, 0000000000},
806 { 0000000000, 0000000000 }, 805 {0000000000, 0000000000},
807 { 0000000000, 0000000000 }, 806 {0000000000, 0000000000},
808 { 0000000000, 0000000000 }, 807 {0000000000, 0000000000},
809 { 0000000000, 0000000000 }, 808 {0000000000, 0000000000},
810 { 0000000000, 0000000000 }, 809 {0000000000, 0000000000},
811 { 0000000000, 0000000000 }, 810 {0000000000, 0000000000},
812 { 0000000000, 0000000000 }, 811 {0000000000, 0000000000},
813 { 0000000000, 0000000000 }, 812 {0000000000, 0000000000},
814 { 0000000000, 0000000000 }, 813 {0000000000, 0000000000},
815 { 0000000000, 0000000000 }, 814 {0000000000, 0000000000},
816 { 0000000000, 0000000000 }, 815 {0000000000, 0000000000},
817 { 0000000000, 0000000000 }, 816 {0000000000, 0000000000},
818}; 817};
819 818
820static int RADEON_READ_PLL(drm_device_t *dev, int addr) 819static int RADEON_READ_PLL(drm_device_t * dev, int addr)
821{ 820{
822 drm_radeon_private_t *dev_priv = dev->dev_private; 821 drm_radeon_private_t *dev_priv = dev->dev_private;
823 822
@@ -825,151 +824,148 @@ static int RADEON_READ_PLL(drm_device_t *dev, int addr)
825 return RADEON_READ(RADEON_CLOCK_CNTL_DATA); 824 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
826} 825}
827 826
828static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) 827static int RADEON_READ_PCIE(drm_radeon_private_t * dev_priv, int addr)
829{ 828{
830 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); 829 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
831 return RADEON_READ(RADEON_PCIE_DATA); 830 return RADEON_READ(RADEON_PCIE_DATA);
832} 831}
833 832
834#if RADEON_FIFO_DEBUG 833#if RADEON_FIFO_DEBUG
835static void radeon_status( drm_radeon_private_t *dev_priv ) 834static void radeon_status(drm_radeon_private_t * dev_priv)
836{ 835{
837 printk( "%s:\n", __FUNCTION__ ); 836 printk("%s:\n", __FUNCTION__);
838 printk( "RBBM_STATUS = 0x%08x\n", 837 printk("RBBM_STATUS = 0x%08x\n",
839 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) ); 838 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
840 printk( "CP_RB_RTPR = 0x%08x\n", 839 printk("CP_RB_RTPR = 0x%08x\n",
841 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) ); 840 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
842 printk( "CP_RB_WTPR = 0x%08x\n", 841 printk("CP_RB_WTPR = 0x%08x\n",
843 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) ); 842 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
844 printk( "AIC_CNTL = 0x%08x\n", 843 printk("AIC_CNTL = 0x%08x\n",
845 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) ); 844 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
846 printk( "AIC_STAT = 0x%08x\n", 845 printk("AIC_STAT = 0x%08x\n",
847 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) ); 846 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
848 printk( "AIC_PT_BASE = 0x%08x\n", 847 printk("AIC_PT_BASE = 0x%08x\n",
849 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) ); 848 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
850 printk( "TLB_ADDR = 0x%08x\n", 849 printk("TLB_ADDR = 0x%08x\n",
851 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) ); 850 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
852 printk( "TLB_DATA = 0x%08x\n", 851 printk("TLB_DATA = 0x%08x\n",
853 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) ); 852 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
854} 853}
855#endif 854#endif
856 855
857
858/* ================================================================ 856/* ================================================================
859 * Engine, FIFO control 857 * Engine, FIFO control
860 */ 858 */
861 859
862static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv ) 860static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
863{ 861{
864 u32 tmp; 862 u32 tmp;
865 int i; 863 int i;
866 864
867 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 865 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
868 866
869 tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ); 867 tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
870 tmp |= RADEON_RB2D_DC_FLUSH_ALL; 868 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
871 RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp ); 869 RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp);
872 870
873 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 871 for (i = 0; i < dev_priv->usec_timeout; i++) {
874 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ) 872 if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
875 & RADEON_RB2D_DC_BUSY) ) { 873 & RADEON_RB2D_DC_BUSY)) {
876 return 0; 874 return 0;
877 } 875 }
878 DRM_UDELAY( 1 ); 876 DRM_UDELAY(1);
879 } 877 }
880 878
881#if RADEON_FIFO_DEBUG 879#if RADEON_FIFO_DEBUG
882 DRM_ERROR( "failed!\n" ); 880 DRM_ERROR("failed!\n");
883 radeon_status( dev_priv ); 881 radeon_status(dev_priv);
884#endif 882#endif
885 return DRM_ERR(EBUSY); 883 return DRM_ERR(EBUSY);
886} 884}
887 885
888static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv, 886static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
889 int entries )
890{ 887{
891 int i; 888 int i;
892 889
893 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 890 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
894 891
895 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 892 for (i = 0; i < dev_priv->usec_timeout; i++) {
896 int slots = ( RADEON_READ( RADEON_RBBM_STATUS ) 893 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
897 & RADEON_RBBM_FIFOCNT_MASK ); 894 & RADEON_RBBM_FIFOCNT_MASK);
898 if ( slots >= entries ) return 0; 895 if (slots >= entries)
899 DRM_UDELAY( 1 ); 896 return 0;
897 DRM_UDELAY(1);
900 } 898 }
901 899
902#if RADEON_FIFO_DEBUG 900#if RADEON_FIFO_DEBUG
903 DRM_ERROR( "failed!\n" ); 901 DRM_ERROR("failed!\n");
904 radeon_status( dev_priv ); 902 radeon_status(dev_priv);
905#endif 903#endif
906 return DRM_ERR(EBUSY); 904 return DRM_ERR(EBUSY);
907} 905}
908 906
909static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv ) 907static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
910{ 908{
911 int i, ret; 909 int i, ret;
912 910
913 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 911 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
914 912
915 ret = radeon_do_wait_for_fifo( dev_priv, 64 ); 913 ret = radeon_do_wait_for_fifo(dev_priv, 64);
916 if ( ret ) return ret; 914 if (ret)
915 return ret;
917 916
918 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 917 for (i = 0; i < dev_priv->usec_timeout; i++) {
919 if ( !(RADEON_READ( RADEON_RBBM_STATUS ) 918 if (!(RADEON_READ(RADEON_RBBM_STATUS)
920 & RADEON_RBBM_ACTIVE) ) { 919 & RADEON_RBBM_ACTIVE)) {
921 radeon_do_pixcache_flush( dev_priv ); 920 radeon_do_pixcache_flush(dev_priv);
922 return 0; 921 return 0;
923 } 922 }
924 DRM_UDELAY( 1 ); 923 DRM_UDELAY(1);
925 } 924 }
926 925
927#if RADEON_FIFO_DEBUG 926#if RADEON_FIFO_DEBUG
928 DRM_ERROR( "failed!\n" ); 927 DRM_ERROR("failed!\n");
929 radeon_status( dev_priv ); 928 radeon_status(dev_priv);
930#endif 929#endif
931 return DRM_ERR(EBUSY); 930 return DRM_ERR(EBUSY);
932} 931}
933 932
934
935/* ================================================================ 933/* ================================================================
936 * CP control, initialization 934 * CP control, initialization
937 */ 935 */
938 936
939/* Load the microcode for the CP */ 937/* Load the microcode for the CP */
940static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv ) 938static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
941{ 939{
942 int i; 940 int i;
943 DRM_DEBUG( "\n" ); 941 DRM_DEBUG("\n");
944 942
945 radeon_do_wait_for_idle( dev_priv ); 943 radeon_do_wait_for_idle(dev_priv);
946 944
947 RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 ); 945 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
948 946
949 if (dev_priv->microcode_version==UCODE_R200) { 947 if (dev_priv->microcode_version == UCODE_R200) {
950 DRM_INFO("Loading R200 Microcode\n"); 948 DRM_INFO("Loading R200 Microcode\n");
951 for ( i = 0 ; i < 256 ; i++ ) 949 for (i = 0; i < 256; i++) {
952 { 950 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
953 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, 951 R200_cp_microcode[i][1]);
954 R200_cp_microcode[i][1] ); 952 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
955 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, 953 R200_cp_microcode[i][0]);
956 R200_cp_microcode[i][0] );
957 } 954 }
958 } else if (dev_priv->microcode_version==UCODE_R300) { 955 } else if (dev_priv->microcode_version == UCODE_R300) {
959 DRM_INFO("Loading R300 Microcode\n"); 956 DRM_INFO("Loading R300 Microcode\n");
960 for ( i = 0 ; i < 256 ; i++ ) 957 for (i = 0; i < 256; i++) {
961 { 958 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
962 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, 959 R300_cp_microcode[i][1]);
963 R300_cp_microcode[i][1] ); 960 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
964 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, 961 R300_cp_microcode[i][0]);
965 R300_cp_microcode[i][0] );
966 } 962 }
967 } else { 963 } else {
968 for ( i = 0 ; i < 256 ; i++ ) { 964 for (i = 0; i < 256; i++) {
969 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, 965 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
970 radeon_cp_microcode[i][1] ); 966 radeon_cp_microcode[i][1]);
971 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, 967 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
972 radeon_cp_microcode[i][0] ); 968 radeon_cp_microcode[i][0]);
973 } 969 }
974 } 970 }
975} 971}
@@ -978,25 +974,25 @@ static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
978 * prior to a wait for idle, as it informs the engine that the command 974 * prior to a wait for idle, as it informs the engine that the command
979 * stream is ending. 975 * stream is ending.
980 */ 976 */
981static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv ) 977static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
982{ 978{
983 DRM_DEBUG( "\n" ); 979 DRM_DEBUG("\n");
984#if 0 980#if 0
985 u32 tmp; 981 u32 tmp;
986 982
987 tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31); 983 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
988 RADEON_WRITE( RADEON_CP_RB_WPTR, tmp ); 984 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
989#endif 985#endif
990} 986}
991 987
992/* Wait for the CP to go idle. 988/* Wait for the CP to go idle.
993 */ 989 */
994int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ) 990int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
995{ 991{
996 RING_LOCALS; 992 RING_LOCALS;
997 DRM_DEBUG( "\n" ); 993 DRM_DEBUG("\n");
998 994
999 BEGIN_RING( 6 ); 995 BEGIN_RING(6);
1000 996
1001 RADEON_PURGE_CACHE(); 997 RADEON_PURGE_CACHE();
1002 RADEON_PURGE_ZCACHE(); 998 RADEON_PURGE_ZCACHE();
@@ -1005,23 +1001,23 @@ int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
1005 ADVANCE_RING(); 1001 ADVANCE_RING();
1006 COMMIT_RING(); 1002 COMMIT_RING();
1007 1003
1008 return radeon_do_wait_for_idle( dev_priv ); 1004 return radeon_do_wait_for_idle(dev_priv);
1009} 1005}
1010 1006
1011/* Start the Command Processor. 1007/* Start the Command Processor.
1012 */ 1008 */
1013static void radeon_do_cp_start( drm_radeon_private_t *dev_priv ) 1009static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1014{ 1010{
1015 RING_LOCALS; 1011 RING_LOCALS;
1016 DRM_DEBUG( "\n" ); 1012 DRM_DEBUG("\n");
1017 1013
1018 radeon_do_wait_for_idle( dev_priv ); 1014 radeon_do_wait_for_idle(dev_priv);
1019 1015
1020 RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode ); 1016 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1021 1017
1022 dev_priv->cp_running = 1; 1018 dev_priv->cp_running = 1;
1023 1019
1024 BEGIN_RING( 6 ); 1020 BEGIN_RING(6);
1025 1021
1026 RADEON_PURGE_CACHE(); 1022 RADEON_PURGE_CACHE();
1027 RADEON_PURGE_ZCACHE(); 1023 RADEON_PURGE_ZCACHE();
@@ -1035,14 +1031,14 @@ static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
1035 * commands, so you must wait for the CP command stream to complete 1031 * commands, so you must wait for the CP command stream to complete
1036 * before calling this routine. 1032 * before calling this routine.
1037 */ 1033 */
1038static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv ) 1034static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1039{ 1035{
1040 u32 cur_read_ptr; 1036 u32 cur_read_ptr;
1041 DRM_DEBUG( "\n" ); 1037 DRM_DEBUG("\n");
1042 1038
1043 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); 1039 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1044 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); 1040 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1045 SET_RING_HEAD( dev_priv, cur_read_ptr ); 1041 SET_RING_HEAD(dev_priv, cur_read_ptr);
1046 dev_priv->ring.tail = cur_read_ptr; 1042 dev_priv->ring.tail = cur_read_ptr;
1047} 1043}
1048 1044
@@ -1050,120 +1046,116 @@ static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
1050 * commands, so you must flush the command stream and wait for the CP 1046 * commands, so you must flush the command stream and wait for the CP
1051 * to go idle before calling this routine. 1047 * to go idle before calling this routine.
1052 */ 1048 */
1053static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv ) 1049static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1054{ 1050{
1055 DRM_DEBUG( "\n" ); 1051 DRM_DEBUG("\n");
1056 1052
1057 RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS ); 1053 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1058 1054
1059 dev_priv->cp_running = 0; 1055 dev_priv->cp_running = 0;
1060} 1056}
1061 1057
1062/* Reset the engine. This will stop the CP if it is running. 1058/* Reset the engine. This will stop the CP if it is running.
1063 */ 1059 */
1064static int radeon_do_engine_reset( drm_device_t *dev ) 1060static int radeon_do_engine_reset(drm_device_t * dev)
1065{ 1061{
1066 drm_radeon_private_t *dev_priv = dev->dev_private; 1062 drm_radeon_private_t *dev_priv = dev->dev_private;
1067 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; 1063 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1068 DRM_DEBUG( "\n" ); 1064 DRM_DEBUG("\n");
1069
1070 radeon_do_pixcache_flush( dev_priv );
1071
1072 clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
1073 mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
1074
1075 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
1076 RADEON_FORCEON_MCLKA |
1077 RADEON_FORCEON_MCLKB |
1078 RADEON_FORCEON_YCLKA |
1079 RADEON_FORCEON_YCLKB |
1080 RADEON_FORCEON_MC |
1081 RADEON_FORCEON_AIC ) );
1082
1083 rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
1084 1065
1085 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset | 1066 radeon_do_pixcache_flush(dev_priv);
1086 RADEON_SOFT_RESET_CP | 1067
1068 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1069 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1070
1071 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1072 RADEON_FORCEON_MCLKA |
1073 RADEON_FORCEON_MCLKB |
1074 RADEON_FORCEON_YCLKA |
1075 RADEON_FORCEON_YCLKB |
1076 RADEON_FORCEON_MC |
1077 RADEON_FORCEON_AIC));
1078
1079 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1080
1081 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1082 RADEON_SOFT_RESET_CP |
1083 RADEON_SOFT_RESET_HI |
1084 RADEON_SOFT_RESET_SE |
1085 RADEON_SOFT_RESET_RE |
1086 RADEON_SOFT_RESET_PP |
1087 RADEON_SOFT_RESET_E2 |
1088 RADEON_SOFT_RESET_RB));
1089 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1090 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1091 ~(RADEON_SOFT_RESET_CP |
1087 RADEON_SOFT_RESET_HI | 1092 RADEON_SOFT_RESET_HI |
1088 RADEON_SOFT_RESET_SE | 1093 RADEON_SOFT_RESET_SE |
1089 RADEON_SOFT_RESET_RE | 1094 RADEON_SOFT_RESET_RE |
1090 RADEON_SOFT_RESET_PP | 1095 RADEON_SOFT_RESET_PP |
1091 RADEON_SOFT_RESET_E2 | 1096 RADEON_SOFT_RESET_E2 |
1092 RADEON_SOFT_RESET_RB ) ); 1097 RADEON_SOFT_RESET_RB)));
1093 RADEON_READ( RADEON_RBBM_SOFT_RESET ); 1098 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1094 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset & 1099
1095 ~( RADEON_SOFT_RESET_CP | 1100 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1096 RADEON_SOFT_RESET_HI | 1101 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1097 RADEON_SOFT_RESET_SE | 1102 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1098 RADEON_SOFT_RESET_RE |
1099 RADEON_SOFT_RESET_PP |
1100 RADEON_SOFT_RESET_E2 |
1101 RADEON_SOFT_RESET_RB ) ) );
1102 RADEON_READ( RADEON_RBBM_SOFT_RESET );
1103
1104
1105 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
1106 RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
1107 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset );
1108 1103
1109 /* Reset the CP ring */ 1104 /* Reset the CP ring */
1110 radeon_do_cp_reset( dev_priv ); 1105 radeon_do_cp_reset(dev_priv);
1111 1106
1112 /* The CP is no longer running after an engine reset */ 1107 /* The CP is no longer running after an engine reset */
1113 dev_priv->cp_running = 0; 1108 dev_priv->cp_running = 0;
1114 1109
1115 /* Reset any pending vertex, indirect buffers */ 1110 /* Reset any pending vertex, indirect buffers */
1116 radeon_freelist_reset( dev ); 1111 radeon_freelist_reset(dev);
1117 1112
1118 return 0; 1113 return 0;
1119} 1114}
1120 1115
1121static void radeon_cp_init_ring_buffer( drm_device_t *dev, 1116static void radeon_cp_init_ring_buffer(drm_device_t * dev,
1122 drm_radeon_private_t *dev_priv ) 1117 drm_radeon_private_t * dev_priv)
1123{ 1118{
1124 u32 ring_start, cur_read_ptr; 1119 u32 ring_start, cur_read_ptr;
1125 u32 tmp; 1120 u32 tmp;
1126 1121
1127 /* Initialize the memory controller */ 1122 /* Initialize the memory controller */
1128 RADEON_WRITE( RADEON_MC_FB_LOCATION, 1123 RADEON_WRITE(RADEON_MC_FB_LOCATION,
1129 ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 ) 1124 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1130 | ( dev_priv->fb_location >> 16 ) ); 1125 | (dev_priv->fb_location >> 16));
1131 1126
1132#if __OS_HAS_AGP 1127#if __OS_HAS_AGP
1133 if ( !dev_priv->is_pci ) { 1128 if (!dev_priv->is_pci) {
1134 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 1129 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1135 (((dev_priv->gart_vm_start - 1 + 1130 (((dev_priv->gart_vm_start - 1 +
1136 dev_priv->gart_size) & 0xffff0000) | 1131 dev_priv->gart_size) & 0xffff0000) |
1137 (dev_priv->gart_vm_start >> 16)) ); 1132 (dev_priv->gart_vm_start >> 16)));
1138 1133
1139 ring_start = (dev_priv->cp_ring->offset 1134 ring_start = (dev_priv->cp_ring->offset
1140 - dev->agp->base 1135 - dev->agp->base + dev_priv->gart_vm_start);
1141 + dev_priv->gart_vm_start); 1136 } else
1142 } else
1143#endif 1137#endif
1144 ring_start = (dev_priv->cp_ring->offset 1138 ring_start = (dev_priv->cp_ring->offset
1145 - dev->sg->handle 1139 - dev->sg->handle + dev_priv->gart_vm_start);
1146 + dev_priv->gart_vm_start);
1147 1140
1148 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start ); 1141 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1149 1142
1150 /* Set the write pointer delay */ 1143 /* Set the write pointer delay */
1151 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 ); 1144 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1152 1145
1153 /* Initialize the ring buffer's read and write pointers */ 1146 /* Initialize the ring buffer's read and write pointers */
1154 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); 1147 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1155 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); 1148 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1156 SET_RING_HEAD( dev_priv, cur_read_ptr ); 1149 SET_RING_HEAD(dev_priv, cur_read_ptr);
1157 dev_priv->ring.tail = cur_read_ptr; 1150 dev_priv->ring.tail = cur_read_ptr;
1158 1151
1159#if __OS_HAS_AGP 1152#if __OS_HAS_AGP
1160 if ( !dev_priv->is_pci ) { 1153 if (!dev_priv->is_pci) {
1161 /* set RADEON_AGP_BASE here instead of relying on X from user space */ 1154 /* set RADEON_AGP_BASE here instead of relying on X from user space */
1162 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); 1155 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1163 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, 1156 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1164 dev_priv->ring_rptr->offset 1157 dev_priv->ring_rptr->offset
1165 - dev->agp->base 1158 - dev->agp->base + dev_priv->gart_vm_start);
1166 + dev_priv->gart_vm_start);
1167 } else 1159 } else
1168#endif 1160#endif
1169 { 1161 {
@@ -1173,11 +1165,10 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
1173 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; 1165 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
1174 page_ofs = tmp_ofs >> PAGE_SHIFT; 1166 page_ofs = tmp_ofs >> PAGE_SHIFT;
1175 1167
1176 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, 1168 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1177 entry->busaddr[page_ofs]); 1169 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1178 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", 1170 (unsigned long)entry->busaddr[page_ofs],
1179 (unsigned long) entry->busaddr[page_ofs], 1171 entry->handle + tmp_ofs);
1180 entry->handle + tmp_ofs );
1181 } 1172 }
1182 1173
1183 /* Initialize the scratch register pointer. This will cause 1174 /* Initialize the scratch register pointer. This will cause
@@ -1187,64 +1178,64 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
1187 * We simply put this behind the ring read pointer, this works 1178 * We simply put this behind the ring read pointer, this works
1188 * with PCI GART as well as (whatever kind of) AGP GART 1179 * with PCI GART as well as (whatever kind of) AGP GART
1189 */ 1180 */
1190 RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR ) 1181 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1191 + RADEON_SCRATCH_REG_OFFSET ); 1182 + RADEON_SCRATCH_REG_OFFSET);
1192 1183
1193 dev_priv->scratch = ((__volatile__ u32 *) 1184 dev_priv->scratch = ((__volatile__ u32 *)
1194 dev_priv->ring_rptr->handle + 1185 dev_priv->ring_rptr->handle +
1195 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); 1186 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1196 1187
1197 RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 ); 1188 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1198 1189
1199 /* Writeback doesn't seem to work everywhere, test it first */ 1190 /* Writeback doesn't seem to work everywhere, test it first */
1200 DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 ); 1191 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1201 RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef ); 1192 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1202 1193
1203 for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) { 1194 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1204 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef ) 1195 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1196 0xdeadbeef)
1205 break; 1197 break;
1206 DRM_UDELAY( 1 ); 1198 DRM_UDELAY(1);
1207 } 1199 }
1208 1200
1209 if ( tmp < dev_priv->usec_timeout ) { 1201 if (tmp < dev_priv->usec_timeout) {
1210 dev_priv->writeback_works = 1; 1202 dev_priv->writeback_works = 1;
1211 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp ); 1203 DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp);
1212 } else { 1204 } else {
1213 dev_priv->writeback_works = 0; 1205 dev_priv->writeback_works = 0;
1214 DRM_DEBUG( "writeback test failed\n" ); 1206 DRM_DEBUG("writeback test failed\n");
1215 } 1207 }
1216 1208
1217 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; 1209 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1218 RADEON_WRITE( RADEON_LAST_FRAME_REG, 1210 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1219 dev_priv->sarea_priv->last_frame );
1220 1211
1221 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; 1212 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1222 RADEON_WRITE( RADEON_LAST_DISPATCH_REG, 1213 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1223 dev_priv->sarea_priv->last_dispatch ); 1214 dev_priv->sarea_priv->last_dispatch);
1224 1215
1225 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; 1216 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1226 RADEON_WRITE( RADEON_LAST_CLEAR_REG, 1217 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1227 dev_priv->sarea_priv->last_clear );
1228 1218
1229 /* Set ring buffer size */ 1219 /* Set ring buffer size */
1230#ifdef __BIG_ENDIAN 1220#ifdef __BIG_ENDIAN
1231 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT ); 1221 RADEON_WRITE(RADEON_CP_RB_CNTL,
1222 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1232#else 1223#else
1233 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw ); 1224 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1234#endif 1225#endif
1235 1226
1236 radeon_do_wait_for_idle( dev_priv ); 1227 radeon_do_wait_for_idle(dev_priv);
1237 1228
1238 /* Turn on bus mastering */ 1229 /* Turn on bus mastering */
1239 tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS; 1230 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1240 RADEON_WRITE( RADEON_BUS_CNTL, tmp ); 1231 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1241 1232
1242 /* Sync everything up */ 1233 /* Sync everything up */
1243 RADEON_WRITE( RADEON_ISYNC_CNTL, 1234 RADEON_WRITE(RADEON_ISYNC_CNTL,
1244 (RADEON_ISYNC_ANY2D_IDLE3D | 1235 (RADEON_ISYNC_ANY2D_IDLE3D |
1245 RADEON_ISYNC_ANY3D_IDLE2D | 1236 RADEON_ISYNC_ANY3D_IDLE2D |
1246 RADEON_ISYNC_WAIT_IDLEGUI | 1237 RADEON_ISYNC_WAIT_IDLEGUI |
1247 RADEON_ISYNC_CPSCRATCH_IDLEGUI) ); 1238 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1248} 1239}
1249 1240
1250/* Enable or disable PCI-E GART on the chip */ 1241/* Enable or disable PCI-E GART on the chip */
@@ -1254,35 +1245,42 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1254 if (on) { 1245 if (on) {
1255 1246
1256 DRM_DEBUG("programming pcie %08X %08lX %08X\n", 1247 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1257 dev_priv->gart_vm_start, (long)dev_priv->gart_info.bus_addr, 1248 dev_priv->gart_vm_start,
1249 (long)dev_priv->gart_info.bus_addr,
1258 dev_priv->gart_size); 1250 dev_priv->gart_size);
1259 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, dev_priv->gart_vm_start); 1251 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1260 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, dev_priv->gart_info.bus_addr); 1252 dev_priv->gart_vm_start);
1261 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, dev_priv->gart_vm_start); 1253 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1262 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, dev_priv->gart_vm_start 1254 dev_priv->gart_info.bus_addr);
1263 + dev_priv->gart_size - 1); 1255 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1264 1256 dev_priv->gart_vm_start);
1257 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1258 dev_priv->gart_vm_start +
1259 dev_priv->gart_size - 1);
1260
1265 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */ 1261 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1266 1262
1267 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, RADEON_PCIE_TX_GART_EN); 1263 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1264 RADEON_PCIE_TX_GART_EN);
1268 } else { 1265 } else {
1269 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 1266 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1267 tmp & ~RADEON_PCIE_TX_GART_EN);
1270 } 1268 }
1271} 1269}
1272 1270
1273/* Enable or disable PCI GART on the chip */ 1271/* Enable or disable PCI GART on the chip */
1274static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on ) 1272static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1275{ 1273{
1276 u32 tmp = RADEON_READ( RADEON_AIC_CNTL ); 1274 u32 tmp = RADEON_READ(RADEON_AIC_CNTL);
1277 1275
1278 if (dev_priv->flags & CHIP_IS_PCIE) 1276 if (dev_priv->flags & CHIP_IS_PCIE) {
1279 {
1280 radeon_set_pciegart(dev_priv, on); 1277 radeon_set_pciegart(dev_priv, on);
1281 return; 1278 return;
1282 } 1279 }
1283 1280
1284 if ( on ) { 1281 if (on) {
1285 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN ); 1282 RADEON_WRITE(RADEON_AIC_CNTL,
1283 tmp | RADEON_PCIGART_TRANSLATE_EN);
1286 1284
1287 /* set PCI GART page-table base address 1285 /* set PCI GART page-table base address
1288 */ 1286 */
@@ -1290,53 +1288,54 @@ static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
1290 1288
1291 /* set address range for PCI address translate 1289 /* set address range for PCI address translate
1292 */ 1290 */
1293 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start ); 1291 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1294 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start 1292 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1295 + dev_priv->gart_size - 1); 1293 + dev_priv->gart_size - 1);
1296 1294
1297 /* Turn off AGP aperture -- is this required for PCI GART? 1295 /* Turn off AGP aperture -- is this required for PCI GART?
1298 */ 1296 */
1299 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */ 1297 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1300 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */ 1298 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1301 } else { 1299 } else {
1302 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN ); 1300 RADEON_WRITE(RADEON_AIC_CNTL,
1301 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1303 } 1302 }
1304} 1303}
1305 1304
1306static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) 1305static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1307{ 1306{
1308 drm_radeon_private_t *dev_priv = dev->dev_private;; 1307 drm_radeon_private_t *dev_priv = dev->dev_private;;
1309 DRM_DEBUG( "\n" ); 1308 DRM_DEBUG("\n");
1310 1309
1311 dev_priv->is_pci = init->is_pci; 1310 dev_priv->is_pci = init->is_pci;
1312 1311
1313 if ( dev_priv->is_pci && !dev->sg ) { 1312 if (dev_priv->is_pci && !dev->sg) {
1314 DRM_ERROR( "PCI GART memory not allocated!\n" ); 1313 DRM_ERROR("PCI GART memory not allocated!\n");
1315 dev->dev_private = (void *)dev_priv; 1314 dev->dev_private = (void *)dev_priv;
1316 radeon_do_cleanup_cp(dev); 1315 radeon_do_cleanup_cp(dev);
1317 return DRM_ERR(EINVAL); 1316 return DRM_ERR(EINVAL);
1318 } 1317 }
1319 1318
1320 dev_priv->usec_timeout = init->usec_timeout; 1319 dev_priv->usec_timeout = init->usec_timeout;
1321 if ( dev_priv->usec_timeout < 1 || 1320 if (dev_priv->usec_timeout < 1 ||
1322 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) { 1321 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1323 DRM_DEBUG( "TIMEOUT problem!\n" ); 1322 DRM_DEBUG("TIMEOUT problem!\n");
1324 dev->dev_private = (void *)dev_priv; 1323 dev->dev_private = (void *)dev_priv;
1325 radeon_do_cleanup_cp(dev); 1324 radeon_do_cleanup_cp(dev);
1326 return DRM_ERR(EINVAL); 1325 return DRM_ERR(EINVAL);
1327 } 1326 }
1328 1327
1329 switch(init->func) { 1328 switch (init->func) {
1330 case RADEON_INIT_R200_CP: 1329 case RADEON_INIT_R200_CP:
1331 dev_priv->microcode_version=UCODE_R200; 1330 dev_priv->microcode_version = UCODE_R200;
1332 break; 1331 break;
1333 case RADEON_INIT_R300_CP: 1332 case RADEON_INIT_R300_CP:
1334 dev_priv->microcode_version=UCODE_R300; 1333 dev_priv->microcode_version = UCODE_R300;
1335 break; 1334 break;
1336 default: 1335 default:
1337 dev_priv->microcode_version=UCODE_R100; 1336 dev_priv->microcode_version = UCODE_R100;
1338 } 1337 }
1339 1338
1340 dev_priv->do_boxes = 0; 1339 dev_priv->do_boxes = 0;
1341 dev_priv->cp_mode = init->cp_mode; 1340 dev_priv->cp_mode = init->cp_mode;
1342 1341
@@ -1344,15 +1343,15 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1344 * but the ring can be in either AGP or PCI space for the ring 1343 * but the ring can be in either AGP or PCI space for the ring
1345 * read pointer. 1344 * read pointer.
1346 */ 1345 */
1347 if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) && 1346 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1348 ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) { 1347 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1349 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode ); 1348 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1350 dev->dev_private = (void *)dev_priv; 1349 dev->dev_private = (void *)dev_priv;
1351 radeon_do_cleanup_cp(dev); 1350 radeon_do_cleanup_cp(dev);
1352 return DRM_ERR(EINVAL); 1351 return DRM_ERR(EINVAL);
1353 } 1352 }
1354 1353
1355 switch ( init->fb_bpp ) { 1354 switch (init->fb_bpp) {
1356 case 16: 1355 case 16:
1357 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 1356 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1358 break; 1357 break;
@@ -1361,12 +1360,12 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1361 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 1360 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1362 break; 1361 break;
1363 } 1362 }
1364 dev_priv->front_offset = init->front_offset; 1363 dev_priv->front_offset = init->front_offset;
1365 dev_priv->front_pitch = init->front_pitch; 1364 dev_priv->front_pitch = init->front_pitch;
1366 dev_priv->back_offset = init->back_offset; 1365 dev_priv->back_offset = init->back_offset;
1367 dev_priv->back_pitch = init->back_pitch; 1366 dev_priv->back_pitch = init->back_pitch;
1368 1367
1369 switch ( init->depth_bpp ) { 1368 switch (init->depth_bpp) {
1370 case 16: 1369 case 16:
1371 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 1370 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1372 break; 1371 break;
@@ -1375,8 +1374,8 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1375 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 1374 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1376 break; 1375 break;
1377 } 1376 }
1378 dev_priv->depth_offset = init->depth_offset; 1377 dev_priv->depth_offset = init->depth_offset;
1379 dev_priv->depth_pitch = init->depth_pitch; 1378 dev_priv->depth_pitch = init->depth_pitch;
1380 1379
1381 /* Hardware state for depth clears. Remove this if/when we no 1380 /* Hardware state for depth clears. Remove this if/when we no
1382 * longer clear the depth buffer with a 3D rectangle. Hard-code 1381 * longer clear the depth buffer with a 3D rectangle. Hard-code
@@ -1385,16 +1384,16 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1385 */ 1384 */
1386 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | 1385 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1387 (dev_priv->color_fmt << 10) | 1386 (dev_priv->color_fmt << 10) |
1388 (dev_priv->microcode_version == UCODE_R100 ? RADEON_ZBLOCK16 : 0)); 1387 (dev_priv->microcode_version ==
1388 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1389 1389
1390 dev_priv->depth_clear.rb3d_zstencilcntl = 1390 dev_priv->depth_clear.rb3d_zstencilcntl =
1391 (dev_priv->depth_fmt | 1391 (dev_priv->depth_fmt |
1392 RADEON_Z_TEST_ALWAYS | 1392 RADEON_Z_TEST_ALWAYS |
1393 RADEON_STENCIL_TEST_ALWAYS | 1393 RADEON_STENCIL_TEST_ALWAYS |
1394 RADEON_STENCIL_S_FAIL_REPLACE | 1394 RADEON_STENCIL_S_FAIL_REPLACE |
1395 RADEON_STENCIL_ZPASS_REPLACE | 1395 RADEON_STENCIL_ZPASS_REPLACE |
1396 RADEON_STENCIL_ZFAIL_REPLACE | 1396 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1397 RADEON_Z_WRITE_ENABLE);
1398 1397
1399 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | 1398 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1400 RADEON_BFACE_SOLID | 1399 RADEON_BFACE_SOLID |
@@ -1416,8 +1415,8 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1416 dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1415 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1417 dev_priv->buffers_offset = init->buffers_offset; 1416 dev_priv->buffers_offset = init->buffers_offset;
1418 dev_priv->gart_textures_offset = init->gart_textures_offset; 1417 dev_priv->gart_textures_offset = init->gart_textures_offset;
1419 1418
1420 if(!dev_priv->sarea) { 1419 if (!dev_priv->sarea) {
1421 DRM_ERROR("could not find sarea!\n"); 1420 DRM_ERROR("could not find sarea!\n");
1422 dev->dev_private = (void *)dev_priv; 1421 dev->dev_private = (void *)dev_priv;
1423 radeon_do_cleanup_cp(dev); 1422 radeon_do_cleanup_cp(dev);
@@ -1425,21 +1424,21 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1425 } 1424 }
1426 1425
1427 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); 1426 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1428 if(!dev_priv->mmio) { 1427 if (!dev_priv->mmio) {
1429 DRM_ERROR("could not find mmio region!\n"); 1428 DRM_ERROR("could not find mmio region!\n");
1430 dev->dev_private = (void *)dev_priv; 1429 dev->dev_private = (void *)dev_priv;
1431 radeon_do_cleanup_cp(dev); 1430 radeon_do_cleanup_cp(dev);
1432 return DRM_ERR(EINVAL); 1431 return DRM_ERR(EINVAL);
1433 } 1432 }
1434 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1433 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1435 if(!dev_priv->cp_ring) { 1434 if (!dev_priv->cp_ring) {
1436 DRM_ERROR("could not find cp ring region!\n"); 1435 DRM_ERROR("could not find cp ring region!\n");
1437 dev->dev_private = (void *)dev_priv; 1436 dev->dev_private = (void *)dev_priv;
1438 radeon_do_cleanup_cp(dev); 1437 radeon_do_cleanup_cp(dev);
1439 return DRM_ERR(EINVAL); 1438 return DRM_ERR(EINVAL);
1440 } 1439 }
1441 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1440 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1442 if(!dev_priv->ring_rptr) { 1441 if (!dev_priv->ring_rptr) {
1443 DRM_ERROR("could not find ring read pointer!\n"); 1442 DRM_ERROR("could not find ring read pointer!\n");
1444 dev->dev_private = (void *)dev_priv; 1443 dev->dev_private = (void *)dev_priv;
1445 radeon_do_cleanup_cp(dev); 1444 radeon_do_cleanup_cp(dev);
@@ -1447,16 +1446,17 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1447 } 1446 }
1448 dev->agp_buffer_token = init->buffers_offset; 1447 dev->agp_buffer_token = init->buffers_offset;
1449 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1448 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1450 if(!dev->agp_buffer_map) { 1449 if (!dev->agp_buffer_map) {
1451 DRM_ERROR("could not find dma buffer region!\n"); 1450 DRM_ERROR("could not find dma buffer region!\n");
1452 dev->dev_private = (void *)dev_priv; 1451 dev->dev_private = (void *)dev_priv;
1453 radeon_do_cleanup_cp(dev); 1452 radeon_do_cleanup_cp(dev);
1454 return DRM_ERR(EINVAL); 1453 return DRM_ERR(EINVAL);
1455 } 1454 }
1456 1455
1457 if ( init->gart_textures_offset ) { 1456 if (init->gart_textures_offset) {
1458 dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset); 1457 dev_priv->gart_textures =
1459 if ( !dev_priv->gart_textures ) { 1458 drm_core_findmap(dev, init->gart_textures_offset);
1459 if (!dev_priv->gart_textures) {
1460 DRM_ERROR("could not find GART texture region!\n"); 1460 DRM_ERROR("could not find GART texture region!\n");
1461 dev->dev_private = (void *)dev_priv; 1461 dev->dev_private = (void *)dev_priv;
1462 radeon_do_cleanup_cp(dev); 1462 radeon_do_cleanup_cp(dev);
@@ -1465,17 +1465,17 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1465 } 1465 }
1466 1466
1467 dev_priv->sarea_priv = 1467 dev_priv->sarea_priv =
1468 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle + 1468 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1469 init->sarea_priv_offset); 1469 init->sarea_priv_offset);
1470 1470
1471#if __OS_HAS_AGP 1471#if __OS_HAS_AGP
1472 if ( !dev_priv->is_pci ) { 1472 if (!dev_priv->is_pci) {
1473 drm_core_ioremap( dev_priv->cp_ring, dev ); 1473 drm_core_ioremap(dev_priv->cp_ring, dev);
1474 drm_core_ioremap( dev_priv->ring_rptr, dev ); 1474 drm_core_ioremap(dev_priv->ring_rptr, dev);
1475 drm_core_ioremap( dev->agp_buffer_map, dev ); 1475 drm_core_ioremap(dev->agp_buffer_map, dev);
1476 if(!dev_priv->cp_ring->handle || 1476 if (!dev_priv->cp_ring->handle ||
1477 !dev_priv->ring_rptr->handle || 1477 !dev_priv->ring_rptr->handle ||
1478 !dev->agp_buffer_map->handle) { 1478 !dev->agp_buffer_map->handle) {
1479 DRM_ERROR("could not find ioremap agp regions!\n"); 1479 DRM_ERROR("could not find ioremap agp regions!\n");
1480 dev->dev_private = (void *)dev_priv; 1480 dev->dev_private = (void *)dev_priv;
1481 radeon_do_cleanup_cp(dev); 1481 radeon_do_cleanup_cp(dev);
@@ -1484,140 +1484,146 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1484 } else 1484 } else
1485#endif 1485#endif
1486 { 1486 {
1487 dev_priv->cp_ring->handle = 1487 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1488 (void *)dev_priv->cp_ring->offset;
1489 dev_priv->ring_rptr->handle = 1488 dev_priv->ring_rptr->handle =
1490 (void *)dev_priv->ring_rptr->offset; 1489 (void *)dev_priv->ring_rptr->offset;
1491 dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset; 1490 dev->agp_buffer_map->handle =
1492 1491 (void *)dev->agp_buffer_map->offset;
1493 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n", 1492
1494 dev_priv->cp_ring->handle ); 1493 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1495 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n", 1494 dev_priv->cp_ring->handle);
1496 dev_priv->ring_rptr->handle ); 1495 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1497 DRM_DEBUG( "dev->agp_buffer_map->handle %p\n", 1496 dev_priv->ring_rptr->handle);
1498 dev->agp_buffer_map->handle ); 1497 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1498 dev->agp_buffer_map->handle);
1499 } 1499 }
1500 1500
1501 dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION ) 1501 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1502 & 0xffff ) << 16; 1502 & 0xffff) << 16;
1503 1503
1504 dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) | 1504 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1505 ( ( dev_priv->front_offset 1505 ((dev_priv->front_offset
1506 + dev_priv->fb_location ) >> 10 ) ); 1506 + dev_priv->fb_location) >> 10));
1507 1507
1508 dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) | 1508 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1509 ( ( dev_priv->back_offset 1509 ((dev_priv->back_offset
1510 + dev_priv->fb_location ) >> 10 ) ); 1510 + dev_priv->fb_location) >> 10));
1511
1512 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1513 ( ( dev_priv->depth_offset
1514 + dev_priv->fb_location ) >> 10 ) );
1515 1511
1512 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1513 ((dev_priv->depth_offset
1514 + dev_priv->fb_location) >> 10));
1516 1515
1517 dev_priv->gart_size = init->gart_size; 1516 dev_priv->gart_size = init->gart_size;
1518 dev_priv->gart_vm_start = dev_priv->fb_location 1517 dev_priv->gart_vm_start = dev_priv->fb_location
1519 + RADEON_READ( RADEON_CONFIG_APER_SIZE ); 1518 + RADEON_READ(RADEON_CONFIG_APER_SIZE);
1520 1519
1521#if __OS_HAS_AGP 1520#if __OS_HAS_AGP
1522 if ( !dev_priv->is_pci ) 1521 if (!dev_priv->is_pci)
1523 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1522 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1524 - dev->agp->base 1523 - dev->agp->base
1525 + dev_priv->gart_vm_start); 1524 + dev_priv->gart_vm_start);
1526 else 1525 else
1527#endif 1526#endif
1528 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1527 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1529 - dev->sg->handle 1528 - dev->sg->handle
1530 + dev_priv->gart_vm_start); 1529 + dev_priv->gart_vm_start);
1531 1530
1532 DRM_DEBUG( "dev_priv->gart_size %d\n", 1531 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1533 dev_priv->gart_size ); 1532 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1534 DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n", 1533 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1535 dev_priv->gart_vm_start ); 1534 dev_priv->gart_buffers_offset);
1536 DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n", 1535
1537 dev_priv->gart_buffers_offset ); 1536 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1538 1537 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1539 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1540 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1541 + init->ring_size / sizeof(u32)); 1538 + init->ring_size / sizeof(u32));
1542 dev_priv->ring.size = init->ring_size; 1539 dev_priv->ring.size = init->ring_size;
1543 dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 ); 1540 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1544 1541
1545 dev_priv->ring.tail_mask = 1542 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1546 (dev_priv->ring.size / sizeof(u32)) - 1;
1547 1543
1548 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 1544 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1549 1545
1550#if __OS_HAS_AGP 1546#if __OS_HAS_AGP
1551 if ( !dev_priv->is_pci ) { 1547 if (!dev_priv->is_pci) {
1552 /* Turn off PCI GART */ 1548 /* Turn off PCI GART */
1553 radeon_set_pcigart( dev_priv, 0 ); 1549 radeon_set_pcigart(dev_priv, 0);
1554 } else 1550 } else
1555#endif 1551#endif
1556 { 1552 {
1557 /* if we have an offset set from userspace */ 1553 /* if we have an offset set from userspace */
1558 if (dev_priv->pcigart_offset) { 1554 if (dev_priv->pcigart_offset) {
1559 dev_priv->gart_info.bus_addr = dev_priv->pcigart_offset + dev_priv->fb_location; 1555 dev_priv->gart_info.bus_addr =
1560 dev_priv->gart_info.addr = (unsigned long)drm_ioremap(dev_priv->gart_info.bus_addr, RADEON_PCIGART_TABLE_SIZE, dev); 1556 dev_priv->pcigart_offset + dev_priv->fb_location;
1561 1557 dev_priv->gart_info.addr =
1562 dev_priv->gart_info.is_pcie = !!(dev_priv->flags & CHIP_IS_PCIE); 1558 (unsigned long)drm_ioremap(dev_priv->gart_info.
1563 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_FB; 1559 bus_addr,
1564 1560 RADEON_PCIGART_TABLE_SIZE,
1565 DRM_DEBUG("Setting phys_pci_gart to %08lX %08lX\n", dev_priv->gart_info.addr, dev_priv->pcigart_offset); 1561 dev);
1566 } 1562
1567 else { 1563 dev_priv->gart_info.is_pcie =
1568 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; 1564 !!(dev_priv->flags & CHIP_IS_PCIE);
1569 dev_priv->gart_info.addr = dev_priv->gart_info.bus_addr= 0; 1565 dev_priv->gart_info.gart_table_location =
1570 if (dev_priv->flags & CHIP_IS_PCIE) 1566 DRM_ATI_GART_FB;
1571 { 1567
1572 DRM_ERROR("Cannot use PCI Express without GART in FB memory\n"); 1568 DRM_DEBUG("Setting phys_pci_gart to %08lX %08lX\n",
1569 dev_priv->gart_info.addr,
1570 dev_priv->pcigart_offset);
1571 } else {
1572 dev_priv->gart_info.gart_table_location =
1573 DRM_ATI_GART_MAIN;
1574 dev_priv->gart_info.addr =
1575 dev_priv->gart_info.bus_addr = 0;
1576 if (dev_priv->flags & CHIP_IS_PCIE) {
1577 DRM_ERROR
1578 ("Cannot use PCI Express without GART in FB memory\n");
1573 radeon_do_cleanup_cp(dev); 1579 radeon_do_cleanup_cp(dev);
1574 return DRM_ERR(EINVAL); 1580 return DRM_ERR(EINVAL);
1575 } 1581 }
1576 } 1582 }
1577 1583
1578 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { 1584 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1579 DRM_ERROR( "failed to init PCI GART!\n" ); 1585 DRM_ERROR("failed to init PCI GART!\n");
1580 dev->dev_private = (void *)dev_priv; 1586 dev->dev_private = (void *)dev_priv;
1581 radeon_do_cleanup_cp(dev); 1587 radeon_do_cleanup_cp(dev);
1582 return DRM_ERR(ENOMEM); 1588 return DRM_ERR(ENOMEM);
1583 } 1589 }
1584 1590
1585 /* Turn on PCI GART */ 1591 /* Turn on PCI GART */
1586 radeon_set_pcigart( dev_priv, 1 ); 1592 radeon_set_pcigart(dev_priv, 1);
1587 } 1593 }
1588 1594
1589 radeon_cp_load_microcode( dev_priv ); 1595 radeon_cp_load_microcode(dev_priv);
1590 radeon_cp_init_ring_buffer( dev, dev_priv ); 1596 radeon_cp_init_ring_buffer(dev, dev_priv);
1591 1597
1592 dev_priv->last_buf = 0; 1598 dev_priv->last_buf = 0;
1593 1599
1594 dev->dev_private = (void *)dev_priv; 1600 dev->dev_private = (void *)dev_priv;
1595 1601
1596 radeon_do_engine_reset( dev ); 1602 radeon_do_engine_reset(dev);
1597 1603
1598 return 0; 1604 return 0;
1599} 1605}
1600 1606
1601static int radeon_do_cleanup_cp( drm_device_t *dev ) 1607static int radeon_do_cleanup_cp(drm_device_t * dev)
1602{ 1608{
1603 drm_radeon_private_t *dev_priv = dev->dev_private; 1609 drm_radeon_private_t *dev_priv = dev->dev_private;
1604 DRM_DEBUG( "\n" ); 1610 DRM_DEBUG("\n");
1605 1611
1606 /* Make sure interrupts are disabled here because the uninstall ioctl 1612 /* Make sure interrupts are disabled here because the uninstall ioctl
1607 * may not have been called from userspace and after dev_private 1613 * may not have been called from userspace and after dev_private
1608 * is freed, it's too late. 1614 * is freed, it's too late.
1609 */ 1615 */
1610 if ( dev->irq_enabled ) drm_irq_uninstall(dev); 1616 if (dev->irq_enabled)
1617 drm_irq_uninstall(dev);
1611 1618
1612#if __OS_HAS_AGP 1619#if __OS_HAS_AGP
1613 if ( !dev_priv->is_pci ) { 1620 if (!dev_priv->is_pci) {
1614 if ( dev_priv->cp_ring != NULL ) 1621 if (dev_priv->cp_ring != NULL)
1615 drm_core_ioremapfree( dev_priv->cp_ring, dev ); 1622 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1616 if ( dev_priv->ring_rptr != NULL ) 1623 if (dev_priv->ring_rptr != NULL)
1617 drm_core_ioremapfree( dev_priv->ring_rptr, dev ); 1624 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1618 if ( dev->agp_buffer_map != NULL ) 1625 if (dev->agp_buffer_map != NULL) {
1619 { 1626 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1620 drm_core_ioremapfree( dev->agp_buffer_map, dev );
1621 dev->agp_buffer_map = NULL; 1627 dev->agp_buffer_map = NULL;
1622 } 1628 }
1623 } else 1629 } else
@@ -1626,103 +1632,103 @@ static int radeon_do_cleanup_cp( drm_device_t *dev )
1626 if (dev_priv->gart_info.bus_addr) 1632 if (dev_priv->gart_info.bus_addr)
1627 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) 1633 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1628 DRM_ERROR("failed to cleanup PCI GART!\n"); 1634 DRM_ERROR("failed to cleanup PCI GART!\n");
1629 1635
1630 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) 1636 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1631 { 1637 drm_ioremapfree((void *)dev_priv->gart_info.addr,
1632 drm_ioremapfree((void *)dev_priv->gart_info.addr, RADEON_PCIGART_TABLE_SIZE, dev); 1638 RADEON_PCIGART_TABLE_SIZE, dev);
1633 dev_priv->gart_info.addr = 0; 1639 dev_priv->gart_info.addr = 0;
1634 } 1640 }
1635 } 1641 }
1636 1642
1637 /* only clear to the start of flags */ 1643 /* only clear to the start of flags */
1638 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1644 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1639 1645
1640 return 0; 1646 return 0;
1641} 1647}
1642 1648
1643/* This code will reinit the Radeon CP hardware after a resume from disc. 1649/* This code will reinit the Radeon CP hardware after a resume from disc.
1644 * AFAIK, it would be very difficult to pickle the state at suspend time, so 1650 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1645 * here we make sure that all Radeon hardware initialisation is re-done without 1651 * here we make sure that all Radeon hardware initialisation is re-done without
1646 * affecting running applications. 1652 * affecting running applications.
1647 * 1653 *
1648 * Charl P. Botha <http://cpbotha.net> 1654 * Charl P. Botha <http://cpbotha.net>
1649 */ 1655 */
1650static int radeon_do_resume_cp( drm_device_t *dev ) 1656static int radeon_do_resume_cp(drm_device_t * dev)
1651{ 1657{
1652 drm_radeon_private_t *dev_priv = dev->dev_private; 1658 drm_radeon_private_t *dev_priv = dev->dev_private;
1653 1659
1654 if ( !dev_priv ) { 1660 if (!dev_priv) {
1655 DRM_ERROR( "Called with no initialization\n" ); 1661 DRM_ERROR("Called with no initialization\n");
1656 return DRM_ERR( EINVAL ); 1662 return DRM_ERR(EINVAL);
1657 } 1663 }
1658 1664
1659 DRM_DEBUG("Starting radeon_do_resume_cp()\n"); 1665 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1660 1666
1661#if __OS_HAS_AGP 1667#if __OS_HAS_AGP
1662 if ( !dev_priv->is_pci ) { 1668 if (!dev_priv->is_pci) {
1663 /* Turn off PCI GART */ 1669 /* Turn off PCI GART */
1664 radeon_set_pcigart( dev_priv, 0 ); 1670 radeon_set_pcigart(dev_priv, 0);
1665 } else 1671 } else
1666#endif 1672#endif
1667 { 1673 {
1668 /* Turn on PCI GART */ 1674 /* Turn on PCI GART */
1669 radeon_set_pcigart( dev_priv, 1 ); 1675 radeon_set_pcigart(dev_priv, 1);
1670 } 1676 }
1671 1677
1672 radeon_cp_load_microcode( dev_priv ); 1678 radeon_cp_load_microcode(dev_priv);
1673 radeon_cp_init_ring_buffer( dev, dev_priv ); 1679 radeon_cp_init_ring_buffer(dev, dev_priv);
1674 1680
1675 radeon_do_engine_reset( dev ); 1681 radeon_do_engine_reset(dev);
1676 1682
1677 DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1683 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1678 1684
1679 return 0; 1685 return 0;
1680} 1686}
1681 1687
1682 1688int radeon_cp_init(DRM_IOCTL_ARGS)
1683int radeon_cp_init( DRM_IOCTL_ARGS )
1684{ 1689{
1685 DRM_DEVICE; 1690 DRM_DEVICE;
1686 drm_radeon_init_t init; 1691 drm_radeon_init_t init;
1687 1692
1688 LOCK_TEST_WITH_RETURN( dev, filp ); 1693 LOCK_TEST_WITH_RETURN(dev, filp);
1689 1694
1690 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) ); 1695 DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
1696 sizeof(init));
1691 1697
1692 if(init.func == RADEON_INIT_R300_CP) 1698 if (init.func == RADEON_INIT_R300_CP)
1693 r300_init_reg_flags(); 1699 r300_init_reg_flags();
1694 1700
1695 switch ( init.func ) { 1701 switch (init.func) {
1696 case RADEON_INIT_CP: 1702 case RADEON_INIT_CP:
1697 case RADEON_INIT_R200_CP: 1703 case RADEON_INIT_R200_CP:
1698 case RADEON_INIT_R300_CP: 1704 case RADEON_INIT_R300_CP:
1699 return radeon_do_init_cp( dev, &init ); 1705 return radeon_do_init_cp(dev, &init);
1700 case RADEON_CLEANUP_CP: 1706 case RADEON_CLEANUP_CP:
1701 return radeon_do_cleanup_cp( dev ); 1707 return radeon_do_cleanup_cp(dev);
1702 } 1708 }
1703 1709
1704 return DRM_ERR(EINVAL); 1710 return DRM_ERR(EINVAL);
1705} 1711}
1706 1712
1707int radeon_cp_start( DRM_IOCTL_ARGS ) 1713int radeon_cp_start(DRM_IOCTL_ARGS)
1708{ 1714{
1709 DRM_DEVICE; 1715 DRM_DEVICE;
1710 drm_radeon_private_t *dev_priv = dev->dev_private; 1716 drm_radeon_private_t *dev_priv = dev->dev_private;
1711 DRM_DEBUG( "\n" ); 1717 DRM_DEBUG("\n");
1712 1718
1713 LOCK_TEST_WITH_RETURN( dev, filp ); 1719 LOCK_TEST_WITH_RETURN(dev, filp);
1714 1720
1715 if ( dev_priv->cp_running ) { 1721 if (dev_priv->cp_running) {
1716 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ ); 1722 DRM_DEBUG("%s while CP running\n", __FUNCTION__);
1717 return 0; 1723 return 0;
1718 } 1724 }
1719 if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) { 1725 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1720 DRM_DEBUG( "%s called with bogus CP mode (%d)\n", 1726 DRM_DEBUG("%s called with bogus CP mode (%d)\n",
1721 __FUNCTION__, dev_priv->cp_mode ); 1727 __FUNCTION__, dev_priv->cp_mode);
1722 return 0; 1728 return 0;
1723 } 1729 }
1724 1730
1725 radeon_do_cp_start( dev_priv ); 1731 radeon_do_cp_start(dev_priv);
1726 1732
1727 return 0; 1733 return 0;
1728} 1734}
@@ -1730,17 +1736,18 @@ int radeon_cp_start( DRM_IOCTL_ARGS )
1730/* Stop the CP. The engine must have been idled before calling this 1736/* Stop the CP. The engine must have been idled before calling this
1731 * routine. 1737 * routine.
1732 */ 1738 */
1733int radeon_cp_stop( DRM_IOCTL_ARGS ) 1739int radeon_cp_stop(DRM_IOCTL_ARGS)
1734{ 1740{
1735 DRM_DEVICE; 1741 DRM_DEVICE;
1736 drm_radeon_private_t *dev_priv = dev->dev_private; 1742 drm_radeon_private_t *dev_priv = dev->dev_private;
1737 drm_radeon_cp_stop_t stop; 1743 drm_radeon_cp_stop_t stop;
1738 int ret; 1744 int ret;
1739 DRM_DEBUG( "\n" ); 1745 DRM_DEBUG("\n");
1740 1746
1741 LOCK_TEST_WITH_RETURN( dev, filp ); 1747 LOCK_TEST_WITH_RETURN(dev, filp);
1742 1748
1743 DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) ); 1749 DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data,
1750 sizeof(stop));
1744 1751
1745 if (!dev_priv->cp_running) 1752 if (!dev_priv->cp_running)
1746 return 0; 1753 return 0;
@@ -1748,32 +1755,32 @@ int radeon_cp_stop( DRM_IOCTL_ARGS )
1748 /* Flush any pending CP commands. This ensures any outstanding 1755 /* Flush any pending CP commands. This ensures any outstanding
1749 * commands are exectuted by the engine before we turn it off. 1756 * commands are exectuted by the engine before we turn it off.
1750 */ 1757 */
1751 if ( stop.flush ) { 1758 if (stop.flush) {
1752 radeon_do_cp_flush( dev_priv ); 1759 radeon_do_cp_flush(dev_priv);
1753 } 1760 }
1754 1761
1755 /* If we fail to make the engine go idle, we return an error 1762 /* If we fail to make the engine go idle, we return an error
1756 * code so that the DRM ioctl wrapper can try again. 1763 * code so that the DRM ioctl wrapper can try again.
1757 */ 1764 */
1758 if ( stop.idle ) { 1765 if (stop.idle) {
1759 ret = radeon_do_cp_idle( dev_priv ); 1766 ret = radeon_do_cp_idle(dev_priv);
1760 if ( ret ) return ret; 1767 if (ret)
1768 return ret;
1761 } 1769 }
1762 1770
1763 /* Finally, we can turn off the CP. If the engine isn't idle, 1771 /* Finally, we can turn off the CP. If the engine isn't idle,
1764 * we will get some dropped triangles as they won't be fully 1772 * we will get some dropped triangles as they won't be fully
1765 * rendered before the CP is shut down. 1773 * rendered before the CP is shut down.
1766 */ 1774 */
1767 radeon_do_cp_stop( dev_priv ); 1775 radeon_do_cp_stop(dev_priv);
1768 1776
1769 /* Reset the engine */ 1777 /* Reset the engine */
1770 radeon_do_engine_reset( dev ); 1778 radeon_do_engine_reset(dev);
1771 1779
1772 return 0; 1780 return 0;
1773} 1781}
1774 1782
1775 1783void radeon_do_release(drm_device_t * dev)
1776void radeon_do_release( drm_device_t *dev )
1777{ 1784{
1778 drm_radeon_private_t *dev_priv = dev->dev_private; 1785 drm_radeon_private_t *dev_priv = dev->dev_private;
1779 int i, ret; 1786 int i, ret;
@@ -1781,7 +1788,7 @@ void radeon_do_release( drm_device_t *dev )
1781 if (dev_priv) { 1788 if (dev_priv) {
1782 if (dev_priv->cp_running) { 1789 if (dev_priv->cp_running) {
1783 /* Stop the cp */ 1790 /* Stop the cp */
1784 while ((ret = radeon_do_cp_idle( dev_priv )) != 0) { 1791 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1785 DRM_DEBUG("radeon_do_cp_idle %d\n", ret); 1792 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1786#ifdef __linux__ 1793#ifdef __linux__
1787 schedule(); 1794 schedule();
@@ -1789,47 +1796,49 @@ void radeon_do_release( drm_device_t *dev )
1789 tsleep(&ret, PZERO, "rdnrel", 1); 1796 tsleep(&ret, PZERO, "rdnrel", 1);
1790#endif 1797#endif
1791 } 1798 }
1792 radeon_do_cp_stop( dev_priv ); 1799 radeon_do_cp_stop(dev_priv);
1793 radeon_do_engine_reset( dev ); 1800 radeon_do_engine_reset(dev);
1794 } 1801 }
1795 1802
1796 /* Disable *all* interrupts */ 1803 /* Disable *all* interrupts */
1797 if (dev_priv->mmio) /* remove this after permanent addmaps */ 1804 if (dev_priv->mmio) /* remove this after permanent addmaps */
1798 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); 1805 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1799 1806
1800 if (dev_priv->mmio) {/* remove all surfaces */ 1807 if (dev_priv->mmio) { /* remove all surfaces */
1801 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1808 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1802 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0); 1809 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1803 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0); 1810 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1804 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0); 1811 16 * i, 0);
1812 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1813 16 * i, 0);
1805 } 1814 }
1806 } 1815 }
1807 1816
1808 /* Free memory heap structures */ 1817 /* Free memory heap structures */
1809 radeon_mem_takedown( &(dev_priv->gart_heap) ); 1818 radeon_mem_takedown(&(dev_priv->gart_heap));
1810 radeon_mem_takedown( &(dev_priv->fb_heap) ); 1819 radeon_mem_takedown(&(dev_priv->fb_heap));
1811 1820
1812 /* deallocate kernel resources */ 1821 /* deallocate kernel resources */
1813 radeon_do_cleanup_cp( dev ); 1822 radeon_do_cleanup_cp(dev);
1814 } 1823 }
1815} 1824}
1816 1825
1817/* Just reset the CP ring. Called as part of an X Server engine reset. 1826/* Just reset the CP ring. Called as part of an X Server engine reset.
1818 */ 1827 */
1819int radeon_cp_reset( DRM_IOCTL_ARGS ) 1828int radeon_cp_reset(DRM_IOCTL_ARGS)
1820{ 1829{
1821 DRM_DEVICE; 1830 DRM_DEVICE;
1822 drm_radeon_private_t *dev_priv = dev->dev_private; 1831 drm_radeon_private_t *dev_priv = dev->dev_private;
1823 DRM_DEBUG( "\n" ); 1832 DRM_DEBUG("\n");
1824 1833
1825 LOCK_TEST_WITH_RETURN( dev, filp ); 1834 LOCK_TEST_WITH_RETURN(dev, filp);
1826 1835
1827 if ( !dev_priv ) { 1836 if (!dev_priv) {
1828 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); 1837 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
1829 return DRM_ERR(EINVAL); 1838 return DRM_ERR(EINVAL);
1830 } 1839 }
1831 1840
1832 radeon_do_cp_reset( dev_priv ); 1841 radeon_do_cp_reset(dev_priv);
1833 1842
1834 /* The CP is no longer running after an engine reset */ 1843 /* The CP is no longer running after an engine reset */
1835 dev_priv->cp_running = 0; 1844 dev_priv->cp_running = 0;
@@ -1837,50 +1846,47 @@ int radeon_cp_reset( DRM_IOCTL_ARGS )
1837 return 0; 1846 return 0;
1838} 1847}
1839 1848
1840int radeon_cp_idle( DRM_IOCTL_ARGS ) 1849int radeon_cp_idle(DRM_IOCTL_ARGS)
1841{ 1850{
1842 DRM_DEVICE; 1851 DRM_DEVICE;
1843 drm_radeon_private_t *dev_priv = dev->dev_private; 1852 drm_radeon_private_t *dev_priv = dev->dev_private;
1844 DRM_DEBUG( "\n" ); 1853 DRM_DEBUG("\n");
1845 1854
1846 LOCK_TEST_WITH_RETURN( dev, filp ); 1855 LOCK_TEST_WITH_RETURN(dev, filp);
1847 1856
1848 return radeon_do_cp_idle( dev_priv ); 1857 return radeon_do_cp_idle(dev_priv);
1849} 1858}
1850 1859
1851/* Added by Charl P. Botha to call radeon_do_resume_cp(). 1860/* Added by Charl P. Botha to call radeon_do_resume_cp().
1852 */ 1861 */
1853int radeon_cp_resume( DRM_IOCTL_ARGS ) 1862int radeon_cp_resume(DRM_IOCTL_ARGS)
1854{ 1863{
1855 DRM_DEVICE; 1864 DRM_DEVICE;
1856 1865
1857 return radeon_do_resume_cp(dev); 1866 return radeon_do_resume_cp(dev);
1858} 1867}
1859 1868
1860 1869int radeon_engine_reset(DRM_IOCTL_ARGS)
1861int radeon_engine_reset( DRM_IOCTL_ARGS )
1862{ 1870{
1863 DRM_DEVICE; 1871 DRM_DEVICE;
1864 DRM_DEBUG( "\n" ); 1872 DRM_DEBUG("\n");
1865 1873
1866 LOCK_TEST_WITH_RETURN( dev, filp ); 1874 LOCK_TEST_WITH_RETURN(dev, filp);
1867 1875
1868 return radeon_do_engine_reset( dev ); 1876 return radeon_do_engine_reset(dev);
1869} 1877}
1870 1878
1871
1872/* ================================================================ 1879/* ================================================================
1873 * Fullscreen mode 1880 * Fullscreen mode
1874 */ 1881 */
1875 1882
1876/* KW: Deprecated to say the least: 1883/* KW: Deprecated to say the least:
1877 */ 1884 */
1878int radeon_fullscreen( DRM_IOCTL_ARGS ) 1885int radeon_fullscreen(DRM_IOCTL_ARGS)
1879{ 1886{
1880 return 0; 1887 return 0;
1881} 1888}
1882 1889
1883
1884/* ================================================================ 1890/* ================================================================
1885 * Freelist management 1891 * Freelist management
1886 */ 1892 */
@@ -1889,20 +1895,20 @@ int radeon_fullscreen( DRM_IOCTL_ARGS )
1889 * bufs until freelist code is used. Note this hides a problem with 1895 * bufs until freelist code is used. Note this hides a problem with
1890 * the scratch register * (used to keep track of last buffer 1896 * the scratch register * (used to keep track of last buffer
1891 * completed) being written to before * the last buffer has actually 1897 * completed) being written to before * the last buffer has actually
1892 * completed rendering. 1898 * completed rendering.
1893 * 1899 *
1894 * KW: It's also a good way to find free buffers quickly. 1900 * KW: It's also a good way to find free buffers quickly.
1895 * 1901 *
1896 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't 1902 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1897 * sleep. However, bugs in older versions of radeon_accel.c mean that 1903 * sleep. However, bugs in older versions of radeon_accel.c mean that
1898 * we essentially have to do this, else old clients will break. 1904 * we essentially have to do this, else old clients will break.
1899 * 1905 *
1900 * However, it does leave open a potential deadlock where all the 1906 * However, it does leave open a potential deadlock where all the
1901 * buffers are held by other clients, which can't release them because 1907 * buffers are held by other clients, which can't release them because
1902 * they can't get the lock. 1908 * they can't get the lock.
1903 */ 1909 */
1904 1910
1905drm_buf_t *radeon_freelist_get( drm_device_t *dev ) 1911drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1906{ 1912{
1907 drm_device_dma_t *dma = dev->dma; 1913 drm_device_dma_t *dma = dev->dma;
1908 drm_radeon_private_t *dev_priv = dev->dev_private; 1914 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1911,19 +1917,19 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1911 int i, t; 1917 int i, t;
1912 int start; 1918 int start;
1913 1919
1914 if ( ++dev_priv->last_buf >= dma->buf_count ) 1920 if (++dev_priv->last_buf >= dma->buf_count)
1915 dev_priv->last_buf = 0; 1921 dev_priv->last_buf = 0;
1916 1922
1917 start = dev_priv->last_buf; 1923 start = dev_priv->last_buf;
1918 1924
1919 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { 1925 for (t = 0; t < dev_priv->usec_timeout; t++) {
1920 u32 done_age = GET_SCRATCH( 1 ); 1926 u32 done_age = GET_SCRATCH(1);
1921 DRM_DEBUG("done_age = %d\n",done_age); 1927 DRM_DEBUG("done_age = %d\n", done_age);
1922 for ( i = start ; i < dma->buf_count ; i++ ) { 1928 for (i = start; i < dma->buf_count; i++) {
1923 buf = dma->buflist[i]; 1929 buf = dma->buflist[i];
1924 buf_priv = buf->dev_private; 1930 buf_priv = buf->dev_private;
1925 if ( buf->filp == 0 || (buf->pending && 1931 if (buf->filp == 0 || (buf->pending &&
1926 buf_priv->age <= done_age) ) { 1932 buf_priv->age <= done_age)) {
1927 dev_priv->stats.requested_bufs++; 1933 dev_priv->stats.requested_bufs++;
1928 buf->pending = 0; 1934 buf->pending = 0;
1929 return buf; 1935 return buf;
@@ -1932,16 +1938,17 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1932 } 1938 }
1933 1939
1934 if (t) { 1940 if (t) {
1935 DRM_UDELAY( 1 ); 1941 DRM_UDELAY(1);
1936 dev_priv->stats.freelist_loops++; 1942 dev_priv->stats.freelist_loops++;
1937 } 1943 }
1938 } 1944 }
1939 1945
1940 DRM_DEBUG( "returning NULL!\n" ); 1946 DRM_DEBUG("returning NULL!\n");
1941 return NULL; 1947 return NULL;
1942} 1948}
1949
1943#if 0 1950#if 0
1944drm_buf_t *radeon_freelist_get( drm_device_t *dev ) 1951drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1945{ 1952{
1946 drm_device_dma_t *dma = dev->dma; 1953 drm_device_dma_t *dma = dev->dma;
1947 drm_radeon_private_t *dev_priv = dev->dev_private; 1954 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1951,18 +1958,18 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1951 int start; 1958 int start;
1952 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); 1959 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1953 1960
1954 if ( ++dev_priv->last_buf >= dma->buf_count ) 1961 if (++dev_priv->last_buf >= dma->buf_count)
1955 dev_priv->last_buf = 0; 1962 dev_priv->last_buf = 0;
1956 1963
1957 start = dev_priv->last_buf; 1964 start = dev_priv->last_buf;
1958 dev_priv->stats.freelist_loops++; 1965 dev_priv->stats.freelist_loops++;
1959 1966
1960 for ( t = 0 ; t < 2 ; t++ ) { 1967 for (t = 0; t < 2; t++) {
1961 for ( i = start ; i < dma->buf_count ; i++ ) { 1968 for (i = start; i < dma->buf_count; i++) {
1962 buf = dma->buflist[i]; 1969 buf = dma->buflist[i];
1963 buf_priv = buf->dev_private; 1970 buf_priv = buf->dev_private;
1964 if ( buf->filp == 0 || (buf->pending && 1971 if (buf->filp == 0 || (buf->pending &&
1965 buf_priv->age <= done_age) ) { 1972 buf_priv->age <= done_age)) {
1966 dev_priv->stats.requested_bufs++; 1973 dev_priv->stats.requested_bufs++;
1967 buf->pending = 0; 1974 buf->pending = 0;
1968 return buf; 1975 return buf;
@@ -1975,73 +1982,74 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1975} 1982}
1976#endif 1983#endif
1977 1984
1978void radeon_freelist_reset( drm_device_t *dev ) 1985void radeon_freelist_reset(drm_device_t * dev)
1979{ 1986{
1980 drm_device_dma_t *dma = dev->dma; 1987 drm_device_dma_t *dma = dev->dma;
1981 drm_radeon_private_t *dev_priv = dev->dev_private; 1988 drm_radeon_private_t *dev_priv = dev->dev_private;
1982 int i; 1989 int i;
1983 1990
1984 dev_priv->last_buf = 0; 1991 dev_priv->last_buf = 0;
1985 for ( i = 0 ; i < dma->buf_count ; i++ ) { 1992 for (i = 0; i < dma->buf_count; i++) {
1986 drm_buf_t *buf = dma->buflist[i]; 1993 drm_buf_t *buf = dma->buflist[i];
1987 drm_radeon_buf_priv_t *buf_priv = buf->dev_private; 1994 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1988 buf_priv->age = 0; 1995 buf_priv->age = 0;
1989 } 1996 }
1990} 1997}
1991 1998
1992
1993/* ================================================================ 1999/* ================================================================
1994 * CP command submission 2000 * CP command submission
1995 */ 2001 */
1996 2002
1997int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ) 2003int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1998{ 2004{
1999 drm_radeon_ring_buffer_t *ring = &dev_priv->ring; 2005 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2000 int i; 2006 int i;
2001 u32 last_head = GET_RING_HEAD( dev_priv ); 2007 u32 last_head = GET_RING_HEAD(dev_priv);
2002 2008
2003 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 2009 for (i = 0; i < dev_priv->usec_timeout; i++) {
2004 u32 head = GET_RING_HEAD( dev_priv ); 2010 u32 head = GET_RING_HEAD(dev_priv);
2005 2011
2006 ring->space = (head - ring->tail) * sizeof(u32); 2012 ring->space = (head - ring->tail) * sizeof(u32);
2007 if ( ring->space <= 0 ) 2013 if (ring->space <= 0)
2008 ring->space += ring->size; 2014 ring->space += ring->size;
2009 if ( ring->space > n ) 2015 if (ring->space > n)
2010 return 0; 2016 return 0;
2011 2017
2012 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 2018 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2013 2019
2014 if (head != last_head) 2020 if (head != last_head)
2015 i = 0; 2021 i = 0;
2016 last_head = head; 2022 last_head = head;
2017 2023
2018 DRM_UDELAY( 1 ); 2024 DRM_UDELAY(1);
2019 } 2025 }
2020 2026
2021 /* FIXME: This return value is ignored in the BEGIN_RING macro! */ 2027 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2022#if RADEON_FIFO_DEBUG 2028#if RADEON_FIFO_DEBUG
2023 radeon_status( dev_priv ); 2029 radeon_status(dev_priv);
2024 DRM_ERROR( "failed!\n" ); 2030 DRM_ERROR("failed!\n");
2025#endif 2031#endif
2026 return DRM_ERR(EBUSY); 2032 return DRM_ERR(EBUSY);
2027} 2033}
2028 2034
2029static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) 2035static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev,
2036 drm_dma_t * d)
2030{ 2037{
2031 int i; 2038 int i;
2032 drm_buf_t *buf; 2039 drm_buf_t *buf;
2033 2040
2034 for ( i = d->granted_count ; i < d->request_count ; i++ ) { 2041 for (i = d->granted_count; i < d->request_count; i++) {
2035 buf = radeon_freelist_get( dev ); 2042 buf = radeon_freelist_get(dev);
2036 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */ 2043 if (!buf)
2044 return DRM_ERR(EBUSY); /* NOTE: broken client */
2037 2045
2038 buf->filp = filp; 2046 buf->filp = filp;
2039 2047
2040 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, 2048 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2041 sizeof(buf->idx) ) ) 2049 sizeof(buf->idx)))
2042 return DRM_ERR(EFAULT); 2050 return DRM_ERR(EFAULT);
2043 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, 2051 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2044 sizeof(buf->total) ) ) 2052 sizeof(buf->total)))
2045 return DRM_ERR(EFAULT); 2053 return DRM_ERR(EFAULT);
2046 2054
2047 d->granted_count++; 2055 d->granted_count++;
@@ -2049,7 +2057,7 @@ static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d
2049 return 0; 2057 return 0;
2050} 2058}
2051 2059
2052int radeon_cp_buffers( DRM_IOCTL_ARGS ) 2060int radeon_cp_buffers(DRM_IOCTL_ARGS)
2053{ 2061{
2054 DRM_DEVICE; 2062 DRM_DEVICE;
2055 drm_device_dma_t *dma = dev->dma; 2063 drm_device_dma_t *dma = dev->dma;
@@ -2057,33 +2065,33 @@ int radeon_cp_buffers( DRM_IOCTL_ARGS )
2057 drm_dma_t __user *argp = (void __user *)data; 2065 drm_dma_t __user *argp = (void __user *)data;
2058 drm_dma_t d; 2066 drm_dma_t d;
2059 2067
2060 LOCK_TEST_WITH_RETURN( dev, filp ); 2068 LOCK_TEST_WITH_RETURN(dev, filp);
2061 2069
2062 DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); 2070 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
2063 2071
2064 /* Please don't send us buffers. 2072 /* Please don't send us buffers.
2065 */ 2073 */
2066 if ( d.send_count != 0 ) { 2074 if (d.send_count != 0) {
2067 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", 2075 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2068 DRM_CURRENTPID, d.send_count ); 2076 DRM_CURRENTPID, d.send_count);
2069 return DRM_ERR(EINVAL); 2077 return DRM_ERR(EINVAL);
2070 } 2078 }
2071 2079
2072 /* We'll send you buffers. 2080 /* We'll send you buffers.
2073 */ 2081 */
2074 if ( d.request_count < 0 || d.request_count > dma->buf_count ) { 2082 if (d.request_count < 0 || d.request_count > dma->buf_count) {
2075 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", 2083 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2076 DRM_CURRENTPID, d.request_count, dma->buf_count ); 2084 DRM_CURRENTPID, d.request_count, dma->buf_count);
2077 return DRM_ERR(EINVAL); 2085 return DRM_ERR(EINVAL);
2078 } 2086 }
2079 2087
2080 d.granted_count = 0; 2088 d.granted_count = 0;
2081 2089
2082 if ( d.request_count ) { 2090 if (d.request_count) {
2083 ret = radeon_cp_get_buffers( filp, dev, &d ); 2091 ret = radeon_cp_get_buffers(filp, dev, &d);
2084 } 2092 }
2085 2093
2086 DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); 2094 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
2087 2095
2088 return ret; 2096 return ret;
2089} 2097}
@@ -2110,13 +2118,13 @@ int radeon_driver_preinit(struct drm_device *dev, unsigned long flags)
2110 dev_priv->flags |= CHIP_HAS_HIERZ; 2118 dev_priv->flags |= CHIP_HAS_HIERZ;
2111 break; 2119 break;
2112 default: 2120 default:
2113 /* all other chips have no hierarchical z buffer */ 2121 /* all other chips have no hierarchical z buffer */
2114 break; 2122 break;
2115 } 2123 }
2116 2124
2117 if (drm_device_is_agp(dev)) 2125 if (drm_device_is_agp(dev))
2118 dev_priv->flags |= CHIP_IS_AGP; 2126 dev_priv->flags |= CHIP_IS_AGP;
2119 2127
2120 if (drm_device_is_pcie(dev)) 2128 if (drm_device_is_pcie(dev))
2121 dev_priv->flags |= CHIP_IS_PCIE; 2129 dev_priv->flags |= CHIP_IS_PCIE;
2122 2130
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 16:05:06 -0500