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path: root/drivers/char/drm/mga_state.c
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Diffstat (limited to 'drivers/char/drm/mga_state.c')
-rw-r--r--drivers/char/drm/mga_state.c894
1 files changed, 432 insertions, 462 deletions
diff --git a/drivers/char/drm/mga_state.c b/drivers/char/drm/mga_state.c
index 05bbb4719376..15114f8aa467 100644
--- a/drivers/char/drm/mga_state.c
+++ b/drivers/char/drm/mga_state.c
@@ -41,15 +41,15 @@
41 * DMA hardware state programming functions 41 * DMA hardware state programming functions
42 */ 42 */
43 43
44static void mga_emit_clip_rect( drm_mga_private_t *dev_priv, 44static void mga_emit_clip_rect(drm_mga_private_t * dev_priv,
45 drm_clip_rect_t *box ) 45 drm_clip_rect_t * box)
46{ 46{
47 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 47 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
48 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; 48 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
49 unsigned int pitch = dev_priv->front_pitch; 49 unsigned int pitch = dev_priv->front_pitch;
50 DMA_LOCALS; 50 DMA_LOCALS;
51 51
52 BEGIN_DMA( 2 ); 52 BEGIN_DMA(2);
53 53
54 /* Force reset of DWGCTL on G400 (eliminates clip disable bit). 54 /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
55 */ 55 */
@@ -61,101 +61,90 @@ static void mga_emit_clip_rect( drm_mga_private_t *dev_priv,
61 } 61 }
62 DMA_BLOCK(MGA_DMAPAD, 0x00000000, 62 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
63 MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1, 63 MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
64 MGA_YTOP, box->y1 * pitch, 64 MGA_YTOP, box->y1 * pitch, MGA_YBOT, (box->y2 - 1) * pitch);
65 MGA_YBOT, (box->y2 - 1) * pitch);
66 65
67 ADVANCE_DMA(); 66 ADVANCE_DMA();
68} 67}
69 68
70static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv ) 69static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv)
71{ 70{
72 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 71 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
73 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; 72 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
74 DMA_LOCALS; 73 DMA_LOCALS;
75 74
76 BEGIN_DMA( 3 ); 75 BEGIN_DMA(3);
77 76
78 DMA_BLOCK( MGA_DSTORG, ctx->dstorg, 77 DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
79 MGA_MACCESS, ctx->maccess, 78 MGA_MACCESS, ctx->maccess,
80 MGA_PLNWT, ctx->plnwt, 79 MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
81 MGA_DWGCTL, ctx->dwgctl );
82 80
83 DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, 81 DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
84 MGA_FOGCOL, ctx->fogcolor, 82 MGA_FOGCOL, ctx->fogcolor,
85 MGA_WFLAG, ctx->wflag, 83 MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
86 MGA_ZORG, dev_priv->depth_offset );
87 84
88 DMA_BLOCK( MGA_FCOL, ctx->fcol, 85 DMA_BLOCK(MGA_FCOL, ctx->fcol,
89 MGA_DMAPAD, 0x00000000, 86 MGA_DMAPAD, 0x00000000,
90 MGA_DMAPAD, 0x00000000, 87 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
91 MGA_DMAPAD, 0x00000000 );
92 88
93 ADVANCE_DMA(); 89 ADVANCE_DMA();
94} 90}
95 91
96static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv ) 92static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv)
97{ 93{
98 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 94 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
99 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; 95 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
100 DMA_LOCALS; 96 DMA_LOCALS;
101 97
102 BEGIN_DMA( 4 ); 98 BEGIN_DMA(4);
103 99
104 DMA_BLOCK( MGA_DSTORG, ctx->dstorg, 100 DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
105 MGA_MACCESS, ctx->maccess, 101 MGA_MACCESS, ctx->maccess,
106 MGA_PLNWT, ctx->plnwt, 102 MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
107 MGA_DWGCTL, ctx->dwgctl );
108 103
109 DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, 104 DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
110 MGA_FOGCOL, ctx->fogcolor, 105 MGA_FOGCOL, ctx->fogcolor,
111 MGA_WFLAG, ctx->wflag, 106 MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
112 MGA_ZORG, dev_priv->depth_offset );
113 107
114 DMA_BLOCK( MGA_WFLAG1, ctx->wflag, 108 DMA_BLOCK(MGA_WFLAG1, ctx->wflag,
115 MGA_TDUALSTAGE0, ctx->tdualstage0, 109 MGA_TDUALSTAGE0, ctx->tdualstage0,
116 MGA_TDUALSTAGE1, ctx->tdualstage1, 110 MGA_TDUALSTAGE1, ctx->tdualstage1, MGA_FCOL, ctx->fcol);
117 MGA_FCOL, ctx->fcol );
118 111
119 DMA_BLOCK( MGA_STENCIL, ctx->stencil, 112 DMA_BLOCK(MGA_STENCIL, ctx->stencil,
120 MGA_STENCILCTL, ctx->stencilctl, 113 MGA_STENCILCTL, ctx->stencilctl,
121 MGA_DMAPAD, 0x00000000, 114 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
122 MGA_DMAPAD, 0x00000000 );
123 115
124 ADVANCE_DMA(); 116 ADVANCE_DMA();
125} 117}
126 118
127static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv ) 119static __inline__ void mga_g200_emit_tex0(drm_mga_private_t * dev_priv)
128{ 120{
129 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 121 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
130 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; 122 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
131 DMA_LOCALS; 123 DMA_LOCALS;
132 124
133 BEGIN_DMA( 4 ); 125 BEGIN_DMA(4);
134 126
135 DMA_BLOCK( MGA_TEXCTL2, tex->texctl2, 127 DMA_BLOCK(MGA_TEXCTL2, tex->texctl2,
136 MGA_TEXCTL, tex->texctl, 128 MGA_TEXCTL, tex->texctl,
137 MGA_TEXFILTER, tex->texfilter, 129 MGA_TEXFILTER, tex->texfilter,
138 MGA_TEXBORDERCOL, tex->texbordercol ); 130 MGA_TEXBORDERCOL, tex->texbordercol);
139 131
140 DMA_BLOCK( MGA_TEXORG, tex->texorg, 132 DMA_BLOCK(MGA_TEXORG, tex->texorg,
141 MGA_TEXORG1, tex->texorg1, 133 MGA_TEXORG1, tex->texorg1,
142 MGA_TEXORG2, tex->texorg2, 134 MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3);
143 MGA_TEXORG3, tex->texorg3 );
144 135
145 DMA_BLOCK( MGA_TEXORG4, tex->texorg4, 136 DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
146 MGA_TEXWIDTH, tex->texwidth, 137 MGA_TEXWIDTH, tex->texwidth,
147 MGA_TEXHEIGHT, tex->texheight, 138 MGA_TEXHEIGHT, tex->texheight, MGA_WR24, tex->texwidth);
148 MGA_WR24, tex->texwidth );
149 139
150 DMA_BLOCK( MGA_WR34, tex->texheight, 140 DMA_BLOCK(MGA_WR34, tex->texheight,
151 MGA_TEXTRANS, 0x0000ffff, 141 MGA_TEXTRANS, 0x0000ffff,
152 MGA_TEXTRANSHIGH, 0x0000ffff, 142 MGA_TEXTRANSHIGH, 0x0000ffff, MGA_DMAPAD, 0x00000000);
153 MGA_DMAPAD, 0x00000000 );
154 143
155 ADVANCE_DMA(); 144 ADVANCE_DMA();
156} 145}
157 146
158static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv ) 147static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
159{ 148{
160 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 149 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
161 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; 150 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
@@ -164,42 +153,38 @@ static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
164/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */ 153/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
165/* tex->texctl, tex->texctl2); */ 154/* tex->texctl, tex->texctl2); */
166 155
167 BEGIN_DMA( 6 ); 156 BEGIN_DMA(6);
168 157
169 DMA_BLOCK( MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC, 158 DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
170 MGA_TEXCTL, tex->texctl, 159 MGA_TEXCTL, tex->texctl,
171 MGA_TEXFILTER, tex->texfilter, 160 MGA_TEXFILTER, tex->texfilter,
172 MGA_TEXBORDERCOL, tex->texbordercol ); 161 MGA_TEXBORDERCOL, tex->texbordercol);
173 162
174 DMA_BLOCK( MGA_TEXORG, tex->texorg, 163 DMA_BLOCK(MGA_TEXORG, tex->texorg,
175 MGA_TEXORG1, tex->texorg1, 164 MGA_TEXORG1, tex->texorg1,
176 MGA_TEXORG2, tex->texorg2, 165 MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3);
177 MGA_TEXORG3, tex->texorg3 );
178 166
179 DMA_BLOCK( MGA_TEXORG4, tex->texorg4, 167 DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
180 MGA_TEXWIDTH, tex->texwidth, 168 MGA_TEXWIDTH, tex->texwidth,
181 MGA_TEXHEIGHT, tex->texheight, 169 MGA_TEXHEIGHT, tex->texheight, MGA_WR49, 0x00000000);
182 MGA_WR49, 0x00000000 );
183 170
184 DMA_BLOCK( MGA_WR57, 0x00000000, 171 DMA_BLOCK(MGA_WR57, 0x00000000,
185 MGA_WR53, 0x00000000, 172 MGA_WR53, 0x00000000,
186 MGA_WR61, 0x00000000, 173 MGA_WR61, 0x00000000, MGA_WR52, MGA_G400_WR_MAGIC);
187 MGA_WR52, MGA_G400_WR_MAGIC );
188 174
189 DMA_BLOCK( MGA_WR60, MGA_G400_WR_MAGIC, 175 DMA_BLOCK(MGA_WR60, MGA_G400_WR_MAGIC,
190 MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC, 176 MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC,
191 MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC, 177 MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC,
192 MGA_DMAPAD, 0x00000000 ); 178 MGA_DMAPAD, 0x00000000);
193 179
194 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 180 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
195 MGA_DMAPAD, 0x00000000, 181 MGA_DMAPAD, 0x00000000,
196 MGA_TEXTRANS, 0x0000ffff, 182 MGA_TEXTRANS, 0x0000ffff, MGA_TEXTRANSHIGH, 0x0000ffff);
197 MGA_TEXTRANSHIGH, 0x0000ffff );
198 183
199 ADVANCE_DMA(); 184 ADVANCE_DMA();
200} 185}
201 186
202static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv ) 187static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
203{ 188{
204 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 189 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
205 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1]; 190 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
@@ -208,55 +193,51 @@ static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
208/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */ 193/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
209/* tex->texctl, tex->texctl2); */ 194/* tex->texctl, tex->texctl2); */
210 195
211 BEGIN_DMA( 5 ); 196 BEGIN_DMA(5);
212 197
213 DMA_BLOCK( MGA_TEXCTL2, (tex->texctl2 | 198 DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 |
214 MGA_MAP1_ENABLE | 199 MGA_MAP1_ENABLE |
215 MGA_G400_TC2_MAGIC), 200 MGA_G400_TC2_MAGIC),
216 MGA_TEXCTL, tex->texctl, 201 MGA_TEXCTL, tex->texctl,
217 MGA_TEXFILTER, tex->texfilter, 202 MGA_TEXFILTER, tex->texfilter,
218 MGA_TEXBORDERCOL, tex->texbordercol ); 203 MGA_TEXBORDERCOL, tex->texbordercol);
219 204
220 DMA_BLOCK( MGA_TEXORG, tex->texorg, 205 DMA_BLOCK(MGA_TEXORG, tex->texorg,
221 MGA_TEXORG1, tex->texorg1, 206 MGA_TEXORG1, tex->texorg1,
222 MGA_TEXORG2, tex->texorg2, 207 MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3);
223 MGA_TEXORG3, tex->texorg3 );
224 208
225 DMA_BLOCK( MGA_TEXORG4, tex->texorg4, 209 DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
226 MGA_TEXWIDTH, tex->texwidth, 210 MGA_TEXWIDTH, tex->texwidth,
227 MGA_TEXHEIGHT, tex->texheight, 211 MGA_TEXHEIGHT, tex->texheight, MGA_WR49, 0x00000000);
228 MGA_WR49, 0x00000000 );
229 212
230 DMA_BLOCK( MGA_WR57, 0x00000000, 213 DMA_BLOCK(MGA_WR57, 0x00000000,
231 MGA_WR53, 0x00000000, 214 MGA_WR53, 0x00000000,
232 MGA_WR61, 0x00000000, 215 MGA_WR61, 0x00000000,
233 MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC ); 216 MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC);
234 217
235 DMA_BLOCK( MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC, 218 DMA_BLOCK(MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC,
236 MGA_TEXTRANS, 0x0000ffff, 219 MGA_TEXTRANS, 0x0000ffff,
237 MGA_TEXTRANSHIGH, 0x0000ffff, 220 MGA_TEXTRANSHIGH, 0x0000ffff,
238 MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC ); 221 MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC);
239 222
240 ADVANCE_DMA(); 223 ADVANCE_DMA();
241} 224}
242 225
243static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv ) 226static __inline__ void mga_g200_emit_pipe(drm_mga_private_t * dev_priv)
244{ 227{
245 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 228 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
246 unsigned int pipe = sarea_priv->warp_pipe; 229 unsigned int pipe = sarea_priv->warp_pipe;
247 DMA_LOCALS; 230 DMA_LOCALS;
248 231
249 BEGIN_DMA( 3 ); 232 BEGIN_DMA(3);
250 233
251 DMA_BLOCK( MGA_WIADDR, MGA_WMODE_SUSPEND, 234 DMA_BLOCK(MGA_WIADDR, MGA_WMODE_SUSPEND,
252 MGA_WVRTXSZ, 0x00000007, 235 MGA_WVRTXSZ, 0x00000007,
253 MGA_WFLAG, 0x00000000, 236 MGA_WFLAG, 0x00000000, MGA_WR24, 0x00000000);
254 MGA_WR24, 0x00000000 );
255 237
256 DMA_BLOCK( MGA_WR25, 0x00000100, 238 DMA_BLOCK(MGA_WR25, 0x00000100,
257 MGA_WR34, 0x00000000, 239 MGA_WR34, 0x00000000,
258 MGA_WR42, 0x0000ffff, 240 MGA_WR42, 0x0000ffff, MGA_WR60, 0x0000ffff);
259 MGA_WR60, 0x0000ffff );
260 241
261 /* Padding required to to hardware bug. 242 /* Padding required to to hardware bug.
262 */ 243 */
@@ -269,7 +250,7 @@ static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv )
269 ADVANCE_DMA(); 250 ADVANCE_DMA();
270} 251}
271 252
272static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv ) 253static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
273{ 254{
274 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 255 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
275 unsigned int pipe = sarea_priv->warp_pipe; 256 unsigned int pipe = sarea_priv->warp_pipe;
@@ -277,68 +258,64 @@ static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
277 258
278/* printk("mga_g400_emit_pipe %x\n", pipe); */ 259/* printk("mga_g400_emit_pipe %x\n", pipe); */
279 260
280 BEGIN_DMA( 10 ); 261 BEGIN_DMA(10);
281 262
282 DMA_BLOCK( MGA_WIADDR2, MGA_WMODE_SUSPEND, 263 DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
283 MGA_DMAPAD, 0x00000000, 264 MGA_DMAPAD, 0x00000000,
284 MGA_DMAPAD, 0x00000000, 265 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
285 MGA_DMAPAD, 0x00000000 );
286 266
287 if ( pipe & MGA_T2 ) { 267 if (pipe & MGA_T2) {
288 DMA_BLOCK( MGA_WVRTXSZ, 0x00001e09, 268 DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09,
289 MGA_DMAPAD, 0x00000000, 269 MGA_DMAPAD, 0x00000000,
290 MGA_DMAPAD, 0x00000000, 270 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
291 MGA_DMAPAD, 0x00000000 );
292 271
293 DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, 272 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
294 MGA_WACCEPTSEQ, 0x00000000, 273 MGA_WACCEPTSEQ, 0x00000000,
295 MGA_WACCEPTSEQ, 0x00000000, 274 MGA_WACCEPTSEQ, 0x00000000,
296 MGA_WACCEPTSEQ, 0x1e000000 ); 275 MGA_WACCEPTSEQ, 0x1e000000);
297 } else { 276 } else {
298 if ( dev_priv->warp_pipe & MGA_T2 ) { 277 if (dev_priv->warp_pipe & MGA_T2) {
299 /* Flush the WARP pipe */ 278 /* Flush the WARP pipe */
300 DMA_BLOCK( MGA_YDST, 0x00000000, 279 DMA_BLOCK(MGA_YDST, 0x00000000,
301 MGA_FXLEFT, 0x00000000, 280 MGA_FXLEFT, 0x00000000,
302 MGA_FXRIGHT, 0x00000001, 281 MGA_FXRIGHT, 0x00000001,
303 MGA_DWGCTL, MGA_DWGCTL_FLUSH ); 282 MGA_DWGCTL, MGA_DWGCTL_FLUSH);
304 283
305 DMA_BLOCK( MGA_LEN + MGA_EXEC, 0x00000001, 284 DMA_BLOCK(MGA_LEN + MGA_EXEC, 0x00000001,
306 MGA_DWGSYNC, 0x00007000, 285 MGA_DWGSYNC, 0x00007000,
307 MGA_TEXCTL2, MGA_G400_TC2_MAGIC, 286 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
308 MGA_LEN + MGA_EXEC, 0x00000000 ); 287 MGA_LEN + MGA_EXEC, 0x00000000);
309 288
310 DMA_BLOCK( MGA_TEXCTL2, (MGA_DUALTEX | 289 DMA_BLOCK(MGA_TEXCTL2, (MGA_DUALTEX |
311 MGA_G400_TC2_MAGIC), 290 MGA_G400_TC2_MAGIC),
312 MGA_LEN + MGA_EXEC, 0x00000000, 291 MGA_LEN + MGA_EXEC, 0x00000000,
313 MGA_TEXCTL2, MGA_G400_TC2_MAGIC, 292 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
314 MGA_DMAPAD, 0x00000000 ); 293 MGA_DMAPAD, 0x00000000);
315 } 294 }
316 295
317 DMA_BLOCK( MGA_WVRTXSZ, 0x00001807, 296 DMA_BLOCK(MGA_WVRTXSZ, 0x00001807,
318 MGA_DMAPAD, 0x00000000, 297 MGA_DMAPAD, 0x00000000,
319 MGA_DMAPAD, 0x00000000, 298 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
320 MGA_DMAPAD, 0x00000000 );
321 299
322 DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, 300 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
323 MGA_WACCEPTSEQ, 0x00000000, 301 MGA_WACCEPTSEQ, 0x00000000,
324 MGA_WACCEPTSEQ, 0x00000000, 302 MGA_WACCEPTSEQ, 0x00000000,
325 MGA_WACCEPTSEQ, 0x18000000 ); 303 MGA_WACCEPTSEQ, 0x18000000);
326 } 304 }
327 305
328 DMA_BLOCK( MGA_WFLAG, 0x00000000, 306 DMA_BLOCK(MGA_WFLAG, 0x00000000,
329 MGA_WFLAG1, 0x00000000, 307 MGA_WFLAG1, 0x00000000,
330 MGA_WR56, MGA_G400_WR56_MAGIC, 308 MGA_WR56, MGA_G400_WR56_MAGIC, MGA_DMAPAD, 0x00000000);
331 MGA_DMAPAD, 0x00000000 );
332 309
333 DMA_BLOCK( MGA_WR49, 0x00000000, /* tex0 */ 310 DMA_BLOCK(MGA_WR49, 0x00000000, /* tex0 */
334 MGA_WR57, 0x00000000, /* tex0 */ 311 MGA_WR57, 0x00000000, /* tex0 */
335 MGA_WR53, 0x00000000, /* tex1 */ 312 MGA_WR53, 0x00000000, /* tex1 */
336 MGA_WR61, 0x00000000 ); /* tex1 */ 313 MGA_WR61, 0x00000000); /* tex1 */
337 314
338 DMA_BLOCK( MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */ 315 DMA_BLOCK(MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */
339 MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */ 316 MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */
340 MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */ 317 MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */
341 MGA_WR60, MGA_G400_WR_MAGIC ); /* tex1 height */ 318 MGA_WR60, MGA_G400_WR_MAGIC); /* tex1 height */
342 319
343 /* Padding required to to hardware bug */ 320 /* Padding required to to hardware bug */
344 DMA_BLOCK(MGA_DMAPAD, 0xffffffff, 321 DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
@@ -350,71 +327,70 @@ static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
350 ADVANCE_DMA(); 327 ADVANCE_DMA();
351} 328}
352 329
353static void mga_g200_emit_state( drm_mga_private_t *dev_priv ) 330static void mga_g200_emit_state(drm_mga_private_t * dev_priv)
354{ 331{
355 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 332 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
356 unsigned int dirty = sarea_priv->dirty; 333 unsigned int dirty = sarea_priv->dirty;
357 334
358 if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { 335 if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
359 mga_g200_emit_pipe( dev_priv ); 336 mga_g200_emit_pipe(dev_priv);
360 dev_priv->warp_pipe = sarea_priv->warp_pipe; 337 dev_priv->warp_pipe = sarea_priv->warp_pipe;
361 } 338 }
362 339
363 if ( dirty & MGA_UPLOAD_CONTEXT ) { 340 if (dirty & MGA_UPLOAD_CONTEXT) {
364 mga_g200_emit_context( dev_priv ); 341 mga_g200_emit_context(dev_priv);
365 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; 342 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
366 } 343 }
367 344
368 if ( dirty & MGA_UPLOAD_TEX0 ) { 345 if (dirty & MGA_UPLOAD_TEX0) {
369 mga_g200_emit_tex0( dev_priv ); 346 mga_g200_emit_tex0(dev_priv);
370 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; 347 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
371 } 348 }
372} 349}
373 350
374static void mga_g400_emit_state( drm_mga_private_t *dev_priv ) 351static void mga_g400_emit_state(drm_mga_private_t * dev_priv)
375{ 352{
376 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 353 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
377 unsigned int dirty = sarea_priv->dirty; 354 unsigned int dirty = sarea_priv->dirty;
378 int multitex = sarea_priv->warp_pipe & MGA_T2; 355 int multitex = sarea_priv->warp_pipe & MGA_T2;
379 356
380 if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { 357 if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
381 mga_g400_emit_pipe( dev_priv ); 358 mga_g400_emit_pipe(dev_priv);
382 dev_priv->warp_pipe = sarea_priv->warp_pipe; 359 dev_priv->warp_pipe = sarea_priv->warp_pipe;
383 } 360 }
384 361
385 if ( dirty & MGA_UPLOAD_CONTEXT ) { 362 if (dirty & MGA_UPLOAD_CONTEXT) {
386 mga_g400_emit_context( dev_priv ); 363 mga_g400_emit_context(dev_priv);
387 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; 364 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
388 } 365 }
389 366
390 if ( dirty & MGA_UPLOAD_TEX0 ) { 367 if (dirty & MGA_UPLOAD_TEX0) {
391 mga_g400_emit_tex0( dev_priv ); 368 mga_g400_emit_tex0(dev_priv);
392 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; 369 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
393 } 370 }
394 371
395 if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) { 372 if ((dirty & MGA_UPLOAD_TEX1) && multitex) {
396 mga_g400_emit_tex1( dev_priv ); 373 mga_g400_emit_tex1(dev_priv);
397 sarea_priv->dirty &= ~MGA_UPLOAD_TEX1; 374 sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
398 } 375 }
399} 376}
400 377
401
402/* ================================================================ 378/* ================================================================
403 * SAREA state verification 379 * SAREA state verification
404 */ 380 */
405 381
406/* Disallow all write destinations except the front and backbuffer. 382/* Disallow all write destinations except the front and backbuffer.
407 */ 383 */
408static int mga_verify_context( drm_mga_private_t *dev_priv ) 384static int mga_verify_context(drm_mga_private_t * dev_priv)
409{ 385{
410 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 386 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
411 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; 387 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
412 388
413 if ( ctx->dstorg != dev_priv->front_offset && 389 if (ctx->dstorg != dev_priv->front_offset &&
414 ctx->dstorg != dev_priv->back_offset ) { 390 ctx->dstorg != dev_priv->back_offset) {
415 DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n", 391 DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n",
416 ctx->dstorg, dev_priv->front_offset, 392 ctx->dstorg, dev_priv->front_offset,
417 dev_priv->back_offset ); 393 dev_priv->back_offset);
418 ctx->dstorg = 0; 394 ctx->dstorg = 0;
419 return DRM_ERR(EINVAL); 395 return DRM_ERR(EINVAL);
420 } 396 }
@@ -424,7 +400,7 @@ static int mga_verify_context( drm_mga_private_t *dev_priv )
424 400
425/* Disallow texture reads from PCI space. 401/* Disallow texture reads from PCI space.
426 */ 402 */
427static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit ) 403static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit)
428{ 404{
429 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 405 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
430 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit]; 406 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
@@ -432,9 +408,8 @@ static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
432 408
433 org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK); 409 org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
434 410
435 if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) { 411 if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) {
436 DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n", 412 DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit);
437 tex->texorg, unit );
438 tex->texorg = 0; 413 tex->texorg = 0;
439 return DRM_ERR(EINVAL); 414 return DRM_ERR(EINVAL);
440 } 415 }
@@ -442,73 +417,70 @@ static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
442 return 0; 417 return 0;
443} 418}
444 419
445static int mga_verify_state( drm_mga_private_t *dev_priv ) 420static int mga_verify_state(drm_mga_private_t * dev_priv)
446{ 421{
447 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 422 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
448 unsigned int dirty = sarea_priv->dirty; 423 unsigned int dirty = sarea_priv->dirty;
449 int ret = 0; 424 int ret = 0;
450 425
451 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) 426 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
452 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; 427 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
453 428
454 if ( dirty & MGA_UPLOAD_CONTEXT ) 429 if (dirty & MGA_UPLOAD_CONTEXT)
455 ret |= mga_verify_context( dev_priv ); 430 ret |= mga_verify_context(dev_priv);
456 431
457 if ( dirty & MGA_UPLOAD_TEX0 ) 432 if (dirty & MGA_UPLOAD_TEX0)
458 ret |= mga_verify_tex( dev_priv, 0 ); 433 ret |= mga_verify_tex(dev_priv, 0);
459 434
460 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) { 435 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) {
461 if (dirty & MGA_UPLOAD_TEX1) 436 if (dirty & MGA_UPLOAD_TEX1)
462 ret |= mga_verify_tex(dev_priv, 1); 437 ret |= mga_verify_tex(dev_priv, 1);
463 438
464 if ( dirty & MGA_UPLOAD_PIPE ) 439 if (dirty & MGA_UPLOAD_PIPE)
465 ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES ); 440 ret |= (sarea_priv->warp_pipe > MGA_MAX_G400_PIPES);
466 } else { 441 } else {
467 if ( dirty & MGA_UPLOAD_PIPE ) 442 if (dirty & MGA_UPLOAD_PIPE)
468 ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES ); 443 ret |= (sarea_priv->warp_pipe > MGA_MAX_G200_PIPES);
469 } 444 }
470 445
471 return ( ret == 0 ); 446 return (ret == 0);
472} 447}
473 448
474static int mga_verify_iload( drm_mga_private_t *dev_priv, 449static int mga_verify_iload(drm_mga_private_t * dev_priv,
475 unsigned int dstorg, unsigned int length ) 450 unsigned int dstorg, unsigned int length)
476{ 451{
477 if ( dstorg < dev_priv->texture_offset || 452 if (dstorg < dev_priv->texture_offset ||
478 dstorg + length > (dev_priv->texture_offset + 453 dstorg + length > (dev_priv->texture_offset +
479 dev_priv->texture_size) ) { 454 dev_priv->texture_size)) {
480 DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg ); 455 DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg);
481 return DRM_ERR(EINVAL); 456 return DRM_ERR(EINVAL);
482 } 457 }
483 458
484 if ( length & MGA_ILOAD_MASK ) { 459 if (length & MGA_ILOAD_MASK) {
485 DRM_ERROR( "*** bad iload length: 0x%x\n", 460 DRM_ERROR("*** bad iload length: 0x%x\n",
486 length & MGA_ILOAD_MASK ); 461 length & MGA_ILOAD_MASK);
487 return DRM_ERR(EINVAL); 462 return DRM_ERR(EINVAL);
488 } 463 }
489 464
490 return 0; 465 return 0;
491} 466}
492 467
493static int mga_verify_blit( drm_mga_private_t *dev_priv, 468static int mga_verify_blit(drm_mga_private_t * dev_priv,
494 unsigned int srcorg, unsigned int dstorg ) 469 unsigned int srcorg, unsigned int dstorg)
495{ 470{
496 if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) || 471 if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
497 (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) { 472 (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) {
498 DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n", 473 DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg);
499 srcorg, dstorg );
500 return DRM_ERR(EINVAL); 474 return DRM_ERR(EINVAL);
501 } 475 }
502 return 0; 476 return 0;
503} 477}
504 478
505
506/* ================================================================ 479/* ================================================================
507 * 480 *
508 */ 481 */
509 482
510static void mga_dma_dispatch_clear( drm_device_t *dev, 483static void mga_dma_dispatch_clear(drm_device_t * dev, drm_mga_clear_t * clear)
511 drm_mga_clear_t *clear )
512{ 484{
513 drm_mga_private_t *dev_priv = dev->dev_private; 485 drm_mga_private_t *dev_priv = dev->dev_private;
514 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 486 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -517,92 +489,86 @@ static void mga_dma_dispatch_clear( drm_device_t *dev,
517 int nbox = sarea_priv->nbox; 489 int nbox = sarea_priv->nbox;
518 int i; 490 int i;
519 DMA_LOCALS; 491 DMA_LOCALS;
520 DRM_DEBUG( "\n" ); 492 DRM_DEBUG("\n");
521 493
522 BEGIN_DMA( 1 ); 494 BEGIN_DMA(1);
523 495
524 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 496 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
525 MGA_DMAPAD, 0x00000000, 497 MGA_DMAPAD, 0x00000000,
526 MGA_DWGSYNC, 0x00007100, 498 MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000);
527 MGA_DWGSYNC, 0x00007000 );
528 499
529 ADVANCE_DMA(); 500 ADVANCE_DMA();
530 501
531 for ( i = 0 ; i < nbox ; i++ ) { 502 for (i = 0; i < nbox; i++) {
532 drm_clip_rect_t *box = &pbox[i]; 503 drm_clip_rect_t *box = &pbox[i];
533 u32 height = box->y2 - box->y1; 504 u32 height = box->y2 - box->y1;
534 505
535 DRM_DEBUG( " from=%d,%d to=%d,%d\n", 506 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
536 box->x1, box->y1, box->x2, box->y2 ); 507 box->x1, box->y1, box->x2, box->y2);
537 508
538 if ( clear->flags & MGA_FRONT ) { 509 if (clear->flags & MGA_FRONT) {
539 BEGIN_DMA( 2 ); 510 BEGIN_DMA(2);
540 511
541 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 512 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
542 MGA_PLNWT, clear->color_mask, 513 MGA_PLNWT, clear->color_mask,
543 MGA_YDSTLEN, (box->y1 << 16) | height, 514 MGA_YDSTLEN, (box->y1 << 16) | height,
544 MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); 515 MGA_FXBNDRY, (box->x2 << 16) | box->x1);
545 516
546 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 517 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
547 MGA_FCOL, clear->clear_color, 518 MGA_FCOL, clear->clear_color,
548 MGA_DSTORG, dev_priv->front_offset, 519 MGA_DSTORG, dev_priv->front_offset,
549 MGA_DWGCTL + MGA_EXEC, 520 MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
550 dev_priv->clear_cmd );
551 521
552 ADVANCE_DMA(); 522 ADVANCE_DMA();
553 } 523 }
554 524
525 if (clear->flags & MGA_BACK) {
526 BEGIN_DMA(2);
555 527
556 if ( clear->flags & MGA_BACK ) { 528 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
557 BEGIN_DMA( 2 ); 529 MGA_PLNWT, clear->color_mask,
558 530 MGA_YDSTLEN, (box->y1 << 16) | height,
559 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 531 MGA_FXBNDRY, (box->x2 << 16) | box->x1);
560 MGA_PLNWT, clear->color_mask,
561 MGA_YDSTLEN, (box->y1 << 16) | height,
562 MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
563 532
564 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 533 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
565 MGA_FCOL, clear->clear_color, 534 MGA_FCOL, clear->clear_color,
566 MGA_DSTORG, dev_priv->back_offset, 535 MGA_DSTORG, dev_priv->back_offset,
567 MGA_DWGCTL + MGA_EXEC, 536 MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
568 dev_priv->clear_cmd );
569 537
570 ADVANCE_DMA(); 538 ADVANCE_DMA();
571 } 539 }
572 540
573 if ( clear->flags & MGA_DEPTH ) { 541 if (clear->flags & MGA_DEPTH) {
574 BEGIN_DMA( 2 ); 542 BEGIN_DMA(2);
575 543
576 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 544 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
577 MGA_PLNWT, clear->depth_mask, 545 MGA_PLNWT, clear->depth_mask,
578 MGA_YDSTLEN, (box->y1 << 16) | height, 546 MGA_YDSTLEN, (box->y1 << 16) | height,
579 MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); 547 MGA_FXBNDRY, (box->x2 << 16) | box->x1);
580 548
581 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 549 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
582 MGA_FCOL, clear->clear_depth, 550 MGA_FCOL, clear->clear_depth,
583 MGA_DSTORG, dev_priv->depth_offset, 551 MGA_DSTORG, dev_priv->depth_offset,
584 MGA_DWGCTL + MGA_EXEC, 552 MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
585 dev_priv->clear_cmd );
586 553
587 ADVANCE_DMA(); 554 ADVANCE_DMA();
588 } 555 }
589 556
590 } 557 }
591 558
592 BEGIN_DMA( 1 ); 559 BEGIN_DMA(1);
593 560
594 /* Force reset of DWGCTL */ 561 /* Force reset of DWGCTL */
595 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 562 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
596 MGA_DMAPAD, 0x00000000, 563 MGA_DMAPAD, 0x00000000,
597 MGA_PLNWT, ctx->plnwt, 564 MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
598 MGA_DWGCTL, ctx->dwgctl );
599 565
600 ADVANCE_DMA(); 566 ADVANCE_DMA();
601 567
602 FLUSH_DMA(); 568 FLUSH_DMA();
603} 569}
604 570
605static void mga_dma_dispatch_swap( drm_device_t *dev ) 571static void mga_dma_dispatch_swap(drm_device_t * dev)
606{ 572{
607 drm_mga_private_t *dev_priv = dev->dev_private; 573 drm_mga_private_t *dev_priv = dev->dev_private;
608 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 574 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -611,56 +577,52 @@ static void mga_dma_dispatch_swap( drm_device_t *dev )
611 int nbox = sarea_priv->nbox; 577 int nbox = sarea_priv->nbox;
612 int i; 578 int i;
613 DMA_LOCALS; 579 DMA_LOCALS;
614 DRM_DEBUG( "\n" ); 580 DRM_DEBUG("\n");
615 581
616 sarea_priv->last_frame.head = dev_priv->prim.tail; 582 sarea_priv->last_frame.head = dev_priv->prim.tail;
617 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap; 583 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
618 584
619 BEGIN_DMA( 4 + nbox ); 585 BEGIN_DMA(4 + nbox);
620 586
621 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 587 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
622 MGA_DMAPAD, 0x00000000, 588 MGA_DMAPAD, 0x00000000,
623 MGA_DWGSYNC, 0x00007100, 589 MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000);
624 MGA_DWGSYNC, 0x00007000 );
625 590
626 DMA_BLOCK( MGA_DSTORG, dev_priv->front_offset, 591 DMA_BLOCK(MGA_DSTORG, dev_priv->front_offset,
627 MGA_MACCESS, dev_priv->maccess, 592 MGA_MACCESS, dev_priv->maccess,
628 MGA_SRCORG, dev_priv->back_offset, 593 MGA_SRCORG, dev_priv->back_offset,
629 MGA_AR5, dev_priv->front_pitch ); 594 MGA_AR5, dev_priv->front_pitch);
630 595
631 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 596 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
632 MGA_DMAPAD, 0x00000000, 597 MGA_DMAPAD, 0x00000000,
633 MGA_PLNWT, 0xffffffff, 598 MGA_PLNWT, 0xffffffff, MGA_DWGCTL, MGA_DWGCTL_COPY);
634 MGA_DWGCTL, MGA_DWGCTL_COPY );
635 599
636 for ( i = 0 ; i < nbox ; i++ ) { 600 for (i = 0; i < nbox; i++) {
637 drm_clip_rect_t *box = &pbox[i]; 601 drm_clip_rect_t *box = &pbox[i];
638 u32 height = box->y2 - box->y1; 602 u32 height = box->y2 - box->y1;
639 u32 start = box->y1 * dev_priv->front_pitch; 603 u32 start = box->y1 * dev_priv->front_pitch;
640 604
641 DRM_DEBUG( " from=%d,%d to=%d,%d\n", 605 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
642 box->x1, box->y1, box->x2, box->y2 ); 606 box->x1, box->y1, box->x2, box->y2);
643 607
644 DMA_BLOCK( MGA_AR0, start + box->x2 - 1, 608 DMA_BLOCK(MGA_AR0, start + box->x2 - 1,
645 MGA_AR3, start + box->x1, 609 MGA_AR3, start + box->x1,
646 MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1, 610 MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
647 MGA_YDSTLEN + MGA_EXEC, 611 MGA_YDSTLEN + MGA_EXEC, (box->y1 << 16) | height);
648 (box->y1 << 16) | height );
649 } 612 }
650 613
651 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 614 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
652 MGA_PLNWT, ctx->plnwt, 615 MGA_PLNWT, ctx->plnwt,
653 MGA_SRCORG, dev_priv->front_offset, 616 MGA_SRCORG, dev_priv->front_offset, MGA_DWGCTL, ctx->dwgctl);
654 MGA_DWGCTL, ctx->dwgctl );
655 617
656 ADVANCE_DMA(); 618 ADVANCE_DMA();
657 619
658 FLUSH_DMA(); 620 FLUSH_DMA();
659 621
660 DRM_DEBUG( "%s... done.\n", __FUNCTION__ ); 622 DRM_DEBUG("%s... done.\n", __FUNCTION__);
661} 623}
662 624
663static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf ) 625static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
664{ 626{
665 drm_mga_private_t *dev_priv = dev->dev_private; 627 drm_mga_private_t *dev_priv = dev->dev_private;
666 drm_mga_buf_priv_t *buf_priv = buf->dev_private; 628 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
@@ -669,20 +631,20 @@ static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
669 u32 length = (u32) buf->used; 631 u32 length = (u32) buf->used;
670 int i = 0; 632 int i = 0;
671 DMA_LOCALS; 633 DMA_LOCALS;
672 DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used ); 634 DRM_DEBUG("vertex: buf=%d used=%d\n", buf->idx, buf->used);
673 635
674 if ( buf->used ) { 636 if (buf->used) {
675 buf_priv->dispatched = 1; 637 buf_priv->dispatched = 1;
676 638
677 MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); 639 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
678 640
679 do { 641 do {
680 if ( i < sarea_priv->nbox ) { 642 if (i < sarea_priv->nbox) {
681 mga_emit_clip_rect( dev_priv, 643 mga_emit_clip_rect(dev_priv,
682 &sarea_priv->boxes[i] ); 644 &sarea_priv->boxes[i]);
683 } 645 }
684 646
685 BEGIN_DMA( 1 ); 647 BEGIN_DMA(1);
686 648
687 DMA_BLOCK(MGA_DMAPAD, 0x00000000, 649 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
688 MGA_DMAPAD, 0x00000000, 650 MGA_DMAPAD, 0x00000000,
@@ -692,23 +654,23 @@ static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
692 dev_priv->dma_access)); 654 dev_priv->dma_access));
693 655
694 ADVANCE_DMA(); 656 ADVANCE_DMA();
695 } while ( ++i < sarea_priv->nbox ); 657 } while (++i < sarea_priv->nbox);
696 } 658 }
697 659
698 if ( buf_priv->discard ) { 660 if (buf_priv->discard) {
699 AGE_BUFFER( buf_priv ); 661 AGE_BUFFER(buf_priv);
700 buf->pending = 0; 662 buf->pending = 0;
701 buf->used = 0; 663 buf->used = 0;
702 buf_priv->dispatched = 0; 664 buf_priv->dispatched = 0;
703 665
704 mga_freelist_put( dev, buf ); 666 mga_freelist_put(dev, buf);
705 } 667 }
706 668
707 FLUSH_DMA(); 669 FLUSH_DMA();
708} 670}
709 671
710static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, 672static void mga_dma_dispatch_indices(drm_device_t * dev, drm_buf_t * buf,
711 unsigned int start, unsigned int end ) 673 unsigned int start, unsigned int end)
712{ 674{
713 drm_mga_private_t *dev_priv = dev->dev_private; 675 drm_mga_private_t *dev_priv = dev->dev_private;
714 drm_mga_buf_priv_t *buf_priv = buf->dev_private; 676 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
@@ -716,20 +678,20 @@ static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
716 u32 address = (u32) buf->bus_address; 678 u32 address = (u32) buf->bus_address;
717 int i = 0; 679 int i = 0;
718 DMA_LOCALS; 680 DMA_LOCALS;
719 DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end ); 681 DRM_DEBUG("indices: buf=%d start=%d end=%d\n", buf->idx, start, end);
720 682
721 if ( start != end ) { 683 if (start != end) {
722 buf_priv->dispatched = 1; 684 buf_priv->dispatched = 1;
723 685
724 MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); 686 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
725 687
726 do { 688 do {
727 if ( i < sarea_priv->nbox ) { 689 if (i < sarea_priv->nbox) {
728 mga_emit_clip_rect( dev_priv, 690 mga_emit_clip_rect(dev_priv,
729 &sarea_priv->boxes[i] ); 691 &sarea_priv->boxes[i]);
730 } 692 }
731 693
732 BEGIN_DMA( 1 ); 694 BEGIN_DMA(1);
733 695
734 DMA_BLOCK(MGA_DMAPAD, 0x00000000, 696 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
735 MGA_DMAPAD, 0x00000000, 697 MGA_DMAPAD, 0x00000000,
@@ -738,16 +700,16 @@ static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
738 dev_priv->dma_access)); 700 dev_priv->dma_access));
739 701
740 ADVANCE_DMA(); 702 ADVANCE_DMA();
741 } while ( ++i < sarea_priv->nbox ); 703 } while (++i < sarea_priv->nbox);
742 } 704 }
743 705
744 if ( buf_priv->discard ) { 706 if (buf_priv->discard) {
745 AGE_BUFFER( buf_priv ); 707 AGE_BUFFER(buf_priv);
746 buf->pending = 0; 708 buf->pending = 0;
747 buf->used = 0; 709 buf->used = 0;
748 buf_priv->dispatched = 0; 710 buf_priv->dispatched = 0;
749 711
750 mga_freelist_put( dev, buf ); 712 mga_freelist_put(dev, buf);
751 } 713 }
752 714
753 FLUSH_DMA(); 715 FLUSH_DMA();
@@ -756,61 +718,55 @@ static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
756/* This copies a 64 byte aligned agp region to the frambuffer with a 718/* This copies a 64 byte aligned agp region to the frambuffer with a
757 * standard blit, the ioctl needs to do checking. 719 * standard blit, the ioctl needs to do checking.
758 */ 720 */
759static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf, 721static void mga_dma_dispatch_iload(drm_device_t * dev, drm_buf_t * buf,
760 unsigned int dstorg, unsigned int length ) 722 unsigned int dstorg, unsigned int length)
761{ 723{
762 drm_mga_private_t *dev_priv = dev->dev_private; 724 drm_mga_private_t *dev_priv = dev->dev_private;
763 drm_mga_buf_priv_t *buf_priv = buf->dev_private; 725 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
764 drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state; 726 drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
765 u32 srcorg = buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM; 727 u32 srcorg =
728 buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM;
766 u32 y2; 729 u32 y2;
767 DMA_LOCALS; 730 DMA_LOCALS;
768 DRM_DEBUG( "buf=%d used=%d\n", buf->idx, buf->used ); 731 DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
769 732
770 y2 = length / 64; 733 y2 = length / 64;
771 734
772 BEGIN_DMA( 5 ); 735 BEGIN_DMA(5);
773 736
774 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 737 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
775 MGA_DMAPAD, 0x00000000, 738 MGA_DMAPAD, 0x00000000,
776 MGA_DWGSYNC, 0x00007100, 739 MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000);
777 MGA_DWGSYNC, 0x00007000 );
778 740
779 DMA_BLOCK( MGA_DSTORG, dstorg, 741 DMA_BLOCK(MGA_DSTORG, dstorg,
780 MGA_MACCESS, 0x00000000, 742 MGA_MACCESS, 0x00000000, MGA_SRCORG, srcorg, MGA_AR5, 64);
781 MGA_SRCORG, srcorg,
782 MGA_AR5, 64 );
783 743
784 DMA_BLOCK( MGA_PITCH, 64, 744 DMA_BLOCK(MGA_PITCH, 64,
785 MGA_PLNWT, 0xffffffff, 745 MGA_PLNWT, 0xffffffff,
786 MGA_DMAPAD, 0x00000000, 746 MGA_DMAPAD, 0x00000000, MGA_DWGCTL, MGA_DWGCTL_COPY);
787 MGA_DWGCTL, MGA_DWGCTL_COPY );
788 747
789 DMA_BLOCK( MGA_AR0, 63, 748 DMA_BLOCK(MGA_AR0, 63,
790 MGA_AR3, 0, 749 MGA_AR3, 0,
791 MGA_FXBNDRY, (63 << 16) | 0, 750 MGA_FXBNDRY, (63 << 16) | 0, MGA_YDSTLEN + MGA_EXEC, y2);
792 MGA_YDSTLEN + MGA_EXEC, y2 );
793 751
794 DMA_BLOCK( MGA_PLNWT, ctx->plnwt, 752 DMA_BLOCK(MGA_PLNWT, ctx->plnwt,
795 MGA_SRCORG, dev_priv->front_offset, 753 MGA_SRCORG, dev_priv->front_offset,
796 MGA_PITCH, dev_priv->front_pitch, 754 MGA_PITCH, dev_priv->front_pitch, MGA_DWGSYNC, 0x00007000);
797 MGA_DWGSYNC, 0x00007000 );
798 755
799 ADVANCE_DMA(); 756 ADVANCE_DMA();
800 757
801 AGE_BUFFER( buf_priv ); 758 AGE_BUFFER(buf_priv);
802 759
803 buf->pending = 0; 760 buf->pending = 0;
804 buf->used = 0; 761 buf->used = 0;
805 buf_priv->dispatched = 0; 762 buf_priv->dispatched = 0;
806 763
807 mga_freelist_put( dev, buf ); 764 mga_freelist_put(dev, buf);
808 765
809 FLUSH_DMA(); 766 FLUSH_DMA();
810} 767}
811 768
812static void mga_dma_dispatch_blit( drm_device_t *dev, 769static void mga_dma_dispatch_blit(drm_device_t * dev, drm_mga_blit_t * blit)
813 drm_mga_blit_t *blit )
814{ 770{
815 drm_mga_private_t *dev_priv = dev->dev_private; 771 drm_mga_private_t *dev_priv = dev->dev_private;
816 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 772 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -819,26 +775,24 @@ static void mga_dma_dispatch_blit( drm_device_t *dev,
819 int nbox = sarea_priv->nbox; 775 int nbox = sarea_priv->nbox;
820 u32 scandir = 0, i; 776 u32 scandir = 0, i;
821 DMA_LOCALS; 777 DMA_LOCALS;
822 DRM_DEBUG( "\n" ); 778 DRM_DEBUG("\n");
823 779
824 BEGIN_DMA( 4 + nbox ); 780 BEGIN_DMA(4 + nbox);
825 781
826 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 782 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
827 MGA_DMAPAD, 0x00000000, 783 MGA_DMAPAD, 0x00000000,
828 MGA_DWGSYNC, 0x00007100, 784 MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000);
829 MGA_DWGSYNC, 0x00007000 );
830 785
831 DMA_BLOCK( MGA_DWGCTL, MGA_DWGCTL_COPY, 786 DMA_BLOCK(MGA_DWGCTL, MGA_DWGCTL_COPY,
832 MGA_PLNWT, blit->planemask, 787 MGA_PLNWT, blit->planemask,
833 MGA_SRCORG, blit->srcorg, 788 MGA_SRCORG, blit->srcorg, MGA_DSTORG, blit->dstorg);
834 MGA_DSTORG, blit->dstorg );
835 789
836 DMA_BLOCK( MGA_SGN, scandir, 790 DMA_BLOCK(MGA_SGN, scandir,
837 MGA_MACCESS, dev_priv->maccess, 791 MGA_MACCESS, dev_priv->maccess,
838 MGA_AR5, blit->ydir * blit->src_pitch, 792 MGA_AR5, blit->ydir * blit->src_pitch,
839 MGA_PITCH, blit->dst_pitch ); 793 MGA_PITCH, blit->dst_pitch);
840 794
841 for ( i = 0 ; i < nbox ; i++ ) { 795 for (i = 0; i < nbox; i++) {
842 int srcx = pbox[i].x1 + blit->delta_sx; 796 int srcx = pbox[i].x1 + blit->delta_sx;
843 int srcy = pbox[i].y1 + blit->delta_sy; 797 int srcy = pbox[i].y1 + blit->delta_sy;
844 int dstx = pbox[i].x1 + blit->delta_dx; 798 int dstx = pbox[i].x1 + blit->delta_dx;
@@ -847,52 +801,51 @@ static void mga_dma_dispatch_blit( drm_device_t *dev,
847 int w = pbox[i].x2 - pbox[i].x1 - 1; 801 int w = pbox[i].x2 - pbox[i].x1 - 1;
848 int start; 802 int start;
849 803
850 if ( blit->ydir == -1 ) { 804 if (blit->ydir == -1) {
851 srcy = blit->height - srcy - 1; 805 srcy = blit->height - srcy - 1;
852 } 806 }
853 807
854 start = srcy * blit->src_pitch + srcx; 808 start = srcy * blit->src_pitch + srcx;
855 809
856 DMA_BLOCK( MGA_AR0, start + w, 810 DMA_BLOCK(MGA_AR0, start + w,
857 MGA_AR3, start, 811 MGA_AR3, start,
858 MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff), 812 MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
859 MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h ); 813 MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h);
860 } 814 }
861 815
862 /* Do something to flush AGP? 816 /* Do something to flush AGP?
863 */ 817 */
864 818
865 /* Force reset of DWGCTL */ 819 /* Force reset of DWGCTL */
866 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 820 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
867 MGA_PLNWT, ctx->plnwt, 821 MGA_PLNWT, ctx->plnwt,
868 MGA_PITCH, dev_priv->front_pitch, 822 MGA_PITCH, dev_priv->front_pitch, MGA_DWGCTL, ctx->dwgctl);
869 MGA_DWGCTL, ctx->dwgctl );
870 823
871 ADVANCE_DMA(); 824 ADVANCE_DMA();
872} 825}
873 826
874
875/* ================================================================ 827/* ================================================================
876 * 828 *
877 */ 829 */
878 830
879static int mga_dma_clear( DRM_IOCTL_ARGS ) 831static int mga_dma_clear(DRM_IOCTL_ARGS)
880{ 832{
881 DRM_DEVICE; 833 DRM_DEVICE;
882 drm_mga_private_t *dev_priv = dev->dev_private; 834 drm_mga_private_t *dev_priv = dev->dev_private;
883 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 835 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
884 drm_mga_clear_t clear; 836 drm_mga_clear_t clear;
885 837
886 LOCK_TEST_WITH_RETURN( dev, filp ); 838 LOCK_TEST_WITH_RETURN(dev, filp);
887 839
888 DRM_COPY_FROM_USER_IOCTL( clear, (drm_mga_clear_t __user *)data, sizeof(clear) ); 840 DRM_COPY_FROM_USER_IOCTL(clear, (drm_mga_clear_t __user *) data,
841 sizeof(clear));
889 842
890 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) 843 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
891 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; 844 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
892 845
893 WRAP_TEST_WITH_RETURN( dev_priv ); 846 WRAP_TEST_WITH_RETURN(dev_priv);
894 847
895 mga_dma_dispatch_clear( dev, &clear ); 848 mga_dma_dispatch_clear(dev, &clear);
896 849
897 /* Make sure we restore the 3D state next time. 850 /* Make sure we restore the 3D state next time.
898 */ 851 */
@@ -901,20 +854,20 @@ static int mga_dma_clear( DRM_IOCTL_ARGS )
901 return 0; 854 return 0;
902} 855}
903 856
904static int mga_dma_swap( DRM_IOCTL_ARGS ) 857static int mga_dma_swap(DRM_IOCTL_ARGS)
905{ 858{
906 DRM_DEVICE; 859 DRM_DEVICE;
907 drm_mga_private_t *dev_priv = dev->dev_private; 860 drm_mga_private_t *dev_priv = dev->dev_private;
908 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 861 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
909 862
910 LOCK_TEST_WITH_RETURN( dev, filp ); 863 LOCK_TEST_WITH_RETURN(dev, filp);
911 864
912 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) 865 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
913 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; 866 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
914 867
915 WRAP_TEST_WITH_RETURN( dev_priv ); 868 WRAP_TEST_WITH_RETURN(dev_priv);
916 869
917 mga_dma_dispatch_swap( dev ); 870 mga_dma_dispatch_swap(dev);
918 871
919 /* Make sure we restore the 3D state next time. 872 /* Make sure we restore the 3D state next time.
920 */ 873 */
@@ -923,7 +876,7 @@ static int mga_dma_swap( DRM_IOCTL_ARGS )
923 return 0; 876 return 0;
924} 877}
925 878
926static int mga_dma_vertex( DRM_IOCTL_ARGS ) 879static int mga_dma_vertex(DRM_IOCTL_ARGS)
927{ 880{
928 DRM_DEVICE; 881 DRM_DEVICE;
929 drm_mga_private_t *dev_priv = dev->dev_private; 882 drm_mga_private_t *dev_priv = dev->dev_private;
@@ -932,37 +885,38 @@ static int mga_dma_vertex( DRM_IOCTL_ARGS )
932 drm_mga_buf_priv_t *buf_priv; 885 drm_mga_buf_priv_t *buf_priv;
933 drm_mga_vertex_t vertex; 886 drm_mga_vertex_t vertex;
934 887
935 LOCK_TEST_WITH_RETURN( dev, filp ); 888 LOCK_TEST_WITH_RETURN(dev, filp);
936 889
937 DRM_COPY_FROM_USER_IOCTL( vertex, 890 DRM_COPY_FROM_USER_IOCTL(vertex,
938 (drm_mga_vertex_t __user *)data, 891 (drm_mga_vertex_t __user *) data,
939 sizeof(vertex) ); 892 sizeof(vertex));
940 893
941 if(vertex.idx < 0 || vertex.idx > dma->buf_count) return DRM_ERR(EINVAL); 894 if (vertex.idx < 0 || vertex.idx > dma->buf_count)
895 return DRM_ERR(EINVAL);
942 buf = dma->buflist[vertex.idx]; 896 buf = dma->buflist[vertex.idx];
943 buf_priv = buf->dev_private; 897 buf_priv = buf->dev_private;
944 898
945 buf->used = vertex.used; 899 buf->used = vertex.used;
946 buf_priv->discard = vertex.discard; 900 buf_priv->discard = vertex.discard;
947 901
948 if ( !mga_verify_state( dev_priv ) ) { 902 if (!mga_verify_state(dev_priv)) {
949 if ( vertex.discard ) { 903 if (vertex.discard) {
950 if ( buf_priv->dispatched == 1 ) 904 if (buf_priv->dispatched == 1)
951 AGE_BUFFER( buf_priv ); 905 AGE_BUFFER(buf_priv);
952 buf_priv->dispatched = 0; 906 buf_priv->dispatched = 0;
953 mga_freelist_put( dev, buf ); 907 mga_freelist_put(dev, buf);
954 } 908 }
955 return DRM_ERR(EINVAL); 909 return DRM_ERR(EINVAL);
956 } 910 }
957 911
958 WRAP_TEST_WITH_RETURN( dev_priv ); 912 WRAP_TEST_WITH_RETURN(dev_priv);
959 913
960 mga_dma_dispatch_vertex( dev, buf ); 914 mga_dma_dispatch_vertex(dev, buf);
961 915
962 return 0; 916 return 0;
963} 917}
964 918
965static int mga_dma_indices( DRM_IOCTL_ARGS ) 919static int mga_dma_indices(DRM_IOCTL_ARGS)
966{ 920{
967 DRM_DEVICE; 921 DRM_DEVICE;
968 drm_mga_private_t *dev_priv = dev->dev_private; 922 drm_mga_private_t *dev_priv = dev->dev_private;
@@ -971,37 +925,38 @@ static int mga_dma_indices( DRM_IOCTL_ARGS )
971 drm_mga_buf_priv_t *buf_priv; 925 drm_mga_buf_priv_t *buf_priv;
972 drm_mga_indices_t indices; 926 drm_mga_indices_t indices;
973 927
974 LOCK_TEST_WITH_RETURN( dev, filp ); 928 LOCK_TEST_WITH_RETURN(dev, filp);
975 929
976 DRM_COPY_FROM_USER_IOCTL( indices, 930 DRM_COPY_FROM_USER_IOCTL(indices,
977 (drm_mga_indices_t __user *)data, 931 (drm_mga_indices_t __user *) data,
978 sizeof(indices) ); 932 sizeof(indices));
979 933
980 if(indices.idx < 0 || indices.idx > dma->buf_count) return DRM_ERR(EINVAL); 934 if (indices.idx < 0 || indices.idx > dma->buf_count)
935 return DRM_ERR(EINVAL);
981 936
982 buf = dma->buflist[indices.idx]; 937 buf = dma->buflist[indices.idx];
983 buf_priv = buf->dev_private; 938 buf_priv = buf->dev_private;
984 939
985 buf_priv->discard = indices.discard; 940 buf_priv->discard = indices.discard;
986 941
987 if ( !mga_verify_state( dev_priv ) ) { 942 if (!mga_verify_state(dev_priv)) {
988 if ( indices.discard ) { 943 if (indices.discard) {
989 if ( buf_priv->dispatched == 1 ) 944 if (buf_priv->dispatched == 1)
990 AGE_BUFFER( buf_priv ); 945 AGE_BUFFER(buf_priv);
991 buf_priv->dispatched = 0; 946 buf_priv->dispatched = 0;
992 mga_freelist_put( dev, buf ); 947 mga_freelist_put(dev, buf);
993 } 948 }
994 return DRM_ERR(EINVAL); 949 return DRM_ERR(EINVAL);
995 } 950 }
996 951
997 WRAP_TEST_WITH_RETURN( dev_priv ); 952 WRAP_TEST_WITH_RETURN(dev_priv);
998 953
999 mga_dma_dispatch_indices( dev, buf, indices.start, indices.end ); 954 mga_dma_dispatch_indices(dev, buf, indices.start, indices.end);
1000 955
1001 return 0; 956 return 0;
1002} 957}
1003 958
1004static int mga_dma_iload( DRM_IOCTL_ARGS ) 959static int mga_dma_iload(DRM_IOCTL_ARGS)
1005{ 960{
1006 DRM_DEVICE; 961 DRM_DEVICE;
1007 drm_device_dma_t *dma = dev->dma; 962 drm_device_dma_t *dma = dev->dma;
@@ -1009,32 +964,34 @@ static int mga_dma_iload( DRM_IOCTL_ARGS )
1009 drm_buf_t *buf; 964 drm_buf_t *buf;
1010 drm_mga_buf_priv_t *buf_priv; 965 drm_mga_buf_priv_t *buf_priv;
1011 drm_mga_iload_t iload; 966 drm_mga_iload_t iload;
1012 DRM_DEBUG( "\n" ); 967 DRM_DEBUG("\n");
1013 968
1014 LOCK_TEST_WITH_RETURN( dev, filp ); 969 LOCK_TEST_WITH_RETURN(dev, filp);
1015 970
1016 DRM_COPY_FROM_USER_IOCTL( iload, (drm_mga_iload_t __user *)data, sizeof(iload) ); 971 DRM_COPY_FROM_USER_IOCTL(iload, (drm_mga_iload_t __user *) data,
972 sizeof(iload));
1017 973
1018#if 0 974#if 0
1019 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { 975 if (mga_do_wait_for_idle(dev_priv) < 0) {
1020 if ( MGA_DMA_DEBUG ) 976 if (MGA_DMA_DEBUG)
1021 DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); 977 DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
1022 return DRM_ERR(EBUSY); 978 return DRM_ERR(EBUSY);
1023 } 979 }
1024#endif 980#endif
1025 if(iload.idx < 0 || iload.idx > dma->buf_count) return DRM_ERR(EINVAL); 981 if (iload.idx < 0 || iload.idx > dma->buf_count)
982 return DRM_ERR(EINVAL);
1026 983
1027 buf = dma->buflist[iload.idx]; 984 buf = dma->buflist[iload.idx];
1028 buf_priv = buf->dev_private; 985 buf_priv = buf->dev_private;
1029 986
1030 if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) { 987 if (mga_verify_iload(dev_priv, iload.dstorg, iload.length)) {
1031 mga_freelist_put( dev, buf ); 988 mga_freelist_put(dev, buf);
1032 return DRM_ERR(EINVAL); 989 return DRM_ERR(EINVAL);
1033 } 990 }
1034 991
1035 WRAP_TEST_WITH_RETURN( dev_priv ); 992 WRAP_TEST_WITH_RETURN(dev_priv);
1036 993
1037 mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length ); 994 mga_dma_dispatch_iload(dev, buf, iload.dstorg, iload.length);
1038 995
1039 /* Make sure we restore the 3D state next time. 996 /* Make sure we restore the 3D state next time.
1040 */ 997 */
@@ -1043,27 +1000,28 @@ static int mga_dma_iload( DRM_IOCTL_ARGS )
1043 return 0; 1000 return 0;
1044} 1001}
1045 1002
1046static int mga_dma_blit( DRM_IOCTL_ARGS ) 1003static int mga_dma_blit(DRM_IOCTL_ARGS)
1047{ 1004{
1048 DRM_DEVICE; 1005 DRM_DEVICE;
1049 drm_mga_private_t *dev_priv = dev->dev_private; 1006 drm_mga_private_t *dev_priv = dev->dev_private;
1050 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 1007 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1051 drm_mga_blit_t blit; 1008 drm_mga_blit_t blit;
1052 DRM_DEBUG( "\n" ); 1009 DRM_DEBUG("\n");
1053 1010
1054 LOCK_TEST_WITH_RETURN( dev, filp ); 1011 LOCK_TEST_WITH_RETURN(dev, filp);
1055 1012
1056 DRM_COPY_FROM_USER_IOCTL( blit, (drm_mga_blit_t __user *)data, sizeof(blit) ); 1013 DRM_COPY_FROM_USER_IOCTL(blit, (drm_mga_blit_t __user *) data,
1014 sizeof(blit));
1057 1015
1058 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) 1016 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
1059 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; 1017 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1060 1018
1061 if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) ) 1019 if (mga_verify_blit(dev_priv, blit.srcorg, blit.dstorg))
1062 return DRM_ERR(EINVAL); 1020 return DRM_ERR(EINVAL);
1063 1021
1064 WRAP_TEST_WITH_RETURN( dev_priv ); 1022 WRAP_TEST_WITH_RETURN(dev_priv);
1065 1023
1066 mga_dma_dispatch_blit( dev, &blit ); 1024 mga_dma_dispatch_blit(dev, &blit);
1067 1025
1068 /* Make sure we restore the 3D state next time. 1026 /* Make sure we restore the 3D state next time.
1069 */ 1027 */
@@ -1072,24 +1030,24 @@ static int mga_dma_blit( DRM_IOCTL_ARGS )
1072 return 0; 1030 return 0;
1073} 1031}
1074 1032
1075static int mga_getparam( DRM_IOCTL_ARGS ) 1033static int mga_getparam(DRM_IOCTL_ARGS)
1076{ 1034{
1077 DRM_DEVICE; 1035 DRM_DEVICE;
1078 drm_mga_private_t *dev_priv = dev->dev_private; 1036 drm_mga_private_t *dev_priv = dev->dev_private;
1079 drm_mga_getparam_t param; 1037 drm_mga_getparam_t param;
1080 int value; 1038 int value;
1081 1039
1082 if ( !dev_priv ) { 1040 if (!dev_priv) {
1083 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 1041 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1084 return DRM_ERR(EINVAL); 1042 return DRM_ERR(EINVAL);
1085 } 1043 }
1086 1044
1087 DRM_COPY_FROM_USER_IOCTL( param, (drm_mga_getparam_t __user *)data, 1045 DRM_COPY_FROM_USER_IOCTL(param, (drm_mga_getparam_t __user *) data,
1088 sizeof(param) ); 1046 sizeof(param));
1089 1047
1090 DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); 1048 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1091 1049
1092 switch( param.param ) { 1050 switch (param.param) {
1093 case MGA_PARAM_IRQ_NR: 1051 case MGA_PARAM_IRQ_NR:
1094 value = dev->irq; 1052 value = dev->irq;
1095 break; 1053 break;
@@ -1100,11 +1058,11 @@ static int mga_getparam( DRM_IOCTL_ARGS )
1100 return DRM_ERR(EINVAL); 1058 return DRM_ERR(EINVAL);
1101 } 1059 }
1102 1060
1103 if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { 1061 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
1104 DRM_ERROR( "copy_to_user\n" ); 1062 DRM_ERROR("copy_to_user\n");
1105 return DRM_ERR(EFAULT); 1063 return DRM_ERR(EFAULT);
1106 } 1064 }
1107 1065
1108 return 0; 1066 return 0;
1109} 1067}
1110 1068
@@ -1132,11 +1090,10 @@ static int mga_set_fence(DRM_IOCTL_ARGS)
1132 BEGIN_DMA(1); 1090 BEGIN_DMA(1);
1133 DMA_BLOCK(MGA_DMAPAD, 0x00000000, 1091 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
1134 MGA_DMAPAD, 0x00000000, 1092 MGA_DMAPAD, 0x00000000,
1135 MGA_DMAPAD, 0x00000000, 1093 MGA_DMAPAD, 0x00000000, MGA_SOFTRAP, 0x00000000);
1136 MGA_SOFTRAP, 0x00000000);
1137 ADVANCE_DMA(); 1094 ADVANCE_DMA();
1138 1095
1139 if (DRM_COPY_TO_USER( (u32 __user *) data, & temp, sizeof(u32))) { 1096 if (DRM_COPY_TO_USER((u32 __user *) data, &temp, sizeof(u32))) {
1140 DRM_ERROR("copy_to_user\n"); 1097 DRM_ERROR("copy_to_user\n");
1141 return DRM_ERR(EFAULT); 1098 return DRM_ERR(EFAULT);
1142 } 1099 }
@@ -1159,9 +1116,9 @@ static int mga_wait_fence(DRM_IOCTL_ARGS)
1159 1116
1160 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); 1117 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1161 1118
1162 mga_driver_fence_wait(dev, & fence); 1119 mga_driver_fence_wait(dev, &fence);
1163 1120
1164 if (DRM_COPY_TO_USER( (u32 __user *) data, & fence, sizeof(u32))) { 1121 if (DRM_COPY_TO_USER((u32 __user *) data, &fence, sizeof(u32))) {
1165 DRM_ERROR("copy_to_user\n"); 1122 DRM_ERROR("copy_to_user\n");
1166 return DRM_ERR(EFAULT); 1123 return DRM_ERR(EFAULT);
1167 } 1124 }
@@ -1170,19 +1127,32 @@ static int mga_wait_fence(DRM_IOCTL_ARGS)
1170} 1127}
1171 1128
1172drm_ioctl_desc_t mga_ioctls[] = { 1129drm_ioctl_desc_t mga_ioctls[] = {
1173 [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, 1, 1}, 1130 [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, 1, 1}
1174 [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, 1, 0}, 1131 ,
1175 [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, 1, 0}, 1132 [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, 1, 0}
1176 [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, 1, 0}, 1133 ,
1177 [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, 1, 0}, 1134 [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, 1, 0}
1178 [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, 1, 0}, 1135 ,
1179 [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, 1, 0}, 1136 [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, 1, 0}
1180 [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, 1, 0}, 1137 ,
1181 [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, 1, 0}, 1138 [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, 1, 0}
1182 [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, 1, 0}, 1139 ,
1183 [DRM_IOCTL_NR(DRM_MGA_SET_FENCE)] = {mga_set_fence, 1, 0}, 1140 [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, 1, 0}
1184 [DRM_IOCTL_NR(DRM_MGA_WAIT_FENCE)] = {mga_wait_fence, 1, 0}, 1141 ,
1185 [DRM_IOCTL_NR(DRM_MGA_DMA_BOOTSTRAP)] = {mga_dma_bootstrap, 1, 1}, 1142 [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, 1, 0}
1143 ,
1144 [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, 1, 0}
1145 ,
1146 [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, 1, 0}
1147 ,
1148 [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, 1, 0}
1149 ,
1150 [DRM_IOCTL_NR(DRM_MGA_SET_FENCE)] = {mga_set_fence, 1, 0}
1151 ,
1152 [DRM_IOCTL_NR(DRM_MGA_WAIT_FENCE)] = {mga_wait_fence, 1, 0}
1153 ,
1154 [DRM_IOCTL_NR(DRM_MGA_DMA_BOOTSTRAP)] = {mga_dma_bootstrap, 1, 1}
1155 ,
1186 1156
1187}; 1157};
1188 1158
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 10:00:56 -0500