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path: root/drivers/char/drm/mga_drv.h
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Diffstat (limited to 'drivers/char/drm/mga_drv.h')
-rw-r--r--drivers/char/drm/mga_drv.h42
1 files changed, 17 insertions, 25 deletions
diff --git a/drivers/char/drm/mga_drv.h b/drivers/char/drm/mga_drv.h
index b22fdbd4f830..05f0f913dedd 100644
--- a/drivers/char/drm/mga_drv.h
+++ b/drivers/char/drm/mga_drv.h
@@ -62,14 +62,14 @@ typedef struct drm_mga_primary_buffer {
62} drm_mga_primary_buffer_t; 62} drm_mga_primary_buffer_t;
63 63
64typedef struct drm_mga_freelist { 64typedef struct drm_mga_freelist {
65 struct drm_mga_freelist *next; 65 struct drm_mga_freelist *next;
66 struct drm_mga_freelist *prev; 66 struct drm_mga_freelist *prev;
67 drm_mga_age_t age; 67 drm_mga_age_t age;
68 drm_buf_t *buf; 68 drm_buf_t *buf;
69} drm_mga_freelist_t; 69} drm_mga_freelist_t;
70 70
71typedef struct { 71typedef struct {
72 drm_mga_freelist_t *list_entry; 72 drm_mga_freelist_t *list_entry;
73 int discard; 73 int discard;
74 int dispatched; 74 int dispatched;
75} drm_mga_buf_priv_t; 75} drm_mga_buf_priv_t;
@@ -78,8 +78,8 @@ typedef struct drm_mga_private {
78 drm_mga_primary_buffer_t prim; 78 drm_mga_primary_buffer_t prim;
79 drm_mga_sarea_t *sarea_priv; 79 drm_mga_sarea_t *sarea_priv;
80 80
81 drm_mga_freelist_t *head; 81 drm_mga_freelist_t *head;
82 drm_mga_freelist_t *tail; 82 drm_mga_freelist_t *tail;
83 83
84 unsigned int warp_pipe; 84 unsigned int warp_pipe;
85 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; 85 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
@@ -109,13 +109,13 @@ typedef struct drm_mga_private {
109 109
110 /** 110 /**
111 * \name MMIO region parameters. 111 * \name MMIO region parameters.
112 * 112 *
113 * \sa drm_mga_private_t::mmio 113 * \sa drm_mga_private_t::mmio
114 */ 114 */
115 /*@{*/ 115 /*@{ */
116 u32 mmio_base; /**< Bus address of base of MMIO. */ 116 u32 mmio_base; /**< Bus address of base of MMIO. */
117 u32 mmio_size; /**< Size of the MMIO region. */ 117 u32 mmio_size; /**< Size of the MMIO region. */
118 /*@}*/ 118 /*@} */
119 119
120 u32 clear_cmd; 120 u32 clear_cmd;
121 u32 maccess; 121 u32 maccess;
@@ -143,7 +143,7 @@ typedef struct drm_mga_private {
143 drm_local_map_t *warp; 143 drm_local_map_t *warp;
144 drm_local_map_t *primary; 144 drm_local_map_t *primary;
145 drm_local_map_t *agp_textures; 145 drm_local_map_t *agp_textures;
146 146
147 DRM_AGP_MEM *agp_mem; 147 DRM_AGP_MEM *agp_mem;
148 unsigned int agp_pages; 148 unsigned int agp_pages;
149} drm_mga_private_t; 149} drm_mga_private_t;
@@ -165,7 +165,7 @@ extern void mga_do_dma_flush(drm_mga_private_t * dev_priv);
165extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv); 165extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv);
166extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); 166extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv);
167 167
168extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ); 168extern int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf);
169 169
170 /* mga_warp.c */ 170 /* mga_warp.c */
171extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv); 171extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv);
@@ -196,7 +196,7 @@ extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
196#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) 196#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
197#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) 197#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
198 198
199static inline u32 _MGA_READ(u32 *addr) 199static inline u32 _MGA_READ(u32 * addr)
200{ 200{
201 DRM_MEMORYBARRIER(); 201 DRM_MEMORYBARRIER();
202 return *(volatile u32 *)addr; 202 return *(volatile u32 *)addr;
@@ -218,8 +218,6 @@ static inline u32 _MGA_READ(u32 *addr)
218#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) 218#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
219#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) 219#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
220 220
221
222
223/* ================================================================ 221/* ================================================================
224 * Helper macross... 222 * Helper macross...
225 */ 223 */
@@ -261,7 +259,6 @@ do { \
261 } \ 259 } \
262} while (0) 260} while (0)
263 261
264
265/* ================================================================ 262/* ================================================================
266 * Primary DMA command stream 263 * Primary DMA command stream
267 */ 264 */
@@ -346,7 +343,6 @@ do { \
346 write += DMA_BLOCK_SIZE; \ 343 write += DMA_BLOCK_SIZE; \
347} while (0) 344} while (0)
348 345
349
350/* Buffer aging via primary DMA stream head pointer. 346/* Buffer aging via primary DMA stream head pointer.
351 */ 347 */
352 348
@@ -373,7 +369,6 @@ do { \
373 } \ 369 } \
374} while (0) 370} while (0)
375 371
376
377#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ 372#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
378 MGA_DWGENGSTS | \ 373 MGA_DWGENGSTS | \
379 MGA_ENDPRDMASTS) 374 MGA_ENDPRDMASTS)
@@ -382,8 +377,6 @@ do { \
382 377
383#define MGA_DMA_DEBUG 0 378#define MGA_DMA_DEBUG 0
384 379
385
386
387/* A reduced set of the mga registers. 380/* A reduced set of the mga registers.
388 */ 381 */
389#define MGA_CRTC_INDEX 0x1fd4 382#define MGA_CRTC_INDEX 0x1fd4
@@ -644,7 +637,6 @@ do { \
644# define MGA_G400_WR_MAGIC (1 << 6) 637# define MGA_G400_WR_MAGIC (1 << 6)
645# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ 638# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
646 639
647
648#define MGA_ILOAD_ALIGN 64 640#define MGA_ILOAD_ALIGN 64
649#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) 641#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
650 642
@@ -679,10 +671,10 @@ do { \
679 671
680/* Simple idle test. 672/* Simple idle test.
681 */ 673 */
682static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv ) 674static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv)
683{ 675{
684 u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; 676 u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
685 return ( status == MGA_ENDPRDMASTS ); 677 return (status == MGA_ENDPRDMASTS);
686} 678}
687 679
688#endif 680#endif