aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/char/drm/mga_drm.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/char/drm/mga_drm.h')
-rw-r--r--drivers/char/drm/mga_drm.h95
1 files changed, 85 insertions, 10 deletions
diff --git a/drivers/char/drm/mga_drm.h b/drivers/char/drm/mga_drm.h
index 4500e6e4920a..2d8aa790379e 100644
--- a/drivers/char/drm/mga_drm.h
+++ b/drivers/char/drm/mga_drm.h
@@ -226,10 +226,6 @@ typedef struct _drm_mga_sarea {
226} drm_mga_sarea_t; 226} drm_mga_sarea_t;
227 227
228 228
229/* WARNING: If you change any of these defines, make sure to change the
230 * defines in the Xserver file (xf86drmMga.h)
231 */
232
233/* MGA specific ioctls 229/* MGA specific ioctls
234 * The device specific ioctl range is 0x40 to 0x79. 230 * The device specific ioctl range is 0x40 to 0x79.
235 */ 231 */
@@ -244,6 +240,14 @@ typedef struct _drm_mga_sarea {
244#define DRM_MGA_BLIT 0x08 240#define DRM_MGA_BLIT 0x08
245#define DRM_MGA_GETPARAM 0x09 241#define DRM_MGA_GETPARAM 0x09
246 242
243/* 3.2:
244 * ioctls for operating on fences.
245 */
246#define DRM_MGA_SET_FENCE 0x0a
247#define DRM_MGA_WAIT_FENCE 0x0b
248#define DRM_MGA_DMA_BOOTSTRAP 0x0c
249
250
247#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) 251#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
248#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t) 252#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
249#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) 253#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
@@ -254,6 +258,9 @@ typedef struct _drm_mga_sarea {
254#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) 258#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
255#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) 259#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
256#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) 260#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
261#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t)
262#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t)
263#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
257 264
258typedef struct _drm_mga_warp_index { 265typedef struct _drm_mga_warp_index {
259 int installed; 266 int installed;
@@ -292,12 +299,72 @@ typedef struct drm_mga_init {
292 unsigned long buffers_offset; 299 unsigned long buffers_offset;
293} drm_mga_init_t; 300} drm_mga_init_t;
294 301
295typedef struct drm_mga_fullscreen { 302typedef struct drm_mga_dma_bootstrap {
296 enum { 303 /**
297 MGA_INIT_FULLSCREEN = 0x01, 304 * \name AGP texture region
298 MGA_CLEANUP_FULLSCREEN = 0x02 305 *
299 } func; 306 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
300} drm_mga_fullscreen_t; 307 * be filled in with the actual AGP texture settings.
308 *
309 * \warning
310 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
311 * is zero, it means that PCI memory (most likely through the use of
312 * an IOMMU) is being used for "AGP" textures.
313 */
314 /*@{*/
315 drm_handle_t texture_handle; /**< Handle used to map AGP textures. */
316 uint32_t texture_size; /**< Size of the AGP texture region. */
317 /*@}*/
318
319
320 /**
321 * Requested size of the primary DMA region.
322 *
323 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
324 * filled in with the actual AGP mode. If AGP was not available
325 */
326 uint32_t primary_size;
327
328
329 /**
330 * Requested number of secondary DMA buffers.
331 *
332 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
333 * filled in with the actual number of secondary DMA buffers
334 * allocated. Particularly when PCI DMA is used, this may be
335 * (subtantially) less than the number requested.
336 */
337 uint32_t secondary_bin_count;
338
339
340 /**
341 * Requested size of each secondary DMA buffer.
342 *
343 * While the kernel \b is free to reduce
344 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
345 * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
346 */
347 uint32_t secondary_bin_size;
348
349
350 /**
351 * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X,
352 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is
353 * zero, it means that PCI DMA should be used, even if AGP is
354 * possible.
355 *
356 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
357 * filled in with the actual AGP mode. If AGP was not available
358 * (i.e., PCI DMA was used), this value will be zero.
359 */
360 uint32_t agp_mode;
361
362
363 /**
364 * Desired AGP GART size, measured in megabytes.
365 */
366 uint8_t agp_size;
367} drm_mga_dma_bootstrap_t;
301 368
302typedef struct drm_mga_clear { 369typedef struct drm_mga_clear {
303 unsigned int flags; 370 unsigned int flags;
@@ -342,6 +409,14 @@ typedef struct _drm_mga_blit {
342 */ 409 */
343#define MGA_PARAM_IRQ_NR 1 410#define MGA_PARAM_IRQ_NR 1
344 411
412/* 3.2: Query the actual card type. The DDX only distinguishes between
413 * G200 chips and non-G200 chips, which it calls G400. It turns out that
414 * there are some very sublte differences between the G4x0 chips and the G550
415 * chips. Using this parameter query, a client-side driver can detect the
416 * difference between a G4x0 and a G550.
417 */
418#define MGA_PARAM_CARD_TYPE 2
419
345typedef struct drm_mga_getparam { 420typedef struct drm_mga_getparam {
346 int param; 421 int param;
347 void __user *value; 422 void __user *value;