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Diffstat (limited to 'drivers/char/drm/mga_dma.c')
-rw-r--r--drivers/char/drm/mga_dma.c511
1 files changed, 244 insertions, 267 deletions
diff --git a/drivers/char/drm/mga_dma.c b/drivers/char/drm/mga_dma.c
index c8e1b6c83636..70dc7f64b7b9 100644
--- a/drivers/char/drm/mga_dma.c
+++ b/drivers/char/drm/mga_dma.c
@@ -28,7 +28,7 @@
28/** 28/**
29 * \file mga_dma.c 29 * \file mga_dma.c
30 * DMA support for MGA G200 / G400. 30 * DMA support for MGA G200 / G400.
31 * 31 *
32 * \author Rickard E. (Rik) Faith <faith@valinux.com> 32 * \author Rickard E. (Rik) Faith <faith@valinux.com>
33 * \author Jeff Hartmann <jhartmann@valinux.com> 33 * \author Jeff Hartmann <jhartmann@valinux.com>
34 * \author Keith Whitwell <keith@tungstengraphics.com> 34 * \author Keith Whitwell <keith@tungstengraphics.com>
@@ -44,40 +44,40 @@
44#define MGA_DEFAULT_USEC_TIMEOUT 10000 44#define MGA_DEFAULT_USEC_TIMEOUT 10000
45#define MGA_FREELIST_DEBUG 0 45#define MGA_FREELIST_DEBUG 0
46 46
47static int mga_do_cleanup_dma( drm_device_t *dev ); 47static int mga_do_cleanup_dma(drm_device_t * dev);
48 48
49/* ================================================================ 49/* ================================================================
50 * Engine control 50 * Engine control
51 */ 51 */
52 52
53int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ) 53int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
54{ 54{
55 u32 status = 0; 55 u32 status = 0;
56 int i; 56 int i;
57 DRM_DEBUG( "\n" ); 57 DRM_DEBUG("\n");
58 58
59 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 59 for (i = 0; i < dev_priv->usec_timeout; i++) {
60 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; 60 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
61 if ( status == MGA_ENDPRDMASTS ) { 61 if (status == MGA_ENDPRDMASTS) {
62 MGA_WRITE8( MGA_CRTC_INDEX, 0 ); 62 MGA_WRITE8(MGA_CRTC_INDEX, 0);
63 return 0; 63 return 0;
64 } 64 }
65 DRM_UDELAY( 1 ); 65 DRM_UDELAY(1);
66 } 66 }
67 67
68#if MGA_DMA_DEBUG 68#if MGA_DMA_DEBUG
69 DRM_ERROR( "failed!\n" ); 69 DRM_ERROR("failed!\n");
70 DRM_INFO( " status=0x%08x\n", status ); 70 DRM_INFO(" status=0x%08x\n", status);
71#endif 71#endif
72 return DRM_ERR(EBUSY); 72 return DRM_ERR(EBUSY);
73} 73}
74 74
75static int mga_do_dma_reset( drm_mga_private_t *dev_priv ) 75static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
76{ 76{
77 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 77 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
78 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 78 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
79 79
80 DRM_DEBUG( "\n" ); 80 DRM_DEBUG("\n");
81 81
82 /* The primary DMA stream should look like new right about now. 82 /* The primary DMA stream should look like new right about now.
83 */ 83 */
@@ -100,24 +100,25 @@ static int mga_do_dma_reset( drm_mga_private_t *dev_priv )
100 * Primary DMA stream 100 * Primary DMA stream
101 */ 101 */
102 102
103void mga_do_dma_flush( drm_mga_private_t *dev_priv ) 103void mga_do_dma_flush(drm_mga_private_t * dev_priv)
104{ 104{
105 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 105 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
106 u32 head, tail; 106 u32 head, tail;
107 u32 status = 0; 107 u32 status = 0;
108 int i; 108 int i;
109 DMA_LOCALS; 109 DMA_LOCALS;
110 DRM_DEBUG( "\n" ); 110 DRM_DEBUG("\n");
111 111
112 /* We need to wait so that we can do an safe flush */ 112 /* We need to wait so that we can do an safe flush */
113 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 113 for (i = 0; i < dev_priv->usec_timeout; i++) {
114 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; 114 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
115 if ( status == MGA_ENDPRDMASTS ) break; 115 if (status == MGA_ENDPRDMASTS)
116 DRM_UDELAY( 1 ); 116 break;
117 DRM_UDELAY(1);
117 } 118 }
118 119
119 if ( primary->tail == primary->last_flush ) { 120 if (primary->tail == primary->last_flush) {
120 DRM_DEBUG( " bailing out...\n" ); 121 DRM_DEBUG(" bailing out...\n");
121 return; 122 return;
122 } 123 }
123 124
@@ -127,48 +128,46 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
127 * actually (partially?) reads the first of these commands. 128 * actually (partially?) reads the first of these commands.
128 * See page 4-16 in the G400 manual, middle of the page or so. 129 * See page 4-16 in the G400 manual, middle of the page or so.
129 */ 130 */
130 BEGIN_DMA( 1 ); 131 BEGIN_DMA(1);
131 132
132 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 133 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
133 MGA_DMAPAD, 0x00000000, 134 MGA_DMAPAD, 0x00000000,
134 MGA_DMAPAD, 0x00000000, 135 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
135 MGA_DMAPAD, 0x00000000 );
136 136
137 ADVANCE_DMA(); 137 ADVANCE_DMA();
138 138
139 primary->last_flush = primary->tail; 139 primary->last_flush = primary->tail;
140 140
141 head = MGA_READ( MGA_PRIMADDRESS ); 141 head = MGA_READ(MGA_PRIMADDRESS);
142 142
143 if ( head <= tail ) { 143 if (head <= tail) {
144 primary->space = primary->size - primary->tail; 144 primary->space = primary->size - primary->tail;
145 } else { 145 } else {
146 primary->space = head - tail; 146 primary->space = head - tail;
147 } 147 }
148 148
149 DRM_DEBUG( " head = 0x%06lx\n", head - dev_priv->primary->offset ); 149 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
150 DRM_DEBUG( " tail = 0x%06lx\n", tail - dev_priv->primary->offset ); 150 DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset);
151 DRM_DEBUG( " space = 0x%06x\n", primary->space ); 151 DRM_DEBUG(" space = 0x%06x\n", primary->space);
152 152
153 mga_flush_write_combine(); 153 mga_flush_write_combine();
154 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); 154 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
155 155
156 DRM_DEBUG( "done.\n" ); 156 DRM_DEBUG("done.\n");
157} 157}
158 158
159void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ) 159void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
160{ 160{
161 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 161 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
162 u32 head, tail; 162 u32 head, tail;
163 DMA_LOCALS; 163 DMA_LOCALS;
164 DRM_DEBUG( "\n" ); 164 DRM_DEBUG("\n");
165 165
166 BEGIN_DMA_WRAP(); 166 BEGIN_DMA_WRAP();
167 167
168 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 168 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
169 MGA_DMAPAD, 0x00000000, 169 MGA_DMAPAD, 0x00000000,
170 MGA_DMAPAD, 0x00000000, 170 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
171 MGA_DMAPAD, 0x00000000 );
172 171
173 ADVANCE_DMA(); 172 ADVANCE_DMA();
174 173
@@ -178,45 +177,43 @@ void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
178 primary->last_flush = 0; 177 primary->last_flush = 0;
179 primary->last_wrap++; 178 primary->last_wrap++;
180 179
181 head = MGA_READ( MGA_PRIMADDRESS ); 180 head = MGA_READ(MGA_PRIMADDRESS);
182 181
183 if ( head == dev_priv->primary->offset ) { 182 if (head == dev_priv->primary->offset) {
184 primary->space = primary->size; 183 primary->space = primary->size;
185 } else { 184 } else {
186 primary->space = head - dev_priv->primary->offset; 185 primary->space = head - dev_priv->primary->offset;
187 } 186 }
188 187
189 DRM_DEBUG( " head = 0x%06lx\n", 188 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
190 head - dev_priv->primary->offset ); 189 DRM_DEBUG(" tail = 0x%06x\n", primary->tail);
191 DRM_DEBUG( " tail = 0x%06x\n", primary->tail ); 190 DRM_DEBUG(" wrap = %d\n", primary->last_wrap);
192 DRM_DEBUG( " wrap = %d\n", primary->last_wrap ); 191 DRM_DEBUG(" space = 0x%06x\n", primary->space);
193 DRM_DEBUG( " space = 0x%06x\n", primary->space );
194 192
195 mga_flush_write_combine(); 193 mga_flush_write_combine();
196 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); 194 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
197 195
198 set_bit( 0, &primary->wrapped ); 196 set_bit(0, &primary->wrapped);
199 DRM_DEBUG( "done.\n" ); 197 DRM_DEBUG("done.\n");
200} 198}
201 199
202void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ) 200void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
203{ 201{
204 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 202 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
205 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 203 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
206 u32 head = dev_priv->primary->offset; 204 u32 head = dev_priv->primary->offset;
207 DRM_DEBUG( "\n" ); 205 DRM_DEBUG("\n");
208 206
209 sarea_priv->last_wrap++; 207 sarea_priv->last_wrap++;
210 DRM_DEBUG( " wrap = %d\n", sarea_priv->last_wrap ); 208 DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap);
211 209
212 mga_flush_write_combine(); 210 mga_flush_write_combine();
213 MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL ); 211 MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
214 212
215 clear_bit( 0, &primary->wrapped ); 213 clear_bit(0, &primary->wrapped);
216 DRM_DEBUG( "done.\n" ); 214 DRM_DEBUG("done.\n");
217} 215}
218 216
219
220/* ================================================================ 217/* ================================================================
221 * Freelist management 218 * Freelist management
222 */ 219 */
@@ -225,63 +222,61 @@ void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
225#define MGA_BUFFER_FREE 0 222#define MGA_BUFFER_FREE 0
226 223
227#if MGA_FREELIST_DEBUG 224#if MGA_FREELIST_DEBUG
228static void mga_freelist_print( drm_device_t *dev ) 225static void mga_freelist_print(drm_device_t * dev)
229{ 226{
230 drm_mga_private_t *dev_priv = dev->dev_private; 227 drm_mga_private_t *dev_priv = dev->dev_private;
231 drm_mga_freelist_t *entry; 228 drm_mga_freelist_t *entry;
232 229
233 DRM_INFO( "\n" ); 230 DRM_INFO("\n");
234 DRM_INFO( "current dispatch: last=0x%x done=0x%x\n", 231 DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
235 dev_priv->sarea_priv->last_dispatch, 232 dev_priv->sarea_priv->last_dispatch,
236 (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) - 233 (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
237 dev_priv->primary->offset) ); 234 dev_priv->primary->offset));
238 DRM_INFO( "current freelist:\n" ); 235 DRM_INFO("current freelist:\n");
239 236
240 for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) { 237 for (entry = dev_priv->head->next; entry; entry = entry->next) {
241 DRM_INFO( " %p idx=%2d age=0x%x 0x%06lx\n", 238 DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n",
242 entry, entry->buf->idx, entry->age.head, 239 entry, entry->buf->idx, entry->age.head,
243 entry->age.head - dev_priv->primary->offset ); 240 entry->age.head - dev_priv->primary->offset);
244 } 241 }
245 DRM_INFO( "\n" ); 242 DRM_INFO("\n");
246} 243}
247#endif 244#endif
248 245
249static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv ) 246static int mga_freelist_init(drm_device_t * dev, drm_mga_private_t * dev_priv)
250{ 247{
251 drm_device_dma_t *dma = dev->dma; 248 drm_device_dma_t *dma = dev->dma;
252 drm_buf_t *buf; 249 drm_buf_t *buf;
253 drm_mga_buf_priv_t *buf_priv; 250 drm_mga_buf_priv_t *buf_priv;
254 drm_mga_freelist_t *entry; 251 drm_mga_freelist_t *entry;
255 int i; 252 int i;
256 DRM_DEBUG( "count=%d\n", dma->buf_count ); 253 DRM_DEBUG("count=%d\n", dma->buf_count);
257 254
258 dev_priv->head = drm_alloc( sizeof(drm_mga_freelist_t), 255 dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
259 DRM_MEM_DRIVER ); 256 if (dev_priv->head == NULL)
260 if ( dev_priv->head == NULL )
261 return DRM_ERR(ENOMEM); 257 return DRM_ERR(ENOMEM);
262 258
263 memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) ); 259 memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
264 SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 ); 260 SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
265 261
266 for ( i = 0 ; i < dma->buf_count ; i++ ) { 262 for (i = 0; i < dma->buf_count; i++) {
267 buf = dma->buflist[i]; 263 buf = dma->buflist[i];
268 buf_priv = buf->dev_private; 264 buf_priv = buf->dev_private;
269 265
270 entry = drm_alloc( sizeof(drm_mga_freelist_t), 266 entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
271 DRM_MEM_DRIVER ); 267 if (entry == NULL)
272 if ( entry == NULL )
273 return DRM_ERR(ENOMEM); 268 return DRM_ERR(ENOMEM);
274 269
275 memset( entry, 0, sizeof(drm_mga_freelist_t) ); 270 memset(entry, 0, sizeof(drm_mga_freelist_t));
276 271
277 entry->next = dev_priv->head->next; 272 entry->next = dev_priv->head->next;
278 entry->prev = dev_priv->head; 273 entry->prev = dev_priv->head;
279 SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); 274 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
280 entry->buf = buf; 275 entry->buf = buf;
281 276
282 if ( dev_priv->head->next != NULL ) 277 if (dev_priv->head->next != NULL)
283 dev_priv->head->next->prev = entry; 278 dev_priv->head->next->prev = entry;
284 if ( entry->next == NULL ) 279 if (entry->next == NULL)
285 dev_priv->tail = entry; 280 dev_priv->tail = entry;
286 281
287 buf_priv->list_entry = entry; 282 buf_priv->list_entry = entry;
@@ -294,17 +289,17 @@ static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv )
294 return 0; 289 return 0;
295} 290}
296 291
297static void mga_freelist_cleanup( drm_device_t *dev ) 292static void mga_freelist_cleanup(drm_device_t * dev)
298{ 293{
299 drm_mga_private_t *dev_priv = dev->dev_private; 294 drm_mga_private_t *dev_priv = dev->dev_private;
300 drm_mga_freelist_t *entry; 295 drm_mga_freelist_t *entry;
301 drm_mga_freelist_t *next; 296 drm_mga_freelist_t *next;
302 DRM_DEBUG( "\n" ); 297 DRM_DEBUG("\n");
303 298
304 entry = dev_priv->head; 299 entry = dev_priv->head;
305 while ( entry ) { 300 while (entry) {
306 next = entry->next; 301 next = entry->next;
307 drm_free( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER ); 302 drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
308 entry = next; 303 entry = next;
309 } 304 }
310 305
@@ -314,71 +309,69 @@ static void mga_freelist_cleanup( drm_device_t *dev )
314#if 0 309#if 0
315/* FIXME: Still needed? 310/* FIXME: Still needed?
316 */ 311 */
317static void mga_freelist_reset( drm_device_t *dev ) 312static void mga_freelist_reset(drm_device_t * dev)
318{ 313{
319 drm_device_dma_t *dma = dev->dma; 314 drm_device_dma_t *dma = dev->dma;
320 drm_buf_t *buf; 315 drm_buf_t *buf;
321 drm_mga_buf_priv_t *buf_priv; 316 drm_mga_buf_priv_t *buf_priv;
322 int i; 317 int i;
323 318
324 for ( i = 0 ; i < dma->buf_count ; i++ ) { 319 for (i = 0; i < dma->buf_count; i++) {
325 buf = dma->buflist[i]; 320 buf = dma->buflist[i];
326 buf_priv = buf->dev_private; 321 buf_priv = buf->dev_private;
327 SET_AGE( &buf_priv->list_entry->age, 322 SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
328 MGA_BUFFER_FREE, 0 );
329 } 323 }
330} 324}
331#endif 325#endif
332 326
333static drm_buf_t *mga_freelist_get( drm_device_t *dev ) 327static drm_buf_t *mga_freelist_get(drm_device_t * dev)
334{ 328{
335 drm_mga_private_t *dev_priv = dev->dev_private; 329 drm_mga_private_t *dev_priv = dev->dev_private;
336 drm_mga_freelist_t *next; 330 drm_mga_freelist_t *next;
337 drm_mga_freelist_t *prev; 331 drm_mga_freelist_t *prev;
338 drm_mga_freelist_t *tail = dev_priv->tail; 332 drm_mga_freelist_t *tail = dev_priv->tail;
339 u32 head, wrap; 333 u32 head, wrap;
340 DRM_DEBUG( "\n" ); 334 DRM_DEBUG("\n");
341 335
342 head = MGA_READ( MGA_PRIMADDRESS ); 336 head = MGA_READ(MGA_PRIMADDRESS);
343 wrap = dev_priv->sarea_priv->last_wrap; 337 wrap = dev_priv->sarea_priv->last_wrap;
344 338
345 DRM_DEBUG( " tail=0x%06lx %d\n", 339 DRM_DEBUG(" tail=0x%06lx %d\n",
346 tail->age.head ? 340 tail->age.head ?
347 tail->age.head - dev_priv->primary->offset : 0, 341 tail->age.head - dev_priv->primary->offset : 0,
348 tail->age.wrap ); 342 tail->age.wrap);
349 DRM_DEBUG( " head=0x%06lx %d\n", 343 DRM_DEBUG(" head=0x%06lx %d\n",
350 head - dev_priv->primary->offset, wrap ); 344 head - dev_priv->primary->offset, wrap);
351 345
352 if ( TEST_AGE( &tail->age, head, wrap ) ) { 346 if (TEST_AGE(&tail->age, head, wrap)) {
353 prev = dev_priv->tail->prev; 347 prev = dev_priv->tail->prev;
354 next = dev_priv->tail; 348 next = dev_priv->tail;
355 prev->next = NULL; 349 prev->next = NULL;
356 next->prev = next->next = NULL; 350 next->prev = next->next = NULL;
357 dev_priv->tail = prev; 351 dev_priv->tail = prev;
358 SET_AGE( &next->age, MGA_BUFFER_USED, 0 ); 352 SET_AGE(&next->age, MGA_BUFFER_USED, 0);
359 return next->buf; 353 return next->buf;
360 } 354 }
361 355
362 DRM_DEBUG( "returning NULL!\n" ); 356 DRM_DEBUG("returning NULL!\n");
363 return NULL; 357 return NULL;
364} 358}
365 359
366int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ) 360int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf)
367{ 361{
368 drm_mga_private_t *dev_priv = dev->dev_private; 362 drm_mga_private_t *dev_priv = dev->dev_private;
369 drm_mga_buf_priv_t *buf_priv = buf->dev_private; 363 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
370 drm_mga_freelist_t *head, *entry, *prev; 364 drm_mga_freelist_t *head, *entry, *prev;
371 365
372 DRM_DEBUG( "age=0x%06lx wrap=%d\n", 366 DRM_DEBUG("age=0x%06lx wrap=%d\n",
373 buf_priv->list_entry->age.head - 367 buf_priv->list_entry->age.head -
374 dev_priv->primary->offset, 368 dev_priv->primary->offset, buf_priv->list_entry->age.wrap);
375 buf_priv->list_entry->age.wrap );
376 369
377 entry = buf_priv->list_entry; 370 entry = buf_priv->list_entry;
378 head = dev_priv->head; 371 head = dev_priv->head;
379 372
380 if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) { 373 if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
381 SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); 374 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
382 prev = dev_priv->tail; 375 prev = dev_priv->tail;
383 prev->next = entry; 376 prev->next = entry;
384 entry->prev = prev; 377 entry->prev = prev;
@@ -394,15 +387,13 @@ int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf )
394 return 0; 387 return 0;
395} 388}
396 389
397
398/* ================================================================ 390/* ================================================================
399 * DMA initialization, cleanup 391 * DMA initialization, cleanup
400 */ 392 */
401 393
402 394int mga_driver_preinit(drm_device_t * dev, unsigned long flags)
403int mga_driver_preinit(drm_device_t *dev, unsigned long flags)
404{ 395{
405 drm_mga_private_t * dev_priv; 396 drm_mga_private_t *dev_priv;
406 397
407 dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); 398 dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
408 if (!dev_priv) 399 if (!dev_priv)
@@ -420,7 +411,7 @@ int mga_driver_preinit(drm_device_t *dev, unsigned long flags)
420#if __OS_HAS_AGP 411#if __OS_HAS_AGP
421/** 412/**
422 * Bootstrap the driver for AGP DMA. 413 * Bootstrap the driver for AGP DMA.
423 * 414 *
424 * \todo 415 * \todo
425 * Investigate whether there is any benifit to storing the WARP microcode in 416 * Investigate whether there is any benifit to storing the WARP microcode in
426 * AGP memory. If not, the microcode may as well always be put in PCI 417 * AGP memory. If not, the microcode may as well always be put in PCI
@@ -436,18 +427,18 @@ int mga_driver_preinit(drm_device_t *dev, unsigned long flags)
436static int mga_do_agp_dma_bootstrap(drm_device_t * dev, 427static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
437 drm_mga_dma_bootstrap_t * dma_bs) 428 drm_mga_dma_bootstrap_t * dma_bs)
438{ 429{
439 drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private; 430 drm_mga_private_t *const dev_priv =
431 (drm_mga_private_t *) dev->dev_private;
440 unsigned int warp_size = mga_warp_microcode_size(dev_priv); 432 unsigned int warp_size = mga_warp_microcode_size(dev_priv);
441 int err; 433 int err;
442 unsigned offset; 434 unsigned offset;
443 const unsigned secondary_size = dma_bs->secondary_bin_count 435 const unsigned secondary_size = dma_bs->secondary_bin_count
444 * dma_bs->secondary_bin_size; 436 * dma_bs->secondary_bin_size;
445 const unsigned agp_size = (dma_bs->agp_size << 20); 437 const unsigned agp_size = (dma_bs->agp_size << 20);
446 drm_buf_desc_t req; 438 drm_buf_desc_t req;
447 drm_agp_mode_t mode; 439 drm_agp_mode_t mode;
448 drm_agp_info_t info; 440 drm_agp_info_t info;
449 441
450
451 /* Acquire AGP. */ 442 /* Acquire AGP. */
452 err = drm_agp_acquire(dev); 443 err = drm_agp_acquire(dev);
453 if (err) { 444 if (err) {
@@ -468,7 +459,6 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
468 return err; 459 return err;
469 } 460 }
470 461
471
472 /* In addition to the usual AGP mode configuration, the G200 AGP cards 462 /* In addition to the usual AGP mode configuration, the G200 AGP cards
473 * need to have the AGP mode "manually" set. 463 * need to have the AGP mode "manually" set.
474 */ 464 */
@@ -476,24 +466,22 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
476 if (dev_priv->chipset == MGA_CARD_TYPE_G200) { 466 if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
477 if (mode.mode & 0x02) { 467 if (mode.mode & 0x02) {
478 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE); 468 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
479 } 469 } else {
480 else {
481 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE); 470 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
482 } 471 }
483 } 472 }
484 473
485
486 /* Allocate and bind AGP memory. */ 474 /* Allocate and bind AGP memory. */
487 dev_priv->agp_pages = agp_size / PAGE_SIZE; 475 dev_priv->agp_pages = agp_size / PAGE_SIZE;
488 dev_priv->agp_mem = drm_alloc_agp( dev, dev_priv->agp_pages, 0 ); 476 dev_priv->agp_mem = drm_alloc_agp(dev, dev_priv->agp_pages, 0);
489 if (dev_priv->agp_mem == NULL) { 477 if (dev_priv->agp_mem == NULL) {
490 dev_priv->agp_pages = 0; 478 dev_priv->agp_pages = 0;
491 DRM_ERROR("Unable to allocate %uMB AGP memory\n", 479 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
492 dma_bs->agp_size); 480 dma_bs->agp_size);
493 return DRM_ERR(ENOMEM); 481 return DRM_ERR(ENOMEM);
494 } 482 }
495 483
496 err = drm_bind_agp( dev_priv->agp_mem, 0 ); 484 err = drm_bind_agp(dev_priv->agp_mem, 0);
497 if (err) { 485 if (err) {
498 DRM_ERROR("Unable to bind AGP memory\n"); 486 DRM_ERROR("Unable to bind AGP memory\n");
499 return err; 487 return err;
@@ -506,44 +494,44 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
506 warp_size = PAGE_SIZE; 494 warp_size = PAGE_SIZE;
507 495
508 offset = 0; 496 offset = 0;
509 err = drm_addmap( dev, offset, warp_size, 497 err = drm_addmap(dev, offset, warp_size,
510 _DRM_AGP, _DRM_READ_ONLY, & dev_priv->warp ); 498 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
511 if (err) { 499 if (err) {
512 DRM_ERROR("Unable to map WARP microcode\n"); 500 DRM_ERROR("Unable to map WARP microcode\n");
513 return err; 501 return err;
514 } 502 }
515 503
516 offset += warp_size; 504 offset += warp_size;
517 err = drm_addmap( dev, offset, dma_bs->primary_size, 505 err = drm_addmap(dev, offset, dma_bs->primary_size,
518 _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary ); 506 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary);
519 if (err) { 507 if (err) {
520 DRM_ERROR("Unable to map primary DMA region\n"); 508 DRM_ERROR("Unable to map primary DMA region\n");
521 return err; 509 return err;
522 } 510 }
523 511
524 offset += dma_bs->primary_size; 512 offset += dma_bs->primary_size;
525 err = drm_addmap( dev, offset, secondary_size, 513 err = drm_addmap(dev, offset, secondary_size,
526 _DRM_AGP, 0, & dev->agp_buffer_map ); 514 _DRM_AGP, 0, &dev->agp_buffer_map);
527 if (err) { 515 if (err) {
528 DRM_ERROR("Unable to map secondary DMA region\n"); 516 DRM_ERROR("Unable to map secondary DMA region\n");
529 return err; 517 return err;
530 } 518 }
531 519
532 (void) memset( &req, 0, sizeof(req) ); 520 (void)memset(&req, 0, sizeof(req));
533 req.count = dma_bs->secondary_bin_count; 521 req.count = dma_bs->secondary_bin_count;
534 req.size = dma_bs->secondary_bin_size; 522 req.size = dma_bs->secondary_bin_size;
535 req.flags = _DRM_AGP_BUFFER; 523 req.flags = _DRM_AGP_BUFFER;
536 req.agp_start = offset; 524 req.agp_start = offset;
537 525
538 err = drm_addbufs_agp( dev, & req ); 526 err = drm_addbufs_agp(dev, &req);
539 if (err) { 527 if (err) {
540 DRM_ERROR("Unable to add secondary DMA buffers\n"); 528 DRM_ERROR("Unable to add secondary DMA buffers\n");
541 return err; 529 return err;
542 } 530 }
543 531
544 offset += secondary_size; 532 offset += secondary_size;
545 err = drm_addmap( dev, offset, agp_size - offset, 533 err = drm_addmap(dev, offset, agp_size - offset,
546 _DRM_AGP, 0, & dev_priv->agp_textures ); 534 _DRM_AGP, 0, &dev_priv->agp_textures);
547 if (err) { 535 if (err) {
548 DRM_ERROR("Unable to map AGP texture region\n"); 536 DRM_ERROR("Unable to map AGP texture region\n");
549 return err; 537 return err;
@@ -577,7 +565,7 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
577 565
578/** 566/**
579 * Bootstrap the driver for PCI DMA. 567 * Bootstrap the driver for PCI DMA.
580 * 568 *
581 * \todo 569 * \todo
582 * The algorithm for decreasing the size of the primary DMA buffer could be 570 * The algorithm for decreasing the size of the primary DMA buffer could be
583 * better. The size should be rounded up to the nearest page size, then 571 * better. The size should be rounded up to the nearest page size, then
@@ -586,20 +574,20 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
586 * \todo 574 * \todo
587 * Determine whether the maximum address passed to drm_pci_alloc is correct. 575 * Determine whether the maximum address passed to drm_pci_alloc is correct.
588 * The same goes for drm_addbufs_pci. 576 * The same goes for drm_addbufs_pci.
589 * 577 *
590 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap 578 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
591 */ 579 */
592static int mga_do_pci_dma_bootstrap(drm_device_t * dev, 580static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
593 drm_mga_dma_bootstrap_t * dma_bs) 581 drm_mga_dma_bootstrap_t * dma_bs)
594{ 582{
595 drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private; 583 drm_mga_private_t *const dev_priv =
584 (drm_mga_private_t *) dev->dev_private;
596 unsigned int warp_size = mga_warp_microcode_size(dev_priv); 585 unsigned int warp_size = mga_warp_microcode_size(dev_priv);
597 unsigned int primary_size; 586 unsigned int primary_size;
598 unsigned int bin_count; 587 unsigned int bin_count;
599 int err; 588 int err;
600 drm_buf_desc_t req; 589 drm_buf_desc_t req;
601 590
602
603 if (dev->dma == NULL) { 591 if (dev->dma == NULL) {
604 DRM_ERROR("dev->dma is NULL\n"); 592 DRM_ERROR("dev->dma is NULL\n");
605 return DRM_ERR(EFAULT); 593 return DRM_ERR(EFAULT);
@@ -624,9 +612,8 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
624 * alignment of the primary or secondary DMA buffers. 612 * alignment of the primary or secondary DMA buffers.
625 */ 613 */
626 614
627 for ( primary_size = dma_bs->primary_size 615 for (primary_size = dma_bs->primary_size; primary_size != 0;
628 ; primary_size != 0 616 primary_size >>= 1) {
629 ; primary_size >>= 1 ) {
630 /* The proper alignment for this mapping is 0x04 */ 617 /* The proper alignment for this mapping is 0x04 */
631 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT, 618 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
632 _DRM_READ_ONLY, &dev_priv->primary); 619 _DRM_READ_ONLY, &dev_priv->primary);
@@ -641,24 +628,23 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
641 628
642 if (dev_priv->primary->size != dma_bs->primary_size) { 629 if (dev_priv->primary->size != dma_bs->primary_size) {
643 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n", 630 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
644 dma_bs->primary_size, 631 dma_bs->primary_size,
645 (unsigned) dev_priv->primary->size); 632 (unsigned)dev_priv->primary->size);
646 dma_bs->primary_size = dev_priv->primary->size; 633 dma_bs->primary_size = dev_priv->primary->size;
647 } 634 }
648 635
649 for ( bin_count = dma_bs->secondary_bin_count 636 for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
650 ; bin_count > 0 637 bin_count--) {
651 ; bin_count-- ) { 638 (void)memset(&req, 0, sizeof(req));
652 (void) memset( &req, 0, sizeof(req) );
653 req.count = bin_count; 639 req.count = bin_count;
654 req.size = dma_bs->secondary_bin_size; 640 req.size = dma_bs->secondary_bin_size;
655 641
656 err = drm_addbufs_pci( dev, & req ); 642 err = drm_addbufs_pci(dev, &req);
657 if (!err) { 643 if (!err) {
658 break; 644 break;
659 } 645 }
660 } 646 }
661 647
662 if (bin_count == 0) { 648 if (bin_count == 0) {
663 DRM_ERROR("Unable to add secondary DMA buffers\n"); 649 DRM_ERROR("Unable to add secondary DMA buffers\n");
664 return err; 650 return err;
@@ -680,38 +666,34 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
680 return 0; 666 return 0;
681} 667}
682 668
683
684static int mga_do_dma_bootstrap(drm_device_t * dev, 669static int mga_do_dma_bootstrap(drm_device_t * dev,
685 drm_mga_dma_bootstrap_t * dma_bs) 670 drm_mga_dma_bootstrap_t * dma_bs)
686{ 671{
687 const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev); 672 const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
688 int err; 673 int err;
689 drm_mga_private_t * const dev_priv = 674 drm_mga_private_t *const dev_priv =
690 (drm_mga_private_t *) dev->dev_private; 675 (drm_mga_private_t *) dev->dev_private;
691
692 676
693 dev_priv->used_new_dma_init = 1; 677 dev_priv->used_new_dma_init = 1;
694 678
695 /* The first steps are the same for both PCI and AGP based DMA. Map 679 /* The first steps are the same for both PCI and AGP based DMA. Map
696 * the cards MMIO registers and map a status page. 680 * the cards MMIO registers and map a status page.
697 */ 681 */
698 err = drm_addmap( dev, dev_priv->mmio_base, dev_priv->mmio_size, 682 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
699 _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio ); 683 _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
700 if (err) { 684 if (err) {
701 DRM_ERROR("Unable to map MMIO region\n"); 685 DRM_ERROR("Unable to map MMIO region\n");
702 return err; 686 return err;
703 } 687 }
704 688
705 689 err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
706 err = drm_addmap( dev, 0, SAREA_MAX, _DRM_SHM, 690 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
707 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL, 691 &dev_priv->status);
708 & dev_priv->status );
709 if (err) { 692 if (err) {
710 DRM_ERROR("Unable to map status region\n"); 693 DRM_ERROR("Unable to map status region\n");
711 return err; 694 return err;
712 } 695 }
713 696
714
715 /* The DMA initialization procedure is slightly different for PCI and 697 /* The DMA initialization procedure is slightly different for PCI and
716 * AGP cards. AGP cards just allocate a large block of AGP memory and 698 * AGP cards. AGP cards just allocate a large block of AGP memory and
717 * carve off portions of it for internal uses. The remaining memory 699 * carve off portions of it for internal uses. The remaining memory
@@ -720,7 +702,7 @@ static int mga_do_dma_bootstrap(drm_device_t * dev,
720 if (is_agp) { 702 if (is_agp) {
721 err = mga_do_agp_dma_bootstrap(dev, dma_bs); 703 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
722 } 704 }
723 705
724 /* If we attempted to initialize the card for AGP DMA but failed, 706 /* If we attempted to initialize the card for AGP DMA but failed,
725 * clean-up any mess that may have been created. 707 * clean-up any mess that may have been created.
726 */ 708 */
@@ -729,7 +711,6 @@ static int mga_do_dma_bootstrap(drm_device_t * dev,
729 mga_do_cleanup_dma(dev); 711 mga_do_cleanup_dma(dev);
730 } 712 }
731 713
732
733 /* Not only do we want to try and initialized PCI cards for PCI DMA, 714 /* Not only do we want to try and initialized PCI cards for PCI DMA,
734 * but we also try to initialized AGP cards that could not be 715 * but we also try to initialized AGP cards that could not be
735 * initialized for AGP DMA. This covers the case where we have an AGP 716 * initialized for AGP DMA. This covers the case where we have an AGP
@@ -742,7 +723,6 @@ static int mga_do_dma_bootstrap(drm_device_t * dev,
742 err = mga_do_pci_dma_bootstrap(dev, dma_bs); 723 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
743 } 724 }
744 725
745
746 return err; 726 return err;
747} 727}
748 728
@@ -752,45 +732,42 @@ int mga_dma_bootstrap(DRM_IOCTL_ARGS)
752 drm_mga_dma_bootstrap_t bootstrap; 732 drm_mga_dma_bootstrap_t bootstrap;
753 int err; 733 int err;
754 734
755
756 DRM_COPY_FROM_USER_IOCTL(bootstrap, 735 DRM_COPY_FROM_USER_IOCTL(bootstrap,
757 (drm_mga_dma_bootstrap_t __user *) data, 736 (drm_mga_dma_bootstrap_t __user *) data,
758 sizeof(bootstrap)); 737 sizeof(bootstrap));
759 738
760 err = mga_do_dma_bootstrap(dev, & bootstrap); 739 err = mga_do_dma_bootstrap(dev, &bootstrap);
761 if (! err) { 740 if (!err) {
762 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 }; 741 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
763 const drm_mga_private_t * const dev_priv = 742 const drm_mga_private_t *const dev_priv =
764 (drm_mga_private_t *) dev->dev_private; 743 (drm_mga_private_t *) dev->dev_private;
765 744
766 if (dev_priv->agp_textures != NULL) { 745 if (dev_priv->agp_textures != NULL) {
767 bootstrap.texture_handle = dev_priv->agp_textures->offset; 746 bootstrap.texture_handle =
747 dev_priv->agp_textures->offset;
768 bootstrap.texture_size = dev_priv->agp_textures->size; 748 bootstrap.texture_size = dev_priv->agp_textures->size;
769 } 749 } else {
770 else {
771 bootstrap.texture_handle = 0; 750 bootstrap.texture_handle = 0;
772 bootstrap.texture_size = 0; 751 bootstrap.texture_size = 0;
773 } 752 }
774 753
775 bootstrap.agp_mode = modes[ bootstrap.agp_mode & 0x07 ]; 754 bootstrap.agp_mode = modes[bootstrap.agp_mode & 0x07];
776 if (DRM_COPY_TO_USER( (void __user *) data, & bootstrap, 755 if (DRM_COPY_TO_USER((void __user *)data, &bootstrap,
777 sizeof(bootstrap))) { 756 sizeof(bootstrap))) {
778 err = DRM_ERR(EFAULT); 757 err = DRM_ERR(EFAULT);
779 } 758 }
780 } 759 } else {
781 else {
782 mga_do_cleanup_dma(dev); 760 mga_do_cleanup_dma(dev);
783 } 761 }
784 762
785 return err; 763 return err;
786} 764}
787 765
788static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) 766static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init)
789{ 767{
790 drm_mga_private_t *dev_priv; 768 drm_mga_private_t *dev_priv;
791 int ret; 769 int ret;
792 DRM_DEBUG( "\n" ); 770 DRM_DEBUG("\n");
793
794 771
795 dev_priv = dev->dev_private; 772 dev_priv = dev->dev_private;
796 773
@@ -799,17 +776,17 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
799 } else { 776 } else {
800 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; 777 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
801 } 778 }
802 dev_priv->maccess = init->maccess; 779 dev_priv->maccess = init->maccess;
803 780
804 dev_priv->fb_cpp = init->fb_cpp; 781 dev_priv->fb_cpp = init->fb_cpp;
805 dev_priv->front_offset = init->front_offset; 782 dev_priv->front_offset = init->front_offset;
806 dev_priv->front_pitch = init->front_pitch; 783 dev_priv->front_pitch = init->front_pitch;
807 dev_priv->back_offset = init->back_offset; 784 dev_priv->back_offset = init->back_offset;
808 dev_priv->back_pitch = init->back_pitch; 785 dev_priv->back_pitch = init->back_pitch;
809 786
810 dev_priv->depth_cpp = init->depth_cpp; 787 dev_priv->depth_cpp = init->depth_cpp;
811 dev_priv->depth_offset = init->depth_offset; 788 dev_priv->depth_offset = init->depth_offset;
812 dev_priv->depth_pitch = init->depth_pitch; 789 dev_priv->depth_pitch = init->depth_pitch;
813 790
814 /* FIXME: Need to support AGP textures... 791 /* FIXME: Need to support AGP textures...
815 */ 792 */
@@ -823,7 +800,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
823 return DRM_ERR(EINVAL); 800 return DRM_ERR(EINVAL);
824 } 801 }
825 802
826 if (! dev_priv->used_new_dma_init) { 803 if (!dev_priv->used_new_dma_init) {
827 804
828 dev_priv->dma_access = MGA_PAGPXFER; 805 dev_priv->dma_access = MGA_PAGPXFER;
829 dev_priv->wagp_enable = MGA_WAGP_ENABLE; 806 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
@@ -849,7 +826,8 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
849 return DRM_ERR(EINVAL); 826 return DRM_ERR(EINVAL);
850 } 827 }
851 dev->agp_buffer_token = init->buffers_offset; 828 dev->agp_buffer_token = init->buffers_offset;
852 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 829 dev->agp_buffer_map =
830 drm_core_findmap(dev, init->buffers_offset);
853 if (!dev->agp_buffer_map) { 831 if (!dev->agp_buffer_map) {
854 DRM_ERROR("failed to find dma buffer region!\n"); 832 DRM_ERROR("failed to find dma buffer region!\n");
855 return DRM_ERR(EINVAL); 833 return DRM_ERR(EINVAL);
@@ -861,8 +839,8 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
861 } 839 }
862 840
863 dev_priv->sarea_priv = 841 dev_priv->sarea_priv =
864 (drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle + 842 (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
865 init->sarea_priv_offset); 843 init->sarea_priv_offset);
866 844
867 if (!dev_priv->warp->handle || 845 if (!dev_priv->warp->handle ||
868 !dev_priv->primary->handle || 846 !dev_priv->primary->handle ||
@@ -885,23 +863,20 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
885 return ret; 863 return ret;
886 } 864 }
887 865
888 dev_priv->prim.status = (u32 *)dev_priv->status->handle; 866 dev_priv->prim.status = (u32 *) dev_priv->status->handle;
889 867
890 mga_do_wait_for_idle( dev_priv ); 868 mga_do_wait_for_idle(dev_priv);
891 869
892 /* Init the primary DMA registers. 870 /* Init the primary DMA registers.
893 */ 871 */
894 MGA_WRITE( MGA_PRIMADDRESS, 872 MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
895 dev_priv->primary->offset | MGA_DMA_GENERAL );
896#if 0 873#if 0
897 MGA_WRITE( MGA_PRIMPTR, 874 MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
898 virt_to_bus((void *)dev_priv->prim.status) | 875 MGA_PRIMPTREN1); /* DWGSYNC */
899 MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
900 MGA_PRIMPTREN1 ); /* DWGSYNC */
901#endif 876#endif
902 877
903 dev_priv->prim.start = (u8 *)dev_priv->primary->handle; 878 dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
904 dev_priv->prim.end = ((u8 *)dev_priv->primary->handle 879 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
905 + dev_priv->primary->size); 880 + dev_priv->primary->size);
906 dev_priv->prim.size = dev_priv->primary->size; 881 dev_priv->prim.size = dev_priv->primary->size;
907 882
@@ -929,7 +904,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
929 return 0; 904 return 0;
930} 905}
931 906
932static int mga_do_cleanup_dma( drm_device_t *dev ) 907static int mga_do_cleanup_dma(drm_device_t * dev)
933{ 908{
934 int err = 0; 909 int err = 0;
935 DRM_DEBUG("\n"); 910 DRM_DEBUG("\n");
@@ -938,16 +913,17 @@ static int mga_do_cleanup_dma( drm_device_t *dev )
938 * may not have been called from userspace and after dev_private 913 * may not have been called from userspace and after dev_private
939 * is freed, it's too late. 914 * is freed, it's too late.
940 */ 915 */
941 if ( dev->irq_enabled ) drm_irq_uninstall(dev); 916 if (dev->irq_enabled)
917 drm_irq_uninstall(dev);
942 918
943 if ( dev->dev_private ) { 919 if (dev->dev_private) {
944 drm_mga_private_t *dev_priv = dev->dev_private; 920 drm_mga_private_t *dev_priv = dev->dev_private;
945 921
946 if ((dev_priv->warp != NULL) 922 if ((dev_priv->warp != NULL)
947 && (dev_priv->warp->type != _DRM_CONSISTENT)) 923 && (dev_priv->warp->type != _DRM_CONSISTENT))
948 drm_core_ioremapfree(dev_priv->warp, dev); 924 drm_core_ioremapfree(dev_priv->warp, dev);
949 925
950 if ((dev_priv->primary != NULL) 926 if ((dev_priv->primary != NULL)
951 && (dev_priv->primary->type != _DRM_CONSISTENT)) 927 && (dev_priv->primary->type != _DRM_CONSISTENT))
952 drm_core_ioremapfree(dev_priv->primary, dev); 928 drm_core_ioremapfree(dev_priv->primary, dev);
953 929
@@ -960,7 +936,8 @@ static int mga_do_cleanup_dma( drm_device_t *dev )
960 dev_priv->agp_textures = NULL; 936 dev_priv->agp_textures = NULL;
961 drm_unbind_agp(dev_priv->agp_mem); 937 drm_unbind_agp(dev_priv->agp_mem);
962 938
963 drm_free_agp(dev_priv->agp_mem, dev_priv->agp_pages); 939 drm_free_agp(dev_priv->agp_mem,
940 dev_priv->agp_pages);
964 dev_priv->agp_pages = 0; 941 dev_priv->agp_pages = 0;
965 dev_priv->agp_mem = NULL; 942 dev_priv->agp_mem = NULL;
966 } 943 }
@@ -982,7 +959,8 @@ static int mga_do_cleanup_dma( drm_device_t *dev )
982 959
983 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim)); 960 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
984 dev_priv->warp_pipe = 0; 961 dev_priv->warp_pipe = 0;
985 memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); 962 memset(dev_priv->warp_pipe_phys, 0,
963 sizeof(dev_priv->warp_pipe_phys));
986 964
987 if (dev_priv->head != NULL) { 965 if (dev_priv->head != NULL) {
988 mga_freelist_cleanup(dev); 966 mga_freelist_cleanup(dev);
@@ -992,103 +970,102 @@ static int mga_do_cleanup_dma( drm_device_t *dev )
992 return err; 970 return err;
993} 971}
994 972
995int mga_dma_init( DRM_IOCTL_ARGS ) 973int mga_dma_init(DRM_IOCTL_ARGS)
996{ 974{
997 DRM_DEVICE; 975 DRM_DEVICE;
998 drm_mga_init_t init; 976 drm_mga_init_t init;
999 int err; 977 int err;
1000 978
1001 LOCK_TEST_WITH_RETURN( dev, filp ); 979 LOCK_TEST_WITH_RETURN(dev, filp);
1002 980
1003 DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data, 981 DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data,
1004 sizeof(init)); 982 sizeof(init));
1005 983
1006 switch ( init.func ) { 984 switch (init.func) {
1007 case MGA_INIT_DMA: 985 case MGA_INIT_DMA:
1008 err = mga_do_init_dma(dev, &init); 986 err = mga_do_init_dma(dev, &init);
1009 if (err) { 987 if (err) {
1010 (void) mga_do_cleanup_dma(dev); 988 (void)mga_do_cleanup_dma(dev);
1011 } 989 }
1012 return err; 990 return err;
1013 case MGA_CLEANUP_DMA: 991 case MGA_CLEANUP_DMA:
1014 return mga_do_cleanup_dma( dev ); 992 return mga_do_cleanup_dma(dev);
1015 } 993 }
1016 994
1017 return DRM_ERR(EINVAL); 995 return DRM_ERR(EINVAL);
1018} 996}
1019 997
1020
1021/* ================================================================ 998/* ================================================================
1022 * Primary DMA stream management 999 * Primary DMA stream management
1023 */ 1000 */
1024 1001
1025int mga_dma_flush( DRM_IOCTL_ARGS ) 1002int mga_dma_flush(DRM_IOCTL_ARGS)
1026{ 1003{
1027 DRM_DEVICE; 1004 DRM_DEVICE;
1028 drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; 1005 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1029 drm_lock_t lock; 1006 drm_lock_t lock;
1030 1007
1031 LOCK_TEST_WITH_RETURN( dev, filp ); 1008 LOCK_TEST_WITH_RETURN(dev, filp);
1032 1009
1033 DRM_COPY_FROM_USER_IOCTL( lock, (drm_lock_t __user *)data, sizeof(lock) ); 1010 DRM_COPY_FROM_USER_IOCTL(lock, (drm_lock_t __user *) data,
1011 sizeof(lock));
1034 1012
1035 DRM_DEBUG( "%s%s%s\n", 1013 DRM_DEBUG("%s%s%s\n",
1036 (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "", 1014 (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1037 (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", 1015 (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1038 (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "" ); 1016 (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1039 1017
1040 WRAP_WAIT_WITH_RETURN( dev_priv ); 1018 WRAP_WAIT_WITH_RETURN(dev_priv);
1041 1019
1042 if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) { 1020 if (lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
1043 mga_do_dma_flush( dev_priv ); 1021 mga_do_dma_flush(dev_priv);
1044 } 1022 }
1045 1023
1046 if ( lock.flags & _DRM_LOCK_QUIESCENT ) { 1024 if (lock.flags & _DRM_LOCK_QUIESCENT) {
1047#if MGA_DMA_DEBUG 1025#if MGA_DMA_DEBUG
1048 int ret = mga_do_wait_for_idle( dev_priv ); 1026 int ret = mga_do_wait_for_idle(dev_priv);
1049 if ( ret < 0 ) 1027 if (ret < 0)
1050 DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); 1028 DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
1051 return ret; 1029 return ret;
1052#else 1030#else
1053 return mga_do_wait_for_idle( dev_priv ); 1031 return mga_do_wait_for_idle(dev_priv);
1054#endif 1032#endif
1055 } else { 1033 } else {
1056 return 0; 1034 return 0;
1057 } 1035 }
1058} 1036}
1059 1037
1060int mga_dma_reset( DRM_IOCTL_ARGS ) 1038int mga_dma_reset(DRM_IOCTL_ARGS)
1061{ 1039{
1062 DRM_DEVICE; 1040 DRM_DEVICE;
1063 drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; 1041 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1064 1042
1065 LOCK_TEST_WITH_RETURN( dev, filp ); 1043 LOCK_TEST_WITH_RETURN(dev, filp);
1066 1044
1067 return mga_do_dma_reset( dev_priv ); 1045 return mga_do_dma_reset(dev_priv);
1068} 1046}
1069 1047
1070
1071/* ================================================================ 1048/* ================================================================
1072 * DMA buffer management 1049 * DMA buffer management
1073 */ 1050 */
1074 1051
1075static int mga_dma_get_buffers( DRMFILE filp, 1052static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
1076 drm_device_t *dev, drm_dma_t *d )
1077{ 1053{
1078 drm_buf_t *buf; 1054 drm_buf_t *buf;
1079 int i; 1055 int i;
1080 1056
1081 for ( i = d->granted_count ; i < d->request_count ; i++ ) { 1057 for (i = d->granted_count; i < d->request_count; i++) {
1082 buf = mga_freelist_get( dev ); 1058 buf = mga_freelist_get(dev);
1083 if ( !buf ) return DRM_ERR(EAGAIN); 1059 if (!buf)
1060 return DRM_ERR(EAGAIN);
1084 1061
1085 buf->filp = filp; 1062 buf->filp = filp;
1086 1063
1087 if ( DRM_COPY_TO_USER( &d->request_indices[i], 1064 if (DRM_COPY_TO_USER(&d->request_indices[i],
1088 &buf->idx, sizeof(buf->idx) ) ) 1065 &buf->idx, sizeof(buf->idx)))
1089 return DRM_ERR(EFAULT); 1066 return DRM_ERR(EFAULT);
1090 if ( DRM_COPY_TO_USER( &d->request_sizes[i], 1067 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1091 &buf->total, sizeof(buf->total) ) ) 1068 &buf->total, sizeof(buf->total)))
1092 return DRM_ERR(EFAULT); 1069 return DRM_ERR(EFAULT);
1093 1070
1094 d->granted_count++; 1071 d->granted_count++;
@@ -1096,44 +1073,44 @@ static int mga_dma_get_buffers( DRMFILE filp,
1096 return 0; 1073 return 0;
1097} 1074}
1098 1075
1099int mga_dma_buffers( DRM_IOCTL_ARGS ) 1076int mga_dma_buffers(DRM_IOCTL_ARGS)
1100{ 1077{
1101 DRM_DEVICE; 1078 DRM_DEVICE;
1102 drm_device_dma_t *dma = dev->dma; 1079 drm_device_dma_t *dma = dev->dma;
1103 drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; 1080 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1104 drm_dma_t __user *argp = (void __user *)data; 1081 drm_dma_t __user *argp = (void __user *)data;
1105 drm_dma_t d; 1082 drm_dma_t d;
1106 int ret = 0; 1083 int ret = 0;
1107 1084
1108 LOCK_TEST_WITH_RETURN( dev, filp ); 1085 LOCK_TEST_WITH_RETURN(dev, filp);
1109 1086
1110 DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); 1087 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
1111 1088
1112 /* Please don't send us buffers. 1089 /* Please don't send us buffers.
1113 */ 1090 */
1114 if ( d.send_count != 0 ) { 1091 if (d.send_count != 0) {
1115 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", 1092 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1116 DRM_CURRENTPID, d.send_count ); 1093 DRM_CURRENTPID, d.send_count);
1117 return DRM_ERR(EINVAL); 1094 return DRM_ERR(EINVAL);
1118 } 1095 }
1119 1096
1120 /* We'll send you buffers. 1097 /* We'll send you buffers.
1121 */ 1098 */
1122 if ( d.request_count < 0 || d.request_count > dma->buf_count ) { 1099 if (d.request_count < 0 || d.request_count > dma->buf_count) {
1123 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", 1100 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1124 DRM_CURRENTPID, d.request_count, dma->buf_count ); 1101 DRM_CURRENTPID, d.request_count, dma->buf_count);
1125 return DRM_ERR(EINVAL); 1102 return DRM_ERR(EINVAL);
1126 } 1103 }
1127 1104
1128 WRAP_TEST_WITH_RETURN( dev_priv ); 1105 WRAP_TEST_WITH_RETURN(dev_priv);
1129 1106
1130 d.granted_count = 0; 1107 d.granted_count = 0;
1131 1108
1132 if ( d.request_count ) { 1109 if (d.request_count) {
1133 ret = mga_dma_get_buffers( filp, dev, &d ); 1110 ret = mga_dma_get_buffers(filp, dev, &d);
1134 } 1111 }
1135 1112
1136 DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); 1113 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
1137 1114
1138 return ret; 1115 return ret;
1139} 1116}
@@ -1154,11 +1131,11 @@ int mga_driver_postcleanup(drm_device_t * dev)
1154 */ 1131 */
1155void mga_driver_pretakedown(drm_device_t * dev) 1132void mga_driver_pretakedown(drm_device_t * dev)
1156{ 1133{
1157 mga_do_cleanup_dma( dev ); 1134 mga_do_cleanup_dma(dev);
1158} 1135}
1159 1136
1160int mga_driver_dma_quiescent(drm_device_t *dev) 1137int mga_driver_dma_quiescent(drm_device_t * dev)
1161{ 1138{
1162 drm_mga_private_t *dev_priv = dev->dev_private; 1139 drm_mga_private_t *dev_priv = dev->dev_private;
1163 return mga_do_wait_for_idle( dev_priv ); 1140 return mga_do_wait_for_idle(dev_priv);
1164} 1141}