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Diffstat (limited to 'drivers/char/drm/mga_dma.c')
-rw-r--r--drivers/char/drm/mga_dma.c511
1 files changed, 244 insertions, 267 deletions
diff --git a/drivers/char/drm/mga_dma.c b/drivers/char/drm/mga_dma.c
index fc7d4a594bca..cfbe35d5d862 100644
--- a/drivers/char/drm/mga_dma.c
+++ b/drivers/char/drm/mga_dma.c
@@ -28,7 +28,7 @@
28/** 28/**
29 * \file mga_dma.c 29 * \file mga_dma.c
30 * DMA support for MGA G200 / G400. 30 * DMA support for MGA G200 / G400.
31 * 31 *
32 * \author Rickard E. (Rik) Faith <faith@valinux.com> 32 * \author Rickard E. (Rik) Faith <faith@valinux.com>
33 * \author Jeff Hartmann <jhartmann@valinux.com> 33 * \author Jeff Hartmann <jhartmann@valinux.com>
34 * \author Keith Whitwell <keith@tungstengraphics.com> 34 * \author Keith Whitwell <keith@tungstengraphics.com>
@@ -44,40 +44,40 @@
44#define MGA_DEFAULT_USEC_TIMEOUT 10000 44#define MGA_DEFAULT_USEC_TIMEOUT 10000
45#define MGA_FREELIST_DEBUG 0 45#define MGA_FREELIST_DEBUG 0
46 46
47static int mga_do_cleanup_dma( drm_device_t *dev ); 47static int mga_do_cleanup_dma(drm_device_t * dev);
48 48
49/* ================================================================ 49/* ================================================================
50 * Engine control 50 * Engine control
51 */ 51 */
52 52
53int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ) 53int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
54{ 54{
55 u32 status = 0; 55 u32 status = 0;
56 int i; 56 int i;
57 DRM_DEBUG( "\n" ); 57 DRM_DEBUG("\n");
58 58
59 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 59 for (i = 0; i < dev_priv->usec_timeout; i++) {
60 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; 60 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
61 if ( status == MGA_ENDPRDMASTS ) { 61 if (status == MGA_ENDPRDMASTS) {
62 MGA_WRITE8( MGA_CRTC_INDEX, 0 ); 62 MGA_WRITE8(MGA_CRTC_INDEX, 0);
63 return 0; 63 return 0;
64 } 64 }
65 DRM_UDELAY( 1 ); 65 DRM_UDELAY(1);
66 } 66 }
67 67
68#if MGA_DMA_DEBUG 68#if MGA_DMA_DEBUG
69 DRM_ERROR( "failed!\n" ); 69 DRM_ERROR("failed!\n");
70 DRM_INFO( " status=0x%08x\n", status ); 70 DRM_INFO(" status=0x%08x\n", status);
71#endif 71#endif
72 return DRM_ERR(EBUSY); 72 return DRM_ERR(EBUSY);
73} 73}
74 74
75static int mga_do_dma_reset( drm_mga_private_t *dev_priv ) 75static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
76{ 76{
77 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 77 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
78 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 78 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
79 79
80 DRM_DEBUG( "\n" ); 80 DRM_DEBUG("\n");
81 81
82 /* The primary DMA stream should look like new right about now. 82 /* The primary DMA stream should look like new right about now.
83 */ 83 */
@@ -100,24 +100,25 @@ static int mga_do_dma_reset( drm_mga_private_t *dev_priv )
100 * Primary DMA stream 100 * Primary DMA stream
101 */ 101 */
102 102
103void mga_do_dma_flush( drm_mga_private_t *dev_priv ) 103void mga_do_dma_flush(drm_mga_private_t * dev_priv)
104{ 104{
105 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 105 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
106 u32 head, tail; 106 u32 head, tail;
107 u32 status = 0; 107 u32 status = 0;
108 int i; 108 int i;
109 DMA_LOCALS; 109 DMA_LOCALS;
110 DRM_DEBUG( "\n" ); 110 DRM_DEBUG("\n");
111 111
112 /* We need to wait so that we can do an safe flush */ 112 /* We need to wait so that we can do an safe flush */
113 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 113 for (i = 0; i < dev_priv->usec_timeout; i++) {
114 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; 114 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
115 if ( status == MGA_ENDPRDMASTS ) break; 115 if (status == MGA_ENDPRDMASTS)
116 DRM_UDELAY( 1 ); 116 break;
117 DRM_UDELAY(1);
117 } 118 }
118 119
119 if ( primary->tail == primary->last_flush ) { 120 if (primary->tail == primary->last_flush) {
120 DRM_DEBUG( " bailing out...\n" ); 121 DRM_DEBUG(" bailing out...\n");
121 return; 122 return;
122 } 123 }
123 124
@@ -127,48 +128,46 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
127 * actually (partially?) reads the first of these commands. 128 * actually (partially?) reads the first of these commands.
128 * See page 4-16 in the G400 manual, middle of the page or so. 129 * See page 4-16 in the G400 manual, middle of the page or so.
129 */ 130 */
130 BEGIN_DMA( 1 ); 131 BEGIN_DMA(1);
131 132
132 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 133 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
133 MGA_DMAPAD, 0x00000000, 134 MGA_DMAPAD, 0x00000000,
134 MGA_DMAPAD, 0x00000000, 135 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
135 MGA_DMAPAD, 0x00000000 );
136 136
137 ADVANCE_DMA(); 137 ADVANCE_DMA();
138 138
139 primary->last_flush = primary->tail; 139 primary->last_flush = primary->tail;
140 140
141 head = MGA_READ( MGA_PRIMADDRESS ); 141 head = MGA_READ(MGA_PRIMADDRESS);
142 142
143 if ( head <= tail ) { 143 if (head <= tail) {
144 primary->space = primary->size - primary->tail; 144 primary->space = primary->size - primary->tail;
145 } else { 145 } else {
146 primary->space = head - tail; 146 primary->space = head - tail;
147 } 147 }
148 148
149 DRM_DEBUG( " head = 0x%06lx\n", head - dev_priv->primary->offset ); 149 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
150 DRM_DEBUG( " tail = 0x%06lx\n", tail - dev_priv->primary->offset ); 150 DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset);
151 DRM_DEBUG( " space = 0x%06x\n", primary->space ); 151 DRM_DEBUG(" space = 0x%06x\n", primary->space);
152 152
153 mga_flush_write_combine(); 153 mga_flush_write_combine();
154 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); 154 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
155 155
156 DRM_DEBUG( "done.\n" ); 156 DRM_DEBUG("done.\n");
157} 157}
158 158
159void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ) 159void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
160{ 160{
161 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 161 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
162 u32 head, tail; 162 u32 head, tail;
163 DMA_LOCALS; 163 DMA_LOCALS;
164 DRM_DEBUG( "\n" ); 164 DRM_DEBUG("\n");
165 165
166 BEGIN_DMA_WRAP(); 166 BEGIN_DMA_WRAP();
167 167
168 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 168 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
169 MGA_DMAPAD, 0x00000000, 169 MGA_DMAPAD, 0x00000000,
170 MGA_DMAPAD, 0x00000000, 170 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
171 MGA_DMAPAD, 0x00000000 );
172 171
173 ADVANCE_DMA(); 172 ADVANCE_DMA();
174 173
@@ -178,45 +177,43 @@ void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
178 primary->last_flush = 0; 177 primary->last_flush = 0;
179 primary->last_wrap++; 178 primary->last_wrap++;
180 179
181 head = MGA_READ( MGA_PRIMADDRESS ); 180 head = MGA_READ(MGA_PRIMADDRESS);
182 181
183 if ( head == dev_priv->primary->offset ) { 182 if (head == dev_priv->primary->offset) {
184 primary->space = primary->size; 183 primary->space = primary->size;
185 } else { 184 } else {
186 primary->space = head - dev_priv->primary->offset; 185 primary->space = head - dev_priv->primary->offset;
187 } 186 }
188 187
189 DRM_DEBUG( " head = 0x%06lx\n", 188 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
190 head - dev_priv->primary->offset ); 189 DRM_DEBUG(" tail = 0x%06x\n", primary->tail);
191 DRM_DEBUG( " tail = 0x%06x\n", primary->tail ); 190 DRM_DEBUG(" wrap = %d\n", primary->last_wrap);
192 DRM_DEBUG( " wrap = %d\n", primary->last_wrap ); 191 DRM_DEBUG(" space = 0x%06x\n", primary->space);
193 DRM_DEBUG( " space = 0x%06x\n", primary->space );
194 192
195 mga_flush_write_combine(); 193 mga_flush_write_combine();
196 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); 194 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
197 195
198 set_bit( 0, &primary->wrapped ); 196 set_bit(0, &primary->wrapped);
199 DRM_DEBUG( "done.\n" ); 197 DRM_DEBUG("done.\n");
200} 198}
201 199
202void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ) 200void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
203{ 201{
204 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 202 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
205 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 203 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
206 u32 head = dev_priv->primary->offset; 204 u32 head = dev_priv->primary->offset;
207 DRM_DEBUG( "\n" ); 205 DRM_DEBUG("\n");
208 206
209 sarea_priv->last_wrap++; 207 sarea_priv->last_wrap++;
210 DRM_DEBUG( " wrap = %d\n", sarea_priv->last_wrap ); 208 DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap);
211 209
212 mga_flush_write_combine(); 210 mga_flush_write_combine();
213 MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL ); 211 MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
214 212
215 clear_bit( 0, &primary->wrapped ); 213 clear_bit(0, &primary->wrapped);
216 DRM_DEBUG( "done.\n" ); 214 DRM_DEBUG("done.\n");
217} 215}
218 216
219
220/* ================================================================ 217/* ================================================================
221 * Freelist management 218 * Freelist management
222 */ 219 */
@@ -225,63 +222,61 @@ void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
225#define MGA_BUFFER_FREE 0 222#define MGA_BUFFER_FREE 0
226 223
227#if MGA_FREELIST_DEBUG 224#if MGA_FREELIST_DEBUG
228static void mga_freelist_print( drm_device_t *dev ) 225static void mga_freelist_print(drm_device_t * dev)
229{ 226{
230 drm_mga_private_t *dev_priv = dev->dev_private; 227 drm_mga_private_t *dev_priv = dev->dev_private;
231 drm_mga_freelist_t *entry; 228 drm_mga_freelist_t *entry;
232 229
233 DRM_INFO( "\n" ); 230 DRM_INFO("\n");
234 DRM_INFO( "current dispatch: last=0x%x done=0x%x\n", 231 DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
235 dev_priv->sarea_priv->last_dispatch, 232 dev_priv->sarea_priv->last_dispatch,
236 (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) - 233 (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
237 dev_priv->primary->offset) ); 234 dev_priv->primary->offset));
238 DRM_INFO( "current freelist:\n" ); 235 DRM_INFO("current freelist:\n");
239 236
240 for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) { 237 for (entry = dev_priv->head->next; entry; entry = entry->next) {
241 DRM_INFO( " %p idx=%2d age=0x%x 0x%06lx\n", 238 DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n",
242 entry, entry->buf->idx, entry->age.head, 239 entry, entry->buf->idx, entry->age.head,
243 entry->age.head - dev_priv->primary->offset ); 240 entry->age.head - dev_priv->primary->offset);
244 } 241 }
245 DRM_INFO( "\n" ); 242 DRM_INFO("\n");
246} 243}
247#endif 244#endif
248 245
249static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv ) 246static int mga_freelist_init(drm_device_t * dev, drm_mga_private_t * dev_priv)
250{ 247{
251 drm_device_dma_t *dma = dev->dma; 248 drm_device_dma_t *dma = dev->dma;
252 drm_buf_t *buf; 249 drm_buf_t *buf;
253 drm_mga_buf_priv_t *buf_priv; 250 drm_mga_buf_priv_t *buf_priv;
254 drm_mga_freelist_t *entry; 251 drm_mga_freelist_t *entry;
255 int i; 252 int i;
256 DRM_DEBUG( "count=%d\n", dma->buf_count ); 253 DRM_DEBUG("count=%d\n", dma->buf_count);
257 254
258 dev_priv->head = drm_alloc( sizeof(drm_mga_freelist_t), 255 dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
259 DRM_MEM_DRIVER ); 256 if (dev_priv->head == NULL)
260 if ( dev_priv->head == NULL )
261 return DRM_ERR(ENOMEM); 257 return DRM_ERR(ENOMEM);
262 258
263 memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) ); 259 memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
264 SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 ); 260 SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
265 261
266 for ( i = 0 ; i < dma->buf_count ; i++ ) { 262 for (i = 0; i < dma->buf_count; i++) {
267 buf = dma->buflist[i]; 263 buf = dma->buflist[i];
268 buf_priv = buf->dev_private; 264 buf_priv = buf->dev_private;
269 265
270 entry = drm_alloc( sizeof(drm_mga_freelist_t), 266 entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
271 DRM_MEM_DRIVER ); 267 if (entry == NULL)
272 if ( entry == NULL )
273 return DRM_ERR(ENOMEM); 268 return DRM_ERR(ENOMEM);
274 269
275 memset( entry, 0, sizeof(drm_mga_freelist_t) ); 270 memset(entry, 0, sizeof(drm_mga_freelist_t));
276 271
277 entry->next = dev_priv->head->next; 272 entry->next = dev_priv->head->next;
278 entry->prev = dev_priv->head; 273 entry->prev = dev_priv->head;
279 SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); 274 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
280 entry->buf = buf; 275 entry->buf = buf;
281 276
282 if ( dev_priv->head->next != NULL ) 277 if (dev_priv->head->next != NULL)
283 dev_priv->head->next->prev = entry; 278 dev_priv->head->next->prev = entry;
284 if ( entry->next == NULL ) 279 if (entry->next == NULL)
285 dev_priv->tail = entry; 280 dev_priv->tail = entry;
286 281
287 buf_priv->list_entry = entry; 282 buf_priv->list_entry = entry;
@@ -294,17 +289,17 @@ static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv )
294 return 0; 289 return 0;
295} 290}
296 291
297static void mga_freelist_cleanup( drm_device_t *dev ) 292static void mga_freelist_cleanup(drm_device_t * dev)
298{ 293{
299 drm_mga_private_t *dev_priv = dev->dev_private; 294 drm_mga_private_t *dev_priv = dev->dev_private;
300 drm_mga_freelist_t *entry; 295 drm_mga_freelist_t *entry;
301 drm_mga_freelist_t *next; 296 drm_mga_freelist_t *next;
302 DRM_DEBUG( "\n" ); 297 DRM_DEBUG("\n");
303 298
304 entry = dev_priv->head; 299 entry = dev_priv->head;
305 while ( entry ) { 300 while (entry) {
306 next = entry->next; 301 next = entry->next;
307 drm_free( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER ); 302 drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
308 entry = next; 303 entry = next;
309 } 304 }
310 305
@@ -314,71 +309,69 @@ static void mga_freelist_cleanup( drm_device_t *dev )
314#if 0 309#if 0
315/* FIXME: Still needed? 310/* FIXME: Still needed?
316 */ 311 */
317static void mga_freelist_reset( drm_device_t *dev ) 312static void mga_freelist_reset(drm_device_t * dev)
318{ 313{
319 drm_device_dma_t *dma = dev->dma; 314 drm_device_dma_t *dma = dev->dma;
320 drm_buf_t *buf; 315 drm_buf_t *buf;
321 drm_mga_buf_priv_t *buf_priv; 316 drm_mga_buf_priv_t *buf_priv;
322 int i; 317 int i;
323 318
324 for ( i = 0 ; i < dma->buf_count ; i++ ) { 319 for (i = 0; i < dma->buf_count; i++) {
325 buf = dma->buflist[i]; 320 buf = dma->buflist[i];
326 buf_priv = buf->dev_private; 321 buf_priv = buf->dev_private;
327 SET_AGE( &buf_priv->list_entry->age, 322 SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
328 MGA_BUFFER_FREE, 0 );
329 } 323 }
330} 324}
331#endif 325#endif
332 326
333static drm_buf_t *mga_freelist_get( drm_device_t *dev ) 327static drm_buf_t *mga_freelist_get(drm_device_t * dev)
334{ 328{
335 drm_mga_private_t *dev_priv = dev->dev_private; 329 drm_mga_private_t *dev_priv = dev->dev_private;
336 drm_mga_freelist_t *next; 330 drm_mga_freelist_t *next;
337 drm_mga_freelist_t *prev; 331 drm_mga_freelist_t *prev;
338 drm_mga_freelist_t *tail = dev_priv->tail; 332 drm_mga_freelist_t *tail = dev_priv->tail;
339 u32 head, wrap; 333 u32 head, wrap;
340 DRM_DEBUG( "\n" ); 334 DRM_DEBUG("\n");
341 335
342 head = MGA_READ( MGA_PRIMADDRESS ); 336 head = MGA_READ(MGA_PRIMADDRESS);
343 wrap = dev_priv->sarea_priv->last_wrap; 337 wrap = dev_priv->sarea_priv->last_wrap;
344 338
345 DRM_DEBUG( " tail=0x%06lx %d\n", 339 DRM_DEBUG(" tail=0x%06lx %d\n",
346 tail->age.head ? 340 tail->age.head ?
347 tail->age.head - dev_priv->primary->offset : 0, 341 tail->age.head - dev_priv->primary->offset : 0,
348 tail->age.wrap ); 342 tail->age.wrap);
349 DRM_DEBUG( " head=0x%06lx %d\n", 343 DRM_DEBUG(" head=0x%06lx %d\n",
350 head - dev_priv->primary->offset, wrap ); 344 head - dev_priv->primary->offset, wrap);
351 345
352 if ( TEST_AGE( &tail->age, head, wrap ) ) { 346 if (TEST_AGE(&tail->age, head, wrap)) {
353 prev = dev_priv->tail->prev; 347 prev = dev_priv->tail->prev;
354 next = dev_priv->tail; 348 next = dev_priv->tail;
355 prev->next = NULL; 349 prev->next = NULL;
356 next->prev = next->next = NULL; 350 next->prev = next->next = NULL;
357 dev_priv->tail = prev; 351 dev_priv->tail = prev;
358 SET_AGE( &next->age, MGA_BUFFER_USED, 0 ); 352 SET_AGE(&next->age, MGA_BUFFER_USED, 0);
359 return next->buf; 353 return next->buf;
360 } 354 }
361 355
362 DRM_DEBUG( "returning NULL!\n" ); 356 DRM_DEBUG("returning NULL!\n");
363 return NULL; 357 return NULL;
364} 358}
365 359
366int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ) 360int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf)
367{ 361{
368 drm_mga_private_t *dev_priv = dev->dev_private; 362 drm_mga_private_t *dev_priv = dev->dev_private;
369 drm_mga_buf_priv_t *buf_priv = buf->dev_private; 363 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
370 drm_mga_freelist_t *head, *entry, *prev; 364 drm_mga_freelist_t *head, *entry, *prev;
371 365
372 DRM_DEBUG( "age=0x%06lx wrap=%d\n", 366 DRM_DEBUG("age=0x%06lx wrap=%d\n",
373 buf_priv->list_entry->age.head - 367 buf_priv->list_entry->age.head -
374 dev_priv->primary->offset, 368 dev_priv->primary->offset, buf_priv->list_entry->age.wrap);
375 buf_priv->list_entry->age.wrap );
376 369
377 entry = buf_priv->list_entry; 370 entry = buf_priv->list_entry;
378 head = dev_priv->head; 371 head = dev_priv->head;
379 372
380 if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) { 373 if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
381 SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); 374 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
382 prev = dev_priv->tail; 375 prev = dev_priv->tail;
383 prev->next = entry; 376 prev->next = entry;
384 entry->prev = prev; 377 entry->prev = prev;
@@ -394,15 +387,13 @@ int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf )
394 return 0; 387 return 0;
395} 388}
396 389
397
398/* ================================================================ 390/* ================================================================
399 * DMA initialization, cleanup 391 * DMA initialization, cleanup
400 */ 392 */
401 393
402 394int mga_driver_preinit(drm_device_t * dev, unsigned long flags)
403int mga_driver_preinit(drm_device_t *dev, unsigned long flags)
404{ 395{
405 drm_mga_private_t * dev_priv; 396 drm_mga_private_t *dev_priv;
406 397
407 dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); 398 dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
408 if (!dev_priv) 399 if (!dev_priv)
@@ -420,7 +411,7 @@ int mga_driver_preinit(drm_device_t *dev, unsigned long flags)
420#if __OS_HAS_AGP 411#if __OS_HAS_AGP
421/** 412/**
422 * Bootstrap the driver for AGP DMA. 413 * Bootstrap the driver for AGP DMA.
423 * 414 *
424 * \todo 415 * \todo
425 * Investigate whether there is any benifit to storing the WARP microcode in 416 * Investigate whether there is any benifit to storing the WARP microcode in
426 * AGP memory. If not, the microcode may as well always be put in PCI 417 * AGP memory. If not, the microcode may as well always be put in PCI
@@ -436,18 +427,18 @@ int mga_driver_preinit(drm_device_t *dev, unsigned long flags)
436static int mga_do_agp_dma_bootstrap(drm_device_t * dev, 427static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
437 drm_mga_dma_bootstrap_t * dma_bs) 428 drm_mga_dma_bootstrap_t * dma_bs)
438{ 429{
439 drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private; 430 drm_mga_private_t *const dev_priv =
431 (drm_mga_private_t *) dev->dev_private;
440 const unsigned int warp_size = mga_warp_microcode_size(dev_priv); 432 const unsigned int warp_size = mga_warp_microcode_size(dev_priv);
441 int err; 433 int err;
442 unsigned offset; 434 unsigned offset;
443 const unsigned secondary_size = dma_bs->secondary_bin_count 435 const unsigned secondary_size = dma_bs->secondary_bin_count
444 * dma_bs->secondary_bin_size; 436 * dma_bs->secondary_bin_size;
445 const unsigned agp_size = (dma_bs->agp_size << 20); 437 const unsigned agp_size = (dma_bs->agp_size << 20);
446 drm_buf_desc_t req; 438 drm_buf_desc_t req;
447 drm_agp_mode_t mode; 439 drm_agp_mode_t mode;
448 drm_agp_info_t info; 440 drm_agp_info_t info;
449 441
450
451 /* Acquire AGP. */ 442 /* Acquire AGP. */
452 err = drm_agp_acquire(dev); 443 err = drm_agp_acquire(dev);
453 if (err) { 444 if (err) {
@@ -468,7 +459,6 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
468 return err; 459 return err;
469 } 460 }
470 461
471
472 /* In addition to the usual AGP mode configuration, the G200 AGP cards 462 /* In addition to the usual AGP mode configuration, the G200 AGP cards
473 * need to have the AGP mode "manually" set. 463 * need to have the AGP mode "manually" set.
474 */ 464 */
@@ -476,68 +466,66 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
476 if (dev_priv->chipset == MGA_CARD_TYPE_G200) { 466 if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
477 if (mode.mode & 0x02) { 467 if (mode.mode & 0x02) {
478 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE); 468 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
479 } 469 } else {
480 else {
481 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE); 470 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
482 } 471 }
483 } 472 }
484 473
485
486 /* Allocate and bind AGP memory. */ 474 /* Allocate and bind AGP memory. */
487 dev_priv->agp_pages = agp_size / PAGE_SIZE; 475 dev_priv->agp_pages = agp_size / PAGE_SIZE;
488 dev_priv->agp_mem = drm_alloc_agp( dev, dev_priv->agp_pages, 0 ); 476 dev_priv->agp_mem = drm_alloc_agp(dev, dev_priv->agp_pages, 0);
489 if (dev_priv->agp_mem == NULL) { 477 if (dev_priv->agp_mem == NULL) {
490 dev_priv->agp_pages = 0; 478 dev_priv->agp_pages = 0;
491 DRM_ERROR("Unable to allocate %uMB AGP memory\n", 479 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
492 dma_bs->agp_size); 480 dma_bs->agp_size);
493 return DRM_ERR(ENOMEM); 481 return DRM_ERR(ENOMEM);
494 } 482 }
495 483
496 err = drm_bind_agp( dev_priv->agp_mem, 0 ); 484 err = drm_bind_agp(dev_priv->agp_mem, 0);
497 if (err) { 485 if (err) {
498 DRM_ERROR("Unable to bind AGP memory\n"); 486 DRM_ERROR("Unable to bind AGP memory\n");
499 return err; 487 return err;
500 } 488 }
501 489
502 offset = 0; 490 offset = 0;
503 err = drm_addmap( dev, offset, warp_size, 491 err = drm_addmap(dev, offset, warp_size,
504 _DRM_AGP, _DRM_READ_ONLY, & dev_priv->warp ); 492 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
505 if (err) { 493 if (err) {
506 DRM_ERROR("Unable to map WARP microcode\n"); 494 DRM_ERROR("Unable to map WARP microcode\n");
507 return err; 495 return err;
508 } 496 }
509 497
510 offset += warp_size; 498 offset += warp_size;
511 err = drm_addmap( dev, offset, dma_bs->primary_size, 499 err = drm_addmap(dev, offset, dma_bs->primary_size,
512 _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary ); 500 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary);
513 if (err) { 501 if (err) {
514 DRM_ERROR("Unable to map primary DMA region\n"); 502 DRM_ERROR("Unable to map primary DMA region\n");
515 return err; 503 return err;
516 } 504 }
517 505
518 offset += dma_bs->primary_size; 506 offset += dma_bs->primary_size;
519 err = drm_addmap( dev, offset, secondary_size, 507 err = drm_addmap(dev, offset, secondary_size,
520 _DRM_AGP, 0, & dev->agp_buffer_map ); 508 _DRM_AGP, 0, &dev->agp_buffer_map);
521 if (err) { 509 if (err) {
522 DRM_ERROR("Unable to map secondary DMA region\n"); 510 DRM_ERROR("Unable to map secondary DMA region\n");
523 return err; 511 return err;
524 } 512 }
525 513
526 (void) memset( &req, 0, sizeof(req) ); 514 (void)memset(&req, 0, sizeof(req));
527 req.count = dma_bs->secondary_bin_count; 515 req.count = dma_bs->secondary_bin_count;
528 req.size = dma_bs->secondary_bin_size; 516 req.size = dma_bs->secondary_bin_size;
529 req.flags = _DRM_AGP_BUFFER; 517 req.flags = _DRM_AGP_BUFFER;
530 req.agp_start = offset; 518 req.agp_start = offset;
531 519
532 err = drm_addbufs_agp( dev, & req ); 520 err = drm_addbufs_agp(dev, &req);
533 if (err) { 521 if (err) {
534 DRM_ERROR("Unable to add secondary DMA buffers\n"); 522 DRM_ERROR("Unable to add secondary DMA buffers\n");
535 return err; 523 return err;
536 } 524 }
537 525
538 offset += secondary_size; 526 offset += secondary_size;
539 err = drm_addmap( dev, offset, agp_size - offset, 527 err = drm_addmap(dev, offset, agp_size - offset,
540 _DRM_AGP, 0, & dev_priv->agp_textures ); 528 _DRM_AGP, 0, &dev_priv->agp_textures);
541 if (err) { 529 if (err) {
542 DRM_ERROR("Unable to map AGP texture region\n"); 530 DRM_ERROR("Unable to map AGP texture region\n");
543 return err; 531 return err;
@@ -571,7 +559,7 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
571 559
572/** 560/**
573 * Bootstrap the driver for PCI DMA. 561 * Bootstrap the driver for PCI DMA.
574 * 562 *
575 * \todo 563 * \todo
576 * The algorithm for decreasing the size of the primary DMA buffer could be 564 * The algorithm for decreasing the size of the primary DMA buffer could be
577 * better. The size should be rounded up to the nearest page size, then 565 * better. The size should be rounded up to the nearest page size, then
@@ -580,20 +568,20 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
580 * \todo 568 * \todo
581 * Determine whether the maximum address passed to drm_pci_alloc is correct. 569 * Determine whether the maximum address passed to drm_pci_alloc is correct.
582 * The same goes for drm_addbufs_pci. 570 * The same goes for drm_addbufs_pci.
583 * 571 *
584 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap 572 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
585 */ 573 */
586static int mga_do_pci_dma_bootstrap(drm_device_t * dev, 574static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
587 drm_mga_dma_bootstrap_t * dma_bs) 575 drm_mga_dma_bootstrap_t * dma_bs)
588{ 576{
589 drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private; 577 drm_mga_private_t *const dev_priv =
578 (drm_mga_private_t *) dev->dev_private;
590 const unsigned int warp_size = mga_warp_microcode_size(dev_priv); 579 const unsigned int warp_size = mga_warp_microcode_size(dev_priv);
591 unsigned int primary_size; 580 unsigned int primary_size;
592 unsigned int bin_count; 581 unsigned int bin_count;
593 int err; 582 int err;
594 drm_buf_desc_t req; 583 drm_buf_desc_t req;
595 584
596
597 if (dev->dma == NULL) { 585 if (dev->dma == NULL) {
598 DRM_ERROR("dev->dma is NULL\n"); 586 DRM_ERROR("dev->dma is NULL\n");
599 return DRM_ERR(EFAULT); 587 return DRM_ERR(EFAULT);
@@ -612,9 +600,8 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
612 * alignment of the primary or secondary DMA buffers. 600 * alignment of the primary or secondary DMA buffers.
613 */ 601 */
614 602
615 for ( primary_size = dma_bs->primary_size 603 for (primary_size = dma_bs->primary_size; primary_size != 0;
616 ; primary_size != 0 604 primary_size >>= 1) {
617 ; primary_size >>= 1 ) {
618 /* The proper alignment for this mapping is 0x04 */ 605 /* The proper alignment for this mapping is 0x04 */
619 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT, 606 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
620 _DRM_READ_ONLY, &dev_priv->primary); 607 _DRM_READ_ONLY, &dev_priv->primary);
@@ -629,24 +616,23 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
629 616
630 if (dev_priv->primary->size != dma_bs->primary_size) { 617 if (dev_priv->primary->size != dma_bs->primary_size) {
631 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n", 618 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
632 dma_bs->primary_size, 619 dma_bs->primary_size,
633 (unsigned) dev_priv->primary->size); 620 (unsigned)dev_priv->primary->size);
634 dma_bs->primary_size = dev_priv->primary->size; 621 dma_bs->primary_size = dev_priv->primary->size;
635 } 622 }
636 623
637 for ( bin_count = dma_bs->secondary_bin_count 624 for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
638 ; bin_count > 0 625 bin_count--) {
639 ; bin_count-- ) { 626 (void)memset(&req, 0, sizeof(req));
640 (void) memset( &req, 0, sizeof(req) );
641 req.count = bin_count; 627 req.count = bin_count;
642 req.size = dma_bs->secondary_bin_size; 628 req.size = dma_bs->secondary_bin_size;
643 629
644 err = drm_addbufs_pci( dev, & req ); 630 err = drm_addbufs_pci(dev, &req);
645 if (!err) { 631 if (!err) {
646 break; 632 break;
647 } 633 }
648 } 634 }
649 635
650 if (bin_count == 0) { 636 if (bin_count == 0) {
651 DRM_ERROR("Unable to add secondary DMA buffers\n"); 637 DRM_ERROR("Unable to add secondary DMA buffers\n");
652 return err; 638 return err;
@@ -668,38 +654,34 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
668 return 0; 654 return 0;
669} 655}
670 656
671
672static int mga_do_dma_bootstrap(drm_device_t * dev, 657static int mga_do_dma_bootstrap(drm_device_t * dev,
673 drm_mga_dma_bootstrap_t * dma_bs) 658 drm_mga_dma_bootstrap_t * dma_bs)
674{ 659{
675 const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev); 660 const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
676 int err; 661 int err;
677 drm_mga_private_t * const dev_priv = 662 drm_mga_private_t *const dev_priv =
678 (drm_mga_private_t *) dev->dev_private; 663 (drm_mga_private_t *) dev->dev_private;
679
680 664
681 dev_priv->used_new_dma_init = 1; 665 dev_priv->used_new_dma_init = 1;
682 666
683 /* The first steps are the same for both PCI and AGP based DMA. Map 667 /* The first steps are the same for both PCI and AGP based DMA. Map
684 * the cards MMIO registers and map a status page. 668 * the cards MMIO registers and map a status page.
685 */ 669 */
686 err = drm_addmap( dev, dev_priv->mmio_base, dev_priv->mmio_size, 670 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
687 _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio ); 671 _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
688 if (err) { 672 if (err) {
689 DRM_ERROR("Unable to map MMIO region\n"); 673 DRM_ERROR("Unable to map MMIO region\n");
690 return err; 674 return err;
691 } 675 }
692 676
693 677 err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
694 err = drm_addmap( dev, 0, SAREA_MAX, _DRM_SHM, 678 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
695 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL, 679 &dev_priv->status);
696 & dev_priv->status );
697 if (err) { 680 if (err) {
698 DRM_ERROR("Unable to map status region\n"); 681 DRM_ERROR("Unable to map status region\n");
699 return err; 682 return err;
700 } 683 }
701 684
702
703 /* The DMA initialization procedure is slightly different for PCI and 685 /* The DMA initialization procedure is slightly different for PCI and
704 * AGP cards. AGP cards just allocate a large block of AGP memory and 686 * AGP cards. AGP cards just allocate a large block of AGP memory and
705 * carve off portions of it for internal uses. The remaining memory 687 * carve off portions of it for internal uses. The remaining memory
@@ -708,7 +690,7 @@ static int mga_do_dma_bootstrap(drm_device_t * dev,
708 if (is_agp) { 690 if (is_agp) {
709 err = mga_do_agp_dma_bootstrap(dev, dma_bs); 691 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
710 } 692 }
711 693
712 /* If we attempted to initialize the card for AGP DMA but failed, 694 /* If we attempted to initialize the card for AGP DMA but failed,
713 * clean-up any mess that may have been created. 695 * clean-up any mess that may have been created.
714 */ 696 */
@@ -717,7 +699,6 @@ static int mga_do_dma_bootstrap(drm_device_t * dev,
717 mga_do_cleanup_dma(dev); 699 mga_do_cleanup_dma(dev);
718 } 700 }
719 701
720
721 /* Not only do we want to try and initialized PCI cards for PCI DMA, 702 /* Not only do we want to try and initialized PCI cards for PCI DMA,
722 * but we also try to initialized AGP cards that could not be 703 * but we also try to initialized AGP cards that could not be
723 * initialized for AGP DMA. This covers the case where we have an AGP 704 * initialized for AGP DMA. This covers the case where we have an AGP
@@ -730,7 +711,6 @@ static int mga_do_dma_bootstrap(drm_device_t * dev,
730 err = mga_do_pci_dma_bootstrap(dev, dma_bs); 711 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
731 } 712 }
732 713
733
734 return err; 714 return err;
735} 715}
736 716
@@ -740,45 +720,42 @@ int mga_dma_bootstrap(DRM_IOCTL_ARGS)
740 drm_mga_dma_bootstrap_t bootstrap; 720 drm_mga_dma_bootstrap_t bootstrap;
741 int err; 721 int err;
742 722
743
744 DRM_COPY_FROM_USER_IOCTL(bootstrap, 723 DRM_COPY_FROM_USER_IOCTL(bootstrap,
745 (drm_mga_dma_bootstrap_t __user *) data, 724 (drm_mga_dma_bootstrap_t __user *) data,
746 sizeof(bootstrap)); 725 sizeof(bootstrap));
747 726
748 err = mga_do_dma_bootstrap(dev, & bootstrap); 727 err = mga_do_dma_bootstrap(dev, &bootstrap);
749 if (! err) { 728 if (!err) {
750 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 }; 729 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
751 const drm_mga_private_t * const dev_priv = 730 const drm_mga_private_t *const dev_priv =
752 (drm_mga_private_t *) dev->dev_private; 731 (drm_mga_private_t *) dev->dev_private;
753 732
754 if (dev_priv->agp_textures != NULL) { 733 if (dev_priv->agp_textures != NULL) {
755 bootstrap.texture_handle = dev_priv->agp_textures->offset; 734 bootstrap.texture_handle =
735 dev_priv->agp_textures->offset;
756 bootstrap.texture_size = dev_priv->agp_textures->size; 736 bootstrap.texture_size = dev_priv->agp_textures->size;
757 } 737 } else {
758 else {
759 bootstrap.texture_handle = 0; 738 bootstrap.texture_handle = 0;
760 bootstrap.texture_size = 0; 739 bootstrap.texture_size = 0;
761 } 740 }
762 741
763 bootstrap.agp_mode = modes[ bootstrap.agp_mode & 0x07 ]; 742 bootstrap.agp_mode = modes[bootstrap.agp_mode & 0x07];
764 if (DRM_COPY_TO_USER( (void __user *) data, & bootstrap, 743 if (DRM_COPY_TO_USER((void __user *)data, &bootstrap,
765 sizeof(bootstrap))) { 744 sizeof(bootstrap))) {
766 err = DRM_ERR(EFAULT); 745 err = DRM_ERR(EFAULT);
767 } 746 }
768 } 747 } else {
769 else {
770 mga_do_cleanup_dma(dev); 748 mga_do_cleanup_dma(dev);
771 } 749 }
772 750
773 return err; 751 return err;
774} 752}
775 753
776static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) 754static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init)
777{ 755{
778 drm_mga_private_t *dev_priv; 756 drm_mga_private_t *dev_priv;
779 int ret; 757 int ret;
780 DRM_DEBUG( "\n" ); 758 DRM_DEBUG("\n");
781
782 759
783 dev_priv = dev->dev_private; 760 dev_priv = dev->dev_private;
784 761
@@ -787,17 +764,17 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
787 } else { 764 } else {
788 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; 765 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
789 } 766 }
790 dev_priv->maccess = init->maccess; 767 dev_priv->maccess = init->maccess;
791 768
792 dev_priv->fb_cpp = init->fb_cpp; 769 dev_priv->fb_cpp = init->fb_cpp;
793 dev_priv->front_offset = init->front_offset; 770 dev_priv->front_offset = init->front_offset;
794 dev_priv->front_pitch = init->front_pitch; 771 dev_priv->front_pitch = init->front_pitch;
795 dev_priv->back_offset = init->back_offset; 772 dev_priv->back_offset = init->back_offset;
796 dev_priv->back_pitch = init->back_pitch; 773 dev_priv->back_pitch = init->back_pitch;
797 774
798 dev_priv->depth_cpp = init->depth_cpp; 775 dev_priv->depth_cpp = init->depth_cpp;
799 dev_priv->depth_offset = init->depth_offset; 776 dev_priv->depth_offset = init->depth_offset;
800 dev_priv->depth_pitch = init->depth_pitch; 777 dev_priv->depth_pitch = init->depth_pitch;
801 778
802 /* FIXME: Need to support AGP textures... 779 /* FIXME: Need to support AGP textures...
803 */ 780 */
@@ -811,7 +788,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
811 return DRM_ERR(EINVAL); 788 return DRM_ERR(EINVAL);
812 } 789 }
813 790
814 if (! dev_priv->used_new_dma_init) { 791 if (!dev_priv->used_new_dma_init) {
815 dev_priv->status = drm_core_findmap(dev, init->status_offset); 792 dev_priv->status = drm_core_findmap(dev, init->status_offset);
816 if (!dev_priv->status) { 793 if (!dev_priv->status) {
817 DRM_ERROR("failed to find status page!\n"); 794 DRM_ERROR("failed to find status page!\n");
@@ -833,7 +810,8 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
833 return DRM_ERR(EINVAL); 810 return DRM_ERR(EINVAL);
834 } 811 }
835 dev->agp_buffer_token = init->buffers_offset; 812 dev->agp_buffer_token = init->buffers_offset;
836 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 813 dev->agp_buffer_map =
814 drm_core_findmap(dev, init->buffers_offset);
837 if (!dev->agp_buffer_map) { 815 if (!dev->agp_buffer_map) {
838 DRM_ERROR("failed to find dma buffer region!\n"); 816 DRM_ERROR("failed to find dma buffer region!\n");
839 return DRM_ERR(EINVAL); 817 return DRM_ERR(EINVAL);
@@ -845,8 +823,8 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
845 } 823 }
846 824
847 dev_priv->sarea_priv = 825 dev_priv->sarea_priv =
848 (drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle + 826 (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
849 init->sarea_priv_offset); 827 init->sarea_priv_offset);
850 828
851 if (!dev_priv->warp->handle || 829 if (!dev_priv->warp->handle ||
852 !dev_priv->primary->handle || 830 !dev_priv->primary->handle ||
@@ -869,23 +847,20 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
869 return ret; 847 return ret;
870 } 848 }
871 849
872 dev_priv->prim.status = (u32 *)dev_priv->status->handle; 850 dev_priv->prim.status = (u32 *) dev_priv->status->handle;
873 851
874 mga_do_wait_for_idle( dev_priv ); 852 mga_do_wait_for_idle(dev_priv);
875 853
876 /* Init the primary DMA registers. 854 /* Init the primary DMA registers.
877 */ 855 */
878 MGA_WRITE( MGA_PRIMADDRESS, 856 MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
879 dev_priv->primary->offset | MGA_DMA_GENERAL );
880#if 0 857#if 0
881 MGA_WRITE( MGA_PRIMPTR, 858 MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
882 virt_to_bus((void *)dev_priv->prim.status) | 859 MGA_PRIMPTREN1); /* DWGSYNC */
883 MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
884 MGA_PRIMPTREN1 ); /* DWGSYNC */
885#endif 860#endif
886 861
887 dev_priv->prim.start = (u8 *)dev_priv->primary->handle; 862 dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
888 dev_priv->prim.end = ((u8 *)dev_priv->primary->handle 863 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
889 + dev_priv->primary->size); 864 + dev_priv->primary->size);
890 dev_priv->prim.size = dev_priv->primary->size; 865 dev_priv->prim.size = dev_priv->primary->size;
891 866
@@ -913,7 +888,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
913 return 0; 888 return 0;
914} 889}
915 890
916static int mga_do_cleanup_dma( drm_device_t *dev ) 891static int mga_do_cleanup_dma(drm_device_t * dev)
917{ 892{
918 int err = 0; 893 int err = 0;
919 DRM_DEBUG("\n"); 894 DRM_DEBUG("\n");
@@ -922,16 +897,17 @@ static int mga_do_cleanup_dma( drm_device_t *dev )
922 * may not have been called from userspace and after dev_private 897 * may not have been called from userspace and after dev_private
923 * is freed, it's too late. 898 * is freed, it's too late.
924 */ 899 */
925 if ( dev->irq_enabled ) drm_irq_uninstall(dev); 900 if (dev->irq_enabled)
901 drm_irq_uninstall(dev);
926 902
927 if ( dev->dev_private ) { 903 if (dev->dev_private) {
928 drm_mga_private_t *dev_priv = dev->dev_private; 904 drm_mga_private_t *dev_priv = dev->dev_private;
929 905
930 if ((dev_priv->warp != NULL) 906 if ((dev_priv->warp != NULL)
931 && (dev_priv->mmio->type != _DRM_CONSISTENT)) 907 && (dev_priv->mmio->type != _DRM_CONSISTENT))
932 drm_core_ioremapfree(dev_priv->warp, dev); 908 drm_core_ioremapfree(dev_priv->warp, dev);
933 909
934 if ((dev_priv->primary != NULL) 910 if ((dev_priv->primary != NULL)
935 && (dev_priv->primary->type != _DRM_CONSISTENT)) 911 && (dev_priv->primary->type != _DRM_CONSISTENT))
936 drm_core_ioremapfree(dev_priv->primary, dev); 912 drm_core_ioremapfree(dev_priv->primary, dev);
937 913
@@ -944,7 +920,8 @@ static int mga_do_cleanup_dma( drm_device_t *dev )
944 dev_priv->agp_textures = NULL; 920 dev_priv->agp_textures = NULL;
945 drm_unbind_agp(dev_priv->agp_mem); 921 drm_unbind_agp(dev_priv->agp_mem);
946 922
947 drm_free_agp(dev_priv->agp_mem, dev_priv->agp_pages); 923 drm_free_agp(dev_priv->agp_mem,
924 dev_priv->agp_pages);
948 dev_priv->agp_pages = 0; 925 dev_priv->agp_pages = 0;
949 dev_priv->agp_mem = NULL; 926 dev_priv->agp_mem = NULL;
950 } 927 }
@@ -966,7 +943,8 @@ static int mga_do_cleanup_dma( drm_device_t *dev )
966 943
967 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim)); 944 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
968 dev_priv->warp_pipe = 0; 945 dev_priv->warp_pipe = 0;
969 memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); 946 memset(dev_priv->warp_pipe_phys, 0,
947 sizeof(dev_priv->warp_pipe_phys));
970 948
971 if (dev_priv->head != NULL) { 949 if (dev_priv->head != NULL) {
972 mga_freelist_cleanup(dev); 950 mga_freelist_cleanup(dev);
@@ -976,103 +954,102 @@ static int mga_do_cleanup_dma( drm_device_t *dev )
976 return err; 954 return err;
977} 955}
978 956
979int mga_dma_init( DRM_IOCTL_ARGS ) 957int mga_dma_init(DRM_IOCTL_ARGS)
980{ 958{
981 DRM_DEVICE; 959 DRM_DEVICE;
982 drm_mga_init_t init; 960 drm_mga_init_t init;
983 int err; 961 int err;
984 962
985 LOCK_TEST_WITH_RETURN( dev, filp ); 963 LOCK_TEST_WITH_RETURN(dev, filp);
986 964
987 DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data, 965 DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data,
988 sizeof(init)); 966 sizeof(init));
989 967
990 switch ( init.func ) { 968 switch (init.func) {
991 case MGA_INIT_DMA: 969 case MGA_INIT_DMA:
992 err = mga_do_init_dma(dev, &init); 970 err = mga_do_init_dma(dev, &init);
993 if (err) { 971 if (err) {
994 (void) mga_do_cleanup_dma(dev); 972 (void)mga_do_cleanup_dma(dev);
995 } 973 }
996 return err; 974 return err;
997 case MGA_CLEANUP_DMA: 975 case MGA_CLEANUP_DMA:
998 return mga_do_cleanup_dma( dev ); 976 return mga_do_cleanup_dma(dev);
999 } 977 }
1000 978
1001 return DRM_ERR(EINVAL); 979 return DRM_ERR(EINVAL);
1002} 980}
1003 981
1004
1005/* ================================================================ 982/* ================================================================
1006 * Primary DMA stream management 983 * Primary DMA stream management
1007 */ 984 */
1008 985
1009int mga_dma_flush( DRM_IOCTL_ARGS ) 986int mga_dma_flush(DRM_IOCTL_ARGS)
1010{ 987{
1011 DRM_DEVICE; 988 DRM_DEVICE;
1012 drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; 989 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1013 drm_lock_t lock; 990 drm_lock_t lock;
1014 991
1015 LOCK_TEST_WITH_RETURN( dev, filp ); 992 LOCK_TEST_WITH_RETURN(dev, filp);
1016 993
1017 DRM_COPY_FROM_USER_IOCTL( lock, (drm_lock_t __user *)data, sizeof(lock) ); 994 DRM_COPY_FROM_USER_IOCTL(lock, (drm_lock_t __user *) data,
995 sizeof(lock));
1018 996
1019 DRM_DEBUG( "%s%s%s\n", 997 DRM_DEBUG("%s%s%s\n",
1020 (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "", 998 (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1021 (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", 999 (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1022 (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "" ); 1000 (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1023 1001
1024 WRAP_WAIT_WITH_RETURN( dev_priv ); 1002 WRAP_WAIT_WITH_RETURN(dev_priv);
1025 1003
1026 if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) { 1004 if (lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
1027 mga_do_dma_flush( dev_priv ); 1005 mga_do_dma_flush(dev_priv);
1028 } 1006 }
1029 1007
1030 if ( lock.flags & _DRM_LOCK_QUIESCENT ) { 1008 if (lock.flags & _DRM_LOCK_QUIESCENT) {
1031#if MGA_DMA_DEBUG 1009#if MGA_DMA_DEBUG
1032 int ret = mga_do_wait_for_idle( dev_priv ); 1010 int ret = mga_do_wait_for_idle(dev_priv);
1033 if ( ret < 0 ) 1011 if (ret < 0)
1034 DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); 1012 DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
1035 return ret; 1013 return ret;
1036#else 1014#else
1037 return mga_do_wait_for_idle( dev_priv ); 1015 return mga_do_wait_for_idle(dev_priv);
1038#endif 1016#endif
1039 } else { 1017 } else {
1040 return 0; 1018 return 0;
1041 } 1019 }
1042} 1020}
1043 1021
1044int mga_dma_reset( DRM_IOCTL_ARGS ) 1022int mga_dma_reset(DRM_IOCTL_ARGS)
1045{ 1023{
1046 DRM_DEVICE; 1024 DRM_DEVICE;
1047 drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; 1025 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1048 1026
1049 LOCK_TEST_WITH_RETURN( dev, filp ); 1027 LOCK_TEST_WITH_RETURN(dev, filp);
1050 1028
1051 return mga_do_dma_reset( dev_priv ); 1029 return mga_do_dma_reset(dev_priv);
1052} 1030}
1053 1031
1054
1055/* ================================================================ 1032/* ================================================================
1056 * DMA buffer management 1033 * DMA buffer management
1057 */ 1034 */
1058 1035
1059static int mga_dma_get_buffers( DRMFILE filp, 1036static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
1060 drm_device_t *dev, drm_dma_t *d )
1061{ 1037{
1062 drm_buf_t *buf; 1038 drm_buf_t *buf;
1063 int i; 1039 int i;
1064 1040
1065 for ( i = d->granted_count ; i < d->request_count ; i++ ) { 1041 for (i = d->granted_count; i < d->request_count; i++) {
1066 buf = mga_freelist_get( dev ); 1042 buf = mga_freelist_get(dev);
1067 if ( !buf ) return DRM_ERR(EAGAIN); 1043 if (!buf)
1044 return DRM_ERR(EAGAIN);
1068 1045
1069 buf->filp = filp; 1046 buf->filp = filp;
1070 1047
1071 if ( DRM_COPY_TO_USER( &d->request_indices[i], 1048 if (DRM_COPY_TO_USER(&d->request_indices[i],
1072 &buf->idx, sizeof(buf->idx) ) ) 1049 &buf->idx, sizeof(buf->idx)))
1073 return DRM_ERR(EFAULT); 1050 return DRM_ERR(EFAULT);
1074 if ( DRM_COPY_TO_USER( &d->request_sizes[i], 1051 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1075 &buf->total, sizeof(buf->total) ) ) 1052 &buf->total, sizeof(buf->total)))
1076 return DRM_ERR(EFAULT); 1053 return DRM_ERR(EFAULT);
1077 1054
1078 d->granted_count++; 1055 d->granted_count++;
@@ -1080,44 +1057,44 @@ static int mga_dma_get_buffers( DRMFILE filp,
1080 return 0; 1057 return 0;
1081} 1058}
1082 1059
1083int mga_dma_buffers( DRM_IOCTL_ARGS ) 1060int mga_dma_buffers(DRM_IOCTL_ARGS)
1084{ 1061{
1085 DRM_DEVICE; 1062 DRM_DEVICE;
1086 drm_device_dma_t *dma = dev->dma; 1063 drm_device_dma_t *dma = dev->dma;
1087 drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; 1064 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1088 drm_dma_t __user *argp = (void __user *)data; 1065 drm_dma_t __user *argp = (void __user *)data;
1089 drm_dma_t d; 1066 drm_dma_t d;
1090 int ret = 0; 1067 int ret = 0;
1091 1068
1092 LOCK_TEST_WITH_RETURN( dev, filp ); 1069 LOCK_TEST_WITH_RETURN(dev, filp);
1093 1070
1094 DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); 1071 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
1095 1072
1096 /* Please don't send us buffers. 1073 /* Please don't send us buffers.
1097 */ 1074 */
1098 if ( d.send_count != 0 ) { 1075 if (d.send_count != 0) {
1099 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", 1076 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1100 DRM_CURRENTPID, d.send_count ); 1077 DRM_CURRENTPID, d.send_count);
1101 return DRM_ERR(EINVAL); 1078 return DRM_ERR(EINVAL);
1102 } 1079 }
1103 1080
1104 /* We'll send you buffers. 1081 /* We'll send you buffers.
1105 */ 1082 */
1106 if ( d.request_count < 0 || d.request_count > dma->buf_count ) { 1083 if (d.request_count < 0 || d.request_count > dma->buf_count) {
1107 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", 1084 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1108 DRM_CURRENTPID, d.request_count, dma->buf_count ); 1085 DRM_CURRENTPID, d.request_count, dma->buf_count);
1109 return DRM_ERR(EINVAL); 1086 return DRM_ERR(EINVAL);
1110 } 1087 }
1111 1088
1112 WRAP_TEST_WITH_RETURN( dev_priv ); 1089 WRAP_TEST_WITH_RETURN(dev_priv);
1113 1090
1114 d.granted_count = 0; 1091 d.granted_count = 0;
1115 1092
1116 if ( d.request_count ) { 1093 if (d.request_count) {
1117 ret = mga_dma_get_buffers( filp, dev, &d ); 1094 ret = mga_dma_get_buffers(filp, dev, &d);
1118 } 1095 }
1119 1096
1120 DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); 1097 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
1121 1098
1122 return ret; 1099 return ret;
1123} 1100}
@@ -1138,11 +1115,11 @@ int mga_driver_postcleanup(drm_device_t * dev)
1138 */ 1115 */
1139void mga_driver_pretakedown(drm_device_t * dev) 1116void mga_driver_pretakedown(drm_device_t * dev)
1140{ 1117{
1141 mga_do_cleanup_dma( dev ); 1118 mga_do_cleanup_dma(dev);
1142} 1119}
1143 1120
1144int mga_driver_dma_quiescent(drm_device_t *dev) 1121int mga_driver_dma_quiescent(drm_device_t * dev)
1145{ 1122{
1146 drm_mga_private_t *dev_priv = dev->dev_private; 1123 drm_mga_private_t *dev_priv = dev->dev_private;
1147 return mga_do_wait_for_idle( dev_priv ); 1124 return mga_do_wait_for_idle(dev_priv);
1148} 1125}