diff options
Diffstat (limited to 'drivers/char/drm/i915_drv.h')
-rw-r--r-- | drivers/char/drm/i915_drv.h | 101 |
1 files changed, 11 insertions, 90 deletions
diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h index db7001f22561..2be7e1d72836 100644 --- a/drivers/char/drm/i915_drv.h +++ b/drivers/char/drm/i915_drv.h | |||
@@ -76,9 +76,8 @@ struct mem_block { | |||
76 | typedef struct _drm_i915_vbl_swap { | 76 | typedef struct _drm_i915_vbl_swap { |
77 | struct list_head head; | 77 | struct list_head head; |
78 | drm_drawable_t drw_id; | 78 | drm_drawable_t drw_id; |
79 | unsigned int plane; | 79 | unsigned int pipe; |
80 | unsigned int sequence; | 80 | unsigned int sequence; |
81 | int flip; | ||
82 | } drm_i915_vbl_swap_t; | 81 | } drm_i915_vbl_swap_t; |
83 | 82 | ||
84 | typedef struct drm_i915_private { | 83 | typedef struct drm_i915_private { |
@@ -91,7 +90,7 @@ typedef struct drm_i915_private { | |||
91 | drm_dma_handle_t *status_page_dmah; | 90 | drm_dma_handle_t *status_page_dmah; |
92 | void *hw_status_page; | 91 | void *hw_status_page; |
93 | dma_addr_t dma_status_page; | 92 | dma_addr_t dma_status_page; |
94 | uint32_t counter; | 93 | unsigned long counter; |
95 | unsigned int status_gfx_addr; | 94 | unsigned int status_gfx_addr; |
96 | drm_local_map_t hws_map; | 95 | drm_local_map_t hws_map; |
97 | 96 | ||
@@ -104,18 +103,13 @@ typedef struct drm_i915_private { | |||
104 | 103 | ||
105 | wait_queue_head_t irq_queue; | 104 | wait_queue_head_t irq_queue; |
106 | atomic_t irq_received; | 105 | atomic_t irq_received; |
107 | atomic_t irq_emited; | 106 | atomic_t irq_emitted; |
108 | 107 | ||
109 | int tex_lru_log_granularity; | 108 | int tex_lru_log_granularity; |
110 | int allow_batchbuffer; | 109 | int allow_batchbuffer; |
111 | struct mem_block *agp_heap; | 110 | struct mem_block *agp_heap; |
112 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; | 111 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
113 | int vblank_pipe; | 112 | int vblank_pipe; |
114 | spinlock_t user_irq_lock; | ||
115 | int user_irq_refcount; | ||
116 | int fence_irq_on; | ||
117 | uint32_t irq_enable_reg; | ||
118 | int irq_enabled; | ||
119 | 113 | ||
120 | spinlock_t swaps_lock; | 114 | spinlock_t swaps_lock; |
121 | drm_i915_vbl_swap_t vbl_swaps; | 115 | drm_i915_vbl_swap_t vbl_swaps; |
@@ -222,7 +216,7 @@ extern void i915_driver_preclose(struct drm_device *dev, | |||
222 | extern int i915_driver_device_is_agp(struct drm_device * dev); | 216 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
223 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, | 217 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
224 | unsigned long arg); | 218 | unsigned long arg); |
225 | extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync); | 219 | |
226 | /* i915_irq.c */ | 220 | /* i915_irq.c */ |
227 | extern int i915_irq_emit(struct drm_device *dev, void *data, | 221 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
228 | struct drm_file *file_priv); | 222 | struct drm_file *file_priv); |
@@ -233,7 +227,7 @@ extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequenc | |||
233 | extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence); | 227 | extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence); |
234 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | 228 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); |
235 | extern void i915_driver_irq_preinstall(struct drm_device * dev); | 229 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
236 | extern int i915_driver_irq_postinstall(struct drm_device * dev); | 230 | extern void i915_driver_irq_postinstall(struct drm_device * dev); |
237 | extern void i915_driver_irq_uninstall(struct drm_device * dev); | 231 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
238 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, | 232 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
239 | struct drm_file *file_priv); | 233 | struct drm_file *file_priv); |
@@ -241,9 +235,6 @@ extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |||
241 | struct drm_file *file_priv); | 235 | struct drm_file *file_priv); |
242 | extern int i915_vblank_swap(struct drm_device *dev, void *data, | 236 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
243 | struct drm_file *file_priv); | 237 | struct drm_file *file_priv); |
244 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); | ||
245 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | ||
246 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | ||
247 | 238 | ||
248 | /* i915_mem.c */ | 239 | /* i915_mem.c */ |
249 | extern int i915_mem_alloc(struct drm_device *dev, void *data, | 240 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
@@ -388,91 +379,21 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); | |||
388 | 379 | ||
389 | /* Interrupt bits: | 380 | /* Interrupt bits: |
390 | */ | 381 | */ |
391 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) | 382 | #define USER_INT_FLAG (1<<1) |
392 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) | 383 | #define VSYNC_PIPEB_FLAG (1<<5) |
393 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) | 384 | #define VSYNC_PIPEA_FLAG (1<<7) |
394 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) | 385 | #define HWB_OOM_FLAG (1<<13) /* binner out of memory */ |
395 | #define I915_HWB_OOM_INTERRUPT (1<<13) /* binner out of memory */ | ||
396 | #define I915_SYNC_STATUS_INTERRUPT (1<<12) | ||
397 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) | ||
398 | #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) | ||
399 | #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) | ||
400 | #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) | ||
401 | #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) | ||
402 | #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) | ||
403 | #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) | ||
404 | #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) | ||
405 | #define I915_DEBUG_INTERRUPT (1<<2) | ||
406 | #define I915_USER_INTERRUPT (1<<1) | ||
407 | |||
408 | 386 | ||
409 | #define I915REG_HWSTAM 0x02098 | 387 | #define I915REG_HWSTAM 0x02098 |
410 | #define I915REG_INT_IDENTITY_R 0x020a4 | 388 | #define I915REG_INT_IDENTITY_R 0x020a4 |
411 | #define I915REG_INT_MASK_R 0x020a8 | 389 | #define I915REG_INT_MASK_R 0x020a8 |
412 | #define I915REG_INT_ENABLE_R 0x020a0 | 390 | #define I915REG_INT_ENABLE_R 0x020a0 |
413 | #define I915REG_INSTPM 0x020c0 | ||
414 | |||
415 | #define PIPEADSL 0x70000 | ||
416 | #define PIPEBDSL 0x71000 | ||
417 | 391 | ||
418 | #define I915REG_PIPEASTAT 0x70024 | 392 | #define I915REG_PIPEASTAT 0x70024 |
419 | #define I915REG_PIPEBSTAT 0x71024 | 393 | #define I915REG_PIPEBSTAT 0x71024 |
420 | /* | ||
421 | * The two pipe frame counter registers are not synchronized, so | ||
422 | * reading a stable value is somewhat tricky. The following code | ||
423 | * should work: | ||
424 | * | ||
425 | * do { | ||
426 | * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | ||
427 | * PIPE_FRAME_HIGH_SHIFT; | ||
428 | * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> | ||
429 | * PIPE_FRAME_LOW_SHIFT); | ||
430 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | ||
431 | * PIPE_FRAME_HIGH_SHIFT); | ||
432 | * } while (high1 != high2); | ||
433 | * frame = (high1 << 8) | low1; | ||
434 | */ | ||
435 | #define PIPEAFRAMEHIGH 0x70040 | ||
436 | #define PIPEBFRAMEHIGH 0x71040 | ||
437 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff | ||
438 | #define PIPE_FRAME_HIGH_SHIFT 0 | ||
439 | #define PIPEAFRAMEPIXEL 0x70044 | ||
440 | #define PIPEBFRAMEPIXEL 0x71044 | ||
441 | 394 | ||
442 | #define PIPE_FRAME_LOW_MASK 0xff000000 | 395 | #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
443 | #define PIPE_FRAME_LOW_SHIFT 24 | 396 | #define I915_VBLANK_CLEAR (1UL<<1) |
444 | /* | ||
445 | * Pixel within the current frame is counted in the PIPEAFRAMEPIXEL register | ||
446 | * and is 24 bits wide. | ||
447 | */ | ||
448 | #define PIPE_PIXEL_MASK 0x00ffffff | ||
449 | #define PIPE_PIXEL_SHIFT 0 | ||
450 | |||
451 | #define I915_FIFO_UNDERRUN_STATUS (1UL<<31) | ||
452 | #define I915_CRC_ERROR_ENABLE (1UL<<29) | ||
453 | #define I915_CRC_DONE_ENABLE (1UL<<28) | ||
454 | #define I915_GMBUS_EVENT_ENABLE (1UL<<27) | ||
455 | #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) | ||
456 | #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) | ||
457 | #define I915_DPST_EVENT_ENABLE (1UL<<23) | ||
458 | #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) | ||
459 | #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) | ||
460 | #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) | ||
461 | #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ | ||
462 | #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) | ||
463 | #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) | ||
464 | #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) | ||
465 | #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) | ||
466 | #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) | ||
467 | #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) | ||
468 | #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) | ||
469 | #define I915_DPST_EVENT_STATUS (1UL<<7) | ||
470 | #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) | ||
471 | #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) | ||
472 | #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) | ||
473 | #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ | ||
474 | #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1) | ||
475 | #define I915_OVERLAY_UPDATED_STATUS (1UL<<0) | ||
476 | 397 | ||
477 | #define SRX_INDEX 0x3c4 | 398 | #define SRX_INDEX 0x3c4 |
478 | #define SRX_DATA 0x3c5 | 399 | #define SRX_DATA 0x3c5 |