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path: root/drivers/char/drm/i830_drv.h
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Diffstat (limited to 'drivers/char/drm/i830_drv.h')
-rw-r--r--drivers/char/drm/i830_drv.h48
1 files changed, 24 insertions, 24 deletions
diff --git a/drivers/char/drm/i830_drv.h b/drivers/char/drm/i830_drv.h
index db3a9fa83960..9843df831d7e 100644
--- a/drivers/char/drm/i830_drv.h
+++ b/drivers/char/drm/i830_drv.h
@@ -25,7 +25,7 @@
25 * DEALINGS IN THE SOFTWARE. 25 * DEALINGS IN THE SOFTWARE.
26 * 26 *
27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com> 27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28 * Jeff Hartmann <jhartmann@valinux.com> 28 * Jeff Hartmann <jhartmann@valinux.com>
29 * 29 *
30 */ 30 */
31 31
@@ -183,7 +183,7 @@ extern int i830_driver_device_is_agp(struct drm_device * dev);
183 183
184extern int i830_wait_ring(struct drm_device * dev, int n, const char *caller); 184extern int i830_wait_ring(struct drm_device * dev, int n, const char *caller);
185 185
186#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 186#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
187#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 187#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
188#define CMD_REPORT_HEAD (7<<23) 188#define CMD_REPORT_HEAD (7<<23)
189#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) 189#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
@@ -203,30 +203,30 @@ extern int i830_wait_ring(struct drm_device * dev, int n, const char *caller);
203 203
204#define I830REG_HWSTAM 0x02098 204#define I830REG_HWSTAM 0x02098
205#define I830REG_INT_IDENTITY_R 0x020a4 205#define I830REG_INT_IDENTITY_R 0x020a4
206#define I830REG_INT_MASK_R 0x020a8 206#define I830REG_INT_MASK_R 0x020a8
207#define I830REG_INT_ENABLE_R 0x020a0 207#define I830REG_INT_ENABLE_R 0x020a0
208 208
209#define I830_IRQ_RESERVED ((1<<13)|(3<<2)) 209#define I830_IRQ_RESERVED ((1<<13)|(3<<2))
210 210
211#define LP_RING 0x2030 211#define LP_RING 0x2030
212#define HP_RING 0x2040 212#define HP_RING 0x2040
213#define RING_TAIL 0x00 213#define RING_TAIL 0x00
214#define TAIL_ADDR 0x001FFFF8 214#define TAIL_ADDR 0x001FFFF8
215#define RING_HEAD 0x04 215#define RING_HEAD 0x04
216#define HEAD_WRAP_COUNT 0xFFE00000 216#define HEAD_WRAP_COUNT 0xFFE00000
217#define HEAD_WRAP_ONE 0x00200000 217#define HEAD_WRAP_ONE 0x00200000
218#define HEAD_ADDR 0x001FFFFC 218#define HEAD_ADDR 0x001FFFFC
219#define RING_START 0x08 219#define RING_START 0x08
220#define START_ADDR 0x0xFFFFF000 220#define START_ADDR 0x0xFFFFF000
221#define RING_LEN 0x0C 221#define RING_LEN 0x0C
222#define RING_NR_PAGES 0x001FF000 222#define RING_NR_PAGES 0x001FF000
223#define RING_REPORT_MASK 0x00000006 223#define RING_REPORT_MASK 0x00000006
224#define RING_REPORT_64K 0x00000002 224#define RING_REPORT_64K 0x00000002
225#define RING_REPORT_128K 0x00000004 225#define RING_REPORT_128K 0x00000004
226#define RING_NO_REPORT 0x00000000 226#define RING_NO_REPORT 0x00000000
227#define RING_VALID_MASK 0x00000001 227#define RING_VALID_MASK 0x00000001
228#define RING_VALID 0x00000001 228#define RING_VALID 0x00000001
229#define RING_INVALID 0x00000000 229#define RING_INVALID 0x00000000
230 230
231#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 231#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
232#define SC_UPDATE_SCISSOR (0x1<<1) 232#define SC_UPDATE_SCISSOR (0x1<<1)
@@ -279,9 +279,9 @@ extern int i830_wait_ring(struct drm_device * dev, int n, const char *caller);
279#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 279#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
280#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 280#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
281 281
282#define MI_BATCH_BUFFER ((0x30<<23)|1) 282#define MI_BATCH_BUFFER ((0x30<<23)|1)
283#define MI_BATCH_BUFFER_START (0x31<<23) 283#define MI_BATCH_BUFFER_START (0x31<<23)
284#define MI_BATCH_BUFFER_END (0xA<<23) 284#define MI_BATCH_BUFFER_END (0xA<<23)
285#define MI_BATCH_NON_SECURE (1) 285#define MI_BATCH_NON_SECURE (1)
286 286
287#define MI_WAIT_FOR_EVENT ((0x3<<23)) 287#define MI_WAIT_FOR_EVENT ((0x3<<23))