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path: root/drivers/char/drm/i830_drm.h
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Diffstat (limited to 'drivers/char/drm/i830_drm.h')
-rw-r--r--drivers/char/drm/i830_drm.h90
1 files changed, 41 insertions, 49 deletions
diff --git a/drivers/char/drm/i830_drm.h b/drivers/char/drm/i830_drm.h
index 03382c0beee3..66dd75027967 100644
--- a/drivers/char/drm/i830_drm.h
+++ b/drivers/char/drm/i830_drm.h
@@ -33,14 +33,14 @@
33#define I830_UPLOAD_CTX 0x1 33#define I830_UPLOAD_CTX 0x1
34#define I830_UPLOAD_BUFFERS 0x2 34#define I830_UPLOAD_BUFFERS 0x2
35#define I830_UPLOAD_CLIPRECTS 0x4 35#define I830_UPLOAD_CLIPRECTS 0x4
36#define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */ 36#define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */
37#define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */ 37#define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */
38#define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */ 38#define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */
39#define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */ 39#define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */
40#define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */ 40#define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */
41#define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */ 41#define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */
42#define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */ 42#define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */
43#define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */ 43#define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */
44#define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2)) 44#define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2))
45#define I830_UPLOAD_TEX_N_CUBE(n) (0x200 << (n * 2)) 45#define I830_UPLOAD_TEX_N_CUBE(n) (0x200 << (n * 2))
46#define I830_UPLOAD_TEXIMAGE_MASK 0xff00 46#define I830_UPLOAD_TEXIMAGE_MASK 0xff00
@@ -65,7 +65,7 @@
65 * or in a piecewise fashion as required. 65 * or in a piecewise fashion as required.
66 */ 66 */
67 67
68/* Destbuffer state 68/* Destbuffer state
69 * - backbuffer linear offset and pitch -- invarient in the current dri 69 * - backbuffer linear offset and pitch -- invarient in the current dri
70 * - zbuffer linear offset and pitch -- also invarient 70 * - zbuffer linear offset and pitch -- also invarient
71 * - drawing origin in back and depth buffers. 71 * - drawing origin in back and depth buffers.
@@ -103,7 +103,7 @@
103#define I830_CTXREG_AA 9 103#define I830_CTXREG_AA 9
104#define I830_CTXREG_FOGCOLOR 10 104#define I830_CTXREG_FOGCOLOR 10
105#define I830_CTXREG_BLENDCOLR0 11 105#define I830_CTXREG_BLENDCOLR0 11
106#define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */ 106#define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */
107#define I830_CTXREG_VF 13 107#define I830_CTXREG_VF 13
108#define I830_CTXREG_VF2 14 108#define I830_CTXREG_VF2 14
109#define I830_CTXREG_MCSB0 15 109#define I830_CTXREG_MCSB0 15
@@ -111,12 +111,11 @@
111#define I830_CTX_SETUP_SIZE 17 111#define I830_CTX_SETUP_SIZE 17
112 112
113/* 1.3: Stipple state 113/* 1.3: Stipple state
114 */ 114 */
115#define I830_STPREG_ST0 0 115#define I830_STPREG_ST0 0
116#define I830_STPREG_ST1 1 116#define I830_STPREG_ST1 1
117#define I830_STP_SETUP_SIZE 2 117#define I830_STP_SETUP_SIZE 2
118 118
119
120/* Texture state (per tex unit) 119/* Texture state (per tex unit)
121 */ 120 */
122 121
@@ -132,23 +131,23 @@
132#define I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS */ 131#define I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS */
133#define I830_TEX_SETUP_SIZE 10 132#define I830_TEX_SETUP_SIZE 10
134 133
135#define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */ 134#define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */
136#define I830_TEXREG_TM0S0 1 135#define I830_TEXREG_TM0S0 1
137#define I830_TEXREG_TM0S1 2 136#define I830_TEXREG_TM0S1 2
138#define I830_TEXREG_TM0S2 3 137#define I830_TEXREG_TM0S2 3
139#define I830_TEXREG_TM0S3 4 138#define I830_TEXREG_TM0S3 4
140#define I830_TEXREG_TM0S4 5 139#define I830_TEXREG_TM0S4 5
141#define I830_TEXREG_NOP0 6 /* noop */ 140#define I830_TEXREG_NOP0 6 /* noop */
142#define I830_TEXREG_NOP1 7 /* noop */ 141#define I830_TEXREG_NOP1 7 /* noop */
143#define I830_TEXREG_NOP2 8 /* noop */ 142#define I830_TEXREG_NOP2 8 /* noop */
144#define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */ 143#define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */
145#define __I830_TEX_SETUP_SIZE 10 144#define __I830_TEX_SETUP_SIZE 10
146 145
147#define I830_FRONT 0x1 146#define I830_FRONT 0x1
148#define I830_BACK 0x2 147#define I830_BACK 0x2
149#define I830_DEPTH 0x4 148#define I830_DEPTH 0x4
150 149
151#endif /* _I830_DEFINES_ */ 150#endif /* _I830_DEFINES_ */
152 151
153typedef struct _drm_i830_init { 152typedef struct _drm_i830_init {
154 enum { 153 enum {
@@ -177,19 +176,19 @@ typedef struct _drm_i830_init {
177 * structure as well */ 176 * structure as well */
178 177
179typedef struct _drm_i830_tex_region { 178typedef struct _drm_i830_tex_region {
180 unsigned char next, prev; /* indices to form a circular LRU */ 179 unsigned char next, prev; /* indices to form a circular LRU */
181 unsigned char in_use; /* owned by a client, or free? */ 180 unsigned char in_use; /* owned by a client, or free? */
182 int age; /* tracked by clients to update local LRU's */ 181 int age; /* tracked by clients to update local LRU's */
183} drm_i830_tex_region_t; 182} drm_i830_tex_region_t;
184 183
185typedef struct _drm_i830_sarea { 184typedef struct _drm_i830_sarea {
186 unsigned int ContextState[I830_CTX_SETUP_SIZE]; 185 unsigned int ContextState[I830_CTX_SETUP_SIZE];
187 unsigned int BufferState[I830_DEST_SETUP_SIZE]; 186 unsigned int BufferState[I830_DEST_SETUP_SIZE];
188 unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE]; 187 unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE];
189 unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE]; 188 unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE];
190 unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT]; 189 unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT];
191 unsigned int Palette[2][256]; 190 unsigned int Palette[2][256];
192 unsigned int dirty; 191 unsigned int dirty;
193 192
194 unsigned int nbox; 193 unsigned int nbox;
195 drm_clip_rect_t boxes[I830_NR_SAREA_CLIPRECTS]; 194 drm_clip_rect_t boxes[I830_NR_SAREA_CLIPRECTS];
@@ -207,26 +206,26 @@ typedef struct _drm_i830_sarea {
207 * texture space, and can make informed decisions as to which 206 * texture space, and can make informed decisions as to which
208 * areas to kick out. There is no need to choose whether to 207 * areas to kick out. There is no need to choose whether to
209 * kick out your own texture or someone else's - simply eject 208 * kick out your own texture or someone else's - simply eject
210 * them all in LRU order. 209 * them all in LRU order.
211 */ 210 */
212 211
213 drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS+1]; 212 drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS + 1];
214 /* Last elt is sentinal */ 213 /* Last elt is sentinal */
215 int texAge; /* last time texture was uploaded */ 214 int texAge; /* last time texture was uploaded */
216 int last_enqueue; /* last time a buffer was enqueued */ 215 int last_enqueue; /* last time a buffer was enqueued */
217 int last_dispatch; /* age of the most recently dispatched buffer */ 216 int last_dispatch; /* age of the most recently dispatched buffer */
218 int last_quiescent; /* */ 217 int last_quiescent; /* */
219 int ctxOwner; /* last context to upload state */ 218 int ctxOwner; /* last context to upload state */
220 219
221 int vertex_prim; 220 int vertex_prim;
222 221
223 int pf_enabled; /* is pageflipping allowed? */ 222 int pf_enabled; /* is pageflipping allowed? */
224 int pf_active; 223 int pf_active;
225 int pf_current_page; /* which buffer is being displayed? */ 224 int pf_current_page; /* which buffer is being displayed? */
225
226 int perf_boxes; /* performance boxes to be displayed */
226 227
227 int perf_boxes; /* performance boxes to be displayed */ 228 /* Here's the state for texunits 2,3:
228
229 /* Here's the state for texunits 2,3:
230 */ 229 */
231 unsigned int TexState2[I830_TEX_SETUP_SIZE]; 230 unsigned int TexState2[I830_TEX_SETUP_SIZE];
232 unsigned int TexBlendState2[I830_TEXBLEND_SIZE]; 231 unsigned int TexBlendState2[I830_TEXBLEND_SIZE];
@@ -241,12 +240,11 @@ typedef struct _drm_i830_sarea {
241 240
242/* Flags for perf_boxes 241/* Flags for perf_boxes
243 */ 242 */
244#define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */ 243#define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */
245#define I830_BOX_FLIP 0x2 /* populated by kernel */ 244#define I830_BOX_FLIP 0x2 /* populated by kernel */
246#define I830_BOX_WAIT 0x4 /* populated by kernel & client */ 245#define I830_BOX_WAIT 0x4 /* populated by kernel & client */
247#define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */ 246#define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */
248#define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */ 247#define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */
249
250 248
251/* I830 specific ioctls 249/* I830 specific ioctls
252 * The device specific ioctl range is 0x40 to 0x79. 250 * The device specific ioctl range is 0x40 to 0x79.
@@ -289,23 +287,21 @@ typedef struct _drm_i830_clear {
289 unsigned int clear_depthmask; 287 unsigned int clear_depthmask;
290} drm_i830_clear_t; 288} drm_i830_clear_t;
291 289
292
293
294/* These may be placeholders if we have more cliprects than 290/* These may be placeholders if we have more cliprects than
295 * I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to 291 * I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to
296 * false, indicating that the buffer will be dispatched again with a 292 * false, indicating that the buffer will be dispatched again with a
297 * new set of cliprects. 293 * new set of cliprects.
298 */ 294 */
299typedef struct _drm_i830_vertex { 295typedef struct _drm_i830_vertex {
300 int idx; /* buffer index */ 296 int idx; /* buffer index */
301 int used; /* nr bytes in use */ 297 int used; /* nr bytes in use */
302 int discard; /* client is finished with the buffer? */ 298 int discard; /* client is finished with the buffer? */
303} drm_i830_vertex_t; 299} drm_i830_vertex_t;
304 300
305typedef struct _drm_i830_copy_t { 301typedef struct _drm_i830_copy_t {
306 int idx; /* buffer index */ 302 int idx; /* buffer index */
307 int used; /* nr bytes in use */ 303 int used; /* nr bytes in use */
308 void __user *address; /* Address to copy from */ 304 void __user *address; /* Address to copy from */
309} drm_i830_copy_t; 305} drm_i830_copy_t;
310 306
311typedef struct drm_i830_dma { 307typedef struct drm_i830_dma {
@@ -315,7 +311,6 @@ typedef struct drm_i830_dma {
315 int granted; 311 int granted;
316} drm_i830_dma_t; 312} drm_i830_dma_t;
317 313
318
319/* 1.3: Userspace can request & wait on irq's: 314/* 1.3: Userspace can request & wait on irq's:
320 */ 315 */
321typedef struct drm_i830_irq_emit { 316typedef struct drm_i830_irq_emit {
@@ -326,7 +321,6 @@ typedef struct drm_i830_irq_wait {
326 int irq_seq; 321 int irq_seq;
327} drm_i830_irq_wait_t; 322} drm_i830_irq_wait_t;
328 323
329
330/* 1.3: New ioctl to query kernel params: 324/* 1.3: New ioctl to query kernel params:
331 */ 325 */
332#define I830_PARAM_IRQ_ACTIVE 1 326#define I830_PARAM_IRQ_ACTIVE 1
@@ -336,7 +330,6 @@ typedef struct drm_i830_getparam {
336 int __user *value; 330 int __user *value;
337} drm_i830_getparam_t; 331} drm_i830_getparam_t;
338 332
339
340/* 1.3: New ioctl to set kernel params: 333/* 1.3: New ioctl to set kernel params:
341 */ 334 */
342#define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1 335#define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1
@@ -346,5 +339,4 @@ typedef struct drm_i830_setparam {
346 int value; 339 int value;
347} drm_i830_setparam_t; 340} drm_i830_setparam_t;
348 341
349 342#endif /* _I830_DRM_H_ */
350#endif /* _I830_DRM_H_ */