diff options
Diffstat (limited to 'drivers/char/drm/i810_drv.h')
-rw-r--r-- | drivers/char/drm/i810_drv.h | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/drivers/char/drm/i810_drv.h b/drivers/char/drm/i810_drv.h index 0af45872f67e..4de172b2305a 100644 --- a/drivers/char/drm/i810_drv.h +++ b/drivers/char/drm/i810_drv.h | |||
@@ -25,7 +25,7 @@ | |||
25 | * DEALINGS IN THE SOFTWARE. | 25 | * DEALINGS IN THE SOFTWARE. |
26 | * | 26 | * |
27 | * Authors: Rickard E. (Rik) Faith <faith@valinux.com> | 27 | * Authors: Rickard E. (Rik) Faith <faith@valinux.com> |
28 | * Jeff Hartmann <jhartmann@valinux.com> | 28 | * Jeff Hartmann <jhartmann@valinux.com> |
29 | * | 29 | * |
30 | */ | 30 | */ |
31 | 31 | ||
@@ -134,7 +134,7 @@ extern int i810_max_ioctl; | |||
134 | #define I810_ADDR(reg) (I810_BASE(reg) + reg) | 134 | #define I810_ADDR(reg) (I810_BASE(reg) + reg) |
135 | #define I810_DEREF(reg) *(__volatile__ int *)I810_ADDR(reg) | 135 | #define I810_DEREF(reg) *(__volatile__ int *)I810_ADDR(reg) |
136 | #define I810_READ(reg) I810_DEREF(reg) | 136 | #define I810_READ(reg) I810_DEREF(reg) |
137 | #define I810_WRITE(reg,val) do { I810_DEREF(reg) = val; } while (0) | 137 | #define I810_WRITE(reg,val) do { I810_DEREF(reg) = val; } while (0) |
138 | #define I810_DEREF16(reg) *(__volatile__ u16 *)I810_ADDR(reg) | 138 | #define I810_DEREF16(reg) *(__volatile__ u16 *)I810_ADDR(reg) |
139 | #define I810_READ16(reg) I810_DEREF16(reg) | 139 | #define I810_READ16(reg) I810_DEREF16(reg) |
140 | #define I810_WRITE16(reg,val) do { I810_DEREF16(reg) = val; } while (0) | 140 | #define I810_WRITE16(reg,val) do { I810_DEREF16(reg) = val; } while (0) |
@@ -155,19 +155,19 @@ extern int i810_max_ioctl; | |||
155 | } while (0) | 155 | } while (0) |
156 | 156 | ||
157 | #define ADVANCE_LP_RING() do { \ | 157 | #define ADVANCE_LP_RING() do { \ |
158 | if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n"); \ | 158 | if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n"); \ |
159 | dev_priv->ring.tail = outring; \ | 159 | dev_priv->ring.tail = outring; \ |
160 | I810_WRITE(LP_RING + RING_TAIL, outring); \ | 160 | I810_WRITE(LP_RING + RING_TAIL, outring); \ |
161 | } while(0) | 161 | } while(0) |
162 | 162 | ||
163 | #define OUT_RING(n) do { \ | 163 | #define OUT_RING(n) do { \ |
164 | if (I810_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ | 164 | if (I810_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ |
165 | *(volatile unsigned int *)(virt + outring) = n; \ | 165 | *(volatile unsigned int *)(virt + outring) = n; \ |
166 | outring += 4; \ | 166 | outring += 4; \ |
167 | outring &= ringmask; \ | 167 | outring &= ringmask; \ |
168 | } while (0) | 168 | } while (0) |
169 | 169 | ||
170 | #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) | 170 | #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) |
171 | #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) | 171 | #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) |
172 | #define CMD_REPORT_HEAD (7<<23) | 172 | #define CMD_REPORT_HEAD (7<<23) |
173 | #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) | 173 | #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) |
@@ -184,28 +184,28 @@ extern int i810_max_ioctl; | |||
184 | 184 | ||
185 | #define I810REG_HWSTAM 0x02098 | 185 | #define I810REG_HWSTAM 0x02098 |
186 | #define I810REG_INT_IDENTITY_R 0x020a4 | 186 | #define I810REG_INT_IDENTITY_R 0x020a4 |
187 | #define I810REG_INT_MASK_R 0x020a8 | 187 | #define I810REG_INT_MASK_R 0x020a8 |
188 | #define I810REG_INT_ENABLE_R 0x020a0 | 188 | #define I810REG_INT_ENABLE_R 0x020a0 |
189 | 189 | ||
190 | #define LP_RING 0x2030 | 190 | #define LP_RING 0x2030 |
191 | #define HP_RING 0x2040 | 191 | #define HP_RING 0x2040 |
192 | #define RING_TAIL 0x00 | 192 | #define RING_TAIL 0x00 |
193 | #define TAIL_ADDR 0x000FFFF8 | 193 | #define TAIL_ADDR 0x000FFFF8 |
194 | #define RING_HEAD 0x04 | 194 | #define RING_HEAD 0x04 |
195 | #define HEAD_WRAP_COUNT 0xFFE00000 | 195 | #define HEAD_WRAP_COUNT 0xFFE00000 |
196 | #define HEAD_WRAP_ONE 0x00200000 | 196 | #define HEAD_WRAP_ONE 0x00200000 |
197 | #define HEAD_ADDR 0x001FFFFC | 197 | #define HEAD_ADDR 0x001FFFFC |
198 | #define RING_START 0x08 | 198 | #define RING_START 0x08 |
199 | #define START_ADDR 0x00FFFFF8 | 199 | #define START_ADDR 0x00FFFFF8 |
200 | #define RING_LEN 0x0C | 200 | #define RING_LEN 0x0C |
201 | #define RING_NR_PAGES 0x000FF000 | 201 | #define RING_NR_PAGES 0x000FF000 |
202 | #define RING_REPORT_MASK 0x00000006 | 202 | #define RING_REPORT_MASK 0x00000006 |
203 | #define RING_REPORT_64K 0x00000002 | 203 | #define RING_REPORT_64K 0x00000002 |
204 | #define RING_REPORT_128K 0x00000004 | 204 | #define RING_REPORT_128K 0x00000004 |
205 | #define RING_NO_REPORT 0x00000000 | 205 | #define RING_NO_REPORT 0x00000000 |
206 | #define RING_VALID_MASK 0x00000001 | 206 | #define RING_VALID_MASK 0x00000001 |
207 | #define RING_VALID 0x00000001 | 207 | #define RING_VALID 0x00000001 |
208 | #define RING_INVALID 0x00000000 | 208 | #define RING_INVALID 0x00000000 |
209 | 209 | ||
210 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | 210 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
211 | #define SC_UPDATE_SCISSOR (0x1<<1) | 211 | #define SC_UPDATE_SCISSOR (0x1<<1) |