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-rw-r--r--drivers/char/agp/intel-agp.c267
1 files changed, 199 insertions, 68 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index 3cb56a049e24..aa4248efc5d8 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -4,12 +4,17 @@
4 4
5#include <linux/module.h> 5#include <linux/module.h>
6#include <linux/pci.h> 6#include <linux/pci.h>
7#include <linux/slab.h>
7#include <linux/init.h> 8#include <linux/init.h>
8#include <linux/kernel.h> 9#include <linux/kernel.h>
9#include <linux/pagemap.h> 10#include <linux/pagemap.h>
10#include <linux/agp_backend.h> 11#include <linux/agp_backend.h>
12#include <asm/smp.h>
11#include "agp.h" 13#include "agp.h"
12 14
15int intel_agp_enabled;
16EXPORT_SYMBOL(intel_agp_enabled);
17
13/* 18/*
14 * If we have Intel graphics, we're not going to have anything other than 19 * If we have Intel graphics, we're not going to have anything other than
15 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 20 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
@@ -36,10 +41,10 @@
36#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 41#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
37#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC 42#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
38#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 43#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
39#define PCI_DEVICE_ID_INTEL_IGDGM_HB 0xA010 44#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010
40#define PCI_DEVICE_ID_INTEL_IGDGM_IG 0xA011 45#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011
41#define PCI_DEVICE_ID_INTEL_IGDG_HB 0xA000 46#define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000
42#define PCI_DEVICE_ID_INTEL_IGDG_IG 0xA001 47#define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001
43#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 48#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
44#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 49#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
45#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 50#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
@@ -50,20 +55,24 @@
50#define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42 55#define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42
51#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 56#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
52#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 57#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
53#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00 58#define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00
54#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02 59#define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02
55#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 60#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
56#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 61#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
57#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 62#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
58#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 63#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
59#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 64#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
60#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 65#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
61#define PCI_DEVICE_ID_INTEL_IGDNG_D_HB 0x0040 66#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040
62#define PCI_DEVICE_ID_INTEL_IGDNG_D_IG 0x0042 67#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042
63#define PCI_DEVICE_ID_INTEL_IGDNG_M_HB 0x0044 68#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044
64#define PCI_DEVICE_ID_INTEL_IGDNG_MA_HB 0x0062 69#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
65#define PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB 0x006a 70#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a
66#define PCI_DEVICE_ID_INTEL_IGDNG_M_IG 0x0046 71#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046
72#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100
73#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102
74#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104
75#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG 0x0106
67 76
68/* cover 915 and 945 variants */ 77/* cover 915 and 945 variants */
69#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ 78#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@ -83,22 +92,26 @@
83#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ 92#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
84 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ 93 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
85 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \ 94 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
86 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \ 95 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
87 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB) 96 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
97
98#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
99 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
88 100
89#define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \ 101#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
90 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB) 102 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
91 103
92#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \ 104#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
93 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ 105 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
94 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ 106 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
95 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ 107 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
96 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ 108 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
97 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \ 109 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
98 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \ 110 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \
99 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \ 111 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
100 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB || \ 112 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
101 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB) 113 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
114 IS_SNB)
102 115
103extern int agp_memory_reserved; 116extern int agp_memory_reserved;
104 117
@@ -147,6 +160,29 @@ extern int agp_memory_reserved;
147#define INTEL_I7505_AGPCTRL 0x70 160#define INTEL_I7505_AGPCTRL 0x70
148#define INTEL_I7505_MCHCFG 0x50 161#define INTEL_I7505_MCHCFG 0x50
149 162
163#define SNB_GMCH_CTRL 0x50
164#define SNB_GMCH_GMS_STOLEN_MASK 0xF8
165#define SNB_GMCH_GMS_STOLEN_32M (1 << 3)
166#define SNB_GMCH_GMS_STOLEN_64M (2 << 3)
167#define SNB_GMCH_GMS_STOLEN_96M (3 << 3)
168#define SNB_GMCH_GMS_STOLEN_128M (4 << 3)
169#define SNB_GMCH_GMS_STOLEN_160M (5 << 3)
170#define SNB_GMCH_GMS_STOLEN_192M (6 << 3)
171#define SNB_GMCH_GMS_STOLEN_224M (7 << 3)
172#define SNB_GMCH_GMS_STOLEN_256M (8 << 3)
173#define SNB_GMCH_GMS_STOLEN_288M (9 << 3)
174#define SNB_GMCH_GMS_STOLEN_320M (0xa << 3)
175#define SNB_GMCH_GMS_STOLEN_352M (0xb << 3)
176#define SNB_GMCH_GMS_STOLEN_384M (0xc << 3)
177#define SNB_GMCH_GMS_STOLEN_416M (0xd << 3)
178#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
179#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
180#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
181#define SNB_GTT_SIZE_0M (0 << 8)
182#define SNB_GTT_SIZE_1M (1 << 8)
183#define SNB_GTT_SIZE_2M (2 << 8)
184#define SNB_GTT_SIZE_MASK (3 << 8)
185
150static const struct aper_size_info_fixed intel_i810_sizes[] = 186static const struct aper_size_info_fixed intel_i810_sizes[] =
151{ 187{
152 {64, 16384, 4}, 188 {64, 16384, 4},
@@ -178,6 +214,7 @@ static struct _intel_private {
178 * popup and for the GTT. 214 * popup and for the GTT.
179 */ 215 */
180 int gtt_entries; /* i830+ */ 216 int gtt_entries; /* i830+ */
217 int gtt_total_size;
181 union { 218 union {
182 void __iomem *i9xx_flush_page; 219 void __iomem *i9xx_flush_page;
183 void *i8xx_flush_page; 220 void *i8xx_flush_page;
@@ -268,7 +305,7 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem,
268 j++; 305 j++;
269 } 306 }
270 } else { 307 } else {
271 /* sg may merge pages, but we have to seperate 308 /* sg may merge pages, but we have to separate
272 * per-page addr for GTT */ 309 * per-page addr for GTT */
273 unsigned int len, m; 310 unsigned int len, m;
274 311
@@ -292,6 +329,13 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem,
292 off_t pg_start, int mask_type) 329 off_t pg_start, int mask_type)
293{ 330{
294 int i, j; 331 int i, j;
332 u32 cache_bits = 0;
333
334 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
335 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
336 {
337 cache_bits = I830_PTE_SYSTEM_CACHED;
338 }
295 339
296 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 340 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
297 writel(agp_bridge->driver->mask_memory(agp_bridge, 341 writel(agp_bridge->driver->mask_memory(agp_bridge,
@@ -612,7 +656,7 @@ static struct aper_size_info_fixed intel_i830_sizes[] =
612static void intel_i830_init_gtt_entries(void) 656static void intel_i830_init_gtt_entries(void)
613{ 657{
614 u16 gmch_ctrl; 658 u16 gmch_ctrl;
615 int gtt_entries; 659 int gtt_entries = 0;
616 u8 rdct; 660 u8 rdct;
617 int local = 0; 661 int local = 0;
618 static const int ddt[4] = { 0, 16, 32, 64 }; 662 static const int ddt[4] = { 0, 16, 32, 64 };
@@ -653,7 +697,7 @@ static void intel_i830_init_gtt_entries(void)
653 size = 512; 697 size = 512;
654 } 698 }
655 size += 4; /* add in BIOS popup space */ 699 size += 4; /* add in BIOS popup space */
656 } else if (IS_G33 && !IS_IGD) { 700 } else if (IS_G33 && !IS_PINEVIEW) {
657 /* G33's GTT size defined in gmch_ctrl */ 701 /* G33's GTT size defined in gmch_ctrl */
658 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { 702 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
659 case G33_PGETBL_SIZE_1M: 703 case G33_PGETBL_SIZE_1M:
@@ -669,7 +713,7 @@ static void intel_i830_init_gtt_entries(void)
669 size = 512; 713 size = 512;
670 } 714 }
671 size += 4; 715 size += 4;
672 } else if (IS_G4X || IS_IGD) { 716 } else if (IS_G4X || IS_PINEVIEW) {
673 /* On 4 series hardware, GTT stolen is separate from graphics 717 /* On 4 series hardware, GTT stolen is separate from graphics
674 * stolen, ignore it in stolen gtt entries counting. However, 718 * stolen, ignore it in stolen gtt entries counting. However,
675 * 4KB of the stolen memory doesn't get mapped to the GTT. 719 * 4KB of the stolen memory doesn't get mapped to the GTT.
@@ -704,6 +748,63 @@ static void intel_i830_init_gtt_entries(void)
704 gtt_entries = 0; 748 gtt_entries = 0;
705 break; 749 break;
706 } 750 }
751 } else if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
752 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) {
753 /*
754 * SandyBridge has new memory control reg at 0x50.w
755 */
756 u16 snb_gmch_ctl;
757 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
758 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
759 case SNB_GMCH_GMS_STOLEN_32M:
760 gtt_entries = MB(32) - KB(size);
761 break;
762 case SNB_GMCH_GMS_STOLEN_64M:
763 gtt_entries = MB(64) - KB(size);
764 break;
765 case SNB_GMCH_GMS_STOLEN_96M:
766 gtt_entries = MB(96) - KB(size);
767 break;
768 case SNB_GMCH_GMS_STOLEN_128M:
769 gtt_entries = MB(128) - KB(size);
770 break;
771 case SNB_GMCH_GMS_STOLEN_160M:
772 gtt_entries = MB(160) - KB(size);
773 break;
774 case SNB_GMCH_GMS_STOLEN_192M:
775 gtt_entries = MB(192) - KB(size);
776 break;
777 case SNB_GMCH_GMS_STOLEN_224M:
778 gtt_entries = MB(224) - KB(size);
779 break;
780 case SNB_GMCH_GMS_STOLEN_256M:
781 gtt_entries = MB(256) - KB(size);
782 break;
783 case SNB_GMCH_GMS_STOLEN_288M:
784 gtt_entries = MB(288) - KB(size);
785 break;
786 case SNB_GMCH_GMS_STOLEN_320M:
787 gtt_entries = MB(320) - KB(size);
788 break;
789 case SNB_GMCH_GMS_STOLEN_352M:
790 gtt_entries = MB(352) - KB(size);
791 break;
792 case SNB_GMCH_GMS_STOLEN_384M:
793 gtt_entries = MB(384) - KB(size);
794 break;
795 case SNB_GMCH_GMS_STOLEN_416M:
796 gtt_entries = MB(416) - KB(size);
797 break;
798 case SNB_GMCH_GMS_STOLEN_448M:
799 gtt_entries = MB(448) - KB(size);
800 break;
801 case SNB_GMCH_GMS_STOLEN_480M:
802 gtt_entries = MB(480) - KB(size);
803 break;
804 case SNB_GMCH_GMS_STOLEN_512M:
805 gtt_entries = MB(512) - KB(size);
806 break;
807 }
707 } else { 808 } else {
708 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 809 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
709 case I855_GMCH_GMS_STOLEN_1M: 810 case I855_GMCH_GMS_STOLEN_1M:
@@ -814,12 +915,6 @@ static void intel_i830_setup_flush(void)
814 intel_i830_fini_flush(); 915 intel_i830_fini_flush();
815} 916}
816 917
817static void
818do_wbinvd(void *null)
819{
820 wbinvd();
821}
822
823/* The chipset_flush interface needs to get data that has already been 918/* The chipset_flush interface needs to get data that has already been
824 * flushed out of the CPU all the way out to main memory, because the GPU 919 * flushed out of the CPU all the way out to main memory, because the GPU
825 * doesn't snoop those buffers. 920 * doesn't snoop those buffers.
@@ -836,12 +931,10 @@ static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
836 931
837 memset(pg, 0, 1024); 932 memset(pg, 0, 1024);
838 933
839 if (cpu_has_clflush) { 934 if (cpu_has_clflush)
840 clflush_cache_range(pg, 1024); 935 clflush_cache_range(pg, 1024);
841 } else { 936 else if (wbinvd_on_all_cpus() != 0)
842 if (on_each_cpu(do_wbinvd, NULL, 1) != 0) 937 printk(KERN_ERR "Timed out waiting for cache flush.\n");
843 printk(KERN_ERR "Timed out waiting for cache flush.\n");
844 }
845} 938}
846 939
847/* The intel i830 automatically initializes the agp aperture during POST. 940/* The intel i830 automatically initializes the agp aperture during POST.
@@ -1114,6 +1207,9 @@ static void intel_i9xx_setup_flush(void)
1114 if (intel_private.ifp_resource.start) 1207 if (intel_private.ifp_resource.start)
1115 return; 1208 return;
1116 1209
1210 if (IS_SNB)
1211 return;
1212
1117 /* setup a resource for this object */ 1213 /* setup a resource for this object */
1118 intel_private.ifp_resource.name = "Intel Flush Page"; 1214 intel_private.ifp_resource.name = "Intel Flush Page";
1119 intel_private.ifp_resource.flags = IORESOURCE_MEM; 1215 intel_private.ifp_resource.flags = IORESOURCE_MEM;
@@ -1153,7 +1249,7 @@ static int intel_i915_configure(void)
1153 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 1249 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1154 1250
1155 if (agp_bridge->driver->needs_scratch_page) { 1251 if (agp_bridge->driver->needs_scratch_page) {
1156 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 1252 for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) {
1157 writel(agp_bridge->scratch_page, intel_private.gtt+i); 1253 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1158 } 1254 }
1159 readl(intel_private.gtt+i-1); /* PCI Posting. */ 1255 readl(intel_private.gtt+i-1); /* PCI Posting. */
@@ -1308,6 +1404,8 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1308 if (!intel_private.gtt) 1404 if (!intel_private.gtt)
1309 return -ENOMEM; 1405 return -ENOMEM;
1310 1406
1407 intel_private.gtt_total_size = gtt_map_size / 4;
1408
1311 temp &= 0xfff80000; 1409 temp &= 0xfff80000;
1312 1410
1313 intel_private.registers = ioremap(temp, 128 * 4096); 1411 intel_private.registers = ioremap(temp, 128 * 4096);
@@ -1350,19 +1448,40 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1350 1448
1351static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 1449static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1352{ 1450{
1451 u16 snb_gmch_ctl;
1452
1353 switch (agp_bridge->dev->device) { 1453 switch (agp_bridge->dev->device) {
1354 case PCI_DEVICE_ID_INTEL_GM45_HB: 1454 case PCI_DEVICE_ID_INTEL_GM45_HB:
1355 case PCI_DEVICE_ID_INTEL_IGD_E_HB: 1455 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
1356 case PCI_DEVICE_ID_INTEL_Q45_HB: 1456 case PCI_DEVICE_ID_INTEL_Q45_HB:
1357 case PCI_DEVICE_ID_INTEL_G45_HB: 1457 case PCI_DEVICE_ID_INTEL_G45_HB:
1358 case PCI_DEVICE_ID_INTEL_G41_HB: 1458 case PCI_DEVICE_ID_INTEL_G41_HB:
1359 case PCI_DEVICE_ID_INTEL_B43_HB: 1459 case PCI_DEVICE_ID_INTEL_B43_HB:
1360 case PCI_DEVICE_ID_INTEL_IGDNG_D_HB: 1460 case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
1361 case PCI_DEVICE_ID_INTEL_IGDNG_M_HB: 1461 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1362 case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB: 1462 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1363 case PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB: 1463 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
1364 *gtt_offset = *gtt_size = MB(2); 1464 *gtt_offset = *gtt_size = MB(2);
1365 break; 1465 break;
1466 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
1467 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
1468 *gtt_offset = MB(2);
1469
1470 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1471 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
1472 default:
1473 case SNB_GTT_SIZE_0M:
1474 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
1475 *gtt_size = MB(0);
1476 break;
1477 case SNB_GTT_SIZE_1M:
1478 *gtt_size = MB(1);
1479 break;
1480 case SNB_GTT_SIZE_2M:
1481 *gtt_size = MB(2);
1482 break;
1483 }
1484 break;
1366 default: 1485 default:
1367 *gtt_offset = *gtt_size = KB(512); 1486 *gtt_offset = *gtt_size = KB(512);
1368 } 1487 }
@@ -1395,6 +1514,8 @@ static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1395 if (!intel_private.gtt) 1514 if (!intel_private.gtt)
1396 return -ENOMEM; 1515 return -ENOMEM;
1397 1516
1517 intel_private.gtt_total_size = gtt_size / 4;
1518
1398 intel_private.registers = ioremap(temp, 128 * 4096); 1519 intel_private.registers = ioremap(temp, 128 * 4096);
1399 if (!intel_private.registers) { 1520 if (!intel_private.registers) {
1400 iounmap(intel_private.gtt); 1521 iounmap(intel_private.gtt);
@@ -1696,8 +1817,6 @@ static int intel_845_configure(void)
1696 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 1817 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1697 /* clear any possible error conditions */ 1818 /* clear any possible error conditions */
1698 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 1819 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1699
1700 intel_i830_setup_flush();
1701 return 0; 1820 return 0;
1702} 1821}
1703 1822
@@ -2067,7 +2186,6 @@ static const struct agp_bridge_driver intel_845_driver = {
2067 .agp_destroy_page = agp_generic_destroy_page, 2186 .agp_destroy_page = agp_generic_destroy_page,
2068 .agp_destroy_pages = agp_generic_destroy_pages, 2187 .agp_destroy_pages = agp_generic_destroy_pages,
2069 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2188 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2070 .chipset_flush = intel_i830_chipset_flush,
2071}; 2189};
2072 2190
2073static const struct agp_bridge_driver intel_850_driver = { 2191static const struct agp_bridge_driver intel_850_driver = {
@@ -2340,14 +2458,14 @@ static const struct intel_driver_description {
2340 NULL, &intel_g33_driver }, 2458 NULL, &intel_g33_driver },
2341 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", 2459 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2342 NULL, &intel_g33_driver }, 2460 NULL, &intel_g33_driver },
2343 { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD", 2461 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "GMA3150",
2344 NULL, &intel_g33_driver }, 2462 NULL, &intel_g33_driver },
2345 { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD", 2463 { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "GMA3150",
2346 NULL, &intel_g33_driver }, 2464 NULL, &intel_g33_driver },
2347 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, 2465 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2348 "Mobile Intel® GM45 Express", NULL, &intel_i965_driver }, 2466 "GM45", NULL, &intel_i965_driver },
2349 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0, 2467 { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, 0,
2350 "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, 2468 "Eaglelake", NULL, &intel_i965_driver },
2351 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, 2469 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2352 "Q45/Q43", NULL, &intel_i965_driver }, 2470 "Q45/Q43", NULL, &intel_i965_driver },
2353 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, 2471 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
@@ -2356,14 +2474,18 @@ static const struct intel_driver_description {
2356 "B43", NULL, &intel_i965_driver }, 2474 "B43", NULL, &intel_i965_driver },
2357 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, 2475 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2358 "G41", NULL, &intel_i965_driver }, 2476 "G41", NULL, &intel_i965_driver },
2359 { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0, 2477 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 0,
2360 "IGDNG/D", NULL, &intel_i965_driver }, 2478 "HD Graphics", NULL, &intel_i965_driver },
2361 { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, 2479 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2362 "IGDNG/M", NULL, &intel_i965_driver }, 2480 "HD Graphics", NULL, &intel_i965_driver },
2363 { PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, 2481 { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2364 "IGDNG/MA", NULL, &intel_i965_driver }, 2482 "HD Graphics", NULL, &intel_i965_driver },
2365 { PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, 2483 { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2366 "IGDNG/MC2", NULL, &intel_i965_driver }, 2484 "HD Graphics", NULL, &intel_i965_driver },
2485 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG, 0,
2486 "Sandybridge", NULL, &intel_i965_driver },
2487 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG, 0,
2488 "Sandybridge", NULL, &intel_i965_driver },
2367 { 0, 0, 0, NULL, NULL, NULL } 2489 { 0, 0, 0, NULL, NULL, NULL }
2368}; 2490};
2369 2491
@@ -2373,7 +2495,7 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
2373 struct agp_bridge_data *bridge; 2495 struct agp_bridge_data *bridge;
2374 u8 cap_ptr = 0; 2496 u8 cap_ptr = 0;
2375 struct resource *r; 2497 struct resource *r;
2376 int i; 2498 int i, err;
2377 2499
2378 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 2500 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2379 2501
@@ -2455,13 +2577,20 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
2455 &bridge->mode); 2577 &bridge->mode);
2456 } 2578 }
2457 2579
2458 if (bridge->driver->mask_memory == intel_i965_mask_memory) 2580 if (bridge->driver->mask_memory == intel_i965_mask_memory) {
2459 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36))) 2581 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
2460 dev_err(&intel_private.pcidev->dev, 2582 dev_err(&intel_private.pcidev->dev,
2461 "set gfx device dma mask 36bit failed!\n"); 2583 "set gfx device dma mask 36bit failed!\n");
2584 else
2585 pci_set_consistent_dma_mask(intel_private.pcidev,
2586 DMA_BIT_MASK(36));
2587 }
2462 2588
2463 pci_set_drvdata(pdev, bridge); 2589 pci_set_drvdata(pdev, bridge);
2464 return agp_add_bridge(bridge); 2590 err = agp_add_bridge(bridge);
2591 if (!err)
2592 intel_agp_enabled = 1;
2593 return err;
2465} 2594}
2466 2595
2467static void __devexit agp_intel_remove(struct pci_dev *pdev) 2596static void __devexit agp_intel_remove(struct pci_dev *pdev)
@@ -2545,8 +2674,8 @@ static struct pci_device_id agp_intel_pci_table[] = {
2545 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 2674 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2546 ID(PCI_DEVICE_ID_INTEL_82945GM_HB), 2675 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2547 ID(PCI_DEVICE_ID_INTEL_82945GME_HB), 2676 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2548 ID(PCI_DEVICE_ID_INTEL_IGDGM_HB), 2677 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB),
2549 ID(PCI_DEVICE_ID_INTEL_IGDG_HB), 2678 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB),
2550 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), 2679 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2551 ID(PCI_DEVICE_ID_INTEL_82G35_HB), 2680 ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2552 ID(PCI_DEVICE_ID_INTEL_82965Q_HB), 2681 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
@@ -2557,15 +2686,17 @@ static struct pci_device_id agp_intel_pci_table[] = {
2557 ID(PCI_DEVICE_ID_INTEL_Q35_HB), 2686 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2558 ID(PCI_DEVICE_ID_INTEL_Q33_HB), 2687 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2559 ID(PCI_DEVICE_ID_INTEL_GM45_HB), 2688 ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2560 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB), 2689 ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB),
2561 ID(PCI_DEVICE_ID_INTEL_Q45_HB), 2690 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2562 ID(PCI_DEVICE_ID_INTEL_G45_HB), 2691 ID(PCI_DEVICE_ID_INTEL_G45_HB),
2563 ID(PCI_DEVICE_ID_INTEL_G41_HB), 2692 ID(PCI_DEVICE_ID_INTEL_G41_HB),
2564 ID(PCI_DEVICE_ID_INTEL_B43_HB), 2693 ID(PCI_DEVICE_ID_INTEL_B43_HB),
2565 ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB), 2694 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
2566 ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB), 2695 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
2567 ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB), 2696 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
2568 ID(PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB), 2697 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
2698 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
2699 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),
2569 { } 2700 { }
2570}; 2701};
2571 2702
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-20 18:49:26 -0400