6 files changed, 844 insertions, 146 deletions

diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 603eb1be4f6a..b99729e36860 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -6,7 +6,7 @@ menu "Bus devices"
 
 config BRCMSTB_GISB_ARB
         bool "Broadcom STB GISB bus arbiter"
-        depends on ARM
+        depends on ARM || MIPS
         help
           Driver for the Broadcom Set Top Box System-on-a-chip internal bus
           arbiter. This driver provides timeout and target abort error handling
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index 7af78df241f2..860da40b78ef 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -16,17 +16,17 @@
 
 #include <linux/arm-cci.h>
 #include <linux/io.h>
+#include <linux/interrupt.h>
 #include <linux/module.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/perf_event.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 
 #include <asm/cacheflush.h>
-#include <asm/irq_regs.h>
-#include <asm/pmu.h>
 #include <asm/smp_plat.h>
 
 #define DRIVER_NAME             "CCI-400"
@@ -98,6 +98,8 @@ static unsigned long cci_ctrl_phys;
 
 #define CCI_PMU_CNTR_BASE(idx)  ((idx) * SZ_4K)
 
+#define CCI_PMU_CNTR_MASK       ((1ULL << 32) -1)
+
 /*
  * Instead of an event id to monitor CCI cycles, a dedicated counter is
  * provided. Use 0xff to represent CCI cycles and hope that no future revisions
@@ -170,18 +172,29 @@ static char *const pmu_names[] = {
         [CCI_REV_R1] = "CCI_400_r1",
 };
 
-struct cci_pmu_drv_data {
+struct cci_pmu_hw_events {
+        struct perf_event *events[CCI_PMU_MAX_HW_EVENTS];
+        unsigned long used_mask[BITS_TO_LONGS(CCI_PMU_MAX_HW_EVENTS)];
+        raw_spinlock_t pmu_lock;
+};
+
+struct cci_pmu {
         void __iomem *base;
-        struct arm_pmu *cci_pmu;
+        struct pmu pmu;
         int nr_irqs;
         int irqs[CCI_PMU_MAX_HW_EVENTS];
         unsigned long active_irqs;
-        struct perf_event *events[CCI_PMU_MAX_HW_EVENTS];
-        unsigned long used_mask[BITS_TO_LONGS(CCI_PMU_MAX_HW_EVENTS)];
         struct pmu_port_event_ranges *port_ranges;
-        struct pmu_hw_events hw_events;
+        struct cci_pmu_hw_events hw_events;
+        struct platform_device *plat_device;
+        int num_events;
+        atomic_t active_events;
+        struct mutex reserve_mutex;
+        cpumask_t cpus;
 };
-static struct cci_pmu_drv_data *pmu;
+static struct cci_pmu *pmu;
+
+#define to_cci_pmu(c)   (container_of(c, struct cci_pmu, pmu))
 
 static bool is_duplicate_irq(int irq, int *irqs, int nr_irqs)
 {
@@ -252,7 +265,7 @@ static int pmu_validate_hw_event(u8 hw_event)
         return -ENOENT;
 }
 
-static int pmu_is_valid_counter(struct arm_pmu *cci_pmu, int idx)
+static int pmu_is_valid_counter(struct cci_pmu *cci_pmu, int idx)
 {
         return CCI_PMU_CYCLE_CNTR_IDX <= idx &&
                 idx <= CCI_PMU_CNTR_LAST(cci_pmu);
@@ -293,14 +306,9 @@ static u32 pmu_get_max_counters(void)
         return n_cnts + 1;
 }
 
-static struct pmu_hw_events *pmu_get_hw_events(void)
-{
-        return &pmu->hw_events;
-}
-
-static int pmu_get_event_idx(struct pmu_hw_events *hw, struct perf_event *event)
+static int pmu_get_event_idx(struct cci_pmu_hw_events *hw, struct perf_event *event)
 {
-        struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
+        struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
         struct hw_perf_event *hw_event = &event->hw;
         unsigned long cci_event = hw_event->config_base & CCI_PMU_EVENT_MASK;
         int idx;
@@ -336,7 +344,7 @@ static int pmu_map_event(struct perf_event *event)
         return mapping;
 }
 
-static int pmu_request_irq(struct arm_pmu *cci_pmu, irq_handler_t handler)
+static int pmu_request_irq(struct cci_pmu *cci_pmu, irq_handler_t handler)
 {
         int i;
         struct platform_device *pmu_device = cci_pmu->plat_device;
@@ -371,17 +379,91 @@ static int pmu_request_irq(struct arm_pmu *cci_pmu, irq_handler_t handler)
         return 0;
 }
 
+static void pmu_free_irq(struct cci_pmu *cci_pmu)
+{
+        int i;
+
+        for (i = 0; i < pmu->nr_irqs; i++) {
+                if (!test_and_clear_bit(i, &pmu->active_irqs))
+                        continue;
+
+                free_irq(pmu->irqs[i], cci_pmu);
+        }
+}
+
+static u32 pmu_read_counter(struct perf_event *event)
+{
+        struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
+        struct hw_perf_event *hw_counter = &event->hw;
+        int idx = hw_counter->idx;
+        u32 value;
+
+        if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {
+                dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
+                return 0;
+        }
+        value = pmu_read_register(idx, CCI_PMU_CNTR);
+
+        return value;
+}
+
+static void pmu_write_counter(struct perf_event *event, u32 value)
+{
+        struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
+        struct hw_perf_event *hw_counter = &event->hw;
+        int idx = hw_counter->idx;
+
+        if (unlikely(!pmu_is_valid_counter(cci_pmu, idx)))
+                dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
+        else
+                pmu_write_register(value, idx, CCI_PMU_CNTR);
+}
+
+static u64 pmu_event_update(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        u64 delta, prev_raw_count, new_raw_count;
+
+        do {
+                prev_raw_count = local64_read(&hwc->prev_count);
+                new_raw_count = pmu_read_counter(event);
+        } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+                 new_raw_count) != prev_raw_count);
+
+        delta = (new_raw_count - prev_raw_count) & CCI_PMU_CNTR_MASK;
+
+        local64_add(delta, &event->count);
+
+        return new_raw_count;
+}
+
+static void pmu_read(struct perf_event *event)
+{
+        pmu_event_update(event);
+}
+
+void pmu_event_set_period(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        /*
+         * The CCI PMU counters have a period of 2^32. To account for the
+         * possiblity of extreme interrupt latency we program for a period of
+         * half that. Hopefully we can handle the interrupt before another 2^31
+         * events occur and the counter overtakes its previous value.
+         */
+        u64 val = 1ULL << 31;
+        local64_set(&hwc->prev_count, val);
+        pmu_write_counter(event, val);
+}
+
 static irqreturn_t pmu_handle_irq(int irq_num, void *dev)
 {
         unsigned long flags;
-        struct arm_pmu *cci_pmu = (struct arm_pmu *)dev;
-        struct pmu_hw_events *events = cci_pmu->get_hw_events();
-        struct perf_sample_data data;
-        struct pt_regs *regs;
+        struct cci_pmu *cci_pmu = dev;
+        struct cci_pmu_hw_events *events = &pmu->hw_events;
         int idx, handled = IRQ_NONE;
 
         raw_spin_lock_irqsave(&events->pmu_lock, flags);
-        regs = get_irq_regs();
         /*
          * Iterate over counters and update the corresponding perf events.
          * This should work regardless of whether we have per-counter overflow
@@ -403,154 +485,407 @@ static irqreturn_t pmu_handle_irq(int irq_num, void *dev)
 
                 pmu_write_register(CCI_PMU_OVRFLW_FLAG, idx, CCI_PMU_OVRFLW);
 
+                pmu_event_update(event);
+                pmu_event_set_period(event);
                 handled = IRQ_HANDLED;
-
-                armpmu_event_update(event);
-                perf_sample_data_init(&data, 0, hw_counter->last_period);
-                if (!armpmu_event_set_period(event))
-                        continue;
-
-                if (perf_event_overflow(event, &data, regs))
-                        cci_pmu->disable(event);
         }
         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 
         return IRQ_RETVAL(handled);
 }
 
-static void pmu_free_irq(struct arm_pmu *cci_pmu)
+static int cci_pmu_get_hw(struct cci_pmu *cci_pmu)
 {
-        int i;
+        int ret = pmu_request_irq(cci_pmu, pmu_handle_irq);
+        if (ret) {
+                pmu_free_irq(cci_pmu);
+                return ret;
+        }
+        return 0;
+}
 
-        for (i = 0; i < pmu->nr_irqs; i++) {
-                if (!test_and_clear_bit(i, &pmu->active_irqs))
-                        continue;
+static void cci_pmu_put_hw(struct cci_pmu *cci_pmu)
+{
+        pmu_free_irq(cci_pmu);
+}
 
-                free_irq(pmu->irqs[i], cci_pmu);
+static void hw_perf_event_destroy(struct perf_event *event)
+{
+        struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
+        atomic_t *active_events = &cci_pmu->active_events;
+        struct mutex *reserve_mutex = &cci_pmu->reserve_mutex;
+
+        if (atomic_dec_and_mutex_lock(active_events, reserve_mutex)) {
+                cci_pmu_put_hw(cci_pmu);
+                mutex_unlock(reserve_mutex);
         }
 }
 
-static void pmu_enable_event(struct perf_event *event)
+static void cci_pmu_enable(struct pmu *pmu)
 {
+        struct cci_pmu *cci_pmu = to_cci_pmu(pmu);
+        struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
+        int enabled = bitmap_weight(hw_events->used_mask, cci_pmu->num_events);
         unsigned long flags;
-        struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
-        struct pmu_hw_events *events = cci_pmu->get_hw_events();
-        struct hw_perf_event *hw_counter = &event->hw;
-        int idx = hw_counter->idx;
+        u32 val;
+
+        if (!enabled)
+                return;
+
+        raw_spin_lock_irqsave(&hw_events->pmu_lock, flags);
+
+        /* Enable all the PMU counters. */
+        val = readl_relaxed(cci_ctrl_base + CCI_PMCR) | CCI_PMCR_CEN;
+        writel(val, cci_ctrl_base + CCI_PMCR);
+        raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags);
+
+}
+
+static void cci_pmu_disable(struct pmu *pmu)
+{
+        struct cci_pmu *cci_pmu = to_cci_pmu(pmu);
+        struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
+        unsigned long flags;
+        u32 val;
+
+        raw_spin_lock_irqsave(&hw_events->pmu_lock, flags);
+
+        /* Disable all the PMU counters. */
+        val = readl_relaxed(cci_ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN;
+        writel(val, cci_ctrl_base + CCI_PMCR);
+        raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags);
+}
+
+static void cci_pmu_start(struct perf_event *event, int pmu_flags)
+{
+        struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
+        struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+        unsigned long flags;
+
+        /*
+         * To handle interrupt latency, we always reprogram the period
+         * regardlesss of PERF_EF_RELOAD.
+         */
+        if (pmu_flags & PERF_EF_RELOAD)
+                WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+
+        hwc->state = 0;
 
         if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {
                 dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
                 return;
         }
 
-        raw_spin_lock_irqsave(&events->pmu_lock, flags);
+        raw_spin_lock_irqsave(&hw_events->pmu_lock, flags);
 
         /* Configure the event to count, unless you are counting cycles */
         if (idx != CCI_PMU_CYCLE_CNTR_IDX)
-                pmu_set_event(idx, hw_counter->config_base);
+                pmu_set_event(idx, hwc->config_base);
 
+        pmu_event_set_period(event);
         pmu_enable_counter(idx);
 
-        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags);
 }
 
-static void pmu_disable_event(struct perf_event *event)
+static void cci_pmu_stop(struct perf_event *event, int pmu_flags)
 {
-        struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
-        struct hw_perf_event *hw_counter = &event->hw;
-        int idx = hw_counter->idx;
+        struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+
+        if (hwc->state & PERF_HES_STOPPED)
+                return;
 
         if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {
                 dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
                 return;
         }
 
+        /*
+         * We always reprogram the counter, so ignore PERF_EF_UPDATE. See
+         * cci_pmu_start()
+         */
         pmu_disable_counter(idx);
+        pmu_event_update(event);
+        hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 }
 
-static void pmu_start(struct arm_pmu *cci_pmu)
+static int cci_pmu_add(struct perf_event *event, int flags)
 {
-        u32 val;
-        unsigned long flags;
-        struct pmu_hw_events *events = cci_pmu->get_hw_events();
+        struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
+        struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
+        struct hw_perf_event *hwc = &event->hw;
+        int idx;
+        int err = 0;
 
-        raw_spin_lock_irqsave(&events->pmu_lock, flags);
+        perf_pmu_disable(event->pmu);
 
-        /* Enable all the PMU counters. */
-        val = readl_relaxed(cci_ctrl_base + CCI_PMCR) | CCI_PMCR_CEN;
-        writel(val, cci_ctrl_base + CCI_PMCR);
+        /* If we don't have a space for the counter then finish early. */
+        idx = pmu_get_event_idx(hw_events, event);
+        if (idx < 0) {
+                err = idx;
+                goto out;
+        }
 
-        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+        event->hw.idx = idx;
+        hw_events->events[idx] = event;
+
+        hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
+        if (flags & PERF_EF_START)
+                cci_pmu_start(event, PERF_EF_RELOAD);
+
+        /* Propagate our changes to the userspace mapping. */
+        perf_event_update_userpage(event);
+
+out:
+        perf_pmu_enable(event->pmu);
+        return err;
 }
 
-static void pmu_stop(struct arm_pmu *cci_pmu)
+static void cci_pmu_del(struct perf_event *event, int flags)
 {
-        u32 val;
-        unsigned long flags;
-        struct pmu_hw_events *events = cci_pmu->get_hw_events();
+        struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
+        struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
 
-        raw_spin_lock_irqsave(&events->pmu_lock, flags);
+        cci_pmu_stop(event, PERF_EF_UPDATE);
+        hw_events->events[idx] = NULL;
+        clear_bit(idx, hw_events->used_mask);
 
-        /* Disable all the PMU counters. */
-        val = readl_relaxed(cci_ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN;
-        writel(val, cci_ctrl_base + CCI_PMCR);
+        perf_event_update_userpage(event);
+}
 
-        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+static int
+validate_event(struct cci_pmu_hw_events *hw_events,
+               struct perf_event *event)
+{
+        if (is_software_event(event))
+                return 1;
+
+        if (event->state < PERF_EVENT_STATE_OFF)
+                return 1;
+
+        if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
+                return 1;
+
+        return pmu_get_event_idx(hw_events, event) >= 0;
 }
 
-static u32 pmu_read_counter(struct perf_event *event)
+static int
+validate_group(struct perf_event *event)
 {
-        struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
-        struct hw_perf_event *hw_counter = &event->hw;
-        int idx = hw_counter->idx;
-        u32 value;
+        struct perf_event *sibling, *leader = event->group_leader;
+        struct cci_pmu_hw_events fake_pmu = {
+                /*
+                 * Initialise the fake PMU. We only need to populate the
+                 * used_mask for the purposes of validation.
+                 */
+                .used_mask = CPU_BITS_NONE,
+        };
 
-        if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {
-                dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
-                return 0;
+        if (!validate_event(&fake_pmu, leader))
+                return -EINVAL;
+
+        list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+                if (!validate_event(&fake_pmu, sibling))
+                        return -EINVAL;
         }
-        value = pmu_read_register(idx, CCI_PMU_CNTR);
 
-        return value;
+        if (!validate_event(&fake_pmu, event))
+                return -EINVAL;
+
+        return 0;
 }
 
-static void pmu_write_counter(struct perf_event *event, u32 value)
+static int
+__hw_perf_event_init(struct perf_event *event)
 {
-        struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
-        struct hw_perf_event *hw_counter = &event->hw;
-        int idx = hw_counter->idx;
+        struct hw_perf_event *hwc = &event->hw;
+        int mapping;
 
-        if (unlikely(!pmu_is_valid_counter(cci_pmu, idx)))
-                dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
-        else
-                pmu_write_register(value, idx, CCI_PMU_CNTR);
+        mapping = pmu_map_event(event);
+
+        if (mapping < 0) {
+                pr_debug("event %x:%llx not supported\n", event->attr.type,
+                         event->attr.config);
+                return mapping;
+        }
+
+        /*
+         * We don't assign an index until we actually place the event onto
+         * hardware. Use -1 to signify that we haven't decided where to put it
+         * yet.
+         */
+        hwc->idx                = -1;
+        hwc->config_base        = 0;
+        hwc->config             = 0;
+        hwc->event_base         = 0;
+
+        /*
+         * Store the event encoding into the config_base field.
+         */
+        hwc->config_base            |= (unsigned long)mapping;
+
+        /*
+         * Limit the sample_period to half of the counter width. That way, the
+         * new counter value is far less likely to overtake the previous one
+         * unless you have some serious IRQ latency issues.
+         */
+        hwc->sample_period  = CCI_PMU_CNTR_MASK >> 1;
+        hwc->last_period    = hwc->sample_period;
+        local64_set(&hwc->period_left, hwc->sample_period);
+
+        if (event->group_leader != event) {
+                if (validate_group(event) != 0)
+                        return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int cci_pmu_event_init(struct perf_event *event)
+{
+        struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
+        atomic_t *active_events = &cci_pmu->active_events;
+        int err = 0;
+        int cpu;
+
+        if (event->attr.type != event->pmu->type)
+                return -ENOENT;
+
+        /* Shared by all CPUs, no meaningful state to sample */
+        if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
+                return -EOPNOTSUPP;
+
+        /* We have no filtering of any kind */
+        if (event->attr.exclude_user    ||
+            event->attr.exclude_kernel  ||
+            event->attr.exclude_hv      ||
+            event->attr.exclude_idle    ||
+            event->attr.exclude_host    ||
+            event->attr.exclude_guest)
+                return -EINVAL;
+
+        /*
+         * Following the example set by other "uncore" PMUs, we accept any CPU
+         * and rewrite its affinity dynamically rather than having perf core
+         * handle cpu == -1 and pid == -1 for this case.
+         *
+         * The perf core will pin online CPUs for the duration of this call and
+         * the event being installed into its context, so the PMU's CPU can't
+         * change under our feet.
+         */
+        cpu = cpumask_first(&cci_pmu->cpus);
+        if (event->cpu < 0 || cpu < 0)
+                return -EINVAL;
+        event->cpu = cpu;
+
+        event->destroy = hw_perf_event_destroy;
+        if (!atomic_inc_not_zero(active_events)) {
+                mutex_lock(&cci_pmu->reserve_mutex);
+                if (atomic_read(active_events) == 0)
+                        err = cci_pmu_get_hw(cci_pmu);
+                if (!err)
+                        atomic_inc(active_events);
+                mutex_unlock(&cci_pmu->reserve_mutex);
+        }
+        if (err)
+                return err;
+
+        err = __hw_perf_event_init(event);
+        if (err)
+                hw_perf_event_destroy(event);
+
+        return err;
 }
 
-static int cci_pmu_init(struct arm_pmu *cci_pmu, struct platform_device *pdev)
+static ssize_t pmu_attr_cpumask_show(struct device *dev,
+                                     struct device_attribute *attr, char *buf)
 {
-        *cci_pmu = (struct arm_pmu){
-                .name             = pmu_names[probe_cci_revision()],
-                .max_period       = (1LLU << 32) - 1,
-                .get_hw_events    = pmu_get_hw_events,
-                .get_event_idx    = pmu_get_event_idx,
-                .map_event        = pmu_map_event,
-                .request_irq      = pmu_request_irq,
-                .handle_irq       = pmu_handle_irq,
-                .free_irq         = pmu_free_irq,
-                .enable           = pmu_enable_event,
-                .disable          = pmu_disable_event,
-                .start            = pmu_start,
-                .stop             = pmu_stop,
-                .read_counter     = pmu_read_counter,
-                .write_counter    = pmu_write_counter,
+        int n = cpulist_scnprintf(buf, PAGE_SIZE - 2, &pmu->cpus);
+
+        buf[n++] = '\n';
+        buf[n] = '\0';
+        return n;
+}
+
+static DEVICE_ATTR(cpumask, S_IRUGO, pmu_attr_cpumask_show, NULL);
+
+static struct attribute *pmu_attrs[] = {
+        &dev_attr_cpumask.attr,
+        NULL,
+};
+
+static struct attribute_group pmu_attr_group = {
+        .attrs = pmu_attrs,
+};
+
+static const struct attribute_group *pmu_attr_groups[] = {
+        &pmu_attr_group,
+        NULL
+};
+
+static int cci_pmu_init(struct cci_pmu *cci_pmu, struct platform_device *pdev)
+{
+        char *name = pmu_names[probe_cci_revision()];
+        cci_pmu->pmu = (struct pmu) {
+                .name           = pmu_names[probe_cci_revision()],
+                .task_ctx_nr    = perf_invalid_context,
+                .pmu_enable     = cci_pmu_enable,
+                .pmu_disable    = cci_pmu_disable,
+                .event_init     = cci_pmu_event_init,
+                .add            = cci_pmu_add,
+                .del            = cci_pmu_del,
+                .start          = cci_pmu_start,
+                .stop           = cci_pmu_stop,
+                .read           = pmu_read,
+                .attr_groups    = pmu_attr_groups,
         };
 
         cci_pmu->plat_device = pdev;
         cci_pmu->num_events = pmu_get_max_counters();
 
-        return armpmu_register(cci_pmu, -1);
+        return perf_pmu_register(&cci_pmu->pmu, name, -1);
 }
 
+static int cci_pmu_cpu_notifier(struct notifier_block *self,
+                                unsigned long action, void *hcpu)
+{
+        unsigned int cpu = (long)hcpu;
+        unsigned int target;
+
+        switch (action & ~CPU_TASKS_FROZEN) {
+        case CPU_DOWN_PREPARE:
+                if (!cpumask_test_and_clear_cpu(cpu, &pmu->cpus))
+                        break;
+                target = cpumask_any_but(cpu_online_mask, cpu);
+                if (target < 0) // UP, last CPU
+                        break;
+                /*
+                 * TODO: migrate context once core races on event->ctx have
+                 * been fixed.
+                 */
+                cpumask_set_cpu(target, &pmu->cpus);
+        default:
+                break;
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block cci_pmu_cpu_nb = {
+        .notifier_call  = cci_pmu_cpu_notifier,
+        /*
+         * to migrate uncore events, our notifier should be executed
+         * before perf core's notifier.
+         */
+        .priority       = CPU_PRI_PERF + 1,
+};
+
 static const struct of_device_id arm_cci_pmu_matches[] = {
         {
                 .compatible = "arm,cci-400-pmu",
@@ -604,15 +939,16 @@ static int cci_pmu_probe(struct platform_device *pdev)
                 return -EINVAL;
         }
 
-        pmu->cci_pmu = devm_kzalloc(&pdev->dev, sizeof(*(pmu->cci_pmu)), GFP_KERNEL);
-        if (!pmu->cci_pmu)
-                return -ENOMEM;
-
-        pmu->hw_events.events = pmu->events;
-        pmu->hw_events.used_mask = pmu->used_mask;
         raw_spin_lock_init(&pmu->hw_events.pmu_lock);
+        mutex_init(&pmu->reserve_mutex);
+        atomic_set(&pmu->active_events, 0);
+        cpumask_set_cpu(smp_processor_id(), &pmu->cpus);
+
+        ret = register_cpu_notifier(&cci_pmu_cpu_nb);
+        if (ret)
+                return ret;
 
-        ret = cci_pmu_init(pmu->cci_pmu, pdev);
+        ret = cci_pmu_init(pmu, pdev);
         if (ret)
                 return ret;
 
diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c
index 5b15cd2cbd8e..738612c45266 100644
--- a/drivers/bus/brcmstb_gisb.c
+++ b/drivers/bus/brcmstb_gisb.c
@@ -23,35 +23,103 @@
 #include <linux/list.h>
 #include <linux/of.h>
 #include <linux/bitops.h>
+#include <linux/pm.h>
 
+#ifdef CONFIG_ARM
 #include <asm/bug.h>
 #include <asm/signal.h>
+#endif
 
-#define ARB_TIMER                       0x008
-#define ARB_ERR_CAP_CLR                 0x7e4
 #define  ARB_ERR_CAP_CLEAR              (1 << 0)
-#define ARB_ERR_CAP_HI_ADDR             0x7e8
-#define ARB_ERR_CAP_ADDR                0x7ec
-#define ARB_ERR_CAP_DATA                0x7f0
-#define ARB_ERR_CAP_STATUS              0x7f4
 #define  ARB_ERR_CAP_STATUS_TIMEOUT     (1 << 12)
 #define  ARB_ERR_CAP_STATUS_TEA         (1 << 11)
 #define  ARB_ERR_CAP_STATUS_BS_SHIFT    (1 << 2)
 #define  ARB_ERR_CAP_STATUS_BS_MASK     0x3c
 #define  ARB_ERR_CAP_STATUS_WRITE       (1 << 1)
 #define  ARB_ERR_CAP_STATUS_VALID       (1 << 0)
-#define ARB_ERR_CAP_MASTER              0x7f8
+
+enum {
+        ARB_TIMER,
+        ARB_ERR_CAP_CLR,
+        ARB_ERR_CAP_HI_ADDR,
+        ARB_ERR_CAP_ADDR,
+        ARB_ERR_CAP_DATA,
+        ARB_ERR_CAP_STATUS,
+        ARB_ERR_CAP_MASTER,
+};
+
+static const int gisb_offsets_bcm7038[] = {
+        [ARB_TIMER]             = 0x00c,
+        [ARB_ERR_CAP_CLR]       = 0x0c4,
+        [ARB_ERR_CAP_HI_ADDR]   = -1,
+        [ARB_ERR_CAP_ADDR]      = 0x0c8,
+        [ARB_ERR_CAP_DATA]      = 0x0cc,
+        [ARB_ERR_CAP_STATUS]    = 0x0d0,
+        [ARB_ERR_CAP_MASTER]    = -1,
+};
+
+static const int gisb_offsets_bcm7400[] = {
+        [ARB_TIMER]             = 0x00c,
+        [ARB_ERR_CAP_CLR]       = 0x0c8,
+        [ARB_ERR_CAP_HI_ADDR]   = -1,
+        [ARB_ERR_CAP_ADDR]      = 0x0cc,
+        [ARB_ERR_CAP_DATA]      = 0x0d0,
+        [ARB_ERR_CAP_STATUS]    = 0x0d4,
+        [ARB_ERR_CAP_MASTER]    = 0x0d8,
+};
+
+static const int gisb_offsets_bcm7435[] = {
+        [ARB_TIMER]             = 0x00c,
+        [ARB_ERR_CAP_CLR]       = 0x168,
+        [ARB_ERR_CAP_HI_ADDR]   = -1,
+        [ARB_ERR_CAP_ADDR]      = 0x16c,
+        [ARB_ERR_CAP_DATA]      = 0x170,
+        [ARB_ERR_CAP_STATUS]    = 0x174,
+        [ARB_ERR_CAP_MASTER]    = 0x178,
+};
+
+static const int gisb_offsets_bcm7445[] = {
+        [ARB_TIMER]             = 0x008,
+        [ARB_ERR_CAP_CLR]       = 0x7e4,
+        [ARB_ERR_CAP_HI_ADDR]   = 0x7e8,
+        [ARB_ERR_CAP_ADDR]      = 0x7ec,
+        [ARB_ERR_CAP_DATA]      = 0x7f0,
+        [ARB_ERR_CAP_STATUS]    = 0x7f4,
+        [ARB_ERR_CAP_MASTER]    = 0x7f8,
+};
 
 struct brcmstb_gisb_arb_device {
         void __iomem    *base;
+        const int       *gisb_offsets;
         struct mutex    lock;
         struct list_head next;
         u32 valid_mask;
         const char *master_names[sizeof(u32) * BITS_PER_BYTE];
+        u32 saved_timeout;
 };
 
 static LIST_HEAD(brcmstb_gisb_arb_device_list);
 
+static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
+{
+        int offset = gdev->gisb_offsets[reg];
+
+        /* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
+        if (offset == -1)
+                return 1;
+
+        return ioread32(gdev->base + offset);
+}
+
+static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
+{
+        int offset = gdev->gisb_offsets[reg];
+
+        if (offset == -1)
+                return;
+        iowrite32(val, gdev->base + reg);
+}
+
 static ssize_t gisb_arb_get_timeout(struct device *dev,
                                     struct device_attribute *attr,
                                     char *buf)
@@ -61,7 +129,7 @@ static ssize_t gisb_arb_get_timeout(struct device *dev,
         u32 timeout;
 
         mutex_lock(&gdev->lock);
-        timeout = ioread32(gdev->base + ARB_TIMER);
+        timeout = gisb_read(gdev, ARB_TIMER);
         mutex_unlock(&gdev->lock);
 
         return sprintf(buf, "%d", timeout);
@@ -83,7 +151,7 @@ static ssize_t gisb_arb_set_timeout(struct device *dev,
                 return -EINVAL;
 
         mutex_lock(&gdev->lock);
-        iowrite32(val, gdev->base + ARB_TIMER);
+        gisb_write(gdev, val, ARB_TIMER);
         mutex_unlock(&gdev->lock);
 
         return count;
@@ -110,18 +178,18 @@ static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
         const char *m_name;
         char m_fmt[11];
 
-        cap_status = ioread32(gdev->base + ARB_ERR_CAP_STATUS);
+        cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);
 
         /* Invalid captured address, bail out */
         if (!(cap_status & ARB_ERR_CAP_STATUS_VALID))
                 return 1;
 
         /* Read the address and master */
-        arb_addr = ioread32(gdev->base + ARB_ERR_CAP_ADDR) & 0xffffffff;
+        arb_addr = gisb_read(gdev, ARB_ERR_CAP_ADDR) & 0xffffffff;
 #if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
-        arb_addr |= (u64)ioread32(gdev->base + ARB_ERR_CAP_HI_ADDR) << 32;
+        arb_addr |= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;
 #endif
-        master = ioread32(gdev->base + ARB_ERR_CAP_MASTER);
+        master = gisb_read(gdev, ARB_ERR_CAP_MASTER);
 
         m_name = brcmstb_gisb_master_to_str(gdev, master);
         if (!m_name) {
@@ -136,11 +204,12 @@ static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
                 m_name);
 
         /* clear the GISB error */
-        iowrite32(ARB_ERR_CAP_CLEAR, gdev->base + ARB_ERR_CAP_CLR);
+        gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);
 
         return 0;
 }
 
+#ifdef CONFIG_ARM
 static int brcmstb_bus_error_handler(unsigned long addr, unsigned int fsr,
                                      struct pt_regs *regs)
 {
@@ -159,12 +228,7 @@ static int brcmstb_bus_error_handler(unsigned long addr, unsigned int fsr,
 
         return ret;
 }
-
-void __init brcmstb_hook_fault_code(void)
-{
-        hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0,
-                        "imprecise external abort");
-}
+#endif
 
 static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
 {
@@ -192,10 +256,20 @@ static struct attribute_group gisb_arb_sysfs_attr_group = {
         .attrs = gisb_arb_sysfs_attrs,
 };
 
-static int brcmstb_gisb_arb_probe(struct platform_device *pdev)
+static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
+        { .compatible = "brcm,gisb-arb",         .data = gisb_offsets_bcm7445 },
+        { .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 },
+        { .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 },
+        { .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
+        { .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
+        { },
+};
+
+static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
 {
         struct device_node *dn = pdev->dev.of_node;
         struct brcmstb_gisb_arb_device *gdev;
+        const struct of_device_id *of_id;
         struct resource *r;
         int err, timeout_irq, tea_irq;
         unsigned int num_masters, j = 0;
@@ -216,6 +290,13 @@ static int brcmstb_gisb_arb_probe(struct platform_device *pdev)
         if (IS_ERR(gdev->base))
                 return PTR_ERR(gdev->base);
 
+        of_id = of_match_node(brcmstb_gisb_arb_of_match, dn);
+        if (!of_id) {
+                pr_err("failed to look up compatible string\n");
+                return -EINVAL;
+        }
+        gdev->gisb_offsets = of_id->data;
+
         err = devm_request_irq(&pdev->dev, timeout_irq,
                                 brcmstb_gisb_timeout_handler, 0, pdev->name,
                                 gdev);
@@ -261,28 +342,62 @@ static int brcmstb_gisb_arb_probe(struct platform_device *pdev)
 
         list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);
 
+#ifdef CONFIG_ARM
+        hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0,
+                        "imprecise external abort");
+#endif
+
         dev_info(&pdev->dev, "registered mem: %p, irqs: %d, %d\n",
                         gdev->base, timeout_irq, tea_irq);
 
         return 0;
 }
 
-static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
-        { .compatible = "brcm,gisb-arb" },
-        { },
+#ifdef CONFIG_PM_SLEEP
+static int brcmstb_gisb_arb_suspend(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
+
+        gdev->saved_timeout = gisb_read(gdev, ARB_TIMER);
+
+        return 0;
+}
+
+/* Make sure we provide the same timeout value that was configured before, and
+ * do this before the GISB timeout interrupt handler has any chance to run.
+ */
+static int brcmstb_gisb_arb_resume_noirq(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
+
+        gisb_write(gdev, gdev->saved_timeout, ARB_TIMER);
+
+        return 0;
+}
+#else
+#define brcmstb_gisb_arb_suspend       NULL
+#define brcmstb_gisb_arb_resume_noirq  NULL
+#endif
+
+static const struct dev_pm_ops brcmstb_gisb_arb_pm_ops = {
+        .suspend        = brcmstb_gisb_arb_suspend,
+        .resume_noirq   = brcmstb_gisb_arb_resume_noirq,
 };
 
 static struct platform_driver brcmstb_gisb_arb_driver = {
-        .probe  = brcmstb_gisb_arb_probe,
         .driver = {
                 .name   = "brcm-gisb-arb",
                 .of_match_table = brcmstb_gisb_arb_of_match,
+                .pm     = &brcmstb_gisb_arb_pm_ops,
         },
 };
 
 static int __init brcm_gisb_driver_init(void)
 {
-        return platform_driver_register(&brcmstb_gisb_arb_driver);
+        return platform_driver_probe(&brcmstb_gisb_arb_driver,
+                                     brcmstb_gisb_arb_probe);
 }
 
 module_init(brcm_gisb_driver_init);
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 26c3779d871d..eb7682dc123b 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -57,6 +57,7 @@
 #include <linux/of_address.h>
 #include <linux/debugfs.h>
 #include <linux/log2.h>
+#include <linux/syscore_ops.h>
 
 /*
  * DDR target is the same on all platforms.
@@ -94,20 +95,42 @@
 
 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
 
+/* Relative to mbusbridge_base */
+#define MBUS_BRIDGE_CTRL_OFF    0x0
+#define MBUS_BRIDGE_BASE_OFF    0x4
+
+/* Maximum number of windows, for all known platforms */
+#define MBUS_WINS_MAX           20
+
 struct mvebu_mbus_state;
 
 struct mvebu_mbus_soc_data {
         unsigned int num_wins;
         unsigned int num_remappable_wins;
+        bool has_mbus_bridge;
         unsigned int (*win_cfg_offset)(const int win);
         void (*setup_cpu_target)(struct mvebu_mbus_state *s);
+        int (*save_cpu_target)(struct mvebu_mbus_state *s,
+                               u32 *store_addr);
         int (*show_cpu_target)(struct mvebu_mbus_state *s,
                                struct seq_file *seq, void *v);
 };
 
+/*
+ * Used to store the state of one MBus window accross suspend/resume.
+ */
+struct mvebu_mbus_win_data {
+        u32 ctrl;
+        u32 base;
+        u32 remap_lo;
+        u32 remap_hi;
+};
+
 struct mvebu_mbus_state {
         void __iomem *mbuswins_base;
         void __iomem *sdramwins_base;
+        void __iomem *mbusbridge_base;
+        phys_addr_t sdramwins_phys_base;
         struct dentry *debugfs_root;
         struct dentry *debugfs_sdram;
         struct dentry *debugfs_devs;
@@ -115,6 +138,11 @@ struct mvebu_mbus_state {
         struct resource pcie_io_aperture;
         const struct mvebu_mbus_soc_data *soc;
         int hw_io_coherency;
+
+        /* Used during suspend/resume */
+        u32 mbus_bridge_ctrl;
+        u32 mbus_bridge_base;
+        struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
 };
 
 static struct mvebu_mbus_state mbus_state;
@@ -516,6 +544,28 @@ mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
         mvebu_mbus_dram_info.num_cs = cs;
 }
 
+static int
+mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
+                                   u32 *store_addr)
+{
+        int i;
+
+        for (i = 0; i < 4; i++) {
+                u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
+                u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
+
+                writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
+                       store_addr++);
+                writel(base, store_addr++);
+                writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
+                       store_addr++);
+                writel(size, store_addr++);
+        }
+
+        /* We've written 16 words to the store address */
+        return 16;
+}
+
 static void __init
 mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
 {
@@ -546,10 +596,35 @@ mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
         mvebu_mbus_dram_info.num_cs = cs;
 }
 
+static int
+mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
+                                u32 *store_addr)
+{
+        int i;
+
+        for (i = 0; i < 2; i++) {
+                u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
+
+                writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
+                       store_addr++);
+                writel(map, store_addr++);
+        }
+
+        /* We've written 4 words to the store address */
+        return 4;
+}
+
+int mvebu_mbus_save_cpu_target(u32 *store_addr)
+{
+        return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
+}
+
 static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
         .num_wins            = 20,
         .num_remappable_wins = 8,
+        .has_mbus_bridge     = true,
         .win_cfg_offset      = armada_370_xp_mbus_win_offset,
+        .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
         .show_cpu_target     = mvebu_sdram_debug_show_orion,
 };
@@ -558,6 +633,7 @@ static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
         .num_wins            = 8,
         .num_remappable_wins = 4,
         .win_cfg_offset      = orion_mbus_win_offset,
+        .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
         .show_cpu_target     = mvebu_sdram_debug_show_orion,
 };
@@ -566,6 +642,7 @@ static const struct mvebu_mbus_soc_data dove_mbus_data = {
         .num_wins            = 8,
         .num_remappable_wins = 4,
         .win_cfg_offset      = orion_mbus_win_offset,
+        .save_cpu_target     = mvebu_mbus_dove_save_cpu_target,
         .setup_cpu_target    = mvebu_mbus_dove_setup_cpu_target,
         .show_cpu_target     = mvebu_sdram_debug_show_dove,
 };
@@ -578,6 +655,7 @@ static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
         .num_wins            = 8,
         .num_remappable_wins = 4,
         .win_cfg_offset      = orion_mbus_win_offset,
+        .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
         .show_cpu_target     = mvebu_sdram_debug_show_orion,
 };
@@ -586,6 +664,7 @@ static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
         .num_wins            = 8,
         .num_remappable_wins = 2,
         .win_cfg_offset      = orion_mbus_win_offset,
+        .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
         .show_cpu_target     = mvebu_sdram_debug_show_orion,
 };
@@ -594,6 +673,7 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
         .num_wins            = 14,
         .num_remappable_wins = 8,
         .win_cfg_offset      = mv78xx0_mbus_win_offset,
+        .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
         .show_cpu_target     = mvebu_sdram_debug_show_orion,
 };
@@ -698,11 +778,73 @@ static __init int mvebu_mbus_debugfs_init(void)
 }
 fs_initcall(mvebu_mbus_debugfs_init);
 
+static int mvebu_mbus_suspend(void)
+{
+        struct mvebu_mbus_state *s = &mbus_state;
+        int win;
+
+        if (!s->mbusbridge_base)
+                return -ENODEV;
+
+        for (win = 0; win < s->soc->num_wins; win++) {
+                void __iomem *addr = s->mbuswins_base +
+                        s->soc->win_cfg_offset(win);
+
+                s->wins[win].base = readl(addr + WIN_BASE_OFF);
+                s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
+
+                if (win >= s->soc->num_remappable_wins)
+                        continue;
+
+                s->wins[win].remap_lo = readl(addr + WIN_REMAP_LO_OFF);
+                s->wins[win].remap_hi = readl(addr + WIN_REMAP_HI_OFF);
+        }
+
+        s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
+                                    MBUS_BRIDGE_CTRL_OFF);
+        s->mbus_bridge_base = readl(s->mbusbridge_base +
+                                    MBUS_BRIDGE_BASE_OFF);
+
+        return 0;
+}
+
+static void mvebu_mbus_resume(void)
+{
+        struct mvebu_mbus_state *s = &mbus_state;
+        int win;
+
+        writel(s->mbus_bridge_ctrl,
+               s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
+        writel(s->mbus_bridge_base,
+               s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
+
+        for (win = 0; win < s->soc->num_wins; win++) {
+                void __iomem *addr = s->mbuswins_base +
+                        s->soc->win_cfg_offset(win);
+
+                writel(s->wins[win].base, addr + WIN_BASE_OFF);
+                writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
+
+                if (win >= s->soc->num_remappable_wins)
+                        continue;
+
+                writel(s->wins[win].remap_lo, addr + WIN_REMAP_LO_OFF);
+                writel(s->wins[win].remap_hi, addr + WIN_REMAP_HI_OFF);
+        }
+}
+
+struct syscore_ops mvebu_mbus_syscore_ops = {
+        .suspend        = mvebu_mbus_suspend,
+        .resume         = mvebu_mbus_resume,
+};
+
 static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
                                          phys_addr_t mbuswins_phys_base,
                                          size_t mbuswins_size,
                                          phys_addr_t sdramwins_phys_base,
-                                         size_t sdramwins_size)
+                                         size_t sdramwins_size,
+                                         phys_addr_t mbusbridge_phys_base,
+                                         size_t mbusbridge_size)
 {
         int win;
 
@@ -716,11 +858,26 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
                 return -ENOMEM;
         }
 
+        mbus->sdramwins_phys_base = sdramwins_phys_base;
+
+        if (mbusbridge_phys_base) {
+                mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
+                                                mbusbridge_size);
+                if (!mbus->mbusbridge_base) {
+                        iounmap(mbus->sdramwins_base);
+                        iounmap(mbus->mbuswins_base);
+                        return -ENOMEM;
+                }
+        } else
+                mbus->mbusbridge_base = NULL;
+
         for (win = 0; win < mbus->soc->num_wins; win++)
                 mvebu_mbus_disable_window(mbus, win);
 
         mbus->soc->setup_cpu_target(mbus);
 
+        register_syscore_ops(&mvebu_mbus_syscore_ops);
+
         return 0;
 }
 
@@ -746,7 +903,7 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
                         mbuswins_phys_base,
                         mbuswins_size,
                         sdramwins_phys_base,
-                        sdramwins_size);
+                        sdramwins_size, 0, 0);
 }
 
 #ifdef CONFIG_OF
@@ -887,7 +1044,7 @@ static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
 
 int __init mvebu_mbus_dt_init(bool is_coherent)
 {
-        struct resource mbuswins_res, sdramwins_res;
+        struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
         struct device_node *np, *controller;
         const struct of_device_id *of_id;
         const __be32 *prop;
@@ -923,6 +1080,19 @@ int __init mvebu_mbus_dt_init(bool is_coherent)
                 return -EINVAL;
         }
 
+        /*
+         * Set the resource to 0 so that it can be left unmapped by
+         * mvebu_mbus_common_init() if the DT doesn't carry the
+         * necessary information. This is needed to preserve backward
+         * compatibility.
+         */
+        memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
+
+        if (mbus_state.soc->has_mbus_bridge) {
+                if (of_address_to_resource(controller, 2, &mbusbridge_res))
+                        pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
+        }
+
         mbus_state.hw_io_coherency = is_coherent;
 
         /* Get optional pcie-{mem,io}-aperture properties */
@@ -933,7 +1103,9 @@ int __init mvebu_mbus_dt_init(bool is_coherent)
                                      mbuswins_res.start,
                                      resource_size(&mbuswins_res),
                                      sdramwins_res.start,
-                                     resource_size(&sdramwins_res));
+                                     resource_size(&sdramwins_res),
+                                     mbusbridge_res.start,
+                                     resource_size(&mbusbridge_res));
         if (ret)
                 return ret;
 
diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c
index 1ff1863415c5..029bc73de001 100644
--- a/drivers/bus/omap_l3_noc.c
+++ b/drivers/bus/omap_l3_noc.c
@@ -222,10 +222,14 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
                         }
 
                         /* Error found so break the for loop */
-                        break;
+                        return IRQ_HANDLED;
                 }
         }
-        return IRQ_HANDLED;
+
+        dev_err(l3->dev, "L3 %s IRQ not handled!!\n",
+                inttype ? "debug" : "application");
+
+        return IRQ_NONE;
 }
 
 static const struct of_device_id l3_noc_match[] = {
@@ -296,10 +300,65 @@ static int omap_l3_probe(struct platform_device *pdev)
         return ret;
 }
 
+#ifdef  CONFIG_PM
+
+/**
+ * l3_resume_noirq() - resume function for l3_noc
+ * @dev:        pointer to l3_noc device structure
+ *
+ * We only have the resume handler only since we
+ * have already maintained the delta register
+ * configuration as part of configuring the system
+ */
+static int l3_resume_noirq(struct device *dev)
+{
+        struct omap_l3 *l3 = dev_get_drvdata(dev);
+        int i;
+        struct l3_flagmux_data *flag_mux;
+        void __iomem *base, *mask_regx = NULL;
+        u32 mask_val;
+
+        for (i = 0; i < l3->num_modules; i++) {
+                base = l3->l3_base[i];
+                flag_mux = l3->l3_flagmux[i];
+                if (!flag_mux->mask_app_bits && !flag_mux->mask_dbg_bits)
+                        continue;
+
+                mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
+                           (L3_APPLICATION_ERROR << 3);
+                mask_val = readl_relaxed(mask_regx);
+                mask_val &= ~(flag_mux->mask_app_bits);
+
+                writel_relaxed(mask_val, mask_regx);
+                mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
+                           (L3_DEBUG_ERROR << 3);
+                mask_val = readl_relaxed(mask_regx);
+                mask_val &= ~(flag_mux->mask_dbg_bits);
+
+                writel_relaxed(mask_val, mask_regx);
+        }
+
+        /* Dummy read to force OCP barrier */
+        if (mask_regx)
+                (void)readl(mask_regx);
+
+        return 0;
+}
+
+static const struct dev_pm_ops l3_dev_pm_ops = {
+        .resume_noirq           = l3_resume_noirq,
+};
+
+#define L3_DEV_PM_OPS (&l3_dev_pm_ops)
+#else
+#define L3_DEV_PM_OPS NULL
+#endif
+
 static struct platform_driver omap_l3_driver = {
         .probe          = omap_l3_probe,
         .driver         = {
                 .name           = "omap_l3_noc",
+                .pm             = L3_DEV_PM_OPS,
                 .of_match_table = of_match_ptr(l3_noc_match),
         },
 };
diff --git a/drivers/bus/omap_l3_smx.c b/drivers/bus/omap_l3_smx.c
index acc216491b8a..597fdaee7315 100644
--- a/drivers/bus/omap_l3_smx.c
+++ b/drivers/bus/omap_l3_smx.c
@@ -27,6 +27,10 @@
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
 #include "omap_l3_smx.h"
 
 static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
@@ -211,7 +215,17 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
         return ret;
 }
 
-static int __init omap3_l3_probe(struct platform_device *pdev)
+#if IS_BUILTIN(CONFIG_OF)
+static const struct of_device_id omap3_l3_match[] = {
+        {
+                .compatible = "ti,omap3-l3-smx",
+        },
+        { },
+};
+MODULE_DEVICE_TABLE(of, omap3_l3_match);
+#endif
+
+static int omap3_l3_probe(struct platform_device *pdev)
 {
         struct omap3_l3 *l3;
         struct resource *res;
@@ -265,7 +279,7 @@ err0:
         return ret;
 }
 
-static int __exit omap3_l3_remove(struct platform_device *pdev)
+static int omap3_l3_remove(struct platform_device *pdev)
 {
         struct omap3_l3         *l3 = platform_get_drvdata(pdev);
 
@@ -278,15 +292,17 @@ static int __exit omap3_l3_remove(struct platform_device *pdev)
 }
 
 static struct platform_driver omap3_l3_driver = {
-        .remove         = __exit_p(omap3_l3_remove),
+        .probe          = omap3_l3_probe,
+        .remove         = omap3_l3_remove,
         .driver         = {
-        .name   = "omap_l3_smx",
+                .name   = "omap_l3_smx",
+                .of_match_table = of_match_ptr(omap3_l3_match),
         },
 };
 
 static int __init omap3_l3_init(void)
 {
-        return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
+        return platform_driver_register(&omap3_l3_driver);
 }
 postcore_initcall_sync(omap3_l3_init);