diff options
Diffstat (limited to 'drivers/block/rsxx/dma.c')
-rw-r--r-- | drivers/block/rsxx/dma.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/drivers/block/rsxx/dma.c b/drivers/block/rsxx/dma.c index 63176e67662f..7c3a57bed2cd 100644 --- a/drivers/block/rsxx/dma.c +++ b/drivers/block/rsxx/dma.c | |||
@@ -432,16 +432,6 @@ static void rsxx_issue_dmas(struct work_struct *work) | |||
432 | 432 | ||
433 | /* Let HW know we've queued commands. */ | 433 | /* Let HW know we've queued commands. */ |
434 | if (cmds_pending) { | 434 | if (cmds_pending) { |
435 | /* | ||
436 | * We must guarantee that the CPU writes to 'ctrl->cmd.buf' | ||
437 | * (which is in PCI-consistent system-memory) from the loop | ||
438 | * above make it into the coherency domain before the | ||
439 | * following PIO "trigger" updating the cmd.idx. A WMB is | ||
440 | * sufficient. We need not explicitly CPU cache-flush since | ||
441 | * the memory is a PCI-consistent (ie; coherent) mapping. | ||
442 | */ | ||
443 | wmb(); | ||
444 | |||
445 | atomic_add(cmds_pending, &ctrl->stats.hw_q_depth); | 435 | atomic_add(cmds_pending, &ctrl->stats.hw_q_depth); |
446 | mod_timer(&ctrl->activity_timer, | 436 | mod_timer(&ctrl->activity_timer, |
447 | jiffies + DMA_ACTIVITY_TIMEOUT); | 437 | jiffies + DMA_ACTIVITY_TIMEOUT); |
@@ -798,8 +788,6 @@ static int rsxx_dma_ctrl_init(struct pci_dev *dev, | |||
798 | iowrite32(ctrl->cmd.idx, ctrl->regmap + HW_CMD_IDX); | 788 | iowrite32(ctrl->cmd.idx, ctrl->regmap + HW_CMD_IDX); |
799 | iowrite32(ctrl->cmd.idx, ctrl->regmap + SW_CMD_IDX); | 789 | iowrite32(ctrl->cmd.idx, ctrl->regmap + SW_CMD_IDX); |
800 | 790 | ||
801 | wmb(); | ||
802 | |||
803 | return 0; | 791 | return 0; |
804 | } | 792 | } |
805 | 793 | ||