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-rw-r--r--drivers/bcma/Kconfig19
-rw-r--r--drivers/bcma/Makefile3
-rw-r--r--drivers/bcma/bcma_private.h31
-rw-r--r--drivers/bcma/core.c10
-rw-r--r--drivers/bcma/driver_chipcommon.c5
-rw-r--r--drivers/bcma/driver_chipcommon_nflash.c19
-rw-r--r--drivers/bcma/driver_chipcommon_pmu.c369
-rw-r--r--drivers/bcma/driver_chipcommon_sflash.c19
-rw-r--r--drivers/bcma/driver_gmac_cmn.c14
-rw-r--r--drivers/bcma/driver_mips.c39
-rw-r--r--drivers/bcma/driver_pci_host.c18
-rw-r--r--drivers/bcma/host_pci.c6
-rw-r--r--drivers/bcma/main.c44
-rw-r--r--drivers/bcma/scan.c63
-rw-r--r--drivers/bcma/scan.h2
-rw-r--r--drivers/bcma/sprom.c30
16 files changed, 515 insertions, 176 deletions
diff --git a/drivers/bcma/Kconfig b/drivers/bcma/Kconfig
index fb7c80fb721e..06b3207adebd 100644
--- a/drivers/bcma/Kconfig
+++ b/drivers/bcma/Kconfig
@@ -46,6 +46,25 @@ config BCMA_DRIVER_MIPS
46 46
47 If unsure, say N 47 If unsure, say N
48 48
49config BCMA_SFLASH
50 bool
51 depends on BCMA_DRIVER_MIPS && BROKEN
52 default y
53
54config BCMA_NFLASH
55 bool
56 depends on BCMA_DRIVER_MIPS && BROKEN
57 default y
58
59config BCMA_DRIVER_GMAC_CMN
60 bool "BCMA Broadcom GBIT MAC COMMON core driver"
61 depends on BCMA
62 help
63 Driver for the Broadcom GBIT MAC COMMON core attached to Broadcom
64 specific Advanced Microcontroller Bus.
65
66 If unsure, say N
67
49config BCMA_DEBUG 68config BCMA_DEBUG
50 bool "BCMA debugging" 69 bool "BCMA debugging"
51 depends on BCMA 70 depends on BCMA
diff --git a/drivers/bcma/Makefile b/drivers/bcma/Makefile
index 82de24e5340c..8ad42d41b2f2 100644
--- a/drivers/bcma/Makefile
+++ b/drivers/bcma/Makefile
@@ -1,8 +1,11 @@
1bcma-y += main.o scan.o core.o sprom.o 1bcma-y += main.o scan.o core.o sprom.o
2bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o 2bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
3bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
4bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
3bcma-y += driver_pci.o 5bcma-y += driver_pci.o
4bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o 6bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
5bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o 7bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
8bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
6bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o 9bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
7bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o 10bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
8obj-$(CONFIG_BCMA) += bcma.o 11obj-$(CONFIG_BCMA) += bcma.o
diff --git a/drivers/bcma/bcma_private.h b/drivers/bcma/bcma_private.h
index b81755bb4798..3cf9cc923cd2 100644
--- a/drivers/bcma/bcma_private.h
+++ b/drivers/bcma/bcma_private.h
@@ -10,6 +10,15 @@
10 10
11#define BCMA_CORE_SIZE 0x1000 11#define BCMA_CORE_SIZE 0x1000
12 12
13#define bcma_err(bus, fmt, ...) \
14 pr_err("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
15#define bcma_warn(bus, fmt, ...) \
16 pr_warn("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
17#define bcma_info(bus, fmt, ...) \
18 pr_info("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
19#define bcma_debug(bus, fmt, ...) \
20 pr_debug("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
21
13struct bcma_bus; 22struct bcma_bus;
14 23
15/* main.c */ 24/* main.c */
@@ -42,6 +51,28 @@ void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
42u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc); 51u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
43u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc); 52u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
44 53
54#ifdef CONFIG_BCMA_SFLASH
55/* driver_chipcommon_sflash.c */
56int bcma_sflash_init(struct bcma_drv_cc *cc);
57#else
58static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
59{
60 bcma_err(cc->core->bus, "Serial flash not supported\n");
61 return 0;
62}
63#endif /* CONFIG_BCMA_SFLASH */
64
65#ifdef CONFIG_BCMA_NFLASH
66/* driver_chipcommon_nflash.c */
67int bcma_nflash_init(struct bcma_drv_cc *cc);
68#else
69static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
70{
71 bcma_err(cc->core->bus, "NAND flash not supported\n");
72 return 0;
73}
74#endif /* CONFIG_BCMA_NFLASH */
75
45#ifdef CONFIG_BCMA_HOST_PCI 76#ifdef CONFIG_BCMA_HOST_PCI
46/* host_pci.c */ 77/* host_pci.c */
47extern int __init bcma_host_pci_init(void); 78extern int __init bcma_host_pci_init(void);
diff --git a/drivers/bcma/core.c b/drivers/bcma/core.c
index bc6e89212ad3..63c8b470536f 100644
--- a/drivers/bcma/core.c
+++ b/drivers/bcma/core.c
@@ -75,7 +75,7 @@ void bcma_core_set_clockmode(struct bcma_device *core,
75 udelay(10); 75 udelay(10);
76 } 76 }
77 if (i) 77 if (i)
78 pr_err("HT force timeout\n"); 78 bcma_err(core->bus, "HT force timeout\n");
79 break; 79 break;
80 case BCMA_CLKMODE_DYNAMIC: 80 case BCMA_CLKMODE_DYNAMIC:
81 bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT); 81 bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT);
@@ -102,9 +102,9 @@ void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, bool on)
102 udelay(10); 102 udelay(10);
103 } 103 }
104 if (i) 104 if (i)
105 pr_err("PLL enable timeout\n"); 105 bcma_err(core->bus, "PLL enable timeout\n");
106 } else { 106 } else {
107 pr_warn("Disabling PLL not supported yet!\n"); 107 bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
108 } 108 }
109} 109}
110EXPORT_SYMBOL_GPL(bcma_core_pll_ctl); 110EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
@@ -120,8 +120,8 @@ u32 bcma_core_dma_translation(struct bcma_device *core)
120 else 120 else
121 return BCMA_DMA_TRANSLATION_DMA32_CMT; 121 return BCMA_DMA_TRANSLATION_DMA32_CMT;
122 default: 122 default:
123 pr_err("DMA translation unknown for host %d\n", 123 bcma_err(core->bus, "DMA translation unknown for host %d\n",
124 core->bus->hosttype); 124 core->bus->hosttype);
125 } 125 }
126 return BCMA_DMA_TRANSLATION_NONE; 126 return BCMA_DMA_TRANSLATION_NONE;
127} 127}
diff --git a/drivers/bcma/driver_chipcommon.c b/drivers/bcma/driver_chipcommon.c
index e9f1b3fd252c..a4c3ebcc4c86 100644
--- a/drivers/bcma/driver_chipcommon.c
+++ b/drivers/bcma/driver_chipcommon.c
@@ -44,7 +44,7 @@ void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
44 if (cc->capabilities & BCMA_CC_CAP_PMU) 44 if (cc->capabilities & BCMA_CC_CAP_PMU)
45 bcma_pmu_init(cc); 45 bcma_pmu_init(cc);
46 if (cc->capabilities & BCMA_CC_CAP_PCTL) 46 if (cc->capabilities & BCMA_CC_CAP_PCTL)
47 pr_err("Power control not implemented!\n"); 47 bcma_err(cc->core->bus, "Power control not implemented!\n");
48 48
49 if (cc->core->id.rev >= 16) { 49 if (cc->core->id.rev >= 16) {
50 if (cc->core->bus->sprom.leddc_on_time && 50 if (cc->core->bus->sprom.leddc_on_time &&
@@ -137,8 +137,7 @@ void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
137 | BCMA_CC_CORECTL_UARTCLKEN); 137 | BCMA_CC_CORECTL_UARTCLKEN);
138 } 138 }
139 } else { 139 } else {
140 pr_err("serial not supported on this device ccrev: 0x%x\n", 140 bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
141 ccrev);
142 return; 141 return;
143 } 142 }
144 143
diff --git a/drivers/bcma/driver_chipcommon_nflash.c b/drivers/bcma/driver_chipcommon_nflash.c
new file mode 100644
index 000000000000..574d62435bc2
--- /dev/null
+++ b/drivers/bcma/driver_chipcommon_nflash.c
@@ -0,0 +1,19 @@
1/*
2 * Broadcom specific AMBA
3 * ChipCommon NAND flash interface
4 *
5 * Licensed under the GNU/GPL. See COPYING for details.
6 */
7
8#include <linux/bcma/bcma.h>
9#include <linux/bcma/bcma_driver_chipcommon.h>
10#include <linux/delay.h>
11
12#include "bcma_private.h"
13
14/* Initialize NAND flash access */
15int bcma_nflash_init(struct bcma_drv_cc *cc)
16{
17 bcma_err(cc->core->bus, "NAND flash support is broken\n");
18 return 0;
19}
diff --git a/drivers/bcma/driver_chipcommon_pmu.c b/drivers/bcma/driver_chipcommon_pmu.c
index 61ce4054b3c3..c9a4f46c5143 100644
--- a/drivers/bcma/driver_chipcommon_pmu.c
+++ b/drivers/bcma/driver_chipcommon_pmu.c
@@ -3,7 +3,8 @@
3 * ChipCommon Power Management Unit driver 3 * ChipCommon Power Management Unit driver
4 * 4 *
5 * Copyright 2009, Michael Buesch <m@bues.ch> 5 * Copyright 2009, Michael Buesch <m@bues.ch>
6 * Copyright 2007, Broadcom Corporation 6 * Copyright 2007, 2011, Broadcom Corporation
7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
7 * 8 *
8 * Licensed under the GNU/GPL. See COPYING for details. 9 * Licensed under the GNU/GPL. See COPYING for details.
9 */ 10 */
@@ -54,39 +55,19 @@ void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
54} 55}
55EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset); 56EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
56 57
57static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
58{
59 struct bcma_bus *bus = cc->core->bus;
60
61 switch (bus->chipinfo.id) {
62 case 0x4313:
63 case 0x4331:
64 case 43224:
65 case 43225:
66 break;
67 default:
68 pr_err("PLL init unknown for device 0x%04X\n",
69 bus->chipinfo.id);
70 }
71}
72
73static void bcma_pmu_resources_init(struct bcma_drv_cc *cc) 58static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
74{ 59{
75 struct bcma_bus *bus = cc->core->bus; 60 struct bcma_bus *bus = cc->core->bus;
76 u32 min_msk = 0, max_msk = 0; 61 u32 min_msk = 0, max_msk = 0;
77 62
78 switch (bus->chipinfo.id) { 63 switch (bus->chipinfo.id) {
79 case 0x4313: 64 case BCMA_CHIP_ID_BCM4313:
80 min_msk = 0x200D; 65 min_msk = 0x200D;
81 max_msk = 0xFFFF; 66 max_msk = 0xFFFF;
82 break; 67 break;
83 case 0x4331:
84 case 43224:
85 case 43225:
86 break;
87 default: 68 default:
88 pr_err("PMU resource config unknown for device 0x%04X\n", 69 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
89 bus->chipinfo.id); 70 bus->chipinfo.id);
90 } 71 }
91 72
92 /* Set the resource masks. */ 73 /* Set the resource masks. */
@@ -94,22 +75,9 @@ static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
94 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk); 75 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
95 if (max_msk) 76 if (max_msk)
96 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk); 77 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
97}
98
99void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
100{
101 struct bcma_bus *bus = cc->core->bus;
102 78
103 switch (bus->chipinfo.id) { 79 /* Add some delay; allow resources to come up and settle. */
104 case 0x4313: 80 mdelay(2);
105 case 0x4331:
106 case 43224:
107 case 43225:
108 break;
109 default:
110 pr_err("PMU switch/regulators init unknown for device "
111 "0x%04X\n", bus->chipinfo.id);
112 }
113} 81}
114 82
115/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */ 83/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
@@ -123,8 +91,11 @@ void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
123 val |= BCMA_CHIPCTL_4331_EXTPA_EN; 91 val |= BCMA_CHIPCTL_4331_EXTPA_EN;
124 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11) 92 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
125 val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; 93 val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
94 else if (bus->chipinfo.rev > 0)
95 val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
126 } else { 96 } else {
127 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN; 97 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
98 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
128 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; 99 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
129 } 100 }
130 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val); 101 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
@@ -135,28 +106,38 @@ void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
135 struct bcma_bus *bus = cc->core->bus; 106 struct bcma_bus *bus = cc->core->bus;
136 107
137 switch (bus->chipinfo.id) { 108 switch (bus->chipinfo.id) {
138 case 0x4313: 109 case BCMA_CHIP_ID_BCM4313:
139 bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7); 110 /* enable 12 mA drive strenth for 4313 and set chipControl
111 register bit 1 */
112 bcma_chipco_chipctl_maskset(cc, 0,
113 ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
114 BCMA_CCTRL_4313_12MA_LED_DRIVE);
140 break; 115 break;
141 case 0x4331: 116 case BCMA_CHIP_ID_BCM4331:
142 case 43431: 117 case BCMA_CHIP_ID_BCM43431:
143 /* Ext PA lines must be enabled for tx on BCM4331 */ 118 /* Ext PA lines must be enabled for tx on BCM4331 */
144 bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true); 119 bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
145 break; 120 break;
146 case 43224: 121 case BCMA_CHIP_ID_BCM43224:
122 case BCMA_CHIP_ID_BCM43421:
123 /* enable 12 mA drive strenth for 43224 and set chipControl
124 register bit 15 */
147 if (bus->chipinfo.rev == 0) { 125 if (bus->chipinfo.rev == 0) {
148 pr_err("Workarounds for 43224 rev 0 not fully " 126 bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
149 "implemented\n"); 127 ~BCMA_CCTRL_43224_GPIO_TOGGLE,
150 bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0); 128 BCMA_CCTRL_43224_GPIO_TOGGLE);
129 bcma_chipco_chipctl_maskset(cc, 0,
130 ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
131 BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
151 } else { 132 } else {
152 bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0); 133 bcma_chipco_chipctl_maskset(cc, 0,
134 ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
135 BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
153 } 136 }
154 break; 137 break;
155 case 43225:
156 break;
157 default: 138 default:
158 pr_err("Workarounds unknown for device 0x%04X\n", 139 bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
159 bus->chipinfo.id); 140 bus->chipinfo.id);
160 } 141 }
161} 142}
162 143
@@ -167,8 +148,8 @@ void bcma_pmu_init(struct bcma_drv_cc *cc)
167 pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP); 148 pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
168 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION); 149 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
169 150
170 pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev, 151 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
171 pmucap); 152 cc->pmu.rev, pmucap);
172 153
173 if (cc->pmu.rev == 1) 154 if (cc->pmu.rev == 1)
174 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, 155 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
@@ -177,12 +158,7 @@ void bcma_pmu_init(struct bcma_drv_cc *cc)
177 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, 158 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
178 BCMA_CC_PMU_CTL_NOILPONW); 159 BCMA_CC_PMU_CTL_NOILPONW);
179 160
180 if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
181 pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
182
183 bcma_pmu_pll_init(cc);
184 bcma_pmu_resources_init(cc); 161 bcma_pmu_resources_init(cc);
185 bcma_pmu_swreg_init(cc);
186 bcma_pmu_workarounds(cc); 162 bcma_pmu_workarounds(cc);
187} 163}
188 164
@@ -191,23 +167,22 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
191 struct bcma_bus *bus = cc->core->bus; 167 struct bcma_bus *bus = cc->core->bus;
192 168
193 switch (bus->chipinfo.id) { 169 switch (bus->chipinfo.id) {
194 case 0x4716: 170 case BCMA_CHIP_ID_BCM4716:
195 case 0x4748: 171 case BCMA_CHIP_ID_BCM4748:
196 case 47162: 172 case BCMA_CHIP_ID_BCM47162:
197 case 0x4313: 173 case BCMA_CHIP_ID_BCM4313:
198 case 0x5357: 174 case BCMA_CHIP_ID_BCM5357:
199 case 0x4749: 175 case BCMA_CHIP_ID_BCM4749:
200 case 53572: 176 case BCMA_CHIP_ID_BCM53572:
201 /* always 20Mhz */ 177 /* always 20Mhz */
202 return 20000 * 1000; 178 return 20000 * 1000;
203 case 0x5356: 179 case BCMA_CHIP_ID_BCM5356:
204 case 0x5300: 180 case BCMA_CHIP_ID_BCM4706:
205 /* always 25Mhz */ 181 /* always 25Mhz */
206 return 25000 * 1000; 182 return 25000 * 1000;
207 default: 183 default:
208 pr_warn("No ALP clock specified for %04X device, " 184 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
209 "pmu rev. %d, using default %d Hz\n", 185 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
210 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
211 } 186 }
212 return BCMA_CC_PMU_ALP_CLOCK; 187 return BCMA_CC_PMU_ALP_CLOCK;
213} 188}
@@ -224,7 +199,8 @@ static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
224 199
225 BUG_ON(!m || m > 4); 200 BUG_ON(!m || m > 4);
226 201
227 if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) { 202 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
203 bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
228 /* Detect failure in clock setting */ 204 /* Detect failure in clock setting */
229 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); 205 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
230 if (tmp & 0x40000) 206 if (tmp & 0x40000)
@@ -250,33 +226,62 @@ static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
250 return (fc / div) * 1000000; 226 return (fc / div) * 1000000;
251} 227}
252 228
229static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
230{
231 u32 tmp, ndiv, p1div, p2div;
232 u32 clock;
233
234 BUG_ON(!m || m > 4);
235
236 /* Get N, P1 and P2 dividers to determine CPU clock */
237 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
238 ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
239 >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
240 p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
241 >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
242 p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
243 >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
244
245 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
246 if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
247 /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
248 clock = (25000000 / 4) * ndiv * p2div / p1div;
249 else
250 /* Fixed reference clock 25MHz and m = 2 */
251 clock = (25000000 / 2) * ndiv * p2div / p1div;
252
253 if (m == BCMA_CC_PMU5_MAINPLL_SSB)
254 clock = clock / 4;
255
256 return clock;
257}
258
253/* query bus clock frequency for PMU-enabled chipcommon */ 259/* query bus clock frequency for PMU-enabled chipcommon */
254u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc) 260u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
255{ 261{
256 struct bcma_bus *bus = cc->core->bus; 262 struct bcma_bus *bus = cc->core->bus;
257 263
258 switch (bus->chipinfo.id) { 264 switch (bus->chipinfo.id) {
259 case 0x4716: 265 case BCMA_CHIP_ID_BCM4716:
260 case 0x4748: 266 case BCMA_CHIP_ID_BCM4748:
261 case 47162: 267 case BCMA_CHIP_ID_BCM47162:
262 return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0, 268 return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
263 BCMA_CC_PMU5_MAINPLL_SSB); 269 BCMA_CC_PMU5_MAINPLL_SSB);
264 case 0x5356: 270 case BCMA_CHIP_ID_BCM5356:
265 return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0, 271 return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
266 BCMA_CC_PMU5_MAINPLL_SSB); 272 BCMA_CC_PMU5_MAINPLL_SSB);
267 case 0x5357: 273 case BCMA_CHIP_ID_BCM5357:
268 case 0x4749: 274 case BCMA_CHIP_ID_BCM4749:
269 return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0, 275 return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
270 BCMA_CC_PMU5_MAINPLL_SSB); 276 BCMA_CC_PMU5_MAINPLL_SSB);
271 case 0x5300: 277 case BCMA_CHIP_ID_BCM4706:
272 return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0, 278 return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
273 BCMA_CC_PMU5_MAINPLL_SSB); 279 BCMA_CC_PMU5_MAINPLL_SSB);
274 case 53572: 280 case BCMA_CHIP_ID_BCM53572:
275 return 75000000; 281 return 75000000;
276 default: 282 default:
277 pr_warn("No backplane clock specified for %04X device, " 283 bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
278 "pmu rev. %d, using default %d Hz\n", 284 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
279 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
280 } 285 }
281 return BCMA_CC_PMU_HT_CLOCK; 286 return BCMA_CC_PMU_HT_CLOCK;
282} 287}
@@ -286,17 +291,21 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
286{ 291{
287 struct bcma_bus *bus = cc->core->bus; 292 struct bcma_bus *bus = cc->core->bus;
288 293
289 if (bus->chipinfo.id == 53572) 294 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
290 return 300000000; 295 return 300000000;
291 296
292 if (cc->pmu.rev >= 5) { 297 if (cc->pmu.rev >= 5) {
293 u32 pll; 298 u32 pll;
294 switch (bus->chipinfo.id) { 299 switch (bus->chipinfo.id) {
295 case 0x5356: 300 case BCMA_CHIP_ID_BCM4706:
301 return bcma_pmu_clock_bcm4706(cc,
302 BCMA_CC_PMU4706_MAINPLL_PLL0,
303 BCMA_CC_PMU5_MAINPLL_CPU);
304 case BCMA_CHIP_ID_BCM5356:
296 pll = BCMA_CC_PMU5356_MAINPLL_PLL0; 305 pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
297 break; 306 break;
298 case 0x5357: 307 case BCMA_CHIP_ID_BCM5357:
299 case 0x4749: 308 case BCMA_CHIP_ID_BCM4749:
300 pll = BCMA_CC_PMU5357_MAINPLL_PLL0; 309 pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
301 break; 310 break;
302 default: 311 default:
@@ -304,10 +313,188 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
304 break; 313 break;
305 } 314 }
306 315
307 /* TODO: if (bus->chipinfo.id == 0x5300)
308 return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
309 return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU); 316 return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
310 } 317 }
311 318
312 return bcma_pmu_get_clockcontrol(cc); 319 return bcma_pmu_get_clockcontrol(cc);
313} 320}
321
322static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
323 u32 value)
324{
325 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
326 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
327}
328
329void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
330{
331 u32 tmp = 0;
332 u8 phypll_offset = 0;
333 u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
334 u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
335 struct bcma_bus *bus = cc->core->bus;
336
337 switch (bus->chipinfo.id) {
338 case BCMA_CHIP_ID_BCM5357:
339 case BCMA_CHIP_ID_BCM4749:
340 case BCMA_CHIP_ID_BCM53572:
341 /* 5357[ab]0, 43236[ab]0, and 6362b0 */
342
343 /* BCM5357 needs to touch PLL1_PLLCTL[02],
344 so offset PLL0_PLLCTL[02] by 6 */
345 phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
346 bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
347 bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
348
349 /* RMW only the P1 divider */
350 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
351 BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
352 tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
353 tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
354 tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
355 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
356
357 /* RMW only the int feedback divider */
358 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
359 BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
360 tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
361 tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
362 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
363 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
364
365 tmp = 1 << 10;
366 break;
367
368 case BCMA_CHIP_ID_BCM4331:
369 case BCMA_CHIP_ID_BCM43431:
370 if (spuravoid == 2) {
371 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
372 0x11500014);
373 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
374 0x0FC00a08);
375 } else if (spuravoid == 1) {
376 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
377 0x11500014);
378 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
379 0x0F600a08);
380 } else {
381 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
382 0x11100014);
383 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
384 0x03000a08);
385 }
386 tmp = 1 << 10;
387 break;
388
389 case BCMA_CHIP_ID_BCM43224:
390 case BCMA_CHIP_ID_BCM43225:
391 case BCMA_CHIP_ID_BCM43421:
392 if (spuravoid == 1) {
393 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
394 0x11500010);
395 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
396 0x000C0C06);
397 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
398 0x0F600a08);
399 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
400 0x00000000);
401 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
402 0x2001E920);
403 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
404 0x88888815);
405 } else {
406 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
407 0x11100010);
408 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
409 0x000c0c06);
410 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
411 0x03000a08);
412 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
413 0x00000000);
414 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
415 0x200005c0);
416 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
417 0x88888815);
418 }
419 tmp = 1 << 10;
420 break;
421
422 case BCMA_CHIP_ID_BCM4716:
423 case BCMA_CHIP_ID_BCM4748:
424 case BCMA_CHIP_ID_BCM47162:
425 if (spuravoid == 1) {
426 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
427 0x11500060);
428 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
429 0x080C0C06);
430 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
431 0x0F600000);
432 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
433 0x00000000);
434 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
435 0x2001E924);
436 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
437 0x88888815);
438 } else {
439 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
440 0x11100060);
441 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
442 0x080c0c06);
443 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
444 0x03000000);
445 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
446 0x00000000);
447 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
448 0x200005c0);
449 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
450 0x88888815);
451 }
452
453 tmp = 3 << 9;
454 break;
455
456 case BCMA_CHIP_ID_BCM43227:
457 case BCMA_CHIP_ID_BCM43228:
458 case BCMA_CHIP_ID_BCM43428:
459 /* LCNXN */
460 /* PLL Settings for spur avoidance on/off mode,
461 no on2 support for 43228A0 */
462 if (spuravoid == 1) {
463 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
464 0x01100014);
465 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
466 0x040C0C06);
467 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
468 0x03140A08);
469 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
470 0x00333333);
471 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
472 0x202C2820);
473 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
474 0x88888815);
475 } else {
476 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
477 0x11100014);
478 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
479 0x040c0c06);
480 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
481 0x03000a08);
482 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
483 0x00000000);
484 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
485 0x200005c0);
486 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
487 0x88888815);
488 }
489 tmp = 1 << 10;
490 break;
491 default:
492 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
493 bus->chipinfo.id);
494 break;
495 }
496
497 tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
498 bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
499}
500EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
diff --git a/drivers/bcma/driver_chipcommon_sflash.c b/drivers/bcma/driver_chipcommon_sflash.c
new file mode 100644
index 000000000000..6e157a58a1d7
--- /dev/null
+++ b/drivers/bcma/driver_chipcommon_sflash.c
@@ -0,0 +1,19 @@
1/*
2 * Broadcom specific AMBA
3 * ChipCommon serial flash interface
4 *
5 * Licensed under the GNU/GPL. See COPYING for details.
6 */
7
8#include <linux/bcma/bcma.h>
9#include <linux/bcma/bcma_driver_chipcommon.h>
10#include <linux/delay.h>
11
12#include "bcma_private.h"
13
14/* Initialize serial flash access */
15int bcma_sflash_init(struct bcma_drv_cc *cc)
16{
17 bcma_err(cc->core->bus, "Serial flash support is broken\n");
18 return 0;
19}
diff --git a/drivers/bcma/driver_gmac_cmn.c b/drivers/bcma/driver_gmac_cmn.c
new file mode 100644
index 000000000000..834225f65e8f
--- /dev/null
+++ b/drivers/bcma/driver_gmac_cmn.c
@@ -0,0 +1,14 @@
1/*
2 * Broadcom specific AMBA
3 * GBIT MAC COMMON Core
4 *
5 * Licensed under the GNU/GPL. See COPYING for details.
6 */
7
8#include "bcma_private.h"
9#include <linux/bcma/bcma.h>
10
11void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc)
12{
13 mutex_init(&gc->phy_mutex);
14}
diff --git a/drivers/bcma/driver_mips.c b/drivers/bcma/driver_mips.c
index c3e9dff4224e..cc65b45b4368 100644
--- a/drivers/bcma/driver_mips.c
+++ b/drivers/bcma/driver_mips.c
@@ -22,15 +22,15 @@
22/* The 47162a0 hangs when reading MIPS DMP registers registers */ 22/* The 47162a0 hangs when reading MIPS DMP registers registers */
23static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev) 23static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
24{ 24{
25 return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 && 25 return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
26 dev->id.id == BCMA_CORE_MIPS_74K; 26 dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
27} 27}
28 28
29/* The 5357b0 hangs when reading USB20H DMP registers */ 29/* The 5357b0 hangs when reading USB20H DMP registers */
30static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev) 30static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
31{ 31{
32 return (dev->bus->chipinfo.id == 0x5357 || 32 return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
33 dev->bus->chipinfo.id == 0x4749) && 33 dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
34 dev->bus->chipinfo.pkg == 11 && 34 dev->bus->chipinfo.pkg == 11 &&
35 dev->id.id == BCMA_CORE_USB20_HOST; 35 dev->id.id == BCMA_CORE_USB20_HOST;
36} 36}
@@ -131,7 +131,7 @@ static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
131 /* backplane irq line is in use, find out who uses 131 /* backplane irq line is in use, find out who uses
132 * it and set user to irq 0 132 * it and set user to irq 0
133 */ 133 */
134 list_for_each_entry_reverse(core, &bus->cores, list) { 134 list_for_each_entry(core, &bus->cores, list) {
135 if ((1 << bcma_core_mips_irqflag(core)) == 135 if ((1 << bcma_core_mips_irqflag(core)) ==
136 oldirqflag) { 136 oldirqflag) {
137 bcma_core_mips_set_irq(core, 0); 137 bcma_core_mips_set_irq(core, 0);
@@ -143,8 +143,8 @@ static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
143 1 << irqflag); 143 1 << irqflag);
144 } 144 }
145 145
146 pr_info("set_irq: core 0x%04x, irq %d => %d\n", 146 bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
147 dev->id.id, oldirq + 2, irq + 2); 147 dev->id.id, oldirq + 2, irq + 2);
148} 148}
149 149
150static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq) 150static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
@@ -161,7 +161,7 @@ static void bcma_core_mips_dump_irq(struct bcma_bus *bus)
161{ 161{
162 struct bcma_device *core; 162 struct bcma_device *core;
163 163
164 list_for_each_entry_reverse(core, &bus->cores, list) { 164 list_for_each_entry(core, &bus->cores, list) {
165 bcma_core_mips_print_irq(core, bcma_core_mips_irq(core)); 165 bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
166 } 166 }
167} 167}
@@ -173,7 +173,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
173 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) 173 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
174 return bcma_pmu_get_clockcpu(&bus->drv_cc); 174 return bcma_pmu_get_clockcpu(&bus->drv_cc);
175 175
176 pr_err("No PMU available, need this to get the cpu clock\n"); 176 bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
177 return 0; 177 return 0;
178} 178}
179EXPORT_SYMBOL(bcma_cpu_clock); 179EXPORT_SYMBOL(bcma_cpu_clock);
@@ -185,10 +185,11 @@ static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
185 switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) { 185 switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
186 case BCMA_CC_FLASHT_STSER: 186 case BCMA_CC_FLASHT_STSER:
187 case BCMA_CC_FLASHT_ATSER: 187 case BCMA_CC_FLASHT_ATSER:
188 pr_err("Serial flash not supported.\n"); 188 bcma_debug(bus, "Found serial flash\n");
189 bcma_sflash_init(&bus->drv_cc);
189 break; 190 break;
190 case BCMA_CC_FLASHT_PARA: 191 case BCMA_CC_FLASHT_PARA:
191 pr_info("found parallel flash.\n"); 192 bcma_debug(bus, "Found parallel flash\n");
192 bus->drv_cc.pflash.window = 0x1c000000; 193 bus->drv_cc.pflash.window = 0x1c000000;
193 bus->drv_cc.pflash.window_size = 0x02000000; 194 bus->drv_cc.pflash.window_size = 0x02000000;
194 195
@@ -199,7 +200,15 @@ static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
199 bus->drv_cc.pflash.buswidth = 2; 200 bus->drv_cc.pflash.buswidth = 2;
200 break; 201 break;
201 default: 202 default:
202 pr_err("flash not supported.\n"); 203 bcma_err(bus, "Flash type not supported\n");
204 }
205
206 if (bus->drv_cc.core->id.rev == 38 ||
207 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
208 if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
209 bcma_debug(bus, "Found NAND flash\n");
210 bcma_nflash_init(&bus->drv_cc);
211 }
203 } 212 }
204} 213}
205 214
@@ -209,13 +218,13 @@ void bcma_core_mips_init(struct bcma_drv_mips *mcore)
209 struct bcma_device *core; 218 struct bcma_device *core;
210 bus = mcore->core->bus; 219 bus = mcore->core->bus;
211 220
212 pr_info("Initializing MIPS core...\n"); 221 bcma_info(bus, "Initializing MIPS core...\n");
213 222
214 if (!mcore->setup_done) 223 if (!mcore->setup_done)
215 mcore->assigned_irqs = 1; 224 mcore->assigned_irqs = 1;
216 225
217 /* Assign IRQs to all cores on the bus */ 226 /* Assign IRQs to all cores on the bus */
218 list_for_each_entry_reverse(core, &bus->cores, list) { 227 list_for_each_entry(core, &bus->cores, list) {
219 int mips_irq; 228 int mips_irq;
220 if (core->irq) 229 if (core->irq)
221 continue; 230 continue;
@@ -244,7 +253,7 @@ void bcma_core_mips_init(struct bcma_drv_mips *mcore)
244 break; 253 break;
245 } 254 }
246 } 255 }
247 pr_info("IRQ reconfiguration done\n"); 256 bcma_info(bus, "IRQ reconfiguration done\n");
248 bcma_core_mips_dump_irq(bus); 257 bcma_core_mips_dump_irq(bus);
249 258
250 if (mcore->setup_done) 259 if (mcore->setup_done)
diff --git a/drivers/bcma/driver_pci_host.c b/drivers/bcma/driver_pci_host.c
index b9a86edfec39..cbae2c231336 100644
--- a/drivers/bcma/driver_pci_host.c
+++ b/drivers/bcma/driver_pci_host.c
@@ -36,7 +36,7 @@ bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
36 return false; 36 return false;
37 37
38 if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) { 38 if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
39 pr_info("This PCI core is disabled and not working\n"); 39 bcma_info(bus, "This PCI core is disabled and not working\n");
40 return false; 40 return false;
41 } 41 }
42 42
@@ -215,7 +215,8 @@ static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
215 } else { 215 } else {
216 writel(val, mmio); 216 writel(val, mmio);
217 217
218 if (chipid == 0x4716 || chipid == 0x4748) 218 if (chipid == BCMA_CHIP_ID_BCM4716 ||
219 chipid == BCMA_CHIP_ID_BCM4748)
219 readl(mmio); 220 readl(mmio);
220 } 221 }
221 222
@@ -340,6 +341,7 @@ static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
340 */ 341 */
341static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc) 342static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
342{ 343{
344 struct bcma_bus *bus = pc->core->bus;
343 u8 cap_ptr, root_ctrl, root_cap, dev; 345 u8 cap_ptr, root_ctrl, root_cap, dev;
344 u16 val16; 346 u16 val16;
345 int i; 347 int i;
@@ -378,7 +380,8 @@ static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
378 udelay(10); 380 udelay(10);
379 } 381 }
380 if (val16 == 0x1) 382 if (val16 == 0x1)
381 pr_err("PCI: Broken device in slot %d\n", dev); 383 bcma_err(bus, "PCI: Broken device in slot %d\n",
384 dev);
382 } 385 }
383 } 386 }
384} 387}
@@ -391,11 +394,11 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
391 u32 pci_membase_1G; 394 u32 pci_membase_1G;
392 unsigned long io_map_base; 395 unsigned long io_map_base;
393 396
394 pr_info("PCIEcore in host mode found\n"); 397 bcma_info(bus, "PCIEcore in host mode found\n");
395 398
396 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL); 399 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
397 if (!pc_host) { 400 if (!pc_host) {
398 pr_err("can not allocate memory"); 401 bcma_err(bus, "can not allocate memory");
399 return; 402 return;
400 } 403 }
401 404
@@ -434,13 +437,14 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
434 * as mips can't generate 64-bit address on the 437 * as mips can't generate 64-bit address on the
435 * backplane. 438 * backplane.
436 */ 439 */
437 if (bus->chipinfo.id == 0x4716 || bus->chipinfo.id == 0x4748) { 440 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
441 bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
438 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; 442 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
439 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + 443 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
440 BCMA_SOC_PCI_MEM_SZ - 1; 444 BCMA_SOC_PCI_MEM_SZ - 1;
441 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, 445 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
442 BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM); 446 BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
443 } else if (bus->chipinfo.id == 0x5300) { 447 } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
444 tmp = BCMA_CORE_PCI_SBTOPCI_MEM; 448 tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
445 tmp |= BCMA_CORE_PCI_SBTOPCI_PREF; 449 tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
446 tmp |= BCMA_CORE_PCI_SBTOPCI_BURST; 450 tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
diff --git a/drivers/bcma/host_pci.c b/drivers/bcma/host_pci.c
index 6c05cf470f96..a6e5672c67e7 100644
--- a/drivers/bcma/host_pci.c
+++ b/drivers/bcma/host_pci.c
@@ -18,7 +18,7 @@ static void bcma_host_pci_switch_core(struct bcma_device *core)
18 pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2, 18 pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
19 core->wrap); 19 core->wrap);
20 core->bus->mapped_core = core; 20 core->bus->mapped_core = core;
21 pr_debug("Switched to core: 0x%X\n", core->id.id); 21 bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
22} 22}
23 23
24/* Provides access to the requested core. Returns base offset that has to be 24/* Provides access to the requested core. Returns base offset that has to be
@@ -188,7 +188,7 @@ static int __devinit bcma_host_pci_probe(struct pci_dev *dev,
188 188
189 /* SSB needed additional powering up, do we have any AMBA PCI cards? */ 189 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
190 if (!pci_is_pcie(dev)) 190 if (!pci_is_pcie(dev))
191 pr_err("PCI card detected, report problems.\n"); 191 bcma_err(bus, "PCI card detected, report problems.\n");
192 192
193 /* Map MMIO */ 193 /* Map MMIO */
194 err = -ENOMEM; 194 err = -ENOMEM;
@@ -268,9 +268,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bcma_host_pci_suspend,
268 268
269static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = { 269static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
270 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) }, 270 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
271 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
271 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) }, 272 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
272 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) }, 273 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
273 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) }, 274 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
275 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
274 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) }, 276 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
275 { 0, }, 277 { 0, },
276}; 278};
diff --git a/drivers/bcma/main.c b/drivers/bcma/main.c
index 7e138ec21357..758af9ccdef0 100644
--- a/drivers/bcma/main.c
+++ b/drivers/bcma/main.c
@@ -61,6 +61,13 @@ static struct bus_type bcma_bus_type = {
61 .dev_attrs = bcma_device_attrs, 61 .dev_attrs = bcma_device_attrs,
62}; 62};
63 63
64static u16 bcma_cc_core_id(struct bcma_bus *bus)
65{
66 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
67 return BCMA_CORE_4706_CHIPCOMMON;
68 return BCMA_CORE_CHIPCOMMON;
69}
70
64struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid) 71struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
65{ 72{
66 struct bcma_device *core; 73 struct bcma_device *core;
@@ -91,10 +98,12 @@ static int bcma_register_cores(struct bcma_bus *bus)
91 list_for_each_entry(core, &bus->cores, list) { 98 list_for_each_entry(core, &bus->cores, list) {
92 /* We support that cores ourself */ 99 /* We support that cores ourself */
93 switch (core->id.id) { 100 switch (core->id.id) {
101 case BCMA_CORE_4706_CHIPCOMMON:
94 case BCMA_CORE_CHIPCOMMON: 102 case BCMA_CORE_CHIPCOMMON:
95 case BCMA_CORE_PCI: 103 case BCMA_CORE_PCI:
96 case BCMA_CORE_PCIE: 104 case BCMA_CORE_PCIE:
97 case BCMA_CORE_MIPS_74K: 105 case BCMA_CORE_MIPS_74K:
106 case BCMA_CORE_4706_MAC_GBIT_COMMON:
98 continue; 107 continue;
99 } 108 }
100 109
@@ -118,8 +127,9 @@ static int bcma_register_cores(struct bcma_bus *bus)
118 127
119 err = device_register(&core->dev); 128 err = device_register(&core->dev);
120 if (err) { 129 if (err) {
121 pr_err("Could not register dev for core 0x%03X\n", 130 bcma_err(bus,
122 core->id.id); 131 "Could not register dev for core 0x%03X\n",
132 core->id.id);
123 continue; 133 continue;
124 } 134 }
125 core->dev_registered = true; 135 core->dev_registered = true;
@@ -151,12 +161,12 @@ int __devinit bcma_bus_register(struct bcma_bus *bus)
151 /* Scan for devices (cores) */ 161 /* Scan for devices (cores) */
152 err = bcma_bus_scan(bus); 162 err = bcma_bus_scan(bus);
153 if (err) { 163 if (err) {
154 pr_err("Failed to scan: %d\n", err); 164 bcma_err(bus, "Failed to scan: %d\n", err);
155 return -1; 165 return -1;
156 } 166 }
157 167
158 /* Init CC core */ 168 /* Init CC core */
159 core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON); 169 core = bcma_find_core(bus, bcma_cc_core_id(bus));
160 if (core) { 170 if (core) {
161 bus->drv_cc.core = core; 171 bus->drv_cc.core = core;
162 bcma_core_chipcommon_init(&bus->drv_cc); 172 bcma_core_chipcommon_init(&bus->drv_cc);
@@ -176,17 +186,24 @@ int __devinit bcma_bus_register(struct bcma_bus *bus)
176 bcma_core_pci_init(&bus->drv_pci); 186 bcma_core_pci_init(&bus->drv_pci);
177 } 187 }
178 188
189 /* Init GBIT MAC COMMON core */
190 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
191 if (core) {
192 bus->drv_gmac_cmn.core = core;
193 bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
194 }
195
179 /* Try to get SPROM */ 196 /* Try to get SPROM */
180 err = bcma_sprom_get(bus); 197 err = bcma_sprom_get(bus);
181 if (err == -ENOENT) { 198 if (err == -ENOENT) {
182 pr_err("No SPROM available\n"); 199 bcma_err(bus, "No SPROM available\n");
183 } else if (err) 200 } else if (err)
184 pr_err("Failed to get SPROM: %d\n", err); 201 bcma_err(bus, "Failed to get SPROM: %d\n", err);
185 202
186 /* Register found cores */ 203 /* Register found cores */
187 bcma_register_cores(bus); 204 bcma_register_cores(bus);
188 205
189 pr_info("Bus registered\n"); 206 bcma_info(bus, "Bus registered\n");
190 207
191 return 0; 208 return 0;
192} 209}
@@ -207,14 +224,14 @@ int __init bcma_bus_early_register(struct bcma_bus *bus,
207 bcma_init_bus(bus); 224 bcma_init_bus(bus);
208 225
209 match.manuf = BCMA_MANUF_BCM; 226 match.manuf = BCMA_MANUF_BCM;
210 match.id = BCMA_CORE_CHIPCOMMON; 227 match.id = bcma_cc_core_id(bus);
211 match.class = BCMA_CL_SIM; 228 match.class = BCMA_CL_SIM;
212 match.rev = BCMA_ANY_REV; 229 match.rev = BCMA_ANY_REV;
213 230
214 /* Scan for chip common core */ 231 /* Scan for chip common core */
215 err = bcma_bus_scan_early(bus, &match, core_cc); 232 err = bcma_bus_scan_early(bus, &match, core_cc);
216 if (err) { 233 if (err) {
217 pr_err("Failed to scan for common core: %d\n", err); 234 bcma_err(bus, "Failed to scan for common core: %d\n", err);
218 return -1; 235 return -1;
219 } 236 }
220 237
@@ -226,12 +243,12 @@ int __init bcma_bus_early_register(struct bcma_bus *bus,
226 /* Scan for mips core */ 243 /* Scan for mips core */
227 err = bcma_bus_scan_early(bus, &match, core_mips); 244 err = bcma_bus_scan_early(bus, &match, core_mips);
228 if (err) { 245 if (err) {
229 pr_err("Failed to scan for mips core: %d\n", err); 246 bcma_err(bus, "Failed to scan for mips core: %d\n", err);
230 return -1; 247 return -1;
231 } 248 }
232 249
233 /* Init CC core */ 250 /* Init CC core */
234 core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON); 251 core = bcma_find_core(bus, bcma_cc_core_id(bus));
235 if (core) { 252 if (core) {
236 bus->drv_cc.core = core; 253 bus->drv_cc.core = core;
237 bcma_core_chipcommon_init(&bus->drv_cc); 254 bcma_core_chipcommon_init(&bus->drv_cc);
@@ -244,7 +261,7 @@ int __init bcma_bus_early_register(struct bcma_bus *bus,
244 bcma_core_mips_init(&bus->drv_mips); 261 bcma_core_mips_init(&bus->drv_mips);
245 } 262 }
246 263
247 pr_info("Early bus registered\n"); 264 bcma_info(bus, "Early bus registered\n");
248 265
249 return 0; 266 return 0;
250} 267}
@@ -270,8 +287,7 @@ int bcma_bus_resume(struct bcma_bus *bus)
270 struct bcma_device *core; 287 struct bcma_device *core;
271 288
272 /* Init CC core */ 289 /* Init CC core */
273 core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON); 290 if (bus->drv_cc.core) {
274 if (core) {
275 bus->drv_cc.setup_done = false; 291 bus->drv_cc.setup_done = false;
276 bcma_core_chipcommon_init(&bus->drv_cc); 292 bcma_core_chipcommon_init(&bus->drv_cc);
277 } 293 }
diff --git a/drivers/bcma/scan.c b/drivers/bcma/scan.c
index 5ed0718fc660..8d0b57164018 100644
--- a/drivers/bcma/scan.c
+++ b/drivers/bcma/scan.c
@@ -21,6 +21,7 @@ struct bcma_device_id_name {
21}; 21};
22 22
23static const struct bcma_device_id_name bcma_arm_device_names[] = { 23static const struct bcma_device_id_name bcma_arm_device_names[] = {
24 { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" },
24 { BCMA_CORE_ARM_1176, "ARM 1176" }, 25 { BCMA_CORE_ARM_1176, "ARM 1176" },
25 { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" }, 26 { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
26 { BCMA_CORE_ARM_CM3, "ARM CM3" }, 27 { BCMA_CORE_ARM_CM3, "ARM CM3" },
@@ -28,6 +29,11 @@ static const struct bcma_device_id_name bcma_arm_device_names[] = {
28 29
29static const struct bcma_device_id_name bcma_bcm_device_names[] = { 30static const struct bcma_device_id_name bcma_bcm_device_names[] = {
30 { BCMA_CORE_OOB_ROUTER, "OOB Router" }, 31 { BCMA_CORE_OOB_ROUTER, "OOB Router" },
32 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
33 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
34 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
35 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
36 { BCMA_CORE_ALTA, "ALTA (I2S)" },
31 { BCMA_CORE_INVALID, "Invalid" }, 37 { BCMA_CORE_INVALID, "Invalid" },
32 { BCMA_CORE_CHIPCOMMON, "ChipCommon" }, 38 { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
33 { BCMA_CORE_ILINE20, "ILine 20" }, 39 { BCMA_CORE_ILINE20, "ILine 20" },
@@ -289,11 +295,15 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
289 295
290 /* check if component is a core at all */ 296 /* check if component is a core at all */
291 if (wrappers[0] + wrappers[1] == 0) { 297 if (wrappers[0] + wrappers[1] == 0) {
292 /* we could save addrl of the router 298 /* Some specific cores don't need wrappers */
293 if (cid == BCMA_CORE_OOB_ROUTER) 299 switch (core->id.id) {
294 */ 300 case BCMA_CORE_4706_MAC_GBIT_COMMON:
295 bcma_erom_skip_component(bus, eromptr); 301 /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
296 return -ENXIO; 302 break;
303 default:
304 bcma_erom_skip_component(bus, eromptr);
305 return -ENXIO;
306 }
297 } 307 }
298 308
299 if (bcma_erom_is_bridge(bus, eromptr)) { 309 if (bcma_erom_is_bridge(bus, eromptr)) {
@@ -334,7 +344,7 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
334 if (tmp <= 0) { 344 if (tmp <= 0) {
335 return -EILSEQ; 345 return -EILSEQ;
336 } else { 346 } else {
337 pr_info("Bridge found\n"); 347 bcma_info(bus, "Bridge found\n");
338 return -ENXIO; 348 return -ENXIO;
339 } 349 }
340 } 350 }
@@ -421,8 +431,8 @@ void bcma_init_bus(struct bcma_bus *bus)
421 chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT; 431 chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
422 chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT; 432 chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
423 chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT; 433 chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
424 pr_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n", 434 bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
425 chipinfo->id, chipinfo->rev, chipinfo->pkg); 435 chipinfo->id, chipinfo->rev, chipinfo->pkg);
426 436
427 bus->init_done = true; 437 bus->init_done = true;
428} 438}
@@ -452,8 +462,10 @@ int bcma_bus_scan(struct bcma_bus *bus)
452 while (eromptr < eromend) { 462 while (eromptr < eromend) {
453 struct bcma_device *other_core; 463 struct bcma_device *other_core;
454 struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL); 464 struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
455 if (!core) 465 if (!core) {
456 return -ENOMEM; 466 err = -ENOMEM;
467 goto out;
468 }
457 INIT_LIST_HEAD(&core->list); 469 INIT_LIST_HEAD(&core->list);
458 core->bus = bus; 470 core->bus = bus;
459 471
@@ -468,7 +480,7 @@ int bcma_bus_scan(struct bcma_bus *bus)
468 } else if (err == -ESPIPE) { 480 } else if (err == -ESPIPE) {
469 break; 481 break;
470 } 482 }
471 return err; 483 goto out;
472 } 484 }
473 485
474 core->core_index = core_num++; 486 core->core_index = core_num++;
@@ -476,19 +488,20 @@ int bcma_bus_scan(struct bcma_bus *bus)
476 other_core = bcma_find_core_reverse(bus, core->id.id); 488 other_core = bcma_find_core_reverse(bus, core->id.id);
477 core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1; 489 core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
478 490
479 pr_info("Core %d found: %s " 491 bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
480 "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", 492 core->core_index, bcma_device_name(&core->id),
481 core->core_index, bcma_device_name(&core->id), 493 core->id.manuf, core->id.id, core->id.rev,
482 core->id.manuf, core->id.id, core->id.rev, 494 core->id.class);
483 core->id.class);
484 495
485 list_add(&core->list, &bus->cores); 496 list_add_tail(&core->list, &bus->cores);
486 } 497 }
487 498
499 err = 0;
500out:
488 if (bus->hosttype == BCMA_HOSTTYPE_SOC) 501 if (bus->hosttype == BCMA_HOSTTYPE_SOC)
489 iounmap(eromptr); 502 iounmap(eromptr);
490 503
491 return 0; 504 return err;
492} 505}
493 506
494int __init bcma_bus_scan_early(struct bcma_bus *bus, 507int __init bcma_bus_scan_early(struct bcma_bus *bus,
@@ -528,21 +541,21 @@ int __init bcma_bus_scan_early(struct bcma_bus *bus,
528 else if (err == -ESPIPE) 541 else if (err == -ESPIPE)
529 break; 542 break;
530 else if (err < 0) 543 else if (err < 0)
531 return err; 544 goto out;
532 545
533 core->core_index = core_num++; 546 core->core_index = core_num++;
534 bus->nr_cores++; 547 bus->nr_cores++;
535 pr_info("Core %d found: %s " 548 bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
536 "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", 549 core->core_index, bcma_device_name(&core->id),
537 core->core_index, bcma_device_name(&core->id), 550 core->id.manuf, core->id.id, core->id.rev,
538 core->id.manuf, core->id.id, core->id.rev, 551 core->id.class);
539 core->id.class);
540 552
541 list_add(&core->list, &bus->cores); 553 list_add_tail(&core->list, &bus->cores);
542 err = 0; 554 err = 0;
543 break; 555 break;
544 } 556 }
545 557
558out:
546 if (bus->hosttype == BCMA_HOSTTYPE_SOC) 559 if (bus->hosttype == BCMA_HOSTTYPE_SOC)
547 iounmap(eromptr); 560 iounmap(eromptr);
548 561
diff --git a/drivers/bcma/scan.h b/drivers/bcma/scan.h
index 113e6a66884c..30eb475e4d19 100644
--- a/drivers/bcma/scan.h
+++ b/drivers/bcma/scan.h
@@ -27,7 +27,7 @@
27#define SCAN_CIB_NMW 0x0007C000 27#define SCAN_CIB_NMW 0x0007C000
28#define SCAN_CIB_NMW_SHIFT 14 28#define SCAN_CIB_NMW_SHIFT 14
29#define SCAN_CIB_NSW 0x00F80000 29#define SCAN_CIB_NSW 0x00F80000
30#define SCAN_CIB_NSW_SHIFT 17 30#define SCAN_CIB_NSW_SHIFT 19
31#define SCAN_CIB_REV 0xFF000000 31#define SCAN_CIB_REV 0xFF000000
32#define SCAN_CIB_REV_SHIFT 24 32#define SCAN_CIB_REV_SHIFT 24
33 33
diff --git a/drivers/bcma/sprom.c b/drivers/bcma/sprom.c
index f16f42d36071..9ea4627dc0c2 100644
--- a/drivers/bcma/sprom.c
+++ b/drivers/bcma/sprom.c
@@ -60,11 +60,11 @@ static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus,
60 if (err) 60 if (err)
61 goto fail; 61 goto fail;
62 62
63 pr_debug("Using SPROM revision %d provided by" 63 bcma_debug(bus, "Using SPROM revision %d provided by platform.\n",
64 " platform.\n", bus->sprom.revision); 64 bus->sprom.revision);
65 return 0; 65 return 0;
66fail: 66fail:
67 pr_warn("Using fallback SPROM failed (err %d)\n", err); 67 bcma_warn(bus, "Using fallback SPROM failed (err %d)\n", err);
68 return err; 68 return err;
69} 69}
70 70
@@ -468,11 +468,11 @@ static bool bcma_sprom_ext_available(struct bcma_bus *bus)
468 /* older chipcommon revisions use chip status register */ 468 /* older chipcommon revisions use chip status register */
469 chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT); 469 chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
470 switch (bus->chipinfo.id) { 470 switch (bus->chipinfo.id) {
471 case 0x4313: 471 case BCMA_CHIP_ID_BCM4313:
472 present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT; 472 present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
473 break; 473 break;
474 474
475 case 0x4331: 475 case BCMA_CHIP_ID_BCM4331:
476 present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT; 476 present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
477 break; 477 break;
478 478
@@ -494,20 +494,22 @@ static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
494 494
495 chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT); 495 chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
496 switch (bus->chipinfo.id) { 496 switch (bus->chipinfo.id) {
497 case 0x4313: 497 case BCMA_CHIP_ID_BCM4313:
498 present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT; 498 present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
499 break; 499 break;
500 500
501 case 0x4331: 501 case BCMA_CHIP_ID_BCM4331:
502 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT; 502 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
503 break; 503 break;
504 504
505 case 43224: 505 case BCMA_CHIP_ID_BCM43224:
506 case 43225: 506 case BCMA_CHIP_ID_BCM43225:
507 /* for these chips OTP is always available */ 507 /* for these chips OTP is always available */
508 present = true; 508 present = true;
509 break; 509 break;
510 510 case BCMA_CHIP_ID_BCM43228:
511 present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
512 break;
511 default: 513 default:
512 present = false; 514 present = false;
513 break; 515 break;
@@ -579,13 +581,15 @@ int bcma_sprom_get(struct bcma_bus *bus)
579 if (!sprom) 581 if (!sprom)
580 return -ENOMEM; 582 return -ENOMEM;
581 583
582 if (bus->chipinfo.id == 0x4331 || bus->chipinfo.id == 43431) 584 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
585 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
583 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false); 586 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
584 587
585 pr_debug("SPROM offset 0x%x\n", offset); 588 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
586 bcma_sprom_read(bus, offset, sprom); 589 bcma_sprom_read(bus, offset, sprom);
587 590
588 if (bus->chipinfo.id == 0x4331 || bus->chipinfo.id == 43431) 591 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
592 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
589 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true); 593 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
590 594
591 err = bcma_sprom_valid(sprom); 595 err = bcma_sprom_valid(sprom);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-03 00:37:21 -0500