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Diffstat (limited to 'drivers/atm/suni.h')
-rw-r--r--drivers/atm/suni.h31
1 files changed, 27 insertions, 4 deletions
diff --git a/drivers/atm/suni.h b/drivers/atm/suni.h
index efa79bfae75b..7e3e656b3993 100644
--- a/drivers/atm/suni.h
+++ b/drivers/atm/suni.h
@@ -1,7 +1,8 @@
1/* drivers/atm/suni.h - PMC PM5346 SUNI (PHY) declarations */ 1/*
2 * drivers/atm/suni.h - S/UNI PHY driver
3 */
2 4
3/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */ 5/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
4
5 6
6#ifndef DRIVER_ATM_SUNI_H 7#ifndef DRIVER_ATM_SUNI_H
7#define DRIVER_ATM_SUNI_H 8#define DRIVER_ATM_SUNI_H
@@ -39,7 +40,8 @@
39#define SUNI_RLOP_LFM 0x1F /* RLOP Line FEBE MSB */ 40#define SUNI_RLOP_LFM 0x1F /* RLOP Line FEBE MSB */
40#define SUNI_TLOP_CTRL 0x20 /* TLOP Control */ 41#define SUNI_TLOP_CTRL 0x20 /* TLOP Control */
41#define SUNI_TLOP_DIAG 0x21 /* TLOP Diagnostic */ 42#define SUNI_TLOP_DIAG 0x21 /* TLOP Diagnostic */
42 /* 0x22-0x2F reserved */ 43 /* 0x22-0x27 reserved */
44#define SUNI_SSTB_CTRL 0x28
43#define SUNI_RPOP_SC 0x30 /* RPOP Status/Control */ 45#define SUNI_RPOP_SC 0x30 /* RPOP Status/Control */
44#define SUNI_RPOP_IS 0x31 /* RPOP Interrupt Status */ 46#define SUNI_RPOP_IS 0x31 /* RPOP Interrupt Status */
45 /* 0x32 reserved */ 47 /* 0x32 reserved */
@@ -52,6 +54,7 @@
52#define SUNI_RPOP_PFM 0x3B /* RPOP Path FEBE MSB */ 54#define SUNI_RPOP_PFM 0x3B /* RPOP Path FEBE MSB */
53 /* 0x3C reserved */ 55 /* 0x3C reserved */
54#define SUNI_RPOP_PBC 0x3D /* RPOP Path BIP-8 Configuration */ 56#define SUNI_RPOP_PBC 0x3D /* RPOP Path BIP-8 Configuration */
57#define SUNI_RPOP_RC 0x3D /* RPOP Ring Control (PM5355) */
55 /* 0x3E-0x3F reserved */ 58 /* 0x3E-0x3F reserved */
56#define SUNI_TPOP_CD 0x40 /* TPOP Control/Diagnostic */ 59#define SUNI_TPOP_CD 0x40 /* TPOP Control/Diagnostic */
57#define SUNI_TPOP_PC 0x41 /* TPOP Pointer Control */ 60#define SUNI_TPOP_PC 0x41 /* TPOP Pointer Control */
@@ -82,7 +85,8 @@
82#define SUNI_TACP_TCC 0x65 /* TACP Transmit Cell Counter */ 85#define SUNI_TACP_TCC 0x65 /* TACP Transmit Cell Counter */
83#define SUNI_TACP_TCCM 0x66 /* TACP Transmit Cell Counter MSB */ 86#define SUNI_TACP_TCCM 0x66 /* TACP Transmit Cell Counter MSB */
84#define SUNI_TACP_CFG 0x67 /* TACP Configuration */ 87#define SUNI_TACP_CFG 0x67 /* TACP Configuration */
85 /* 0x68-0x7F reserved */ 88#define SUNI_SPTB_CTRL 0x68 /* SPTB Control */
89 /* 0x69-0x7F reserved */
86#define SUNI_MT 0x80 /* Master Test */ 90#define SUNI_MT 0x80 /* Master Test */
87 /* 0x81-0xFF reserved */ 91 /* 0x81-0xFF reserved */
88 92
@@ -94,9 +98,18 @@
94#define SUNI_MRI_ID_SHIFT 0 98#define SUNI_MRI_ID_SHIFT 0
95#define SUNI_MRI_TYPE 0x70 /* R, SUNI type (lite is 011) */ 99#define SUNI_MRI_TYPE 0x70 /* R, SUNI type (lite is 011) */
96#define SUNI_MRI_TYPE_SHIFT 4 100#define SUNI_MRI_TYPE_SHIFT 4
101#define SUNI_MRI_TYPE_PM5346 0x3 /* S/UNI 155 LITE */
102#define SUNI_MRI_TYPE_PM5347 0x4 /* S/UNI 155 PLUS */
103#define SUNI_MRI_TYPE_PM5350 0x7 /* S/UNI 155 ULTRA */
104#define SUNI_MRI_TYPE_PM5355 0x1 /* S/UNI 622 */
97#define SUNI_MRI_RESET 0x80 /* RW, reset & power down chip 105#define SUNI_MRI_RESET 0x80 /* RW, reset & power down chip
98 0: normal operation 106 0: normal operation
99 1: reset & low power */ 107 1: reset & low power */
108
109/* MCM is reg 0x4 */
110#define SUNI_MCM_LLE 0x20 /* line loopback (PM5355) */
111#define SUNI_MCM_DLE 0x10 /* diagnostic loopback (PM5355) */
112
100/* MCT is reg 5 */ 113/* MCT is reg 5 */
101#define SUNI_MCT_LOOPT 0x01 /* RW, timing source, 0: from 114#define SUNI_MCT_LOOPT 0x01 /* RW, timing source, 0: from
102 TRCLK+/- */ 115 TRCLK+/- */
@@ -144,6 +157,12 @@
144/* TLOP_DIAG is reg 0x21 */ 157/* TLOP_DIAG is reg 0x21 */
145#define SUNI_TLOP_DIAG_DBIP 0x01 /* insert line BIP err (continuously) */ 158#define SUNI_TLOP_DIAG_DBIP 0x01 /* insert line BIP err (continuously) */
146 159
160/* SSTB_CTRL is reg 0x28 */
161#define SUNI_SSTB_CTRL_LEN16 0x01 /* path trace message length bit */
162
163/* RPOP_RC is reg 0x3D (PM5355) */
164#define SUNI_RPOP_RC_ENSS 0x40 /* enable size bit */
165
147/* TPOP_DIAG is reg 0x40 */ 166/* TPOP_DIAG is reg 0x40 */
148#define SUNI_TPOP_DIAG_PAIS 0x01 /* insert STS path alarm ind (cont) */ 167#define SUNI_TPOP_DIAG_PAIS 0x01 /* insert STS path alarm ind (cont) */
149#define SUNI_TPOP_DIAG_DB3 0x02 /* insert path BIP err (continuously) */ 168#define SUNI_TPOP_DIAG_DB3 0x02 /* insert path BIP err (continuously) */
@@ -191,6 +210,9 @@
191 pattern */ 210 pattern */
192#define SUNI_TACP_IUCHP_GFC_SHIFT 4 211#define SUNI_TACP_IUCHP_GFC_SHIFT 4
193 212
213/* SPTB_CTRL is reg 0x68 */
214#define SUNI_SPTB_CTRL_LEN16 0x01 /* path trace message length */
215
194/* MT is reg 0x80 */ 216/* MT is reg 0x80 */
195#define SUNI_MT_HIZIO 0x01 /* RW, all but data bus & MP interface 217#define SUNI_MT_HIZIO 0x01 /* RW, all but data bus & MP interface
196 tri-state */ 218 tri-state */
@@ -208,6 +230,7 @@
208struct suni_priv { 230struct suni_priv {
209 struct k_sonet_stats sonet_stats; /* link diagnostics */ 231 struct k_sonet_stats sonet_stats; /* link diagnostics */
210 int loop_mode; /* loopback mode */ 232 int loop_mode; /* loopback mode */
233 int type; /* phy type */
211 struct atm_dev *dev; /* device back-pointer */ 234 struct atm_dev *dev; /* device back-pointer */
212 struct suni_priv *next; /* next SUNI */ 235 struct suni_priv *next; /* next SUNI */
213}; 236};