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-rw-r--r--drivers/atm/iphase.h395
1 files changed, 192 insertions, 203 deletions
diff --git a/drivers/atm/iphase.h b/drivers/atm/iphase.h
index 077735e0e04b..6a0955e6d4fc 100644
--- a/drivers/atm/iphase.h
+++ b/drivers/atm/iphase.h
@@ -889,79 +889,71 @@ typedef struct ia_rtn_q {
889} IARTN_Q; 889} IARTN_Q;
890 890
891#define SUNI_LOSV 0x04 891#define SUNI_LOSV 0x04
892typedef struct { 892enum ia_suni {
893 u32 suni_master_reset; /* SUNI Master Reset and Identity */ 893 SUNI_MASTER_RESET = 0x000, /* SUNI Master Reset and Identity */
894 u32 suni_master_config; /* SUNI Master Configuration */ 894 SUNI_MASTER_CONFIG = 0x004, /* SUNI Master Configuration */
895 u32 suni_master_intr_stat; /* SUNI Master Interrupt Status */ 895 SUNI_MASTER_INTR_STAT = 0x008, /* SUNI Master Interrupt Status */
896 u32 suni_reserved1; /* Reserved */ 896 SUNI_RESERVED1 = 0x00c, /* Reserved */
897 u32 suni_master_clk_monitor;/* SUNI Master Clock Monitor */ 897 SUNI_MASTER_CLK_MONITOR = 0x010, /* SUNI Master Clock Monitor */
898 u32 suni_master_control; /* SUNI Master Clock Monitor */ 898 SUNI_MASTER_CONTROL = 0x014, /* SUNI Master Clock Monitor */
899 u32 suni_reserved2[10]; /* Reserved */ 899 /* Reserved (10) */
900 900 SUNI_RSOP_CONTROL = 0x040, /* RSOP Control/Interrupt Enable */
901 u32 suni_rsop_control; /* RSOP Control/Interrupt Enable */ 901 SUNI_RSOP_STATUS = 0x044, /* RSOP Status/Interrupt States */
902 u32 suni_rsop_status; /* RSOP Status/Interrupt States */ 902 SUNI_RSOP_SECTION_BIP8L = 0x048, /* RSOP Section BIP-8 LSB */
903 u32 suni_rsop_section_bip8l;/* RSOP Section BIP-8 LSB */ 903 SUNI_RSOP_SECTION_BIP8M = 0x04c, /* RSOP Section BIP-8 MSB */
904 u32 suni_rsop_section_bip8m;/* RSOP Section BIP-8 MSB */ 904
905 905 SUNI_TSOP_CONTROL = 0x050, /* TSOP Control */
906 u32 suni_tsop_control; /* TSOP Control */ 906 SUNI_TSOP_DIAG = 0x054, /* TSOP Disgnostics */
907 u32 suni_tsop_diag; /* TSOP Disgnostics */ 907 /* Reserved (2) */
908 u32 suni_tsop_reserved[2]; /* TSOP Reserved */ 908 SUNI_RLOP_CS = 0x060, /* RLOP Control/Status */
909 909 SUNI_RLOP_INTR = 0x064, /* RLOP Interrupt Enable/Status */
910 u32 suni_rlop_cs; /* RLOP Control/Status */ 910 SUNI_RLOP_LINE_BIP24L = 0x068, /* RLOP Line BIP-24 LSB */
911 u32 suni_rlop_intr; /* RLOP Interrupt Enable/Status */ 911 SUNI_RLOP_LINE_BIP24 = 0x06c, /* RLOP Line BIP-24 */
912 u32 suni_rlop_line_bip24l; /* RLOP Line BIP-24 LSB */ 912 SUNI_RLOP_LINE_BIP24M = 0x070, /* RLOP Line BIP-24 MSB */
913 u32 suni_rlop_line_bip24; /* RLOP Line BIP-24 */ 913 SUNI_RLOP_LINE_FEBEL = 0x074, /* RLOP Line FEBE LSB */
914 u32 suni_rlop_line_bip24m; /* RLOP Line BIP-24 MSB */ 914 SUNI_RLOP_LINE_FEBE = 0x078, /* RLOP Line FEBE */
915 u32 suni_rlop_line_febel; /* RLOP Line FEBE LSB */ 915 SUNI_RLOP_LINE_FEBEM = 0x07c, /* RLOP Line FEBE MSB */
916 u32 suni_rlop_line_febe; /* RLOP Line FEBE */ 916
917 u32 suni_rlop_line_febem; /* RLOP Line FEBE MSB */ 917 SUNI_TLOP_CONTROL = 0x080, /* TLOP Control */
918 918 SUNI_TLOP_DISG = 0x084, /* TLOP Disgnostics */
919 u32 suni_tlop_control; /* TLOP Control */ 919 /* Reserved (14) */
920 u32 suni_tlop_disg; /* TLOP Disgnostics */ 920 SUNI_RPOP_CS = 0x0c0, /* RPOP Status/Control */
921 u32 suni_tlop_reserved[14]; /* TLOP Reserved */ 921 SUNI_RPOP_INTR = 0x0c4, /* RPOP Interrupt/Status */
922 922 SUNI_RPOP_RESERVED = 0x0c8, /* RPOP Reserved */
923 u32 suni_rpop_cs; /* RPOP Status/Control */ 923 SUNI_RPOP_INTR_ENA = 0x0cc, /* RPOP Interrupt Enable */
924 u32 suni_rpop_intr; /* RPOP Interrupt/Status */ 924 /* Reserved (3) */
925 u32 suni_rpop_reserved; /* RPOP Reserved */ 925 SUNI_RPOP_PATH_SIG = 0x0dc, /* RPOP Path Signal Label */
926 u32 suni_rpop_intr_ena; /* RPOP Interrupt Enable */ 926 SUNI_RPOP_BIP8L = 0x0e0, /* RPOP Path BIP-8 LSB */
927 u32 suni_rpop_reserved1[3]; /* RPOP Reserved */ 927 SUNI_RPOP_BIP8M = 0x0e4, /* RPOP Path BIP-8 MSB */
928 u32 suni_rpop_path_sig; /* RPOP Path Signal Label */ 928 SUNI_RPOP_FEBEL = 0x0e8, /* RPOP Path FEBE LSB */
929 u32 suni_rpop_bip8l; /* RPOP Path BIP-8 LSB */ 929 SUNI_RPOP_FEBEM = 0x0ec, /* RPOP Path FEBE MSB */
930 u32 suni_rpop_bip8m; /* RPOP Path BIP-8 MSB */ 930 /* Reserved (4) */
931 u32 suni_rpop_febel; /* RPOP Path FEBE LSB */ 931 SUNI_TPOP_CNTRL_DAIG = 0x100, /* TPOP Control/Disgnostics */
932 u32 suni_rpop_febem; /* RPOP Path FEBE MSB */ 932 SUNI_TPOP_POINTER_CTRL = 0x104, /* TPOP Pointer Control */
933 u32 suni_rpop_reserved2[4]; /* RPOP Reserved */ 933 SUNI_TPOP_SOURCER_CTRL = 0x108, /* TPOP Source Control */
934 934 /* Reserved (2) */
935 u32 suni_tpop_cntrl_daig; /* TPOP Control/Disgnostics */ 935 SUNI_TPOP_ARB_PRTL = 0x114, /* TPOP Arbitrary Pointer LSB */
936 u32 suni_tpop_pointer_ctrl; /* TPOP Pointer Control */ 936 SUNI_TPOP_ARB_PRTM = 0x118, /* TPOP Arbitrary Pointer MSB */
937 u32 suni_tpop_sourcer_ctrl; /* TPOP Source Control */ 937 SUNI_TPOP_RESERVED2 = 0x11c, /* TPOP Reserved */
938 u32 suni_tpop_reserved1[2]; /* TPOP Reserved */ 938 SUNI_TPOP_PATH_SIG = 0x120, /* TPOP Path Signal Lable */
939 u32 suni_tpop_arb_prtl; /* TPOP Arbitrary Pointer LSB */ 939 SUNI_TPOP_PATH_STATUS = 0x124, /* TPOP Path Status */
940 u32 suni_tpop_arb_prtm; /* TPOP Arbitrary Pointer MSB */ 940 /* Reserved (6) */
941 u32 suni_tpop_reserved2; /* TPOP Reserved */ 941 SUNI_RACP_CS = 0x140, /* RACP Control/Status */
942 u32 suni_tpop_path_sig; /* TPOP Path Signal Lable */ 942 SUNI_RACP_INTR = 0x144, /* RACP Interrupt Enable/Status */
943 u32 suni_tpop_path_status; /* TPOP Path Status */ 943 SUNI_RACP_HDR_PATTERN = 0x148, /* RACP Match Header Pattern */
944 u32 suni_tpop_reserved3[6]; /* TPOP Reserved */ 944 SUNI_RACP_HDR_MASK = 0x14c, /* RACP Match Header Mask */
945 945 SUNI_RACP_CORR_HCS = 0x150, /* RACP Correctable HCS Error Count */
946 u32 suni_racp_cs; /* RACP Control/Status */ 946 SUNI_RACP_UNCORR_HCS = 0x154, /* RACP Uncorrectable HCS Err Count */
947 u32 suni_racp_intr; /* RACP Interrupt Enable/Status */ 947 /* Reserved (10) */
948 u32 suni_racp_hdr_pattern; /* RACP Match Header Pattern */ 948 SUNI_TACP_CONTROL = 0x180, /* TACP Control */
949 u32 suni_racp_hdr_mask; /* RACP Match Header Mask */ 949 SUNI_TACP_IDLE_HDR_PAT = 0x184, /* TACP Idle Cell Header Pattern */
950 u32 suni_racp_corr_hcs; /* RACP Correctable HCS Error Count */ 950 SUNI_TACP_IDLE_PAY_PAY = 0x188, /* TACP Idle Cell Payld Octet Patrn */
951 u32 suni_racp_uncorr_hcs; /* RACP Uncorrectable HCS Error Count */ 951 /* Reserved (5) */
952 u32 suni_racp_reserved[10]; /* RACP Reserved */ 952 /* Reserved (24) */
953 953 /* FIXME: unused but name conflicts.
954 u32 suni_tacp_control; /* TACP Control */ 954 * SUNI_MASTER_TEST = 0x200, SUNI Master Test */
955 u32 suni_tacp_idle_hdr_pat; /* TACP Idle Cell Header Pattern */ 955 SUNI_RESERVED_TEST = 0x204 /* SUNI Reserved for Test */
956 u32 suni_tacp_idle_pay_pay; /* TACP Idle Cell Payld Octet Pattern */ 956};
957 u32 suni_tacp_reserved[5]; /* TACP Reserved */
958
959 u32 suni_reserved3[24]; /* Reserved */
960
961 u32 suni_master_test; /* SUNI Master Test */
962 u32 suni_reserved_test; /* SUNI Reserved for Test */
963} IA_SUNI;
964
965 957
966typedef struct _SUNI_STATS_ 958typedef struct _SUNI_STATS_
967{ 959{
@@ -993,13 +985,11 @@ typedef struct _SUNI_STATS_
993 u32 racp_uchcs_count; // uncorrectable HCS error count 985 u32 racp_uchcs_count; // uncorrectable HCS error count
994} IA_SUNI_STATS; 986} IA_SUNI_STATS;
995 987
996typedef struct iadev_t { 988typedef struct iadev_priv {
997 /*-----base pointers into (i)chipSAR+ address space */ 989 /*-----base pointers into (i)chipSAR+ address space */
998 u32 __iomem *phy; /* base pointer into phy(SUNI) */ 990 u32 __iomem *phy; /* Base pointer into phy (SUNI). */
999 u32 __iomem *dma; /* base pointer into DMA control 991 u32 __iomem *dma; /* Base pointer into DMA control registers. */
1000 registers */ 992 u32 __iomem *reg; /* Base pointer to SAR registers. */
1001 u32 __iomem *reg; /* base pointer to SAR registers
1002 - Bus Interface Control Regs */
1003 u32 __iomem *seg_reg; /* base pointer to segmentation engine 993 u32 __iomem *seg_reg; /* base pointer to segmentation engine
1004 internal registers */ 994 internal registers */
1005 u32 __iomem *reass_reg; /* base pointer to reassemble engine 995 u32 __iomem *reass_reg; /* base pointer to reassemble engine
@@ -1071,14 +1061,14 @@ typedef struct iadev_t {
1071#define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data) 1061#define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data)
1072 1062
1073/******************* IDT77105 25MB/s PHY DEFINE *****************************/ 1063/******************* IDT77105 25MB/s PHY DEFINE *****************************/
1074typedef struct { 1064enum ia_mb25 {
1075 u_int mb25_master_ctrl; /* Master control */ 1065 MB25_MASTER_CTRL = 0x00, /* Master control */
1076 u_int mb25_intr_status; /* Interrupt status */ 1066 MB25_INTR_STATUS = 0x04, /* Interrupt status */
1077 u_int mb25_diag_control; /* Diagnostic control */ 1067 MB25_DIAG_CONTROL = 0x08, /* Diagnostic control */
1078 u_int mb25_led_hec; /* LED driver and HEC status/control */ 1068 MB25_LED_HEC = 0x0c, /* LED driver and HEC status/control */
1079 u_int mb25_low_byte_counter; /* Low byte counter */ 1069 MB25_LOW_BYTE_COUNTER = 0x10,
1080 u_int mb25_high_byte_counter; /* High byte counter */ 1070 MB25_HIGH_BYTE_COUNTER = 0x14
1081} ia_mb25_t; 1071};
1082 1072
1083/* 1073/*
1084 * Master Control 1074 * Master Control
@@ -1127,122 +1117,121 @@ typedef struct {
1127#define FE_E3_PHY 0x0090 /* E3 */ 1117#define FE_E3_PHY 0x0090 /* E3 */
1128 1118
1129/*********************** SUNI_PM7345 PHY DEFINE HERE *********************/ 1119/*********************** SUNI_PM7345 PHY DEFINE HERE *********************/
1130typedef struct _suni_pm7345_t 1120enum suni_pm7345 {
1131{ 1121 SUNI_CONFIG = 0x000, /* SUNI Configuration */
1132 u_int suni_config; /* SUNI Configuration */ 1122 SUNI_INTR_ENBL = 0x004, /* SUNI Interrupt Enable */
1133 u_int suni_intr_enbl; /* SUNI Interrupt Enable */ 1123 SUNI_INTR_STAT = 0x008, /* SUNI Interrupt Status */
1134 u_int suni_intr_stat; /* SUNI Interrupt Status */ 1124 SUNI_CONTROL = 0x00c, /* SUNI Control */
1135 u_int suni_control; /* SUNI Control */ 1125 SUNI_ID_RESET = 0x010, /* SUNI Reset and Identity */
1136 u_int suni_id_reset; /* SUNI Reset and Identity */ 1126 SUNI_DATA_LINK_CTRL = 0x014,
1137 u_int suni_data_link_ctrl; 1127 SUNI_RBOC_CONF_INTR_ENBL = 0x018,
1138 u_int suni_rboc_conf_intr_enbl; 1128 SUNI_RBOC_STAT = 0x01c,
1139 u_int suni_rboc_stat; 1129 SUNI_DS3_FRM_CFG = 0x020,
1140 u_int suni_ds3_frm_cfg; 1130 SUNI_DS3_FRM_INTR_ENBL = 0x024,
1141 u_int suni_ds3_frm_intr_enbl; 1131 SUNI_DS3_FRM_INTR_STAT = 0x028,
1142 u_int suni_ds3_frm_intr_stat; 1132 SUNI_DS3_FRM_STAT = 0x02c,
1143 u_int suni_ds3_frm_stat; 1133 SUNI_RFDL_CFG = 0x030,
1144 u_int suni_rfdl_cfg; 1134 SUNI_RFDL_ENBL_STAT = 0x034,
1145 u_int suni_rfdl_enbl_stat; 1135 SUNI_RFDL_STAT = 0x038,
1146 u_int suni_rfdl_stat; 1136 SUNI_RFDL_DATA = 0x03c,
1147 u_int suni_rfdl_data; 1137 SUNI_PMON_CHNG = 0x040,
1148 u_int suni_pmon_chng; 1138 SUNI_PMON_INTR_ENBL_STAT = 0x044,
1149 u_int suni_pmon_intr_enbl_stat; 1139 /* SUNI_RESERVED1 (0x13 - 0x11) */
1150 u_int suni_reserved1[0x13-0x11]; 1140 SUNI_PMON_LCV_EVT_CNT_LSB = 0x050,
1151 u_int suni_pmon_lcv_evt_cnt_lsb; 1141 SUNI_PMON_LCV_EVT_CNT_MSB = 0x054,
1152 u_int suni_pmon_lcv_evt_cnt_msb; 1142 SUNI_PMON_FBE_EVT_CNT_LSB = 0x058,
1153 u_int suni_pmon_fbe_evt_cnt_lsb; 1143 SUNI_PMON_FBE_EVT_CNT_MSB = 0x05c,
1154 u_int suni_pmon_fbe_evt_cnt_msb; 1144 SUNI_PMON_SEZ_DET_CNT_LSB = 0x060,
1155 u_int suni_pmon_sez_det_cnt_lsb; 1145 SUNI_PMON_SEZ_DET_CNT_MSB = 0x064,
1156 u_int suni_pmon_sez_det_cnt_msb; 1146 SUNI_PMON_PE_EVT_CNT_LSB = 0x068,
1157 u_int suni_pmon_pe_evt_cnt_lsb; 1147 SUNI_PMON_PE_EVT_CNT_MSB = 0x06c,
1158 u_int suni_pmon_pe_evt_cnt_msb; 1148 SUNI_PMON_PPE_EVT_CNT_LSB = 0x070,
1159 u_int suni_pmon_ppe_evt_cnt_lsb; 1149 SUNI_PMON_PPE_EVT_CNT_MSB = 0x074,
1160 u_int suni_pmon_ppe_evt_cnt_msb; 1150 SUNI_PMON_FEBE_EVT_CNT_LSB = 0x078,
1161 u_int suni_pmon_febe_evt_cnt_lsb; 1151 SUNI_PMON_FEBE_EVT_CNT_MSB = 0x07c,
1162 u_int suni_pmon_febe_evt_cnt_msb; 1152 SUNI_DS3_TRAN_CFG = 0x080,
1163 u_int suni_ds3_tran_cfg; 1153 SUNI_DS3_TRAN_DIAG = 0x084,
1164 u_int suni_ds3_tran_diag; 1154 /* SUNI_RESERVED2 (0x23 - 0x21) */
1165 u_int suni_reserved2[0x23-0x21]; 1155 SUNI_XFDL_CFG = 0x090,
1166 u_int suni_xfdl_cfg; 1156 SUNI_XFDL_INTR_ST = 0x094,
1167 u_int suni_xfdl_intr_st; 1157 SUNI_XFDL_XMIT_DATA = 0x098,
1168 u_int suni_xfdl_xmit_data; 1158 SUNI_XBOC_CODE = 0x09c,
1169 u_int suni_xboc_code; 1159 SUNI_SPLR_CFG = 0x0a0,
1170 u_int suni_splr_cfg; 1160 SUNI_SPLR_INTR_EN = 0x0a4,
1171 u_int suni_splr_intr_en; 1161 SUNI_SPLR_INTR_ST = 0x0a8,
1172 u_int suni_splr_intr_st; 1162 SUNI_SPLR_STATUS = 0x0ac,
1173 u_int suni_splr_status; 1163 SUNI_SPLT_CFG = 0x0b0,
1174 u_int suni_splt_cfg; 1164 SUNI_SPLT_CNTL = 0x0b4,
1175 u_int suni_splt_cntl; 1165 SUNI_SPLT_DIAG_G1 = 0x0b8,
1176 u_int suni_splt_diag_g1; 1166 SUNI_SPLT_F1 = 0x0bc,
1177 u_int suni_splt_f1; 1167 SUNI_CPPM_LOC_METERS = 0x0c0,
1178 u_int suni_cppm_loc_meters; 1168 SUNI_CPPM_CHG_OF_CPPM_PERF_METR = 0x0c4,
1179 u_int suni_cppm_chng_of_cppm_perf_meter; 1169 SUNI_CPPM_B1_ERR_CNT_LSB = 0x0c8,
1180 u_int suni_cppm_b1_err_cnt_lsb; 1170 SUNI_CPPM_B1_ERR_CNT_MSB = 0x0cc,
1181 u_int suni_cppm_b1_err_cnt_msb; 1171 SUNI_CPPM_FRAMING_ERR_CNT_LSB = 0x0d0,
1182 u_int suni_cppm_framing_err_cnt_lsb; 1172 SUNI_CPPM_FRAMING_ERR_CNT_MSB = 0x0d4,
1183 u_int suni_cppm_framing_err_cnt_msb; 1173 SUNI_CPPM_FEBE_CNT_LSB = 0x0d8,
1184 u_int suni_cppm_febe_cnt_lsb; 1174 SUNI_CPPM_FEBE_CNT_MSB = 0x0dc,
1185 u_int suni_cppm_febe_cnt_msb; 1175 SUNI_CPPM_HCS_ERR_CNT_LSB = 0x0e0,
1186 u_int suni_cppm_hcs_err_cnt_lsb; 1176 SUNI_CPPM_HCS_ERR_CNT_MSB = 0x0e4,
1187 u_int suni_cppm_hcs_err_cnt_msb; 1177 SUNI_CPPM_IDLE_UN_CELL_CNT_LSB = 0x0e8,
1188 u_int suni_cppm_idle_un_cell_cnt_lsb; 1178 SUNI_CPPM_IDLE_UN_CELL_CNT_MSB = 0x0ec,
1189 u_int suni_cppm_idle_un_cell_cnt_msb; 1179 SUNI_CPPM_RCV_CELL_CNT_LSB = 0x0f0,
1190 u_int suni_cppm_rcv_cell_cnt_lsb; 1180 SUNI_CPPM_RCV_CELL_CNT_MSB = 0x0f4,
1191 u_int suni_cppm_rcv_cell_cnt_msb; 1181 SUNI_CPPM_XMIT_CELL_CNT_LSB = 0x0f8,
1192 u_int suni_cppm_xmit_cell_cnt_lsb; 1182 SUNI_CPPM_XMIT_CELL_CNT_MSB = 0x0fc,
1193 u_int suni_cppm_xmit_cell_cnt_msb; 1183 SUNI_RXCP_CTRL = 0x100,
1194 u_int suni_rxcp_ctrl; 1184 SUNI_RXCP_FCTRL = 0x104,
1195 u_int suni_rxcp_fctrl; 1185 SUNI_RXCP_INTR_EN_STS = 0x108,
1196 u_int suni_rxcp_intr_en_sts; 1186 SUNI_RXCP_IDLE_PAT_H1 = 0x10c,
1197 u_int suni_rxcp_idle_pat_h1; 1187 SUNI_RXCP_IDLE_PAT_H2 = 0x110,
1198 u_int suni_rxcp_idle_pat_h2; 1188 SUNI_RXCP_IDLE_PAT_H3 = 0x114,
1199 u_int suni_rxcp_idle_pat_h3; 1189 SUNI_RXCP_IDLE_PAT_H4 = 0x118,
1200 u_int suni_rxcp_idle_pat_h4; 1190 SUNI_RXCP_IDLE_MASK_H1 = 0x11c,
1201 u_int suni_rxcp_idle_mask_h1; 1191 SUNI_RXCP_IDLE_MASK_H2 = 0x120,
1202 u_int suni_rxcp_idle_mask_h2; 1192 SUNI_RXCP_IDLE_MASK_H3 = 0x124,
1203 u_int suni_rxcp_idle_mask_h3; 1193 SUNI_RXCP_IDLE_MASK_H4 = 0x128,
1204 u_int suni_rxcp_idle_mask_h4; 1194 SUNI_RXCP_CELL_PAT_H1 = 0x12c,
1205 u_int suni_rxcp_cell_pat_h1; 1195 SUNI_RXCP_CELL_PAT_H2 = 0x130,
1206 u_int suni_rxcp_cell_pat_h2; 1196 SUNI_RXCP_CELL_PAT_H3 = 0x134,
1207 u_int suni_rxcp_cell_pat_h3; 1197 SUNI_RXCP_CELL_PAT_H4 = 0x138,
1208 u_int suni_rxcp_cell_pat_h4; 1198 SUNI_RXCP_CELL_MASK_H1 = 0x13c,
1209 u_int suni_rxcp_cell_mask_h1; 1199 SUNI_RXCP_CELL_MASK_H2 = 0x140,
1210 u_int suni_rxcp_cell_mask_h2; 1200 SUNI_RXCP_CELL_MASK_H3 = 0x144,
1211 u_int suni_rxcp_cell_mask_h3; 1201 SUNI_RXCP_CELL_MASK_H4 = 0x148,
1212 u_int suni_rxcp_cell_mask_h4; 1202 SUNI_RXCP_HCS_CS = 0x14c,
1213 u_int suni_rxcp_hcs_cs; 1203 SUNI_RXCP_LCD_CNT_THRESHOLD = 0x150,
1214 u_int suni_rxcp_lcd_cnt_threshold; 1204 /* SUNI_RESERVED3 (0x57 - 0x54) */
1215 u_int suni_reserved3[0x57-0x54]; 1205 SUNI_TXCP_CTRL = 0x160,
1216 u_int suni_txcp_ctrl; 1206 SUNI_TXCP_INTR_EN_STS = 0x164,
1217 u_int suni_txcp_intr_en_sts; 1207 SUNI_TXCP_IDLE_PAT_H1 = 0x168,
1218 u_int suni_txcp_idle_pat_h1; 1208 SUNI_TXCP_IDLE_PAT_H2 = 0x16c,
1219 u_int suni_txcp_idle_pat_h2; 1209 SUNI_TXCP_IDLE_PAT_H3 = 0x170,
1220 u_int suni_txcp_idle_pat_h3; 1210 SUNI_TXCP_IDLE_PAT_H4 = 0x174,
1221 u_int suni_txcp_idle_pat_h4; 1211 SUNI_TXCP_IDLE_PAT_H5 = 0x178,
1222 u_int suni_txcp_idle_pat_h5; 1212 SUNI_TXCP_IDLE_PAYLOAD = 0x17c,
1223 u_int suni_txcp_idle_payload; 1213 SUNI_E3_FRM_FRAM_OPTIONS = 0x180,
1224 u_int suni_e3_frm_fram_options; 1214 SUNI_E3_FRM_MAINT_OPTIONS = 0x184,
1225 u_int suni_e3_frm_maint_options; 1215 SUNI_E3_FRM_FRAM_INTR_ENBL = 0x188,
1226 u_int suni_e3_frm_fram_intr_enbl; 1216 SUNI_E3_FRM_FRAM_INTR_IND_STAT = 0x18c,
1227 u_int suni_e3_frm_fram_intr_ind_stat; 1217 SUNI_E3_FRM_MAINT_INTR_ENBL = 0x190,
1228 u_int suni_e3_frm_maint_intr_enbl; 1218 SUNI_E3_FRM_MAINT_INTR_IND = 0x194,
1229 u_int suni_e3_frm_maint_intr_ind; 1219 SUNI_E3_FRM_MAINT_STAT = 0x198,
1230 u_int suni_e3_frm_maint_stat; 1220 SUNI_RESERVED4 = 0x19c,
1231 u_int suni_reserved4; 1221 SUNI_E3_TRAN_FRAM_OPTIONS = 0x1a0,
1232 u_int suni_e3_tran_fram_options; 1222 SUNI_E3_TRAN_STAT_DIAG_OPTIONS = 0x1a4,
1233 u_int suni_e3_tran_stat_diag_options; 1223 SUNI_E3_TRAN_BIP_8_ERR_MASK = 0x1a8,
1234 u_int suni_e3_tran_bip_8_err_mask; 1224 SUNI_E3_TRAN_MAINT_ADAPT_OPTS = 0x1ac,
1235 u_int suni_e3_tran_maint_adapt_options; 1225 SUNI_TTB_CTRL = 0x1b0,
1236 u_int suni_ttb_ctrl; 1226 SUNI_TTB_TRAIL_TRACE_ID_STAT = 0x1b4,
1237 u_int suni_ttb_trail_trace_id_stat; 1227 SUNI_TTB_IND_ADDR = 0x1b8,
1238 u_int suni_ttb_ind_addr; 1228 SUNI_TTB_IND_DATA = 0x1bc,
1239 u_int suni_ttb_ind_data; 1229 SUNI_TTB_EXP_PAYLOAD_TYPE = 0x1c0,
1240 u_int suni_ttb_exp_payload_type; 1230 SUNI_TTB_PAYLOAD_TYPE_CTRL_STAT = 0x1c4,
1241 u_int suni_ttb_payload_type_ctrl_stat; 1231 /* SUNI_PAD5 (0x7f - 0x71) */
1242 u_int suni_pad5[0x7f-0x71]; 1232 SUNI_MASTER_TEST = 0x200,
1243 u_int suni_master_test; 1233 /* SUNI_PAD6 (0xff - 0x80) */
1244 u_int suni_pad6[0xff-0x80]; 1234};
1245}suni_pm7345_t;
1246 1235
1247#define SUNI_PM7345_T suni_pm7345_t 1236#define SUNI_PM7345_T suni_pm7345_t
1248#define SUNI_PM7345 0x20 /* Suni chip type */ 1237#define SUNI_PM7345 0x20 /* Suni chip type */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-02 16:11:31 -0400