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-rw-r--r--drivers/ata/Kconfig9
-rw-r--r--drivers/ata/Makefile1
-rw-r--r--drivers/ata/ahci.h2
-rw-r--r--drivers/ata/ahci_imx.c184
-rw-r--r--drivers/ata/ahci_st.c2
-rw-r--r--drivers/ata/ahci_tegra.c377
-rw-r--r--drivers/ata/ahci_xgene.c23
-rw-r--r--drivers/ata/libahci_platform.c13
-rw-r--r--drivers/ata/pata_samsung_cf.c13
-rw-r--r--drivers/ata/sata_fsl.c5
-rw-r--r--drivers/ata/sata_sil24.c4
11 files changed, 591 insertions, 42 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 7671dbac6015..e65d400efd44 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -141,6 +141,15 @@ config AHCI_SUNXI
141 141
142 If unsure, say N. 142 If unsure, say N.
143 143
144config AHCI_TEGRA
145 tristate "NVIDIA Tegra124 AHCI SATA support"
146 depends on ARCH_TEGRA
147 help
148 This option enables support for the NVIDIA Tegra124 SoC's
149 onboard AHCI SATA.
150
151 If unsure, say N.
152
144config AHCI_XGENE 153config AHCI_XGENE
145 tristate "APM X-Gene 6.0Gbps AHCI SATA host controller support" 154 tristate "APM X-Gene 6.0Gbps AHCI SATA host controller support"
146 depends on PHY_XGENE 155 depends on PHY_XGENE
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 5a02aeecef5b..ae41107afc1f 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
15obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o 15obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
16obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o 16obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
17obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o libahci_platform.o 17obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o libahci_platform.o
18obj-$(CONFIG_AHCI_TEGRA) += ahci_tegra.o libahci.o libahci_platform.o
18obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o libahci.o libahci_platform.o 19obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o libahci.o libahci_platform.o
19 20
20# SFF w/ custom DMA 21# SFF w/ custom DMA
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 5513296e5e2e..2ed84e1c70ea 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -53,7 +53,7 @@
53 53
54enum { 54enum {
55 AHCI_MAX_PORTS = 32, 55 AHCI_MAX_PORTS = 32,
56 AHCI_MAX_CLKS = 3, 56 AHCI_MAX_CLKS = 4,
57 AHCI_MAX_SG = 168, /* hardware max is 64K */ 57 AHCI_MAX_SG = 168, /* hardware max is 64K */
58 AHCI_DMA_BOUNDARY = 0xffffffff, 58 AHCI_DMA_BOUNDARY = 0xffffffff,
59 AHCI_MAX_CMDS = 32, 59 AHCI_MAX_CMDS = 32,
diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
index cac4360f272a..1e5fa5f21aff 100644
--- a/drivers/ata/ahci_imx.c
+++ b/drivers/ata/ahci_imx.c
@@ -64,6 +64,7 @@ struct imx_ahci_priv {
64 struct regmap *gpr; 64 struct regmap *gpr;
65 bool no_device; 65 bool no_device;
66 bool first_time; 66 bool first_time;
67 u32 phy_params;
67}; 68};
68 69
69static int ahci_imx_hotplug; 70static int ahci_imx_hotplug;
@@ -248,14 +249,7 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv)
248 IMX6Q_GPR13_SATA_TX_LVL_MASK | 249 IMX6Q_GPR13_SATA_TX_LVL_MASK |
249 IMX6Q_GPR13_SATA_MPLL_CLK_EN | 250 IMX6Q_GPR13_SATA_MPLL_CLK_EN |
250 IMX6Q_GPR13_SATA_TX_EDGE_RATE, 251 IMX6Q_GPR13_SATA_TX_EDGE_RATE,
251 IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB | 252 imxpriv->phy_params);
252 IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
253 IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
254 IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
255 IMX6Q_GPR13_SATA_MPLL_SS_EN |
256 IMX6Q_GPR13_SATA_TX_ATTEN_9_16 |
257 IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB |
258 IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
259 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 253 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
260 IMX6Q_GPR13_SATA_MPLL_CLK_EN, 254 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
261 IMX6Q_GPR13_SATA_MPLL_CLK_EN); 255 IMX6Q_GPR13_SATA_MPLL_CLK_EN);
@@ -265,7 +259,7 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv)
265 ret = imx_sata_phy_reset(hpriv); 259 ret = imx_sata_phy_reset(hpriv);
266 if (ret) { 260 if (ret) {
267 dev_err(dev, "failed to reset phy: %d\n", ret); 261 dev_err(dev, "failed to reset phy: %d\n", ret);
268 goto disable_regulator; 262 goto disable_clk;
269 } 263 }
270 } 264 }
271 265
@@ -273,6 +267,8 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv)
273 267
274 return 0; 268 return 0;
275 269
270disable_clk:
271 clk_disable_unprepare(imxpriv->sata_ref_clk);
276disable_regulator: 272disable_regulator:
277 if (hpriv->target_pwr) 273 if (hpriv->target_pwr)
278 regulator_disable(hpriv->target_pwr); 274 regulator_disable(hpriv->target_pwr);
@@ -369,6 +365,165 @@ static const struct of_device_id imx_ahci_of_match[] = {
369}; 365};
370MODULE_DEVICE_TABLE(of, imx_ahci_of_match); 366MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
371 367
368struct reg_value {
369 u32 of_value;
370 u32 reg_value;
371};
372
373struct reg_property {
374 const char *name;
375 const struct reg_value *values;
376 size_t num_values;
377 u32 def_value;
378 u32 set_value;
379};
380
381static const struct reg_value gpr13_tx_level[] = {
382 { 937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
383 { 947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
384 { 957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
385 { 966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
386 { 976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
387 { 986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
388 { 996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
389 { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
390 { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
391 { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
392 { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
393 { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
394 { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
395 { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
396 { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
397 { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
398 { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
399 { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
400 { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
401 { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
402 { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
403 { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
404 { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
405 { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
406 { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
407 { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
408 { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
409 { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
410 { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
411 { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
412 { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
413 { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
414};
415
416static const struct reg_value gpr13_tx_boost[] = {
417 { 0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
418 { 370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
419 { 740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
420 { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
421 { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
422 { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
423 { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
424 { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
425 { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
426 { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
427 { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
428 { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
429 { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
430 { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
431 { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
432 { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
433};
434
435static const struct reg_value gpr13_tx_atten[] = {
436 { 8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
437 { 9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
438 { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
439 { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
440 { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
441 { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
442};
443
444static const struct reg_value gpr13_rx_eq[] = {
445 { 500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
446 { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
447 { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
448 { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
449 { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
450 { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
451 { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
452 { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
453};
454
455static const struct reg_property gpr13_props[] = {
456 {
457 .name = "fsl,transmit-level-mV",
458 .values = gpr13_tx_level,
459 .num_values = ARRAY_SIZE(gpr13_tx_level),
460 .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
461 }, {
462 .name = "fsl,transmit-boost-mdB",
463 .values = gpr13_tx_boost,
464 .num_values = ARRAY_SIZE(gpr13_tx_boost),
465 .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
466 }, {
467 .name = "fsl,transmit-atten-16ths",
468 .values = gpr13_tx_atten,
469 .num_values = ARRAY_SIZE(gpr13_tx_atten),
470 .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
471 }, {
472 .name = "fsl,receive-eq-mdB",
473 .values = gpr13_rx_eq,
474 .num_values = ARRAY_SIZE(gpr13_rx_eq),
475 .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
476 }, {
477 .name = "fsl,no-spread-spectrum",
478 .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
479 .set_value = 0,
480 },
481};
482
483static u32 imx_ahci_parse_props(struct device *dev,
484 const struct reg_property *prop, size_t num)
485{
486 struct device_node *np = dev->of_node;
487 u32 reg_value = 0;
488 int i, j;
489
490 for (i = 0; i < num; i++, prop++) {
491 u32 of_val;
492
493 if (prop->num_values == 0) {
494 if (of_property_read_bool(np, prop->name))
495 reg_value |= prop->set_value;
496 else
497 reg_value |= prop->def_value;
498 continue;
499 }
500
501 if (of_property_read_u32(np, prop->name, &of_val)) {
502 dev_info(dev, "%s not specified, using %08x\n",
503 prop->name, prop->def_value);
504 reg_value |= prop->def_value;
505 continue;
506 }
507
508 for (j = 0; j < prop->num_values; j++) {
509 if (prop->values[j].of_value == of_val) {
510 dev_info(dev, "%s value %u, using %08x\n",
511 prop->name, of_val, prop->values[j].reg_value);
512 reg_value |= prop->values[j].reg_value;
513 break;
514 }
515 }
516
517 if (j == prop->num_values) {
518 dev_err(dev, "DT property %s is not a valid value\n",
519 prop->name);
520 reg_value |= prop->def_value;
521 }
522 }
523
524 return reg_value;
525}
526
372static int imx_ahci_probe(struct platform_device *pdev) 527static int imx_ahci_probe(struct platform_device *pdev)
373{ 528{
374 struct device *dev = &pdev->dev; 529 struct device *dev = &pdev->dev;
@@ -410,6 +565,8 @@ static int imx_ahci_probe(struct platform_device *pdev)
410 } 565 }
411 566
412 if (imxpriv->type == AHCI_IMX6Q) { 567 if (imxpriv->type == AHCI_IMX6Q) {
568 u32 reg_value;
569
413 imxpriv->gpr = syscon_regmap_lookup_by_compatible( 570 imxpriv->gpr = syscon_regmap_lookup_by_compatible(
414 "fsl,imx6q-iomuxc-gpr"); 571 "fsl,imx6q-iomuxc-gpr");
415 if (IS_ERR(imxpriv->gpr)) { 572 if (IS_ERR(imxpriv->gpr)) {
@@ -417,6 +574,15 @@ static int imx_ahci_probe(struct platform_device *pdev)
417 "failed to find fsl,imx6q-iomux-gpr regmap\n"); 574 "failed to find fsl,imx6q-iomux-gpr regmap\n");
418 return PTR_ERR(imxpriv->gpr); 575 return PTR_ERR(imxpriv->gpr);
419 } 576 }
577
578 reg_value = imx_ahci_parse_props(dev, gpr13_props,
579 ARRAY_SIZE(gpr13_props));
580
581 imxpriv->phy_params =
582 IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
583 IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
584 IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
585 reg_value;
420 } 586 }
421 587
422 hpriv = ahci_platform_get_resources(pdev); 588 hpriv = ahci_platform_get_resources(pdev);
diff --git a/drivers/ata/ahci_st.c b/drivers/ata/ahci_st.c
index 2595598df9ce..29821b9fd13d 100644
--- a/drivers/ata/ahci_st.c
+++ b/drivers/ata/ahci_st.c
@@ -221,7 +221,7 @@ static int st_ahci_resume(struct device *dev)
221 221
222static SIMPLE_DEV_PM_OPS(st_ahci_pm_ops, st_ahci_suspend, st_ahci_resume); 222static SIMPLE_DEV_PM_OPS(st_ahci_pm_ops, st_ahci_suspend, st_ahci_resume);
223 223
224static struct of_device_id st_ahci_match[] = { 224static const struct of_device_id st_ahci_match[] = {
225 { .compatible = "st,ahci", }, 225 { .compatible = "st,ahci", },
226 {}, 226 {},
227}; 227};
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
new file mode 100644
index 000000000000..d30bb21afd67
--- /dev/null
+++ b/drivers/ata/ahci_tegra.c
@@ -0,0 +1,377 @@
1/*
2 * drivers/ata/ahci_tegra.c
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Author:
7 * Mikko Perttunen <mperttunen@nvidia.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/ahci_platform.h>
21#include <linux/reset.h>
22#include <linux/errno.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/tegra-powergate.h>
28#include <linux/regulator/consumer.h>
29#include "ahci.h"
30
31#define SATA_CONFIGURATION_0 0x180
32#define SATA_CONFIGURATION_EN_FPCI BIT(0)
33
34#define SCFG_OFFSET 0x1000
35
36#define T_SATA0_CFG_1 0x04
37#define T_SATA0_CFG_1_IO_SPACE BIT(0)
38#define T_SATA0_CFG_1_MEMORY_SPACE BIT(1)
39#define T_SATA0_CFG_1_BUS_MASTER BIT(2)
40#define T_SATA0_CFG_1_SERR BIT(8)
41
42#define T_SATA0_CFG_9 0x24
43#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13
44
45#define SATA_FPCI_BAR5 0x94
46#define SATA_FPCI_BAR5_START_SHIFT 4
47
48#define SATA_INTR_MASK 0x188
49#define SATA_INTR_MASK_IP_INT_MASK BIT(16)
50
51#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
52
53#define T_SATA0_BKDOOR_CC 0x4a4
54
55#define T_SATA0_CFG_SATA 0x54c
56#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
57
58#define T_SATA0_CFG_MISC 0x550
59
60#define T_SATA0_INDEX 0x680
61
62#define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690
63#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff
64#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
65#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
66#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
67
68#define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694
69#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff
70#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
71#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
72#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
73
74#define T_SATA0_CHX_PHY_CTRL2 0x69c
75#define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23
76
77#define T_SATA0_CHX_PHY_CTRL11 0x6d0
78#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
79
80#define FUSE_SATA_CALIB 0x124
81#define FUSE_SATA_CALIB_MASK 0x3
82
83struct sata_pad_calibration {
84 u8 gen1_tx_amp;
85 u8 gen1_tx_peak;
86 u8 gen2_tx_amp;
87 u8 gen2_tx_peak;
88};
89
90static const struct sata_pad_calibration tegra124_pad_calibration[] = {
91 {0x18, 0x04, 0x18, 0x0a},
92 {0x0e, 0x04, 0x14, 0x0a},
93 {0x0e, 0x07, 0x1a, 0x0e},
94 {0x14, 0x0e, 0x1a, 0x0e},
95};
96
97struct tegra_ahci_priv {
98 struct platform_device *pdev;
99 void __iomem *sata_regs;
100 struct reset_control *sata_rst;
101 struct reset_control *sata_oob_rst;
102 struct reset_control *sata_cold_rst;
103 /* Needs special handling, cannot use ahci_platform */
104 struct clk *sata_clk;
105 struct regulator_bulk_data supplies[5];
106};
107
108static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
109{
110 struct tegra_ahci_priv *tegra = hpriv->plat_data;
111 int ret;
112
113 ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
114 tegra->supplies);
115 if (ret)
116 return ret;
117
118 ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
119 tegra->sata_clk,
120 tegra->sata_rst);
121 if (ret)
122 goto disable_regulators;
123
124 reset_control_assert(tegra->sata_oob_rst);
125 reset_control_assert(tegra->sata_cold_rst);
126
127 ret = ahci_platform_enable_resources(hpriv);
128 if (ret)
129 goto disable_power;
130
131 reset_control_deassert(tegra->sata_cold_rst);
132 reset_control_deassert(tegra->sata_oob_rst);
133
134 return 0;
135
136disable_power:
137 clk_disable_unprepare(tegra->sata_clk);
138
139 tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
140
141disable_regulators:
142 regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
143
144 return ret;
145}
146
147static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
148{
149 struct tegra_ahci_priv *tegra = hpriv->plat_data;
150
151 ahci_platform_disable_resources(hpriv);
152
153 reset_control_assert(tegra->sata_rst);
154 reset_control_assert(tegra->sata_oob_rst);
155 reset_control_assert(tegra->sata_cold_rst);
156
157 clk_disable_unprepare(tegra->sata_clk);
158 tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
159
160 regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
161}
162
163static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
164{
165 struct tegra_ahci_priv *tegra = hpriv->plat_data;
166 int ret;
167 unsigned int val;
168 struct sata_pad_calibration calib;
169
170 ret = tegra_ahci_power_on(hpriv);
171 if (ret) {
172 dev_err(&tegra->pdev->dev,
173 "failed to power on AHCI controller: %d\n", ret);
174 return ret;
175 }
176
177 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
178 val |= SATA_CONFIGURATION_EN_FPCI;
179 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
180
181 /* Pad calibration */
182
183 /* FIXME Always use calibration 0. Change this to read the calibration
184 * fuse once the fuse driver has landed. */
185 val = 0;
186
187 calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
188
189 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
190
191 val = readl(tegra->sata_regs +
192 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
193 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
194 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
195 val |= calib.gen1_tx_amp <<
196 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
197 val |= calib.gen1_tx_peak <<
198 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
199 writel(val, tegra->sata_regs + SCFG_OFFSET +
200 T_SATA0_CHX_PHY_CTRL1_GEN1);
201
202 val = readl(tegra->sata_regs +
203 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
204 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
205 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
206 val |= calib.gen2_tx_amp <<
207 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
208 val |= calib.gen2_tx_peak <<
209 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
210 writel(val, tegra->sata_regs + SCFG_OFFSET +
211 T_SATA0_CHX_PHY_CTRL1_GEN2);
212
213 writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
214 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
215 writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
216 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
217
218 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
219
220 /* Program controller device ID */
221
222 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
223 val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
224 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
225
226 writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
227
228 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
229 val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
230 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
231
232 /* Enable IO & memory access, bus master mode */
233
234 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
235 val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
236 T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR;
237 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
238
239 /* Program SATA MMIO */
240
241 writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
242 tegra->sata_regs + SATA_FPCI_BAR5);
243
244 writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
245 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
246
247 /* Unmask SATA interrupts */
248
249 val = readl(tegra->sata_regs + SATA_INTR_MASK);
250 val |= SATA_INTR_MASK_IP_INT_MASK;
251 writel(val, tegra->sata_regs + SATA_INTR_MASK);
252
253 return 0;
254}
255
256static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
257{
258 tegra_ahci_power_off(hpriv);
259}
260
261static void tegra_ahci_host_stop(struct ata_host *host)
262{
263 struct ahci_host_priv *hpriv = host->private_data;
264
265 tegra_ahci_controller_deinit(hpriv);
266}
267
268static struct ata_port_operations ahci_tegra_port_ops = {
269 .inherits = &ahci_ops,
270 .host_stop = tegra_ahci_host_stop,
271};
272
273static const struct ata_port_info ahci_tegra_port_info = {
274 .flags = AHCI_FLAG_COMMON,
275 .pio_mask = ATA_PIO4,
276 .udma_mask = ATA_UDMA6,
277 .port_ops = &ahci_tegra_port_ops,
278};
279
280static const struct of_device_id tegra_ahci_of_match[] = {
281 { .compatible = "nvidia,tegra124-ahci" },
282 {}
283};
284MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
285
286static int tegra_ahci_probe(struct platform_device *pdev)
287{
288 struct ahci_host_priv *hpriv;
289 struct tegra_ahci_priv *tegra;
290 struct resource *res;
291 int ret;
292
293 hpriv = ahci_platform_get_resources(pdev);
294 if (IS_ERR(hpriv))
295 return PTR_ERR(hpriv);
296
297 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
298 if (!tegra)
299 return -ENOMEM;
300
301 hpriv->plat_data = tegra;
302
303 tegra->pdev = pdev;
304
305 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
306 tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
307 if (IS_ERR(tegra->sata_regs))
308 return PTR_ERR(tegra->sata_regs);
309
310 tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
311 if (IS_ERR(tegra->sata_rst)) {
312 dev_err(&pdev->dev, "Failed to get sata reset\n");
313 return PTR_ERR(tegra->sata_rst);
314 }
315
316 tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");
317 if (IS_ERR(tegra->sata_oob_rst)) {
318 dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
319 return PTR_ERR(tegra->sata_oob_rst);
320 }
321
322 tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
323 if (IS_ERR(tegra->sata_cold_rst)) {
324 dev_err(&pdev->dev, "Failed to get sata-cold reset\n");
325 return PTR_ERR(tegra->sata_cold_rst);
326 }
327
328 tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");
329 if (IS_ERR(tegra->sata_clk)) {
330 dev_err(&pdev->dev, "Failed to get sata clock\n");
331 return PTR_ERR(tegra->sata_clk);
332 }
333
334 tegra->supplies[0].supply = "avdd";
335 tegra->supplies[1].supply = "hvdd";
336 tegra->supplies[2].supply = "vddio";
337 tegra->supplies[3].supply = "target-5v";
338 tegra->supplies[4].supply = "target-12v";
339
340 ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies),
341 tegra->supplies);
342 if (ret) {
343 dev_err(&pdev->dev, "Failed to get regulators\n");
344 return ret;
345 }
346
347 ret = tegra_ahci_controller_init(hpriv);
348 if (ret)
349 return ret;
350
351 ret = ahci_platform_init_host(pdev, hpriv, &ahci_tegra_port_info,
352 0, 0, 0);
353 if (ret)
354 goto deinit_controller;
355
356 return 0;
357
358deinit_controller:
359 tegra_ahci_controller_deinit(hpriv);
360
361 return ret;
362};
363
364static struct platform_driver tegra_ahci_driver = {
365 .probe = tegra_ahci_probe,
366 .remove = ata_platform_remove_one,
367 .driver = {
368 .name = "tegra-ahci",
369 .of_match_table = tegra_ahci_of_match,
370 },
371 /* LP0 suspend support not implemented */
372};
373module_platform_driver(tegra_ahci_driver);
374
375MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
376MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
377MODULE_LICENSE("GPL v2");
diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c
index ee3a3659bd9e..1cfbdca638d2 100644
--- a/drivers/ata/ahci_xgene.c
+++ b/drivers/ata/ahci_xgene.c
@@ -67,6 +67,9 @@
67#define PORTAXICFG 0x000000bc 67#define PORTAXICFG 0x000000bc
68#define PORTAXICFG_OUTTRANS_SET(dst, src) \ 68#define PORTAXICFG_OUTTRANS_SET(dst, src) \
69 (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000)) 69 (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
70#define PORTRANSCFG 0x000000c8
71#define PORTRANSCFG_RXWM_SET(dst, src) \
72 (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))
70 73
71/* SATA host controller AXI CSR */ 74/* SATA host controller AXI CSR */
72#define INT_SLV_TMOMASK 0x00000010 75#define INT_SLV_TMOMASK 0x00000010
@@ -193,11 +196,11 @@ static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
193 /* Disable fix rate */ 196 /* Disable fix rate */
194 writel(0x0001fffe, mmio + PORTPHY1CFG); 197 writel(0x0001fffe, mmio + PORTPHY1CFG);
195 readl(mmio + PORTPHY1CFG); /* Force a barrier */ 198 readl(mmio + PORTPHY1CFG); /* Force a barrier */
196 writel(0x5018461c, mmio + PORTPHY2CFG); 199 writel(0x28183219, mmio + PORTPHY2CFG);
197 readl(mmio + PORTPHY2CFG); /* Force a barrier */ 200 readl(mmio + PORTPHY2CFG); /* Force a barrier */
198 writel(0x1c081907, mmio + PORTPHY3CFG); 201 writel(0x13081008, mmio + PORTPHY3CFG);
199 readl(mmio + PORTPHY3CFG); /* Force a barrier */ 202 readl(mmio + PORTPHY3CFG); /* Force a barrier */
200 writel(0x1c080815, mmio + PORTPHY4CFG); 203 writel(0x00480815, mmio + PORTPHY4CFG);
201 readl(mmio + PORTPHY4CFG); /* Force a barrier */ 204 readl(mmio + PORTPHY4CFG); /* Force a barrier */
202 /* Set window negotiation */ 205 /* Set window negotiation */
203 val = readl(mmio + PORTPHY5CFG); 206 val = readl(mmio + PORTPHY5CFG);
@@ -209,6 +212,10 @@ static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
209 val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */ 212 val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
210 writel(val, mmio + PORTAXICFG); 213 writel(val, mmio + PORTAXICFG);
211 readl(mmio + PORTAXICFG); /* Force a barrier */ 214 readl(mmio + PORTAXICFG); /* Force a barrier */
215 /* Set the watermark threshold of the receive FIFO */
216 val = readl(mmio + PORTRANSCFG);
217 val = PORTRANSCFG_RXWM_SET(val, 0x30);
218 writel(val, mmio + PORTRANSCFG);
212} 219}
213 220
214/** 221/**
@@ -474,16 +481,6 @@ static int xgene_ahci_probe(struct platform_device *pdev)
474 /* Configure the host controller */ 481 /* Configure the host controller */
475 xgene_ahci_hw_init(hpriv); 482 xgene_ahci_hw_init(hpriv);
476 483
477 /*
478 * Setup DMA mask. This is preliminary until the DMA range is sorted
479 * out.
480 */
481 rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
482 if (rc) {
483 dev_err(dev, "Unable to set dma mask\n");
484 goto disable_resources;
485 }
486
487 hflags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ; 484 hflags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ;
488 485
489 rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info, 486 rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info,
diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
index b0077589f065..28840a2f470f 100644
--- a/drivers/ata/libahci_platform.c
+++ b/drivers/ata/libahci_platform.c
@@ -369,6 +369,19 @@ int ahci_platform_init_host(struct platform_device *pdev,
369 ap->ops = &ata_dummy_port_ops; 369 ap->ops = &ata_dummy_port_ops;
370 } 370 }
371 371
372 if (hpriv->cap & HOST_CAP_64) {
373 rc = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
374 if (rc) {
375 rc = dma_coerce_mask_and_coherent(dev,
376 DMA_BIT_MASK(32));
377 if (rc) {
378 dev_err(dev, "Failed to enable 64-bit DMA.\n");
379 return rc;
380 }
381 dev_warn(dev, "Enable 32-bit DMA instead of 64-bit.\n");
382 }
383 }
384
372 rc = ahci_reset_controller(host); 385 rc = ahci_reset_controller(host);
373 if (rc) 386 if (rc)
374 return rc; 387 return rc;
diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
index fb528831fb92..2578fc16960a 100644
--- a/drivers/ata/pata_samsung_cf.c
+++ b/drivers/ata/pata_samsung_cf.c
@@ -54,7 +54,6 @@
54 54
55enum s3c_cpu_type { 55enum s3c_cpu_type {
56 TYPE_S3C64XX, 56 TYPE_S3C64XX,
57 TYPE_S5PC100,
58 TYPE_S5PV210, 57 TYPE_S5PV210,
59}; 58};
60 59
@@ -476,10 +475,6 @@ static void pata_s3c_hwinit(struct s3c_ide_info *info,
476 writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK); 475 writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
477 break; 476 break;
478 477
479 case TYPE_S5PC100:
480 pata_s3c_cfg_mode(info->sfr_addr);
481 /* FALLTHROUGH */
482
483 case TYPE_S5PV210: 478 case TYPE_S5PV210:
484 /* Configure as little endian */ 479 /* Configure as little endian */
485 pata_s3c_set_endian(info->ide_addr, 0); 480 pata_s3c_set_endian(info->ide_addr, 0);
@@ -549,11 +544,6 @@ static int __init pata_s3c_probe(struct platform_device *pdev)
549 info->sfr_addr = info->ide_addr + 0x1800; 544 info->sfr_addr = info->ide_addr + 0x1800;
550 info->ide_addr += 0x1900; 545 info->ide_addr += 0x1900;
551 info->fifo_status_reg = 0x94; 546 info->fifo_status_reg = 0x94;
552 } else if (cpu_type == TYPE_S5PC100) {
553 ap->ops = &pata_s5p_port_ops;
554 info->sfr_addr = info->ide_addr + 0x1800;
555 info->ide_addr += 0x1900;
556 info->fifo_status_reg = 0x84;
557 } else { 547 } else {
558 ap->ops = &pata_s5p_port_ops; 548 ap->ops = &pata_s5p_port_ops;
559 info->fifo_status_reg = 0x84; 549 info->fifo_status_reg = 0x84;
@@ -653,9 +643,6 @@ static struct platform_device_id pata_s3c_driver_ids[] = {
653 .name = "s3c64xx-pata", 643 .name = "s3c64xx-pata",
654 .driver_data = TYPE_S3C64XX, 644 .driver_data = TYPE_S3C64XX,
655 }, { 645 }, {
656 .name = "s5pc100-pata",
657 .driver_data = TYPE_S5PC100,
658 }, {
659 .name = "s5pv210-pata", 646 .name = "s5pv210-pata",
660 .driver_data = TYPE_S5PV210, 647 .driver_data = TYPE_S5PV210,
661 }, 648 },
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index 616a6d2ac20c..07bc7e4dbd04 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -734,13 +734,12 @@ static int sata_fsl_port_start(struct ata_port *ap)
734 if (!pp) 734 if (!pp)
735 return -ENOMEM; 735 return -ENOMEM;
736 736
737 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 737 mem = dma_zalloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
738 GFP_KERNEL); 738 GFP_KERNEL);
739 if (!mem) { 739 if (!mem) {
740 kfree(pp); 740 kfree(pp);
741 return -ENOMEM; 741 return -ENOMEM;
742 } 742 }
743 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
744 743
745 pp->cmdslot = mem; 744 pp->cmdslot = mem;
746 pp->cmdslot_paddr = mem_dma; 745 pp->cmdslot_paddr = mem_dma;
diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c
index 0534890f118a..d81b20ddb527 100644
--- a/drivers/ata/sata_sil24.c
+++ b/drivers/ata/sata_sil24.c
@@ -1154,8 +1154,8 @@ static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1154 status = readl(host_base + HOST_IRQ_STAT); 1154 status = readl(host_base + HOST_IRQ_STAT);
1155 1155
1156 if (status == 0xffffffff) { 1156 if (status == 0xffffffff) {
1157 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " 1157 dev_err(host->dev, "IRQ status == 0xffffffff, "
1158 "PCI fault or device removal?\n"); 1158 "PCI fault or device removal?\n");
1159 goto out; 1159 goto out;
1160 } 1160 }
1161 1161
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 20:27:28 -0500