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-rw-r--r--drivers/ata/Kconfig15
-rw-r--r--drivers/ata/Makefile1
-rw-r--r--drivers/ata/ahci.c32
-rw-r--r--drivers/ata/ata_piix.c34
-rw-r--r--drivers/ata/libata-core.c73
-rw-r--r--drivers/ata/libata-scsi.c37
-rw-r--r--drivers/ata/libata-sff.c21
-rw-r--r--drivers/ata/pata_ali.c28
-rw-r--r--drivers/ata/pata_atiixp.c32
-rw-r--r--drivers/ata/pata_it821x.c17
-rw-r--r--drivers/ata/pata_octeon_cf.c965
-rw-r--r--drivers/ata/pata_rb532_cf.c2
-rw-r--r--drivers/ata/pata_via.c22
-rw-r--r--drivers/ata/sata_fsl.c2
-rw-r--r--drivers/ata/sata_mv.c56
-rw-r--r--drivers/ata/sata_nv.c70
-rw-r--r--drivers/ata/sata_sil.c36
-rw-r--r--drivers/ata/sata_via.c2
18 files changed, 1292 insertions, 153 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 1a7be96d627b..0bcf26464670 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -112,11 +112,11 @@ config ATA_PIIX
112 If unsure, say N. 112 If unsure, say N.
113 113
114config SATA_MV 114config SATA_MV
115 tristate "Marvell SATA support (HIGHLY EXPERIMENTAL)" 115 tristate "Marvell SATA support"
116 depends on EXPERIMENTAL
117 help 116 help
118 This option enables support for the Marvell Serial ATA family. 117 This option enables support for the Marvell Serial ATA family.
119 Currently supports 88SX[56]0[48][01] chips. 118 Currently supports 88SX[56]0[48][01] PCI(-X) chips,
119 as well as the newer [67]042 PCI-X/PCIe and SOC devices.
120 120
121 If unsure, say N. 121 If unsure, say N.
122 122
@@ -698,6 +698,15 @@ config PATA_IXP4XX_CF
698 698
699 If unsure, say N. 699 If unsure, say N.
700 700
701config PATA_OCTEON_CF
702 tristate "OCTEON Boot Bus Compact Flash support"
703 depends on CPU_CAVIUM_OCTEON
704 help
705 This option enables a polled compact flash driver for use with
706 compact flash cards attached to the OCTEON boot bus.
707
708 If unsure, say N.
709
701config PATA_SCC 710config PATA_SCC
702 tristate "Toshiba's Cell Reference Set IDE support" 711 tristate "Toshiba's Cell Reference Set IDE support"
703 depends on PCI && PPC_CELLEB 712 depends on PCI && PPC_CELLEB
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 674965fa326d..7f1ecf99528c 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_PATA_IXP4XX_CF) += pata_ixp4xx_cf.o
69obj-$(CONFIG_PATA_SCC) += pata_scc.o 69obj-$(CONFIG_PATA_SCC) += pata_scc.o
70obj-$(CONFIG_PATA_SCH) += pata_sch.o 70obj-$(CONFIG_PATA_SCH) += pata_sch.o
71obj-$(CONFIG_PATA_BF54X) += pata_bf54x.o 71obj-$(CONFIG_PATA_BF54X) += pata_bf54x.o
72obj-$(CONFIG_PATA_OCTEON_CF) += pata_octeon_cf.o
72obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o 73obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
73obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o 74obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
74obj-$(CONFIG_PATA_ICSIDE) += pata_icside.o 75obj-$(CONFIG_PATA_ICSIDE) += pata_icside.o
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 96039671e3b9..77bba4c083cb 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -2548,6 +2548,32 @@ static void ahci_p5wdh_workaround(struct ata_host *host)
2548 } 2548 }
2549} 2549}
2550 2550
2551static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
2552{
2553 static const struct dmi_system_id broken_systems[] = {
2554 {
2555 .ident = "HP Compaq nx6310",
2556 .matches = {
2557 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2558 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
2559 },
2560 /* PCI slot number of the controller */
2561 .driver_data = (void *)0x1FUL,
2562 },
2563
2564 { } /* terminate list */
2565 };
2566 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
2567
2568 if (dmi) {
2569 unsigned long slot = (unsigned long)dmi->driver_data;
2570 /* apply the quirk only to on-board controllers */
2571 return slot == PCI_SLOT(pdev->devfn);
2572 }
2573
2574 return false;
2575}
2576
2551static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 2577static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2552{ 2578{
2553 static int printed_version; 2579 static int printed_version;
@@ -2647,6 +2673,12 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2647 } 2673 }
2648 } 2674 }
2649 2675
2676 if (ahci_broken_system_poweroff(pdev)) {
2677 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
2678 dev_info(&pdev->dev,
2679 "quirky BIOS, skipping spindown on poweroff\n");
2680 }
2681
2650 /* CAP.NP sometimes indicate the index of the last enabled 2682 /* CAP.NP sometimes indicate the index of the last enabled
2651 * port, at other times, that of the last possible port, so 2683 * port, at other times, that of the last possible port, so
2652 * determining the maximum port number requires looking at 2684 * determining the maximum port number requires looking at
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index 887d8f46a287..54961c0b2c73 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -1387,6 +1387,32 @@ static void piix_iocfg_bit18_quirk(struct ata_host *host)
1387 } 1387 }
1388} 1388}
1389 1389
1390static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1391{
1392 static const struct dmi_system_id broken_systems[] = {
1393 {
1394 .ident = "HP Compaq 2510p",
1395 .matches = {
1396 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1397 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1398 },
1399 /* PCI slot number of the controller */
1400 .driver_data = (void *)0x1FUL,
1401 },
1402
1403 { } /* terminate list */
1404 };
1405 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1406
1407 if (dmi) {
1408 unsigned long slot = (unsigned long)dmi->driver_data;
1409 /* apply the quirk only to on-board controllers */
1410 return slot == PCI_SLOT(pdev->devfn);
1411 }
1412
1413 return false;
1414}
1415
1390/** 1416/**
1391 * piix_init_one - Register PIIX ATA PCI device with kernel services 1417 * piix_init_one - Register PIIX ATA PCI device with kernel services
1392 * @pdev: PCI device to register 1418 * @pdev: PCI device to register
@@ -1422,6 +1448,14 @@ static int __devinit piix_init_one(struct pci_dev *pdev,
1422 if (!in_module_init) 1448 if (!in_module_init)
1423 return -ENODEV; 1449 return -ENODEV;
1424 1450
1451 if (piix_broken_system_poweroff(pdev)) {
1452 piix_port_info[ent->driver_data].flags |=
1453 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1454 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1455 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1456 "on poweroff and hibernation\n");
1457 }
1458
1425 port_info[0] = piix_port_info[ent->driver_data]; 1459 port_info[0] = piix_port_info[ent->driver_data];
1426 port_info[1] = piix_port_info[ent->driver_data]; 1460 port_info[1] = piix_port_info[ent->driver_data];
1427 1461
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 71218d76d75e..88c242856dae 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -3029,33 +3029,33 @@ int sata_set_spd(struct ata_link *link)
3029 */ 3029 */
3030 3030
3031static const struct ata_timing ata_timing[] = { 3031static const struct ata_timing ata_timing[] = {
3032/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */ 3032/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 0, 960, 0 }, */
3033 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 }, 3033 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 0, 600, 0 },
3034 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 }, 3034 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 0, 383, 0 },
3035 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 }, 3035 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 0, 240, 0 },
3036 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 }, 3036 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 0, 180, 0 },
3037 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 }, 3037 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 0, 120, 0 },
3038 { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 100, 0 }, 3038 { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 0, 100, 0 },
3039 { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 80, 0 }, 3039 { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 0, 80, 0 },
3040 3040
3041 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 }, 3041 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 50, 960, 0 },
3042 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 }, 3042 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 30, 480, 0 },
3043 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 }, 3043 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 20, 240, 0 },
3044 3044
3045 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 }, 3045 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 20, 480, 0 },
3046 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 }, 3046 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 5, 150, 0 },
3047 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 }, 3047 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 5, 120, 0 },
3048 { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 100, 0 }, 3048 { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 5, 100, 0 },
3049 { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 80, 0 }, 3049 { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 5, 80, 0 },
3050 3050
3051/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */ 3051/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 0, 150 }, */
3052 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 }, 3052 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 0, 120 },
3053 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 }, 3053 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 0, 80 },
3054 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 }, 3054 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 0, 60 },
3055 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 }, 3055 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 0, 45 },
3056 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 }, 3056 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 0, 30 },
3057 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 }, 3057 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 0, 20 },
3058 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 }, 3058 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 0, 15 },
3059 3059
3060 { 0xFF } 3060 { 0xFF }
3061}; 3061};
@@ -3065,14 +3065,15 @@ static const struct ata_timing ata_timing[] = {
3065 3065
3066static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT) 3066static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
3067{ 3067{
3068 q->setup = EZ(t->setup * 1000, T); 3068 q->setup = EZ(t->setup * 1000, T);
3069 q->act8b = EZ(t->act8b * 1000, T); 3069 q->act8b = EZ(t->act8b * 1000, T);
3070 q->rec8b = EZ(t->rec8b * 1000, T); 3070 q->rec8b = EZ(t->rec8b * 1000, T);
3071 q->cyc8b = EZ(t->cyc8b * 1000, T); 3071 q->cyc8b = EZ(t->cyc8b * 1000, T);
3072 q->active = EZ(t->active * 1000, T); 3072 q->active = EZ(t->active * 1000, T);
3073 q->recover = EZ(t->recover * 1000, T); 3073 q->recover = EZ(t->recover * 1000, T);
3074 q->cycle = EZ(t->cycle * 1000, T); 3074 q->dmack_hold = EZ(t->dmack_hold * 1000, T);
3075 q->udma = EZ(t->udma * 1000, UT); 3075 q->cycle = EZ(t->cycle * 1000, T);
3076 q->udma = EZ(t->udma * 1000, UT);
3076} 3077}
3077 3078
3078void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b, 3079void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
@@ -3084,6 +3085,7 @@ void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
3084 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b); 3085 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
3085 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active); 3086 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
3086 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover); 3087 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
3088 if (what & ATA_TIMING_DMACK_HOLD) m->dmack_hold = max(a->dmack_hold, b->dmack_hold);
3087 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle); 3089 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
3088 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma); 3090 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
3089} 3091}
@@ -6638,7 +6640,6 @@ EXPORT_SYMBOL_GPL(ata_dev_pair);
6638EXPORT_SYMBOL_GPL(ata_port_disable); 6640EXPORT_SYMBOL_GPL(ata_port_disable);
6639EXPORT_SYMBOL_GPL(ata_ratelimit); 6641EXPORT_SYMBOL_GPL(ata_ratelimit);
6640EXPORT_SYMBOL_GPL(ata_wait_register); 6642EXPORT_SYMBOL_GPL(ata_wait_register);
6641EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
6642EXPORT_SYMBOL_GPL(ata_scsi_queuecmd); 6643EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
6643EXPORT_SYMBOL_GPL(ata_scsi_slave_config); 6644EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
6644EXPORT_SYMBOL_GPL(ata_scsi_slave_destroy); 6645EXPORT_SYMBOL_GPL(ata_scsi_slave_destroy);
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index 9e92107691f2..3c4c5ae277ba 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -46,6 +46,7 @@
46#include <linux/libata.h> 46#include <linux/libata.h>
47#include <linux/hdreg.h> 47#include <linux/hdreg.h>
48#include <linux/uaccess.h> 48#include <linux/uaccess.h>
49#include <linux/suspend.h>
49 50
50#include "libata.h" 51#include "libata.h"
51 52
@@ -423,9 +424,9 @@ int ata_std_bios_param(struct scsi_device *sdev, struct block_device *bdev,
423 * RETURNS: 424 * RETURNS:
424 * Zero on success, negative errno on error. 425 * Zero on success, negative errno on error.
425 */ 426 */
426static int ata_get_identity(struct scsi_device *sdev, void __user *arg) 427static int ata_get_identity(struct ata_port *ap, struct scsi_device *sdev,
428 void __user *arg)
427{ 429{
428 struct ata_port *ap = ata_shost_to_port(sdev->host);
429 struct ata_device *dev = ata_scsi_find_dev(ap, sdev); 430 struct ata_device *dev = ata_scsi_find_dev(ap, sdev);
430 u16 __user *dst = arg; 431 u16 __user *dst = arg;
431 char buf[40]; 432 char buf[40];
@@ -645,7 +646,8 @@ int ata_task_ioctl(struct scsi_device *scsidev, void __user *arg)
645 return rc; 646 return rc;
646} 647}
647 648
648int ata_scsi_ioctl(struct scsi_device *scsidev, int cmd, void __user *arg) 649int ata_sas_scsi_ioctl(struct ata_port *ap, struct scsi_device *scsidev,
650 int cmd, void __user *arg)
649{ 651{
650 int val = -EINVAL, rc = -EINVAL; 652 int val = -EINVAL, rc = -EINVAL;
651 653
@@ -663,7 +665,7 @@ int ata_scsi_ioctl(struct scsi_device *scsidev, int cmd, void __user *arg)
663 return 0; 665 return 0;
664 666
665 case HDIO_GET_IDENTITY: 667 case HDIO_GET_IDENTITY:
666 return ata_get_identity(scsidev, arg); 668 return ata_get_identity(ap, scsidev, arg);
667 669
668 case HDIO_DRIVE_CMD: 670 case HDIO_DRIVE_CMD:
669 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) 671 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
@@ -682,6 +684,14 @@ int ata_scsi_ioctl(struct scsi_device *scsidev, int cmd, void __user *arg)
682 684
683 return rc; 685 return rc;
684} 686}
687EXPORT_SYMBOL_GPL(ata_sas_scsi_ioctl);
688
689int ata_scsi_ioctl(struct scsi_device *scsidev, int cmd, void __user *arg)
690{
691 return ata_sas_scsi_ioctl(ata_shost_to_port(scsidev->host),
692 scsidev, cmd, arg);
693}
694EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
685 695
686/** 696/**
687 * ata_scsi_qc_new - acquire new ata_queued_cmd reference 697 * ata_scsi_qc_new - acquire new ata_queued_cmd reference
@@ -1294,6 +1304,17 @@ static unsigned int ata_scsi_start_stop_xlat(struct ata_queued_cmd *qc)
1294 1304
1295 tf->command = ATA_CMD_VERIFY; /* READ VERIFY */ 1305 tf->command = ATA_CMD_VERIFY; /* READ VERIFY */
1296 } else { 1306 } else {
1307 /* Some odd clown BIOSen issue spindown on power off (ACPI S4
1308 * or S5) causing some drives to spin up and down again.
1309 */
1310 if ((qc->ap->flags & ATA_FLAG_NO_POWEROFF_SPINDOWN) &&
1311 system_state == SYSTEM_POWER_OFF)
1312 goto skip;
1313
1314 if ((qc->ap->flags & ATA_FLAG_NO_HIBERNATE_SPINDOWN) &&
1315 system_entering_hibernation())
1316 goto skip;
1317
1297 /* XXX: This is for backward compatibility, will be 1318 /* XXX: This is for backward compatibility, will be
1298 * removed. Read Documentation/feature-removal-schedule.txt 1319 * removed. Read Documentation/feature-removal-schedule.txt
1299 * for more info. 1320 * for more info.
@@ -1317,8 +1338,7 @@ static unsigned int ata_scsi_start_stop_xlat(struct ata_queued_cmd *qc)
1317 scmd->scsi_done = qc->scsidone; 1338 scmd->scsi_done = qc->scsidone;
1318 qc->scsidone = ata_delayed_done; 1339 qc->scsidone = ata_delayed_done;
1319 } 1340 }
1320 scmd->result = SAM_STAT_GOOD; 1341 goto skip;
1321 return 1;
1322 } 1342 }
1323 1343
1324 /* Issue ATA STANDBY IMMEDIATE command */ 1344 /* Issue ATA STANDBY IMMEDIATE command */
@@ -1334,10 +1354,13 @@ static unsigned int ata_scsi_start_stop_xlat(struct ata_queued_cmd *qc)
1334 1354
1335 return 0; 1355 return 0;
1336 1356
1337invalid_fld: 1357 invalid_fld:
1338 ata_scsi_set_sense(scmd, ILLEGAL_REQUEST, 0x24, 0x0); 1358 ata_scsi_set_sense(scmd, ILLEGAL_REQUEST, 0x24, 0x0);
1339 /* "Invalid field in cbd" */ 1359 /* "Invalid field in cbd" */
1340 return 1; 1360 return 1;
1361 skip:
1362 scmd->result = SAM_STAT_GOOD;
1363 return 1;
1341} 1364}
1342 1365
1343 1366
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c
index 0eae9b453556..0b299b0f8172 100644
--- a/drivers/ata/libata-sff.c
+++ b/drivers/ata/libata-sff.c
@@ -1013,9 +1013,12 @@ next_sg:
1013 qc->cursg_ofs = 0; 1013 qc->cursg_ofs = 0;
1014 } 1014 }
1015 1015
1016 /* consumed can be larger than count only for the last transfer */ 1016 /*
1017 WARN_ON_ONCE(qc->cursg && count != consumed); 1017 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
1018 1018 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
1019 * check correctly as it doesn't know if it is the last request being
1020 * made. Somebody should implement a proper sanity check.
1021 */
1019 if (bytes) 1022 if (bytes)
1020 goto next_sg; 1023 goto next_sg;
1021 return 0; 1024 return 0;
@@ -1319,7 +1322,7 @@ fsm_start:
1319 * condition. Mark hint. 1322 * condition. Mark hint.
1320 */ 1323 */
1321 ata_ehi_push_desc(ehi, "ST-ATA: " 1324 ata_ehi_push_desc(ehi, "ST-ATA: "
1322 "DRQ=1 with device error, " 1325 "DRQ=0 without device error, "
1323 "dev_stat 0x%X", status); 1326 "dev_stat 0x%X", status);
1324 qc->err_mask |= AC_ERR_HSM | 1327 qc->err_mask |= AC_ERR_HSM |
1325 AC_ERR_NODEV_HINT; 1328 AC_ERR_NODEV_HINT;
@@ -1355,6 +1358,16 @@ fsm_start:
1355 qc->err_mask |= AC_ERR_HSM; 1358 qc->err_mask |= AC_ERR_HSM;
1356 } 1359 }
1357 1360
1361 /* There are oddball controllers with
1362 * status register stuck at 0x7f and
1363 * lbal/m/h at zero which makes it
1364 * pass all other presence detection
1365 * mechanisms we have. Set NODEV_HINT
1366 * for it. Kernel bz#7241.
1367 */
1368 if (status == 0x7f)
1369 qc->err_mask |= AC_ERR_NODEV_HINT;
1370
1358 /* ata_pio_sectors() might change the 1371 /* ata_pio_sectors() might change the
1359 * state to HSM_ST_LAST. so, the state 1372 * state to HSM_ST_LAST. so, the state
1360 * is changed after ata_pio_sectors(). 1373 * is changed after ata_pio_sectors().
diff --git a/drivers/ata/pata_ali.c b/drivers/ata/pata_ali.c
index a7999c19f0c9..eb99dbe78081 100644
--- a/drivers/ata/pata_ali.c
+++ b/drivers/ata/pata_ali.c
@@ -41,7 +41,7 @@ static int ali_atapi_dma = 0;
41module_param_named(atapi_dma, ali_atapi_dma, int, 0644); 41module_param_named(atapi_dma, ali_atapi_dma, int, 0644);
42MODULE_PARM_DESC(atapi_dma, "Enable ATAPI DMA (0=disable, 1=enable)"); 42MODULE_PARM_DESC(atapi_dma, "Enable ATAPI DMA (0=disable, 1=enable)");
43 43
44static struct pci_dev *isa_bridge; 44static struct pci_dev *ali_isa_bridge;
45 45
46/* 46/*
47 * Cable special cases 47 * Cable special cases
@@ -346,13 +346,13 @@ static void ali_c2_c3_postreset(struct ata_link *link, unsigned int *classes)
346 int port_bit = 4 << link->ap->port_no; 346 int port_bit = 4 << link->ap->port_no;
347 347
348 /* If our bridge is an ALI 1533 then do the extra work */ 348 /* If our bridge is an ALI 1533 then do the extra work */
349 if (isa_bridge) { 349 if (ali_isa_bridge) {
350 /* Tristate and re-enable the bus signals */ 350 /* Tristate and re-enable the bus signals */
351 pci_read_config_byte(isa_bridge, 0x58, &r); 351 pci_read_config_byte(ali_isa_bridge, 0x58, &r);
352 r &= ~port_bit; 352 r &= ~port_bit;
353 pci_write_config_byte(isa_bridge, 0x58, r); 353 pci_write_config_byte(ali_isa_bridge, 0x58, r);
354 r |= port_bit; 354 r |= port_bit;
355 pci_write_config_byte(isa_bridge, 0x58, r); 355 pci_write_config_byte(ali_isa_bridge, 0x58, r);
356 } 356 }
357 ata_sff_postreset(link, classes); 357 ata_sff_postreset(link, classes);
358} 358}
@@ -467,14 +467,14 @@ static void ali_init_chipset(struct pci_dev *pdev)
467 pci_write_config_byte(pdev, 0x53, tmp); 467 pci_write_config_byte(pdev, 0x53, tmp);
468 } 468 }
469 north = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); 469 north = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
470 if (north && north->vendor == PCI_VENDOR_ID_AL && isa_bridge) { 470 if (north && north->vendor == PCI_VENDOR_ID_AL && ali_isa_bridge) {
471 /* Configure the ALi bridge logic. For non ALi rely on BIOS. 471 /* Configure the ALi bridge logic. For non ALi rely on BIOS.
472 Set the south bridge enable bit */ 472 Set the south bridge enable bit */
473 pci_read_config_byte(isa_bridge, 0x79, &tmp); 473 pci_read_config_byte(ali_isa_bridge, 0x79, &tmp);
474 if (pdev->revision == 0xC2) 474 if (pdev->revision == 0xC2)
475 pci_write_config_byte(isa_bridge, 0x79, tmp | 0x04); 475 pci_write_config_byte(ali_isa_bridge, 0x79, tmp | 0x04);
476 else if (pdev->revision > 0xC2 && pdev->revision < 0xC5) 476 else if (pdev->revision > 0xC2 && pdev->revision < 0xC5)
477 pci_write_config_byte(isa_bridge, 0x79, tmp | 0x02); 477 pci_write_config_byte(ali_isa_bridge, 0x79, tmp | 0x02);
478 } 478 }
479 pci_dev_put(north); 479 pci_dev_put(north);
480 ata_pci_bmdma_clear_simplex(pdev); 480 ata_pci_bmdma_clear_simplex(pdev);
@@ -571,9 +571,9 @@ static int ali_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
571 571
572 ali_init_chipset(pdev); 572 ali_init_chipset(pdev);
573 573
574 if (isa_bridge && pdev->revision >= 0x20 && pdev->revision < 0xC2) { 574 if (ali_isa_bridge && pdev->revision >= 0x20 && pdev->revision < 0xC2) {
575 /* Are we paired with a UDMA capable chip */ 575 /* Are we paired with a UDMA capable chip */
576 pci_read_config_byte(isa_bridge, 0x5E, &tmp); 576 pci_read_config_byte(ali_isa_bridge, 0x5E, &tmp);
577 if ((tmp & 0x1E) == 0x12) 577 if ((tmp & 0x1E) == 0x12)
578 ppi[0] = &info_20_udma; 578 ppi[0] = &info_20_udma;
579 } 579 }
@@ -617,11 +617,11 @@ static struct pci_driver ali_pci_driver = {
617static int __init ali_init(void) 617static int __init ali_init(void)
618{ 618{
619 int ret; 619 int ret;
620 isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL); 620 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
621 621
622 ret = pci_register_driver(&ali_pci_driver); 622 ret = pci_register_driver(&ali_pci_driver);
623 if (ret < 0) 623 if (ret < 0)
624 pci_dev_put(isa_bridge); 624 pci_dev_put(ali_isa_bridge);
625 return ret; 625 return ret;
626} 626}
627 627
@@ -629,7 +629,7 @@ static int __init ali_init(void)
629static void __exit ali_exit(void) 629static void __exit ali_exit(void)
630{ 630{
631 pci_unregister_driver(&ali_pci_driver); 631 pci_unregister_driver(&ali_pci_driver);
632 pci_dev_put(isa_bridge); 632 pci_dev_put(ali_isa_bridge);
633} 633}
634 634
635 635
diff --git a/drivers/ata/pata_atiixp.c b/drivers/ata/pata_atiixp.c
index 0e2cde8f9973..506adde8ebb3 100644
--- a/drivers/ata/pata_atiixp.c
+++ b/drivers/ata/pata_atiixp.c
@@ -32,21 +32,6 @@ enum {
32 ATIIXP_IDE_UDMA_MODE = 0x56 32 ATIIXP_IDE_UDMA_MODE = 0x56
33}; 33};
34 34
35static int atiixp_pre_reset(struct ata_link *link, unsigned long deadline)
36{
37 struct ata_port *ap = link->ap;
38 static const struct pci_bits atiixp_enable_bits[] = {
39 { 0x48, 1, 0x01, 0x00 },
40 { 0x48, 1, 0x08, 0x00 }
41 };
42 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
43
44 if (!pci_test_config_bits(pdev, &atiixp_enable_bits[ap->port_no]))
45 return -ENOENT;
46
47 return ata_sff_prereset(link, deadline);
48}
49
50static int atiixp_cable_detect(struct ata_port *ap) 35static int atiixp_cable_detect(struct ata_port *ap)
51{ 36{
52 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 37 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
@@ -229,10 +214,9 @@ static struct ata_port_operations atiixp_port_ops = {
229 .cable_detect = atiixp_cable_detect, 214 .cable_detect = atiixp_cable_detect,
230 .set_piomode = atiixp_set_piomode, 215 .set_piomode = atiixp_set_piomode,
231 .set_dmamode = atiixp_set_dmamode, 216 .set_dmamode = atiixp_set_dmamode,
232 .prereset = atiixp_pre_reset,
233}; 217};
234 218
235static int atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id) 219static int atiixp_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
236{ 220{
237 static const struct ata_port_info info = { 221 static const struct ata_port_info info = {
238 .flags = ATA_FLAG_SLAVE_POSS, 222 .flags = ATA_FLAG_SLAVE_POSS,
@@ -241,8 +225,18 @@ static int atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
241 .udma_mask = 0x3F, 225 .udma_mask = 0x3F,
242 .port_ops = &atiixp_port_ops 226 .port_ops = &atiixp_port_ops
243 }; 227 };
244 const struct ata_port_info *ppi[] = { &info, NULL }; 228 static const struct pci_bits atiixp_enable_bits[] = {
245 return ata_pci_sff_init_one(dev, ppi, &atiixp_sht, NULL); 229 { 0x48, 1, 0x01, 0x00 },
230 { 0x48, 1, 0x08, 0x00 }
231 };
232 const struct ata_port_info *ppi[] = { &info, &info };
233 int i;
234
235 for (i = 0; i < 2; i++)
236 if (!pci_test_config_bits(pdev, &atiixp_enable_bits[i]))
237 ppi[i] = &ata_dummy_port_info;
238
239 return ata_pci_sff_init_one(pdev, ppi, &atiixp_sht, NULL);
246} 240}
247 241
248static const struct pci_device_id atiixp[] = { 242static const struct pci_device_id atiixp[] = {
diff --git a/drivers/ata/pata_it821x.c b/drivers/ata/pata_it821x.c
index f828a29d7756..f1bb2f9fecbf 100644
--- a/drivers/ata/pata_it821x.c
+++ b/drivers/ata/pata_it821x.c
@@ -80,7 +80,7 @@
80 80
81 81
82#define DRV_NAME "pata_it821x" 82#define DRV_NAME "pata_it821x"
83#define DRV_VERSION "0.4.0" 83#define DRV_VERSION "0.4.2"
84 84
85struct it821x_dev 85struct it821x_dev
86{ 86{
@@ -494,8 +494,6 @@ static int it821x_smart_set_mode(struct ata_link *link, struct ata_device **unus
494 * special. In our case we need to lock the sector count to avoid 494 * special. In our case we need to lock the sector count to avoid
495 * blowing the brains out of the firmware with large LBA48 requests 495 * blowing the brains out of the firmware with large LBA48 requests
496 * 496 *
497 * FIXME: When FUA appears we need to block FUA too. And SMART and
498 * basically we need to filter commands for this chip.
499 */ 497 */
500 498
501static void it821x_dev_config(struct ata_device *adev) 499static void it821x_dev_config(struct ata_device *adev)
@@ -890,6 +888,13 @@ static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
890 .flags = ATA_FLAG_SLAVE_POSS, 888 .flags = ATA_FLAG_SLAVE_POSS,
891 .pio_mask = 0x1f, 889 .pio_mask = 0x1f,
892 .mwdma_mask = 0x07, 890 .mwdma_mask = 0x07,
891 .udma_mask = ATA_UDMA6,
892 .port_ops = &it821x_rdc_port_ops
893 };
894 static const struct ata_port_info info_rdc_11 = {
895 .flags = ATA_FLAG_SLAVE_POSS,
896 .pio_mask = 0x1f,
897 .mwdma_mask = 0x07,
893 /* No UDMA */ 898 /* No UDMA */
894 .port_ops = &it821x_rdc_port_ops 899 .port_ops = &it821x_rdc_port_ops
895 }; 900 };
@@ -903,7 +908,11 @@ static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
903 return rc; 908 return rc;
904 909
905 if (pdev->vendor == PCI_VENDOR_ID_RDC) { 910 if (pdev->vendor == PCI_VENDOR_ID_RDC) {
906 ppi[0] = &info_rdc; 911 /* Deal with Vortex86SX */
912 if (pdev->revision == 0x11)
913 ppi[0] = &info_rdc_11;
914 else
915 ppi[0] = &info_rdc;
907 } else { 916 } else {
908 /* Force the card into bypass mode if so requested */ 917 /* Force the card into bypass mode if so requested */
909 if (it8212_noraid) { 918 if (it8212_noraid) {
diff --git a/drivers/ata/pata_octeon_cf.c b/drivers/ata/pata_octeon_cf.c
new file mode 100644
index 000000000000..0fe4ef309c62
--- /dev/null
+++ b/drivers/ata/pata_octeon_cf.c
@@ -0,0 +1,965 @@
1/*
2 * Driver for the Octeon bootbus compact flash.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2005 - 2009 Cavium Networks
9 * Copyright (C) 2008 Wind River Systems
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/libata.h>
15#include <linux/irq.h>
16#include <linux/platform_device.h>
17#include <linux/workqueue.h>
18#include <scsi/scsi_host.h>
19
20#include <asm/octeon/octeon.h>
21
22/*
23 * The Octeon bootbus compact flash interface is connected in at least
24 * 3 different configurations on various evaluation boards:
25 *
26 * -- 8 bits no irq, no DMA
27 * -- 16 bits no irq, no DMA
28 * -- 16 bits True IDE mode with DMA, but no irq.
29 *
30 * In the last case the DMA engine can generate an interrupt when the
31 * transfer is complete. For the first two cases only PIO is supported.
32 *
33 */
34
35#define DRV_NAME "pata_octeon_cf"
36#define DRV_VERSION "2.1"
37
38
39struct octeon_cf_port {
40 struct workqueue_struct *wq;
41 struct delayed_work delayed_finish;
42 struct ata_port *ap;
43 int dma_finished;
44};
45
46static struct scsi_host_template octeon_cf_sht = {
47 ATA_PIO_SHT(DRV_NAME),
48};
49
50/**
51 * Convert nanosecond based time to setting used in the
52 * boot bus timing register, based on timing multiple
53 */
54static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs)
55{
56 unsigned int val;
57
58 /*
59 * Compute # of eclock periods to get desired duration in
60 * nanoseconds.
61 */
62 val = DIV_ROUND_UP(nsecs * (octeon_get_clock_rate() / 1000000),
63 1000 * tim_mult);
64
65 return val;
66}
67
68static void octeon_cf_set_boot_reg_cfg(int cs)
69{
70 union cvmx_mio_boot_reg_cfgx reg_cfg;
71 reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
72 reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */
73 reg_cfg.s.tim_mult = 2; /* Timing mutiplier 2x */
74 reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */
75 reg_cfg.s.sam = 0; /* Don't combine write and output enable */
76 reg_cfg.s.we_ext = 0; /* No write enable extension */
77 reg_cfg.s.oe_ext = 0; /* No read enable extension */
78 reg_cfg.s.en = 1; /* Enable this region */
79 reg_cfg.s.orbit = 0; /* Don't combine with previous region */
80 reg_cfg.s.ale = 0; /* Don't do address multiplexing */
81 cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64);
82}
83
84/**
85 * Called after libata determines the needed PIO mode. This
86 * function programs the Octeon bootbus regions to support the
87 * timing requirements of the PIO mode.
88 *
89 * @ap: ATA port information
90 * @dev: ATA device
91 */
92static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
93{
94 struct octeon_cf_data *ocd = ap->dev->platform_data;
95 union cvmx_mio_boot_reg_timx reg_tim;
96 int cs = ocd->base_region;
97 int T;
98 struct ata_timing timing;
99
100 int use_iordy;
101 int trh;
102 int pause;
103 /* These names are timing parameters from the ATA spec */
104 int t1;
105 int t2;
106 int t2i;
107
108 T = (int)(2000000000000LL / octeon_get_clock_rate());
109
110 if (ata_timing_compute(dev, dev->pio_mode, &timing, T, T))
111 BUG();
112
113 t1 = timing.setup;
114 if (t1)
115 t1--;
116 t2 = timing.active;
117 if (t2)
118 t2--;
119 t2i = timing.act8b;
120 if (t2i)
121 t2i--;
122
123 trh = ns_to_tim_reg(2, 20);
124 if (trh)
125 trh--;
126
127 pause = timing.cycle - timing.active - timing.setup - trh;
128 if (pause)
129 pause--;
130
131 octeon_cf_set_boot_reg_cfg(cs);
132 if (ocd->dma_engine >= 0)
133 /* True IDE mode, program both chip selects. */
134 octeon_cf_set_boot_reg_cfg(cs + 1);
135
136
137 use_iordy = ata_pio_need_iordy(dev);
138
139 reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cs));
140 /* Disable page mode */
141 reg_tim.s.pagem = 0;
142 /* Enable dynamic timing */
143 reg_tim.s.waitm = use_iordy;
144 /* Pages are disabled */
145 reg_tim.s.pages = 0;
146 /* We don't use multiplexed address mode */
147 reg_tim.s.ale = 0;
148 /* Not used */
149 reg_tim.s.page = 0;
150 /* Time after IORDY to coninue to assert the data */
151 reg_tim.s.wait = 0;
152 /* Time to wait to complete the cycle. */
153 reg_tim.s.pause = pause;
154 /* How long to hold after a write to de-assert CE. */
155 reg_tim.s.wr_hld = trh;
156 /* How long to wait after a read to de-assert CE. */
157 reg_tim.s.rd_hld = trh;
158 /* How long write enable is asserted */
159 reg_tim.s.we = t2;
160 /* How long read enable is asserted */
161 reg_tim.s.oe = t2;
162 /* Time after CE that read/write starts */
163 reg_tim.s.ce = ns_to_tim_reg(2, 5);
164 /* Time before CE that address is valid */
165 reg_tim.s.adr = 0;
166
167 /* Program the bootbus region timing for the data port chip select. */
168 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs), reg_tim.u64);
169 if (ocd->dma_engine >= 0)
170 /* True IDE mode, program both chip selects. */
171 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs + 1), reg_tim.u64);
172}
173
174static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
175{
176 struct octeon_cf_data *ocd = dev->link->ap->dev->platform_data;
177 union cvmx_mio_boot_dma_timx dma_tim;
178 unsigned int oe_a;
179 unsigned int oe_n;
180 unsigned int dma_ackh;
181 unsigned int dma_arq;
182 unsigned int pause;
183 unsigned int T0, Tkr, Td;
184 unsigned int tim_mult;
185
186 const struct ata_timing *timing;
187
188 timing = ata_timing_find_mode(dev->dma_mode);
189 T0 = timing->cycle;
190 Td = timing->active;
191 Tkr = timing->recover;
192 dma_ackh = timing->dmack_hold;
193
194 dma_tim.u64 = 0;
195 /* dma_tim.s.tim_mult = 0 --> 4x */
196 tim_mult = 4;
197
198 /* not spec'ed, value in eclocks, not affected by tim_mult */
199 dma_arq = 8;
200 pause = 25 - dma_arq * 1000 /
201 (octeon_get_clock_rate() / 1000000); /* Tz */
202
203 oe_a = Td;
204 /* Tkr from cf spec, lengthened to meet T0 */
205 oe_n = max(T0 - oe_a, Tkr);
206
207 dma_tim.s.dmack_pi = 1;
208
209 dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n);
210 dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a);
211
212 /*
213 * This is tI, C.F. spec. says 0, but Sony CF card requires
214 * more, we use 20 nS.
215 */
216 dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, 20);;
217 dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh);
218
219 dma_tim.s.dmarq = dma_arq;
220 dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause);
221
222 dma_tim.s.rd_dly = 0; /* Sample right on edge */
223
224 /* writes only */
225 dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n);
226 dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a);
227
228 pr_debug("ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60,
229 ns_to_tim_reg(tim_mult, 60));
230 pr_debug("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: "
231 "%d, dmarq: %d, pause: %d\n",
232 dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s,
233 dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause);
234
235 cvmx_write_csr(CVMX_MIO_BOOT_DMA_TIMX(ocd->dma_engine),
236 dma_tim.u64);
237
238}
239
240/**
241 * Handle an 8 bit I/O request.
242 *
243 * @dev: Device to access
244 * @buffer: Data buffer
245 * @buflen: Length of the buffer.
246 * @rw: True to write.
247 */
248static unsigned int octeon_cf_data_xfer8(struct ata_device *dev,
249 unsigned char *buffer,
250 unsigned int buflen,
251 int rw)
252{
253 struct ata_port *ap = dev->link->ap;
254 void __iomem *data_addr = ap->ioaddr.data_addr;
255 unsigned long words;
256 int count;
257
258 words = buflen;
259 if (rw) {
260 count = 16;
261 while (words--) {
262 iowrite8(*buffer, data_addr);
263 buffer++;
264 /*
265 * Every 16 writes do a read so the bootbus
266 * FIFO doesn't fill up.
267 */
268 if (--count == 0) {
269 ioread8(ap->ioaddr.altstatus_addr);
270 count = 16;
271 }
272 }
273 } else {
274 ioread8_rep(data_addr, buffer, words);
275 }
276 return buflen;
277}
278
279/**
280 * Handle a 16 bit I/O request.
281 *
282 * @dev: Device to access
283 * @buffer: Data buffer
284 * @buflen: Length of the buffer.
285 * @rw: True to write.
286 */
287static unsigned int octeon_cf_data_xfer16(struct ata_device *dev,
288 unsigned char *buffer,
289 unsigned int buflen,
290 int rw)
291{
292 struct ata_port *ap = dev->link->ap;
293 void __iomem *data_addr = ap->ioaddr.data_addr;
294 unsigned long words;
295 int count;
296
297 words = buflen / 2;
298 if (rw) {
299 count = 16;
300 while (words--) {
301 iowrite16(*(uint16_t *)buffer, data_addr);
302 buffer += sizeof(uint16_t);
303 /*
304 * Every 16 writes do a read so the bootbus
305 * FIFO doesn't fill up.
306 */
307 if (--count == 0) {
308 ioread8(ap->ioaddr.altstatus_addr);
309 count = 16;
310 }
311 }
312 } else {
313 while (words--) {
314 *(uint16_t *)buffer = ioread16(data_addr);
315 buffer += sizeof(uint16_t);
316 }
317 }
318 /* Transfer trailing 1 byte, if any. */
319 if (unlikely(buflen & 0x01)) {
320 __le16 align_buf[1] = { 0 };
321
322 if (rw == READ) {
323 align_buf[0] = cpu_to_le16(ioread16(data_addr));
324 memcpy(buffer, align_buf, 1);
325 } else {
326 memcpy(align_buf, buffer, 1);
327 iowrite16(le16_to_cpu(align_buf[0]), data_addr);
328 }
329 words++;
330 }
331 return buflen;
332}
333
334/**
335 * Read the taskfile for 16bit non-True IDE only.
336 */
337static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf)
338{
339 u16 blob;
340 /* The base of the registers is at ioaddr.data_addr. */
341 void __iomem *base = ap->ioaddr.data_addr;
342
343 blob = __raw_readw(base + 0xc);
344 tf->feature = blob >> 8;
345
346 blob = __raw_readw(base + 2);
347 tf->nsect = blob & 0xff;
348 tf->lbal = blob >> 8;
349
350 blob = __raw_readw(base + 4);
351 tf->lbam = blob & 0xff;
352 tf->lbah = blob >> 8;
353
354 blob = __raw_readw(base + 6);
355 tf->device = blob & 0xff;
356 tf->command = blob >> 8;
357
358 if (tf->flags & ATA_TFLAG_LBA48) {
359 if (likely(ap->ioaddr.ctl_addr)) {
360 iowrite8(tf->ctl | ATA_HOB, ap->ioaddr.ctl_addr);
361
362 blob = __raw_readw(base + 0xc);
363 tf->hob_feature = blob >> 8;
364
365 blob = __raw_readw(base + 2);
366 tf->hob_nsect = blob & 0xff;
367 tf->hob_lbal = blob >> 8;
368
369 blob = __raw_readw(base + 4);
370 tf->hob_lbam = blob & 0xff;
371 tf->hob_lbah = blob >> 8;
372
373 iowrite8(tf->ctl, ap->ioaddr.ctl_addr);
374 ap->last_ctl = tf->ctl;
375 } else {
376 WARN_ON(1);
377 }
378 }
379}
380
381static u8 octeon_cf_check_status16(struct ata_port *ap)
382{
383 u16 blob;
384 void __iomem *base = ap->ioaddr.data_addr;
385
386 blob = __raw_readw(base + 6);
387 return blob >> 8;
388}
389
390static int octeon_cf_softreset16(struct ata_link *link, unsigned int *classes,
391 unsigned long deadline)
392{
393 struct ata_port *ap = link->ap;
394 void __iomem *base = ap->ioaddr.data_addr;
395 int rc;
396 u8 err;
397
398 DPRINTK("about to softreset\n");
399 __raw_writew(ap->ctl, base + 0xe);
400 udelay(20);
401 __raw_writew(ap->ctl | ATA_SRST, base + 0xe);
402 udelay(20);
403 __raw_writew(ap->ctl, base + 0xe);
404
405 rc = ata_sff_wait_after_reset(link, 1, deadline);
406 if (rc) {
407 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
408 return rc;
409 }
410
411 /* determine by signature whether we have ATA or ATAPI devices */
412 classes[0] = ata_sff_dev_classify(&link->device[0], 1, &err);
413 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
414 return 0;
415}
416
417/**
418 * Load the taskfile for 16bit non-True IDE only. The device_addr is
419 * not loaded, we do this as part of octeon_cf_exec_command16.
420 */
421static void octeon_cf_tf_load16(struct ata_port *ap,
422 const struct ata_taskfile *tf)
423{
424 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
425 /* The base of the registers is at ioaddr.data_addr. */
426 void __iomem *base = ap->ioaddr.data_addr;
427
428 if (tf->ctl != ap->last_ctl) {
429 iowrite8(tf->ctl, ap->ioaddr.ctl_addr);
430 ap->last_ctl = tf->ctl;
431 ata_wait_idle(ap);
432 }
433 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
434 __raw_writew(tf->hob_feature << 8, base + 0xc);
435 __raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2);
436 __raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4);
437 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
438 tf->hob_feature,
439 tf->hob_nsect,
440 tf->hob_lbal,
441 tf->hob_lbam,
442 tf->hob_lbah);
443 }
444 if (is_addr) {
445 __raw_writew(tf->feature << 8, base + 0xc);
446 __raw_writew(tf->nsect | tf->lbal << 8, base + 2);
447 __raw_writew(tf->lbam | tf->lbah << 8, base + 4);
448 VPRINTK("feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
449 tf->feature,
450 tf->nsect,
451 tf->lbal,
452 tf->lbam,
453 tf->lbah);
454 }
455 ata_wait_idle(ap);
456}
457
458
459static void octeon_cf_dev_select(struct ata_port *ap, unsigned int device)
460{
461/* There is only one device, do nothing. */
462 return;
463}
464
465/*
466 * Issue ATA command to host controller. The device_addr is also sent
467 * as it must be written in a combined write with the command.
468 */
469static void octeon_cf_exec_command16(struct ata_port *ap,
470 const struct ata_taskfile *tf)
471{
472 /* The base of the registers is at ioaddr.data_addr. */
473 void __iomem *base = ap->ioaddr.data_addr;
474 u16 blob;
475
476 if (tf->flags & ATA_TFLAG_DEVICE) {
477 VPRINTK("device 0x%X\n", tf->device);
478 blob = tf->device;
479 } else {
480 blob = 0;
481 }
482
483 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
484 blob |= (tf->command << 8);
485 __raw_writew(blob, base + 6);
486
487
488 ata_wait_idle(ap);
489}
490
491static u8 octeon_cf_irq_on(struct ata_port *ap)
492{
493 return 0;
494}
495
496static void octeon_cf_irq_clear(struct ata_port *ap)
497{
498 return;
499}
500
501static void octeon_cf_dma_setup(struct ata_queued_cmd *qc)
502{
503 struct ata_port *ap = qc->ap;
504 struct octeon_cf_port *cf_port;
505
506 cf_port = (struct octeon_cf_port *)ap->private_data;
507 DPRINTK("ENTER\n");
508 /* issue r/w command */
509 qc->cursg = qc->sg;
510 cf_port->dma_finished = 0;
511 ap->ops->sff_exec_command(ap, &qc->tf);
512 DPRINTK("EXIT\n");
513}
514
515/**
516 * Start a DMA transfer that was already setup
517 *
518 * @qc: Information about the DMA
519 */
520static void octeon_cf_dma_start(struct ata_queued_cmd *qc)
521{
522 struct octeon_cf_data *ocd = qc->ap->dev->platform_data;
523 union cvmx_mio_boot_dma_cfgx mio_boot_dma_cfg;
524 union cvmx_mio_boot_dma_intx mio_boot_dma_int;
525 struct scatterlist *sg;
526
527 VPRINTK("%d scatterlists\n", qc->n_elem);
528
529 /* Get the scatter list entry we need to DMA into */
530 sg = qc->cursg;
531 BUG_ON(!sg);
532
533 /*
534 * Clear the DMA complete status.
535 */
536 mio_boot_dma_int.u64 = 0;
537 mio_boot_dma_int.s.done = 1;
538 cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine),
539 mio_boot_dma_int.u64);
540
541 /* Enable the interrupt. */
542 cvmx_write_csr(CVMX_MIO_BOOT_DMA_INT_ENX(ocd->dma_engine),
543 mio_boot_dma_int.u64);
544
545 /* Set the direction of the DMA */
546 mio_boot_dma_cfg.u64 = 0;
547 mio_boot_dma_cfg.s.en = 1;
548 mio_boot_dma_cfg.s.rw = ((qc->tf.flags & ATA_TFLAG_WRITE) != 0);
549
550 /*
551 * Don't stop the DMA if the device deasserts DMARQ. Many
552 * compact flashes deassert DMARQ for a short time between
553 * sectors. Instead of stopping and restarting the DMA, we'll
554 * let the hardware do it. If the DMA is really stopped early
555 * due to an error condition, a later timeout will force us to
556 * stop.
557 */
558 mio_boot_dma_cfg.s.clr = 0;
559
560 /* Size is specified in 16bit words and minus one notation */
561 mio_boot_dma_cfg.s.size = sg_dma_len(sg) / 2 - 1;
562
563 /* We need to swap the high and low bytes of every 16 bits */
564 mio_boot_dma_cfg.s.swap8 = 1;
565
566 mio_boot_dma_cfg.s.adr = sg_dma_address(sg);
567
568 VPRINTK("%s %d bytes address=%p\n",
569 (mio_boot_dma_cfg.s.rw) ? "write" : "read", sg->length,
570 (void *)(unsigned long)mio_boot_dma_cfg.s.adr);
571
572 cvmx_write_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine),
573 mio_boot_dma_cfg.u64);
574}
575
576/**
577 *
578 * LOCKING:
579 * spin_lock_irqsave(host lock)
580 *
581 */
582static unsigned int octeon_cf_dma_finished(struct ata_port *ap,
583 struct ata_queued_cmd *qc)
584{
585 struct ata_eh_info *ehi = &ap->link.eh_info;
586 struct octeon_cf_data *ocd = ap->dev->platform_data;
587 union cvmx_mio_boot_dma_cfgx dma_cfg;
588 union cvmx_mio_boot_dma_intx dma_int;
589 struct octeon_cf_port *cf_port;
590 u8 status;
591
592 VPRINTK("ata%u: protocol %d task_state %d\n",
593 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
594
595
596 if (ap->hsm_task_state != HSM_ST_LAST)
597 return 0;
598
599 cf_port = (struct octeon_cf_port *)ap->private_data;
600
601 dma_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine));
602 if (dma_cfg.s.size != 0xfffff) {
603 /* Error, the transfer was not complete. */
604 qc->err_mask |= AC_ERR_HOST_BUS;
605 ap->hsm_task_state = HSM_ST_ERR;
606 }
607
608 /* Stop and clear the dma engine. */
609 dma_cfg.u64 = 0;
610 dma_cfg.s.size = -1;
611 cvmx_write_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine), dma_cfg.u64);
612
613 /* Disable the interrupt. */
614 dma_int.u64 = 0;
615 cvmx_write_csr(CVMX_MIO_BOOT_DMA_INT_ENX(ocd->dma_engine), dma_int.u64);
616
617 /* Clear the DMA complete status */
618 dma_int.s.done = 1;
619 cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine), dma_int.u64);
620
621 status = ap->ops->sff_check_status(ap);
622
623 ata_sff_hsm_move(ap, qc, status, 0);
624
625 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA))
626 ata_ehi_push_desc(ehi, "DMA stat 0x%x", status);
627
628 return 1;
629}
630
631/*
632 * Check if any queued commands have more DMAs, if so start the next
633 * transfer, else do end of transfer handling.
634 */
635static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance)
636{
637 struct ata_host *host = dev_instance;
638 struct octeon_cf_port *cf_port;
639 int i;
640 unsigned int handled = 0;
641 unsigned long flags;
642
643 spin_lock_irqsave(&host->lock, flags);
644
645 DPRINTK("ENTER\n");
646 for (i = 0; i < host->n_ports; i++) {
647 u8 status;
648 struct ata_port *ap;
649 struct ata_queued_cmd *qc;
650 union cvmx_mio_boot_dma_intx dma_int;
651 union cvmx_mio_boot_dma_cfgx dma_cfg;
652 struct octeon_cf_data *ocd;
653
654 ap = host->ports[i];
655 ocd = ap->dev->platform_data;
656 if (!ap || (ap->flags & ATA_FLAG_DISABLED))
657 continue;
658
659 ocd = ap->dev->platform_data;
660 cf_port = (struct octeon_cf_port *)ap->private_data;
661 dma_int.u64 =
662 cvmx_read_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine));
663 dma_cfg.u64 =
664 cvmx_read_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine));
665
666 qc = ata_qc_from_tag(ap, ap->link.active_tag);
667
668 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
669 (qc->flags & ATA_QCFLAG_ACTIVE)) {
670 if (dma_int.s.done && !dma_cfg.s.en) {
671 if (!sg_is_last(qc->cursg)) {
672 qc->cursg = sg_next(qc->cursg);
673 handled = 1;
674 octeon_cf_dma_start(qc);
675 continue;
676 } else {
677 cf_port->dma_finished = 1;
678 }
679 }
680 if (!cf_port->dma_finished)
681 continue;
682 status = ioread8(ap->ioaddr.altstatus_addr);
683 if (status & (ATA_BUSY | ATA_DRQ)) {
684 /*
685 * We are busy, try to handle it
686 * later. This is the DMA finished
687 * interrupt, and it could take a
688 * little while for the card to be
689 * ready for more commands.
690 */
691 /* Clear DMA irq. */
692 dma_int.u64 = 0;
693 dma_int.s.done = 1;
694 cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine),
695 dma_int.u64);
696
697 queue_delayed_work(cf_port->wq,
698 &cf_port->delayed_finish, 1);
699 handled = 1;
700 } else {
701 handled |= octeon_cf_dma_finished(ap, qc);
702 }
703 }
704 }
705 spin_unlock_irqrestore(&host->lock, flags);
706 DPRINTK("EXIT\n");
707 return IRQ_RETVAL(handled);
708}
709
710static void octeon_cf_delayed_finish(struct work_struct *work)
711{
712 struct octeon_cf_port *cf_port = container_of(work,
713 struct octeon_cf_port,
714 delayed_finish.work);
715 struct ata_port *ap = cf_port->ap;
716 struct ata_host *host = ap->host;
717 struct ata_queued_cmd *qc;
718 unsigned long flags;
719 u8 status;
720
721 spin_lock_irqsave(&host->lock, flags);
722
723 /*
724 * If the port is not waiting for completion, it must have
725 * handled it previously. The hsm_task_state is
726 * protected by host->lock.
727 */
728 if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished)
729 goto out;
730
731 status = ioread8(ap->ioaddr.altstatus_addr);
732 if (status & (ATA_BUSY | ATA_DRQ)) {
733 /* Still busy, try again. */
734 queue_delayed_work(cf_port->wq,
735 &cf_port->delayed_finish, 1);
736 goto out;
737 }
738 qc = ata_qc_from_tag(ap, ap->link.active_tag);
739 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
740 (qc->flags & ATA_QCFLAG_ACTIVE))
741 octeon_cf_dma_finished(ap, qc);
742out:
743 spin_unlock_irqrestore(&host->lock, flags);
744}
745
746static void octeon_cf_dev_config(struct ata_device *dev)
747{
748 /*
749 * A maximum of 2^20 - 1 16 bit transfers are possible with
750 * the bootbus DMA. So we need to throttle max_sectors to
751 * (2^12 - 1 == 4095) to assure that this can never happen.
752 */
753 dev->max_sectors = min(dev->max_sectors, 4095U);
754}
755
756/*
757 * Trap if driver tries to do standard bmdma commands. They are not
758 * supported.
759 */
760static void unreachable_qc(struct ata_queued_cmd *qc)
761{
762 BUG();
763}
764
765static u8 unreachable_port(struct ata_port *ap)
766{
767 BUG();
768}
769
770/*
771 * We don't do ATAPI DMA so return 0.
772 */
773static int octeon_cf_check_atapi_dma(struct ata_queued_cmd *qc)
774{
775 return 0;
776}
777
778static unsigned int octeon_cf_qc_issue(struct ata_queued_cmd *qc)
779{
780 struct ata_port *ap = qc->ap;
781
782 switch (qc->tf.protocol) {
783 case ATA_PROT_DMA:
784 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
785
786 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
787 octeon_cf_dma_setup(qc); /* set up dma */
788 octeon_cf_dma_start(qc); /* initiate dma */
789 ap->hsm_task_state = HSM_ST_LAST;
790 break;
791
792 case ATAPI_PROT_DMA:
793 dev_err(ap->dev, "Error, ATAPI not supported\n");
794 BUG();
795
796 default:
797 return ata_sff_qc_issue(qc);
798 }
799
800 return 0;
801}
802
803static struct ata_port_operations octeon_cf_ops = {
804 .inherits = &ata_sff_port_ops,
805 .check_atapi_dma = octeon_cf_check_atapi_dma,
806 .qc_prep = ata_noop_qc_prep,
807 .qc_issue = octeon_cf_qc_issue,
808 .sff_dev_select = octeon_cf_dev_select,
809 .sff_irq_on = octeon_cf_irq_on,
810 .sff_irq_clear = octeon_cf_irq_clear,
811 .bmdma_setup = unreachable_qc,
812 .bmdma_start = unreachable_qc,
813 .bmdma_stop = unreachable_qc,
814 .bmdma_status = unreachable_port,
815 .cable_detect = ata_cable_40wire,
816 .set_piomode = octeon_cf_set_piomode,
817 .set_dmamode = octeon_cf_set_dmamode,
818 .dev_config = octeon_cf_dev_config,
819};
820
821static int __devinit octeon_cf_probe(struct platform_device *pdev)
822{
823 struct resource *res_cs0, *res_cs1;
824
825 void __iomem *cs0;
826 void __iomem *cs1 = NULL;
827 struct ata_host *host;
828 struct ata_port *ap;
829 struct octeon_cf_data *ocd;
830 int irq = 0;
831 irq_handler_t irq_handler = NULL;
832 void __iomem *base;
833 struct octeon_cf_port *cf_port;
834
835 res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
836
837 if (!res_cs0)
838 return -EINVAL;
839
840 ocd = pdev->dev.platform_data;
841
842 cs0 = devm_ioremap_nocache(&pdev->dev, res_cs0->start,
843 res_cs0->end - res_cs0->start + 1);
844
845 if (!cs0)
846 return -ENOMEM;
847
848 /* Determine from availability of DMA if True IDE mode or not */
849 if (ocd->dma_engine >= 0) {
850 res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
851 if (!res_cs1)
852 return -EINVAL;
853
854 cs1 = devm_ioremap_nocache(&pdev->dev, res_cs1->start,
855 res_cs0->end - res_cs1->start + 1);
856
857 if (!cs1)
858 return -ENOMEM;
859 }
860
861 cf_port = kzalloc(sizeof(*cf_port), GFP_KERNEL);
862 if (!cf_port)
863 return -ENOMEM;
864
865 /* allocate host */
866 host = ata_host_alloc(&pdev->dev, 1);
867 if (!host)
868 goto free_cf_port;
869
870 ap = host->ports[0];
871 ap->private_data = cf_port;
872 cf_port->ap = ap;
873 ap->ops = &octeon_cf_ops;
874 ap->pio_mask = 0x7f; /* Support PIO 0-6 */
875 ap->flags |= ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY
876 | ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING;
877
878 base = cs0 + ocd->base_region_bias;
879 if (!ocd->is16bit) {
880 ap->ioaddr.cmd_addr = base;
881 ata_sff_std_ports(&ap->ioaddr);
882
883 ap->ioaddr.altstatus_addr = base + 0xe;
884 ap->ioaddr.ctl_addr = base + 0xe;
885 octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer8;
886 } else if (cs1) {
887 /* Presence of cs1 indicates True IDE mode. */
888 ap->ioaddr.cmd_addr = base + (ATA_REG_CMD << 1) + 1;
889 ap->ioaddr.data_addr = base + (ATA_REG_DATA << 1);
890 ap->ioaddr.error_addr = base + (ATA_REG_ERR << 1) + 1;
891 ap->ioaddr.feature_addr = base + (ATA_REG_FEATURE << 1) + 1;
892 ap->ioaddr.nsect_addr = base + (ATA_REG_NSECT << 1) + 1;
893 ap->ioaddr.lbal_addr = base + (ATA_REG_LBAL << 1) + 1;
894 ap->ioaddr.lbam_addr = base + (ATA_REG_LBAM << 1) + 1;
895 ap->ioaddr.lbah_addr = base + (ATA_REG_LBAH << 1) + 1;
896 ap->ioaddr.device_addr = base + (ATA_REG_DEVICE << 1) + 1;
897 ap->ioaddr.status_addr = base + (ATA_REG_STATUS << 1) + 1;
898 ap->ioaddr.command_addr = base + (ATA_REG_CMD << 1) + 1;
899 ap->ioaddr.altstatus_addr = cs1 + (6 << 1) + 1;
900 ap->ioaddr.ctl_addr = cs1 + (6 << 1) + 1;
901 octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
902
903 ap->mwdma_mask = 0x1f; /* Support MWDMA 0-4 */
904 irq = platform_get_irq(pdev, 0);
905 irq_handler = octeon_cf_interrupt;
906
907 /* True IDE mode needs delayed work to poll for not-busy. */
908 cf_port->wq = create_singlethread_workqueue(DRV_NAME);
909 if (!cf_port->wq)
910 goto free_cf_port;
911 INIT_DELAYED_WORK(&cf_port->delayed_finish,
912 octeon_cf_delayed_finish);
913
914 } else {
915 /* 16 bit but not True IDE */
916 octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
917 octeon_cf_ops.softreset = octeon_cf_softreset16;
918 octeon_cf_ops.sff_check_status = octeon_cf_check_status16;
919 octeon_cf_ops.sff_tf_read = octeon_cf_tf_read16;
920 octeon_cf_ops.sff_tf_load = octeon_cf_tf_load16;
921 octeon_cf_ops.sff_exec_command = octeon_cf_exec_command16;
922
923 ap->ioaddr.data_addr = base + ATA_REG_DATA;
924 ap->ioaddr.nsect_addr = base + ATA_REG_NSECT;
925 ap->ioaddr.lbal_addr = base + ATA_REG_LBAL;
926 ap->ioaddr.ctl_addr = base + 0xe;
927 ap->ioaddr.altstatus_addr = base + 0xe;
928 }
929
930 ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr);
931
932
933 dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n",
934 (ocd->is16bit) ? 16 : 8,
935 (cs1) ? ", True IDE" : "");
936
937
938 return ata_host_activate(host, irq, irq_handler, 0, &octeon_cf_sht);
939
940free_cf_port:
941 kfree(cf_port);
942 return -ENOMEM;
943}
944
945static struct platform_driver octeon_cf_driver = {
946 .probe = octeon_cf_probe,
947 .driver = {
948 .name = DRV_NAME,
949 .owner = THIS_MODULE,
950 },
951};
952
953static int __init octeon_cf_init(void)
954{
955 return platform_driver_register(&octeon_cf_driver);
956}
957
958
959MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
960MODULE_DESCRIPTION("low-level driver for Cavium OCTEON Compact Flash PATA");
961MODULE_LICENSE("GPL");
962MODULE_VERSION(DRV_VERSION);
963MODULE_ALIAS("platform:" DRV_NAME);
964
965module_init(octeon_cf_init);
diff --git a/drivers/ata/pata_rb532_cf.c b/drivers/ata/pata_rb532_cf.c
index c2e6fb9f2ef9..ebfcda26d639 100644
--- a/drivers/ata/pata_rb532_cf.c
+++ b/drivers/ata/pata_rb532_cf.c
@@ -63,8 +63,6 @@ static inline void rb532_pata_finish_io(struct ata_port *ap)
63 ata_sff_sync might be sufficient. */ 63 ata_sff_sync might be sufficient. */
64 ata_sff_dma_pause(ap); 64 ata_sff_dma_pause(ap);
65 ndelay(RB500_CF_IO_DELAY); 65 ndelay(RB500_CF_IO_DELAY);
66
67 set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
68} 66}
69 67
70static void rb532_pata_exec_command(struct ata_port *ap, 68static void rb532_pata_exec_command(struct ata_port *ap,
diff --git a/drivers/ata/pata_via.c b/drivers/ata/pata_via.c
index 681169c9c640..79a6c9a0b721 100644
--- a/drivers/ata/pata_via.c
+++ b/drivers/ata/pata_via.c
@@ -86,6 +86,10 @@ enum {
86 VIA_SATA_PATA = 0x800, /* SATA/PATA combined configuration */ 86 VIA_SATA_PATA = 0x800, /* SATA/PATA combined configuration */
87}; 87};
88 88
89enum {
90 VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */
91};
92
89/* 93/*
90 * VIA SouthBridge chips. 94 * VIA SouthBridge chips.
91 */ 95 */
@@ -97,8 +101,12 @@ static const struct via_isa_bridge {
97 u8 rev_max; 101 u8 rev_max;
98 u16 flags; 102 u16 flags;
99} via_isa_bridges[] = { 103} via_isa_bridges[] = {
104 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f,
105 VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA },
100 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, VIA_UDMA_133 | 106 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, VIA_UDMA_133 |
101 VIA_BAD_AST | VIA_SATA_PATA }, 107 VIA_BAD_AST | VIA_SATA_PATA },
108 { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f,
109 VIA_UDMA_133 | VIA_BAD_AST },
102 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 110 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
103 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 111 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
104 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA }, 112 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA },
@@ -122,6 +130,8 @@ static const struct via_isa_bridge {
122 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO }, 130 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
123 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK }, 131 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
124 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, 132 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
133 { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f,
134 VIA_UDMA_133 | VIA_BAD_AST },
125 { NULL } 135 { NULL }
126}; 136};
127 137
@@ -460,6 +470,7 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
460 static int printed_version; 470 static int printed_version;
461 u8 enable; 471 u8 enable;
462 u32 timing; 472 u32 timing;
473 unsigned long flags = id->driver_data;
463 int rc; 474 int rc;
464 475
465 if (!printed_version++) 476 if (!printed_version++)
@@ -469,9 +480,13 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
469 if (rc) 480 if (rc)
470 return rc; 481 return rc;
471 482
483 if (flags & VIA_IDFLAG_SINGLE)
484 ppi[1] = &ata_dummy_port_info;
485
472 /* To find out how the IDE will behave and what features we 486 /* To find out how the IDE will behave and what features we
473 actually have to look at the bridge not the IDE controller */ 487 actually have to look at the bridge not the IDE controller */
474 for (config = via_isa_bridges; config->id; config++) 488 for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON;
489 config++)
475 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA + 490 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
476 !!(config->flags & VIA_BAD_ID), 491 !!(config->flags & VIA_BAD_ID),
477 config->id, NULL))) { 492 config->id, NULL))) {
@@ -482,10 +497,6 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
482 pci_dev_put(isa); 497 pci_dev_put(isa);
483 } 498 }
484 499
485 if (!config->id) {
486 printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
487 return -ENODEV;
488 }
489 pci_dev_put(isa); 500 pci_dev_put(isa);
490 501
491 if (!(config->flags & VIA_NO_ENABLES)) { 502 if (!(config->flags & VIA_NO_ENABLES)) {
@@ -587,6 +598,7 @@ static const struct pci_device_id via[] = {
587 { PCI_VDEVICE(VIA, 0x1571), }, 598 { PCI_VDEVICE(VIA, 0x1571), },
588 { PCI_VDEVICE(VIA, 0x3164), }, 599 { PCI_VDEVICE(VIA, 0x3164), },
589 { PCI_VDEVICE(VIA, 0x5324), }, 600 { PCI_VDEVICE(VIA, 0x5324), },
601 { PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE },
590 602
591 { }, 603 { },
592}; 604};
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index 1a56db92ff7a..55bc88c1707b 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -1288,7 +1288,7 @@ static const struct ata_port_info sata_fsl_port_info[] = {
1288static int sata_fsl_probe(struct of_device *ofdev, 1288static int sata_fsl_probe(struct of_device *ofdev,
1289 const struct of_device_id *match) 1289 const struct of_device_id *match)
1290{ 1290{
1291 int retval = 0; 1291 int retval = -ENXIO;
1292 void __iomem *hcr_base = NULL; 1292 void __iomem *hcr_base = NULL;
1293 void __iomem *ssr_base = NULL; 1293 void __iomem *ssr_base = NULL;
1294 void __iomem *csr_base = NULL; 1294 void __iomem *csr_base = NULL;
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 86918634a4c5..f2d8a020ea53 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -33,10 +33,6 @@
33 * 33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it). 34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 * 35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it. 36 * --> Develop a low-power-consumption strategy, and implement it.
41 * 37 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing. 38 * --> [Experiment, low priority] Investigate interrupt coalescing.
@@ -72,7 +68,7 @@
72#include <linux/libata.h> 68#include <linux/libata.h>
73 69
74#define DRV_NAME "sata_mv" 70#define DRV_NAME "sata_mv"
75#define DRV_VERSION "1.24" 71#define DRV_VERSION "1.25"
76 72
77enum { 73enum {
78 /* BAR's are enumerated in terms of pci_resource_start() terms */ 74 /* BAR's are enumerated in terms of pci_resource_start() terms */
@@ -351,8 +347,6 @@ enum {
351 347
352 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */ 348 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
353 349
354 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
355
356 /* Host private flags (hp_flags) */ 350 /* Host private flags (hp_flags) */
357 MV_HP_FLAG_MSI = (1 << 0), 351 MV_HP_FLAG_MSI = (1 << 0),
358 MV_HP_ERRATA_50XXB0 = (1 << 1), 352 MV_HP_ERRATA_50XXB0 = (1 << 1),
@@ -883,19 +877,15 @@ static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
883 struct mv_host_priv *hpriv = ap->host->private_data; 877 struct mv_host_priv *hpriv = ap->host->private_data;
884 int hardport = mv_hardport_from_port(ap->port_no); 878 int hardport = mv_hardport_from_port(ap->port_no);
885 void __iomem *hc_mmio = mv_hc_base_from_port( 879 void __iomem *hc_mmio = mv_hc_base_from_port(
886 mv_host_base(ap->host), hardport); 880 mv_host_base(ap->host), ap->port_no);
887 u32 hc_irq_cause, ipending; 881 u32 hc_irq_cause;
888 882
889 /* clear EDMA event indicators, if any */ 883 /* clear EDMA event indicators, if any */
890 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 884 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
891 885
892 /* clear EDMA interrupt indicator, if any */ 886 /* clear pending irq events */
893 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 887 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
894 ipending = (DEV_IRQ | DMA_IRQ) << hardport; 888 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
895 if (hc_irq_cause & ipending) {
896 writelfl(hc_irq_cause & ~ipending,
897 hc_mmio + HC_IRQ_CAUSE_OFS);
898 }
899 889
900 mv_edma_cfg(ap, want_ncq); 890 mv_edma_cfg(ap, want_ncq);
901 891
@@ -1099,20 +1089,12 @@ static void mv6_dev_config(struct ata_device *adev)
1099 * 1089 *
1100 * Gen-II does not support NCQ over a port multiplier 1090 * Gen-II does not support NCQ over a port multiplier
1101 * (no FIS-based switching). 1091 * (no FIS-based switching).
1102 *
1103 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1104 * See mv_qc_prep() for more info.
1105 */ 1092 */
1106 if (adev->flags & ATA_DFLAG_NCQ) { 1093 if (adev->flags & ATA_DFLAG_NCQ) {
1107 if (sata_pmp_attached(adev->link->ap)) { 1094 if (sata_pmp_attached(adev->link->ap)) {
1108 adev->flags &= ~ATA_DFLAG_NCQ; 1095 adev->flags &= ~ATA_DFLAG_NCQ;
1109 ata_dev_printk(adev, KERN_INFO, 1096 ata_dev_printk(adev, KERN_INFO,
1110 "NCQ disabled for command-based switching\n"); 1097 "NCQ disabled for command-based switching\n");
1111 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1112 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1113 ata_dev_printk(adev, KERN_INFO,
1114 "max_sectors limited to %u for NCQ\n",
1115 adev->max_sectors);
1116 } 1098 }
1117 } 1099 }
1118} 1100}
@@ -1450,7 +1432,8 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
1450 * only 11 bytes...so we must pick and choose required 1432 * only 11 bytes...so we must pick and choose required
1451 * registers based on the command. So, we drop feature and 1433 * registers based on the command. So, we drop feature and
1452 * hob_feature for [RW] DMA commands, but they are needed for 1434 * hob_feature for [RW] DMA commands, but they are needed for
1453 * NCQ. NCQ will drop hob_nsect. 1435 * NCQ. NCQ will drop hob_nsect, which is not needed there
1436 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
1454 */ 1437 */
1455 switch (tf->command) { 1438 switch (tf->command) {
1456 case ATA_CMD_READ: 1439 case ATA_CMD_READ:
@@ -2214,9 +2197,15 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2214 struct ata_host *host = dev_instance; 2197 struct ata_host *host = dev_instance;
2215 struct mv_host_priv *hpriv = host->private_data; 2198 struct mv_host_priv *hpriv = host->private_data;
2216 unsigned int handled = 0; 2199 unsigned int handled = 0;
2200 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2217 u32 main_irq_cause, pending_irqs; 2201 u32 main_irq_cause, pending_irqs;
2218 2202
2219 spin_lock(&host->lock); 2203 spin_lock(&host->lock);
2204
2205 /* for MSI: block new interrupts while in here */
2206 if (using_msi)
2207 writel(0, hpriv->main_irq_mask_addr);
2208
2220 main_irq_cause = readl(hpriv->main_irq_cause_addr); 2209 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2221 pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2210 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2222 /* 2211 /*
@@ -2230,6 +2219,11 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2230 handled = mv_host_intr(host, pending_irqs); 2219 handled = mv_host_intr(host, pending_irqs);
2231 } 2220 }
2232 spin_unlock(&host->lock); 2221 spin_unlock(&host->lock);
2222
2223 /* for MSI: unmask; interrupt cause bits will retrigger now */
2224 if (using_msi)
2225 writel(hpriv->main_irq_mask, hpriv->main_irq_mask_addr);
2226
2233 return IRQ_RETVAL(handled); 2227 return IRQ_RETVAL(handled);
2234} 2228}
2235 2229
@@ -2821,8 +2815,7 @@ static void mv_eh_thaw(struct ata_port *ap)
2821 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2815 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2822 2816
2823 /* clear pending irq events */ 2817 /* clear pending irq events */
2824 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 2818 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
2825 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2826 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2819 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
2827 2820
2828 mv_enable_port_irqs(ap, ERR_IRQ); 2821 mv_enable_port_irqs(ap, ERR_IRQ);
@@ -3075,6 +3068,9 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3075 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS; 3068 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3076 } 3069 }
3077 3070
3071 /* initialize shadow irq mask with register's value */
3072 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3073
3078 /* global interrupt mask: 0 == mask everything */ 3074 /* global interrupt mask: 0 == mask everything */
3079 mv_set_main_irq_mask(host, ~0, 0); 3075 mv_set_main_irq_mask(host, ~0, 0);
3080 3076
@@ -3430,9 +3426,9 @@ static int mv_pci_init_one(struct pci_dev *pdev,
3430 if (rc) 3426 if (rc)
3431 return rc; 3427 return rc;
3432 3428
3433 /* Enable interrupts */ 3429 /* Enable message-switched interrupts, if requested */
3434 if (msi && pci_enable_msi(pdev)) 3430 if (msi && pci_enable_msi(pdev) == 0)
3435 pci_intx(pdev, 1); 3431 hpriv->hp_flags |= MV_HP_FLAG_MSI;
3436 3432
3437 mv_dump_pci_cfg(pdev, 0x68); 3433 mv_dump_pci_cfg(pdev, 0x68);
3438 mv_print_info(host); 3434 mv_print_info(host);
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c
index 6f1460614325..c49ad0e61b6f 100644
--- a/drivers/ata/sata_nv.c
+++ b/drivers/ata/sata_nv.c
@@ -305,10 +305,10 @@ static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
305static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 305static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
306static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 306static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
307 307
308static int nv_noclassify_hardreset(struct ata_link *link, unsigned int *class,
309 unsigned long deadline);
308static void nv_nf2_freeze(struct ata_port *ap); 310static void nv_nf2_freeze(struct ata_port *ap);
309static void nv_nf2_thaw(struct ata_port *ap); 311static void nv_nf2_thaw(struct ata_port *ap);
310static int nv_nf2_hardreset(struct ata_link *link, unsigned int *class,
311 unsigned long deadline);
312static void nv_ck804_freeze(struct ata_port *ap); 312static void nv_ck804_freeze(struct ata_port *ap);
313static void nv_ck804_thaw(struct ata_port *ap); 313static void nv_ck804_thaw(struct ata_port *ap);
314static int nv_adma_slave_config(struct scsi_device *sdev); 314static int nv_adma_slave_config(struct scsi_device *sdev);
@@ -352,6 +352,7 @@ enum nv_host_type
352 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */ 352 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
353 CK804, 353 CK804,
354 ADMA, 354 ADMA,
355 MCP5x,
355 SWNCQ, 356 SWNCQ,
356}; 357};
357 358
@@ -363,10 +364,10 @@ static const struct pci_device_id nv_pci_tbl[] = {
363 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 }, 364 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
364 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 }, 365 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
365 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 }, 366 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
366 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), SWNCQ }, 367 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), MCP5x },
367 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), SWNCQ }, 368 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), MCP5x },
368 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), SWNCQ }, 369 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), MCP5x },
369 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), SWNCQ }, 370 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), MCP5x },
370 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC }, 371 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
371 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC }, 372 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
372 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC }, 373 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
@@ -432,7 +433,7 @@ static struct ata_port_operations nv_nf2_ops = {
432 .inherits = &nv_common_ops, 433 .inherits = &nv_common_ops,
433 .freeze = nv_nf2_freeze, 434 .freeze = nv_nf2_freeze,
434 .thaw = nv_nf2_thaw, 435 .thaw = nv_nf2_thaw,
435 .hardreset = nv_nf2_hardreset, 436 .hardreset = nv_noclassify_hardreset,
436}; 437};
437 438
438/* CK804 finally gets hardreset right */ 439/* CK804 finally gets hardreset right */
@@ -467,8 +468,19 @@ static struct ata_port_operations nv_adma_ops = {
467 .host_stop = nv_adma_host_stop, 468 .host_stop = nv_adma_host_stop,
468}; 469};
469 470
471/* Kernel bz#12351 reports that when SWNCQ is enabled, for hotplug to
472 * work, hardreset should be used and hardreset can't report proper
473 * signature, which suggests that mcp5x is closer to nf2 as long as
474 * reset quirkiness is concerned. Define separate ops for mcp5x with
475 * nv_noclassify_hardreset().
476 */
477static struct ata_port_operations nv_mcp5x_ops = {
478 .inherits = &nv_common_ops,
479 .hardreset = nv_noclassify_hardreset,
480};
481
470static struct ata_port_operations nv_swncq_ops = { 482static struct ata_port_operations nv_swncq_ops = {
471 .inherits = &nv_generic_ops, 483 .inherits = &nv_mcp5x_ops,
472 484
473 .qc_defer = ata_std_qc_defer, 485 .qc_defer = ata_std_qc_defer,
474 .qc_prep = nv_swncq_qc_prep, 486 .qc_prep = nv_swncq_qc_prep,
@@ -531,6 +543,15 @@ static const struct ata_port_info nv_port_info[] = {
531 .port_ops = &nv_adma_ops, 543 .port_ops = &nv_adma_ops,
532 .private_data = NV_PI_PRIV(nv_adma_interrupt, &nv_adma_sht), 544 .private_data = NV_PI_PRIV(nv_adma_interrupt, &nv_adma_sht),
533 }, 545 },
546 /* MCP5x */
547 {
548 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
549 .pio_mask = NV_PIO_MASK,
550 .mwdma_mask = NV_MWDMA_MASK,
551 .udma_mask = NV_UDMA_MASK,
552 .port_ops = &nv_mcp5x_ops,
553 .private_data = NV_PI_PRIV(nv_generic_interrupt, &nv_sht),
554 },
534 /* SWNCQ */ 555 /* SWNCQ */
535 { 556 {
536 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 557 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
@@ -1530,6 +1551,17 @@ static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
1530 return 0; 1551 return 0;
1531} 1552}
1532 1553
1554static int nv_noclassify_hardreset(struct ata_link *link, unsigned int *class,
1555 unsigned long deadline)
1556{
1557 bool online;
1558 int rc;
1559
1560 rc = sata_link_hardreset(link, sata_deb_timing_hotplug, deadline,
1561 &online, NULL);
1562 return online ? -EAGAIN : rc;
1563}
1564
1533static void nv_nf2_freeze(struct ata_port *ap) 1565static void nv_nf2_freeze(struct ata_port *ap)
1534{ 1566{
1535 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr; 1567 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
@@ -1554,17 +1586,6 @@ static void nv_nf2_thaw(struct ata_port *ap)
1554 iowrite8(mask, scr_addr + NV_INT_ENABLE); 1586 iowrite8(mask, scr_addr + NV_INT_ENABLE);
1555} 1587}
1556 1588
1557static int nv_nf2_hardreset(struct ata_link *link, unsigned int *class,
1558 unsigned long deadline)
1559{
1560 bool online;
1561 int rc;
1562
1563 rc = sata_link_hardreset(link, sata_deb_timing_hotplug, deadline,
1564 &online, NULL);
1565 return online ? -EAGAIN : rc;
1566}
1567
1568static void nv_ck804_freeze(struct ata_port *ap) 1589static void nv_ck804_freeze(struct ata_port *ap)
1569{ 1590{
1570 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; 1591 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
@@ -2355,14 +2376,9 @@ static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2355 if (type == CK804 && adma_enabled) { 2376 if (type == CK804 && adma_enabled) {
2356 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n"); 2377 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
2357 type = ADMA; 2378 type = ADMA;
2358 } 2379 } else if (type == MCP5x && swncq_enabled) {
2359 2380 dev_printk(KERN_NOTICE, &pdev->dev, "Using SWNCQ mode\n");
2360 if (type == SWNCQ) { 2381 type = SWNCQ;
2361 if (swncq_enabled)
2362 dev_printk(KERN_NOTICE, &pdev->dev,
2363 "Using SWNCQ mode\n");
2364 else
2365 type = GENERIC;
2366 } 2382 }
2367 2383
2368 ppi[0] = &nv_port_info[type]; 2384 ppi[0] = &nv_port_info[type];
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c
index 564c142b03b0..bfd55b085ae6 100644
--- a/drivers/ata/sata_sil.c
+++ b/drivers/ata/sata_sil.c
@@ -695,11 +695,38 @@ static void sil_init_controller(struct ata_host *host)
695 } 695 }
696} 696}
697 697
698static bool sil_broken_system_poweroff(struct pci_dev *pdev)
699{
700 static const struct dmi_system_id broken_systems[] = {
701 {
702 .ident = "HP Compaq nx6325",
703 .matches = {
704 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
705 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6325"),
706 },
707 /* PCI slot number of the controller */
708 .driver_data = (void *)0x12UL,
709 },
710
711 { } /* terminate list */
712 };
713 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
714
715 if (dmi) {
716 unsigned long slot = (unsigned long)dmi->driver_data;
717 /* apply the quirk only to on-board controllers */
718 return slot == PCI_SLOT(pdev->devfn);
719 }
720
721 return false;
722}
723
698static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 724static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
699{ 725{
700 static int printed_version; 726 static int printed_version;
701 int board_id = ent->driver_data; 727 int board_id = ent->driver_data;
702 const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL }; 728 struct ata_port_info pi = sil_port_info[board_id];
729 const struct ata_port_info *ppi[] = { &pi, NULL };
703 struct ata_host *host; 730 struct ata_host *host;
704 void __iomem *mmio_base; 731 void __iomem *mmio_base;
705 int n_ports, rc; 732 int n_ports, rc;
@@ -713,6 +740,13 @@ static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
713 if (board_id == sil_3114) 740 if (board_id == sil_3114)
714 n_ports = 4; 741 n_ports = 4;
715 742
743 if (sil_broken_system_poweroff(pdev)) {
744 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN |
745 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
746 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
747 "on poweroff and hibernation\n");
748 }
749
716 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 750 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
717 if (!host) 751 if (!host)
718 return -ENOMEM; 752 return -ENOMEM;
diff --git a/drivers/ata/sata_via.c b/drivers/ata/sata_via.c
index c18935f0bda2..5c62da9cd491 100644
--- a/drivers/ata/sata_via.c
+++ b/drivers/ata/sata_via.c
@@ -92,6 +92,8 @@ static const struct pci_device_id svia_pci_tbl[] = {
92 { PCI_VDEVICE(VIA, 0x5372), vt6420 }, 92 { PCI_VDEVICE(VIA, 0x5372), vt6420 },
93 { PCI_VDEVICE(VIA, 0x7372), vt6420 }, 93 { PCI_VDEVICE(VIA, 0x7372), vt6420 },
94 { PCI_VDEVICE(VIA, 0x5287), vt8251 }, /* 2 sata chnls (Master/Slave) */ 94 { PCI_VDEVICE(VIA, 0x5287), vt8251 }, /* 2 sata chnls (Master/Slave) */
95 { PCI_VDEVICE(VIA, 0x9000), vt8251 },
96 { PCI_VDEVICE(VIA, 0x9040), vt8251 },
95 97
96 { } /* terminate list */ 98 { } /* terminate list */
97}; 99};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 19:44:07 -0500