85 files changed, 8104 insertions, 4894 deletions

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 01c52c415bdc..11ec911016c6 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -57,6 +57,8 @@ config SATA_PMP
           This option adds support for SATA Port Multipliers
           (the SATA version of an ethernet hub, or SAS expander).
 
+comment "Controllers with non-SFF native interface"
+
 config SATA_AHCI
         tristate "AHCI SATA support"
         depends on PCI
@@ -65,11 +67,11 @@ config SATA_AHCI
 
           If unsure, say N.
 
-config SATA_SIL24
-        tristate "Silicon Image 3124/3132 SATA support"
-        depends on PCI
+config SATA_AHCI_PLATFORM
+        tristate "Platform AHCI SATA support"
         help
-          This option enables support for Silicon Image 3124/3132 Serial ATA.
+          This option enables support for Platform AHCI Serial ATA
+          controllers.
 
           If unsure, say N.
 
@@ -82,6 +84,20 @@ config SATA_FSL
 
           If unsure, say N.
 
+config SATA_INIC162X
+        tristate "Initio 162x SATA support"
+        depends on PCI
+        help
+          This option enables support for Initio 162x Serial ATA.
+
+config SATA_SIL24
+        tristate "Silicon Image 3124/3132 SATA support"
+        depends on PCI
+        help
+          This option enables support for Silicon Image 3124/3132 Serial ATA.
+
+          If unsure, say N.
+
 config ATA_SFF
         bool "ATA SFF support"
         default y
@@ -102,15 +118,65 @@ config ATA_SFF
 
 if ATA_SFF
 
-config SATA_SVW
-        tristate "ServerWorks Frodo / Apple K2 SATA support"
+comment "SFF controllers with custom DMA interface"
+
+config PDC_ADMA
+        tristate "Pacific Digital ADMA support"
         depends on PCI
         help
-          This option enables support for Broadcom/Serverworks/Apple K2
-          SATA support.
+          This option enables support for Pacific Digital ADMA controllers
+
+          If unsure, say N.
+
+config PATA_MPC52xx
+        tristate "Freescale MPC52xx SoC internal IDE"
+        depends on PPC_MPC52xx && PPC_BESTCOMM
+        select PPC_BESTCOMM_ATA
+        help
+          This option enables support for integrated IDE controller
+          of the Freescale MPC52xx SoC.
+
+          If unsure, say N.
+
+config PATA_OCTEON_CF
+        tristate "OCTEON Boot Bus Compact Flash support"
+        depends on CPU_CAVIUM_OCTEON
+        help
+          This option enables a polled compact flash driver for use with
+          compact flash cards attached to the OCTEON boot bus.
+
+          If unsure, say N.
+
+config SATA_QSTOR
+        tristate "Pacific Digital SATA QStor support"
+        depends on PCI
+        help
+          This option enables support for Pacific Digital Serial ATA QStor.
+
+          If unsure, say N.
+
+config SATA_SX4
+        tristate "Promise SATA SX4 support (Experimental)"
+        depends on PCI && EXPERIMENTAL
+        help
+          This option enables support for Promise Serial ATA SX4.
 
           If unsure, say N.
 
+config ATA_BMDMA
+        bool "ATA BMDMA support"
+        default y
+        help
+          This option adds support for SFF ATA controllers with BMDMA
+          capability.  BMDMA stands for bus-master DMA and is the
+          de facto DMA interface for SFF controllers.
+
+          If unsure, say Y.
+
+if ATA_BMDMA
+
+comment "SATA SFF controllers with BMDMA"
+
 config ATA_PIIX
         tristate "Intel ESB, ICH, PIIX3, PIIX4 PATA/SATA support"
         depends on PCI
@@ -121,6 +187,15 @@ config ATA_PIIX
 
           If unsure, say N.
 
+config SATA_DWC
+        tristate "DesignWare Cores SATA support"
+        depends on 460EX
+        help
+          This option enables support for the on-chip SATA controller of the
+          AppliedMicro processor 460EX.
+
+          If unsure, say N.
+
 config SATA_MV
         tristate "Marvell SATA support"
         help
@@ -138,22 +213,6 @@ config SATA_NV
 
           If unsure, say N.
 
-config PDC_ADMA
-        tristate "Pacific Digital ADMA support"
-        depends on PCI
-        help
-          This option enables support for Pacific Digital ADMA controllers
-
-          If unsure, say N.
-
-config SATA_QSTOR
-        tristate "Pacific Digital SATA QStor support"
-        depends on PCI
-        help
-          This option enables support for Pacific Digital Serial ATA QStor.
-
-          If unsure, say N.
-
 config SATA_PROMISE
         tristate "Promise SATA TX2/TX4 support"
         depends on PCI
@@ -162,14 +221,6 @@ config SATA_PROMISE
 
           If unsure, say N.
 
-config SATA_SX4
-        tristate "Promise SATA SX4 support (Experimental)"
-        depends on PCI && EXPERIMENTAL
-        help
-          This option enables support for Promise Serial ATA SX4.
-
-          If unsure, say N.
-
 config SATA_SIL
         tristate "Silicon Image SATA support"
         depends on PCI
@@ -189,6 +240,15 @@ config SATA_SIS
           enable the PATA_SIS driver in the config.
           If unsure, say N.
 
+config SATA_SVW
+        tristate "ServerWorks Frodo / Apple K2 SATA support"
+        depends on PCI
+        help
+          This option enables support for Broadcom/Serverworks/Apple K2
+          SATA support.
+
+          If unsure, say N.
+
 config SATA_ULI
         tristate "ULi Electronics SATA support"
         depends on PCI
@@ -213,20 +273,7 @@ config SATA_VITESSE
 
           If unsure, say N.
 
-config SATA_INIC162X
-        tristate "Initio 162x SATA support"
-        depends on PCI
-        help
-          This option enables support for Initio 162x Serial ATA.
-
-config PATA_ACPI
-        tristate "ACPI firmware driver for PATA"
-        depends on ATA_ACPI
-        help
-          This option enables an ACPI method driver which drives
-          motherboard PATA controller interfaces through the ACPI
-          firmware in the BIOS. This driver can sometimes handle
-          otherwise unsupported hardware.
+comment "PATA SFF controllers with BMDMA"
 
 config PATA_ALI
         tristate "ALi PATA support"
@@ -254,40 +301,30 @@ config PATA_ARTOP
 
           If unsure, say N.
 
-config PATA_ATP867X
-        tristate "ARTOP/Acard ATP867X PATA support"
+config PATA_ATIIXP
+        tristate "ATI PATA support"
         depends on PCI
         help
-          This option enables support for ARTOP/Acard ATP867X PATA
-          controllers.
-
-          If unsure, say N.
-
-config PATA_AT32
-        tristate "Atmel AVR32 PATA support (Experimental)"
-        depends on AVR32 && PLATFORM_AT32AP && EXPERIMENTAL
-        help
-          This option enables support for the IDE devices on the
-          Atmel AT32AP platform.
+          This option enables support for the ATI ATA interfaces
+          found on the many ATI chipsets.
 
           If unsure, say N.
 
-config PATA_ATIIXP
-        tristate "ATI PATA support"
+config PATA_ATP867X
+        tristate "ARTOP/Acard ATP867X PATA support"
         depends on PCI
         help
-          This option enables support for the ATI ATA interfaces
-          found on the many ATI chipsets.
+          This option enables support for ARTOP/Acard ATP867X PATA
+          controllers.
 
           If unsure, say N.
 
-config PATA_CMD640_PCI
-        tristate "CMD640 PCI PATA support (Experimental)"
-        depends on PCI && EXPERIMENTAL
+config PATA_BF54X
+        tristate "Blackfin 54x ATAPI support"
+        depends on BF542 || BF548 || BF549
         help
-          This option enables support for the CMD640 PCI IDE
-          interface chip. Only the primary channel is currently
-          supported.
+          This option enables support for the built-in ATAPI controller on
+          Blackfin 54x family chips.
 
           If unsure, say N.
 
@@ -354,15 +391,6 @@ config PATA_EFAR
 
           If unsure, say N.
 
-config ATA_GENERIC
-        tristate "Generic ATA support"
-        depends on PCI
-        help
-          This option enables support for generic BIOS configured
-          ATA controllers via the new ATA layer
-
-          If unsure, say N.
-
 config PATA_HPT366
         tristate "HPT 366/368 PATA support"
         depends on PCI
@@ -407,12 +435,20 @@ config PATA_HPT3X3_DMA
           controllers. Enable with care as there are still some
           problems with DMA on this chipset.
 
-config PATA_ISAPNP
-        tristate "ISA Plug and Play PATA support"
-        depends on ISAPNP
+config PATA_ICSIDE
+        tristate "Acorn ICS PATA support"
+        depends on ARM && ARCH_ACORN
         help
-          This option enables support for ISA plug & play ATA
-          controllers such as those found on old soundcards.
+          On Acorn systems, say Y here if you wish to use the ICS PATA
+          interface card.  This is not required for ICS partition support.
+          If you are unsure, say N to this.
+
+config PATA_IT8213
+        tristate "IT8213 PATA support (Experimental)"
+        depends on PCI && EXPERIMENTAL
+        help
+          This option enables support for the ITE 821 PATA
+          controllers via the new ATA layer.
 
           If unsure, say N.
 
@@ -426,15 +462,6 @@ config PATA_IT821X
 
           If unsure, say N.
 
-config PATA_IT8213
-        tristate "IT8213 PATA support (Experimental)"
-        depends on PCI && EXPERIMENTAL
-        help
-          This option enables support for the ITE 821 PATA
-          controllers via the new ATA layer.
-
-          If unsure, say N.
-
 config PATA_JMICRON
         tristate "JMicron PATA support"
         depends on PCI
@@ -444,23 +471,14 @@ config PATA_JMICRON
 
           If unsure, say N.
 
-config PATA_LEGACY
-        tristate "Legacy ISA PATA support (Experimental)"
-        depends on (ISA || PCI)  && EXPERIMENTAL
-        help
-          This option enables support for ISA/VLB/PCI bus legacy PATA
-          ports and allows them to be accessed via the new ATA layer.
-
-          If unsure, say N.
-
-config PATA_TRIFLEX
-        tristate "Compaq Triflex PATA support"
-        depends on PCI
+config PATA_MACIO
+        tristate "Apple PowerMac/PowerBook internal 'MacIO' IDE"
+        depends on PPC_PMAC
         help
-          Enable support for the Compaq 'Triflex' IDE controller as found
-          on many Compaq Pentium-Pro systems, via the new ATA layer.
-
-          If unsure, say N.
+          Most IDE capable PowerMacs have IDE busses driven by a variant
+          of this controller which is part of the Apple chipset used on
+          most PowerMac models. Some models have multiple busses using
+          different chipsets, though generally, MacIO is one of them.
 
 config PATA_MARVELL
         tristate "Marvell PATA support via legacy mode"
@@ -473,32 +491,6 @@ config PATA_MARVELL
 
           If unsure, say N.
 
-config PATA_MPC52xx
-        tristate "Freescale MPC52xx SoC internal IDE"
-        depends on PPC_MPC52xx && PPC_BESTCOMM
-        select PPC_BESTCOMM_ATA
-        help
-          This option enables support for integrated IDE controller
-          of the Freescale MPC52xx SoC.
-
-          If unsure, say N.
-
-config PATA_MPIIX
-        tristate "Intel PATA MPIIX support"
-        depends on PCI
-        help
-          This option enables support for MPIIX PATA support.
-
-          If unsure, say N.
-
-config PATA_OLDPIIX
-        tristate "Intel PATA old PIIX support"
-        depends on PCI
-        help
-          This option enables support for early PIIX PATA support.
-
-          If unsure, say N.
-
 config PATA_NETCELL
         tristate "NETCELL Revolution RAID support"
         depends on PCI
@@ -517,15 +509,6 @@ config PATA_NINJA32
 
           If unsure, say N.
 
-config PATA_NS87410
-        tristate "Nat Semi NS87410 PATA support"
-        depends on PCI
-        help
-          This option enables support for the National Semiconductor
-          NS87410 PCI-IDE controller.
-
-          If unsure, say N.
-
 config PATA_NS87415
         tristate "Nat Semi NS87415 PATA support"
         depends on PCI
@@ -535,12 +518,11 @@ config PATA_NS87415
 
           If unsure, say N.
 
-config PATA_OPTI
-        tristate "OPTI621/6215 PATA support (Very Experimental)"
-        depends on PCI && EXPERIMENTAL
+config PATA_OLDPIIX
+        tristate "Intel PATA old PIIX support"
+        depends on PCI
         help
-          This option enables full PIO support for the early Opti ATA
-          controllers found on some old motherboards.
+          This option enables support for early PIIX PATA support.
 
           If unsure, say N.
 
@@ -554,24 +536,6 @@ config PATA_OPTIDMA
 
           If unsure, say N.
 
-config PATA_PALMLD
-        tristate "Palm LifeDrive PATA support"
-        depends on MACH_PALMLD
-        help
-          This option enables support for Palm LifeDrive's internal ATA
-          port via the new ATA layer.
-
-          If unsure, say N.
-
-config PATA_PCMCIA
-        tristate "PCMCIA PATA support"
-        depends on PCMCIA
-        help
-          This option enables support for PCMCIA ATA interfaces, including
-          compact flash card adapters via the new ATA layer.
-
-          If unsure, say N.
-
 config PATA_PDC2027X
         tristate "Promise PATA 2027x support"
         depends on PCI
@@ -589,12 +553,6 @@ config PATA_PDC_OLD
 
           If unsure, say N.
 
-config PATA_QDI
-        tristate "QDI VLB PATA support"
-        depends on ISA
-        help
-          Support for QDI 6500 and 6580 PATA controllers on VESA local bus.
-
 config PATA_RADISYS
         tristate "RADISYS 82600 PATA support (Experimental)"
         depends on PCI && EXPERIMENTAL
@@ -604,15 +562,6 @@ config PATA_RADISYS
 
           If unsure, say N.
 
-config PATA_RB532
-        tristate "RouterBoard 532 PATA CompactFlash support"
-        depends on MIKROTIK_RB532
-        help
-          This option enables support for the RouterBoard 532
-          PATA CompactFlash controller.
-
-          If unsure, say N.
-
 config PATA_RDC
         tristate "RDC PATA support"
         depends on PCI
@@ -623,21 +572,30 @@ config PATA_RDC
 
           If unsure, say N.
 
-config PATA_RZ1000
-        tristate "PC Tech RZ1000 PATA support"
+config PATA_SC1200
+        tristate "SC1200 PATA support"
         depends on PCI
         help
-          This option enables basic support for the PC Tech RZ1000/1
-          PATA controllers via the new ATA layer
+          This option enables support for the NatSemi/AMD SC1200 SoC
+          companion chip used with the Geode processor family.
 
           If unsure, say N.
 
-config PATA_SC1200
-        tristate "SC1200 PATA support"
+config PATA_SCC
+        tristate "Toshiba's Cell Reference Set IDE support"
+        depends on PCI && PPC_CELLEB
+        help
+          This option enables support for the built-in IDE controller on
+          Toshiba Cell Reference Board.
+
+          If unsure, say N.
+
+config PATA_SCH
+        tristate "Intel SCH PATA support"
         depends on PCI
         help
-          This option enables support for the NatSemi/AMD SC1200 SoC
-          companion chip used with the Geode processor family.
+          This option enables support for Intel SCH PATA on the Intel
+          SCH (US15W, US15L, UL11L) series host controllers.
 
           If unsure, say N.
 
@@ -675,6 +633,15 @@ config PATA_TOSHIBA
 
           If unsure, say N.
 
+config PATA_TRIFLEX
+        tristate "Compaq Triflex PATA support"
+        depends on PCI
+        help
+          Enable support for the Compaq 'Triflex' IDE controller as found
+          on many Compaq Pentium-Pro systems, via the new ATA layer.
+
+          If unsure, say N.
+
 config PATA_VIA
         tristate "VIA PATA support"
         depends on PCI
@@ -684,6 +651,17 @@ config PATA_VIA
 
           If unsure, say N.
 
+config PATA_PXA
+        tristate "PXA DMA-capable PATA support"
+        depends on ARCH_PXA
+        help
+          This option enables support for harddrive attached to PXA CPU's bus.
+
+          NOTE: This driver utilizes PXA DMA controller, in case your hardware
+                is not capable of doing MWDMA, use pata_platform instead.
+
+          If unsure, say N.
+
 config PATA_WINBOND
         tristate "Winbond SL82C105 PATA support"
         depends on PCI
@@ -693,12 +671,99 @@ config PATA_WINBOND
 
           If unsure, say N.
 
-config PATA_WINBOND_VLB
-        tristate "Winbond W83759A VLB PATA support (Experimental)"
-        depends on ISA && EXPERIMENTAL
+endif # ATA_BMDMA
+
+comment "PIO-only SFF controllers"
+
+config PATA_AT32
+        tristate "Atmel AVR32 PATA support (Experimental)"
+        depends on AVR32 && PLATFORM_AT32AP && EXPERIMENTAL
         help
-          Support for the Winbond W83759A controller on Vesa Local Bus
-          systems.
+          This option enables support for the IDE devices on the
+          Atmel AT32AP platform.
+
+          If unsure, say N.
+
+config PATA_AT91
+        tristate "PATA support for AT91SAM9260"
+        depends on ARM && ARCH_AT91
+        help
+          This option enables support for IDE devices on the Atmel AT91SAM9260 SoC.
+
+          If unsure, say N.
+
+config PATA_CMD640_PCI
+        tristate "CMD640 PCI PATA support (Experimental)"
+        depends on PCI && EXPERIMENTAL
+        help
+          This option enables support for the CMD640 PCI IDE
+          interface chip. Only the primary channel is currently
+          supported.
+
+          If unsure, say N.
+
+config PATA_ISAPNP
+        tristate "ISA Plug and Play PATA support"
+        depends on ISAPNP
+        help
+          This option enables support for ISA plug & play ATA
+          controllers such as those found on old soundcards.
+
+          If unsure, say N.
+
+config PATA_IXP4XX_CF
+        tristate "IXP4XX Compact Flash support"
+        depends on ARCH_IXP4XX
+        help
+          This option enables support for a Compact Flash connected on
+          the ixp4xx expansion bus. This driver had been written for
+          Loft/Avila boards in mind but can work with others.
+
+          If unsure, say N.
+
+config PATA_MPIIX
+        tristate "Intel PATA MPIIX support"
+        depends on PCI
+        help
+          This option enables support for MPIIX PATA support.
+
+          If unsure, say N.
+
+config PATA_NS87410
+        tristate "Nat Semi NS87410 PATA support"
+        depends on PCI
+        help
+          This option enables support for the National Semiconductor
+          NS87410 PCI-IDE controller.
+
+          If unsure, say N.
+
+config PATA_OPTI
+        tristate "OPTI621/6215 PATA support (Very Experimental)"
+        depends on PCI && EXPERIMENTAL
+        help
+          This option enables full PIO support for the early Opti ATA
+          controllers found on some old motherboards.
+
+          If unsure, say N.
+
+config PATA_PALMLD
+        tristate "Palm LifeDrive PATA support"
+        depends on MACH_PALMLD
+        help
+          This option enables support for Palm LifeDrive's internal ATA
+          port via the new ATA layer.
+
+          If unsure, say N.
+
+config PATA_PCMCIA
+        tristate "PCMCIA PATA support"
+        depends on PCMCIA
+        help
+          This option enables support for PCMCIA ATA interfaces, including
+          compact flash card adapters via the new ATA layer.
+
+          If unsure, say N.
 
 config HAVE_PATA_PLATFORM
         bool
@@ -717,14 +782,6 @@ config PATA_PLATFORM
 
           If unsure, say N.
 
-config PATA_AT91
-        tristate "PATA support for AT91SAM9260"
-        depends on ARM && ARCH_AT91
-        help
-          This option enables support for IDE devices on the Atmel AT91SAM9260 SoC.
-
-          If unsure, say N.
-
 config PATA_OF_PLATFORM
         tristate "OpenFirmware platform device PATA support"
         depends on PATA_PLATFORM && PPC_OF
@@ -735,69 +792,75 @@ config PATA_OF_PLATFORM
 
           If unsure, say N.
 
-config PATA_ICSIDE
-        tristate "Acorn ICS PATA support"
-        depends on ARM && ARCH_ACORN
+config PATA_QDI
+        tristate "QDI VLB PATA support"
+        depends on ISA
         help
-          On Acorn systems, say Y here if you wish to use the ICS PATA
-          interface card.  This is not required for ICS partition support.
-          If you are unsure, say N to this.
+          Support for QDI 6500 and 6580 PATA controllers on VESA local bus.
 
-config PATA_IXP4XX_CF
-        tristate "IXP4XX Compact Flash support"
-        depends on ARCH_IXP4XX
+config PATA_RB532
+        tristate "RouterBoard 532 PATA CompactFlash support"
+        depends on MIKROTIK_RB532
         help
-          This option enables support for a Compact Flash connected on
-          the ixp4xx expansion bus. This driver had been written for
-          Loft/Avila boards in mind but can work with others.
+          This option enables support for the RouterBoard 532
+          PATA CompactFlash controller.
 
           If unsure, say N.
 
-config PATA_OCTEON_CF
-        tristate "OCTEON Boot Bus Compact Flash support"
-        depends on CPU_CAVIUM_OCTEON
+config PATA_RZ1000
+        tristate "PC Tech RZ1000 PATA support"
+        depends on PCI
         help
-          This option enables a polled compact flash driver for use with
-          compact flash cards attached to the OCTEON boot bus.
+          This option enables basic support for the PC Tech RZ1000/1
+          PATA controllers via the new ATA layer
 
           If unsure, say N.
 
-config PATA_SCC
-        tristate "Toshiba's Cell Reference Set IDE support"
-        depends on PCI && PPC_CELLEB
+config PATA_SAMSUNG_CF
+        tristate "Samsung SoC PATA support"
+        depends on SAMSUNG_DEV_IDE
         help
-          This option enables support for the built-in IDE controller on
-          Toshiba Cell Reference Board.
+          This option enables basic support for Samsung's S3C/S5P board
+          PATA controllers via the new ATA layer
 
           If unsure, say N.
 
-config PATA_SCH
-        tristate "Intel SCH PATA support"
-        depends on PCI
+config PATA_WINBOND_VLB
+        tristate "Winbond W83759A VLB PATA support (Experimental)"
+        depends on ISA && EXPERIMENTAL
+        select PATA_LEGACY
         help
-          This option enables support for Intel SCH PATA on the Intel
-          SCH (US15W, US15L, UL11L) series host controllers.
+          Support for the Winbond W83759A controller on Vesa Local Bus
+          systems.
 
-          If unsure, say N.
+comment "Generic fallback / legacy drivers"
 
-config PATA_BF54X
-        tristate "Blackfin 54x ATAPI support"
-        depends on BF542 || BF548 || BF549
+config PATA_ACPI
+        tristate "ACPI firmware driver for PATA"
+        depends on ATA_ACPI && ATA_BMDMA
         help
-          This option enables support for the built-in ATAPI controller on
-          Blackfin 54x family chips.
+          This option enables an ACPI method driver which drives
+          motherboard PATA controller interfaces through the ACPI
+          firmware in the BIOS. This driver can sometimes handle
+          otherwise unsupported hardware.
+
+config ATA_GENERIC
+        tristate "Generic ATA support"
+        depends on PCI && ATA_BMDMA
+        help
+          This option enables support for generic BIOS configured
+          ATA controllers via the new ATA layer
 
           If unsure, say N.
 
-config PATA_MACIO
-        tristate "Apple PowerMac/PowerBook internal 'MacIO' IDE"
-        depends on PPC_PMAC
+config PATA_LEGACY
+        tristate "Legacy ISA PATA support (Experimental)"
+        depends on (ISA || PCI) && EXPERIMENTAL
         help
-          Most IDE capable PowerMacs have IDE busses driven by a variant
-          of this controller which is part of the Apple chipset used on
-          most PowerMac models. Some models have multiple busses using
-          different chipsets, though generally, MacIO is one of them.
+          This option enables support for ISA/VLB/PCI bus legacy PATA
+          ports and allows them to be accessed via the new ATA layer.
 
+          If unsure, say N.
 
 endif # ATA_SFF
 endif # ATA
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index fc936d4471d6..d5df04a395ca 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -1,32 +1,40 @@
 
 obj-$(CONFIG_ATA)               += libata.o
 
-obj-$(CONFIG_SATA_AHCI)         += ahci.o
-obj-$(CONFIG_SATA_SVW)          += sata_svw.o
+# non-SFF interface
+obj-$(CONFIG_SATA_AHCI)         += ahci.o libahci.o
+obj-$(CONFIG_SATA_AHCI_PLATFORM) += ahci_platform.o libahci.o
+obj-$(CONFIG_SATA_FSL)          += sata_fsl.o
+obj-$(CONFIG_SATA_INIC162X)     += sata_inic162x.o
+obj-$(CONFIG_SATA_SIL24)        += sata_sil24.o
+obj-$(CONFIG_SATA_DWC)          += sata_dwc_460ex.o
+
+# SFF w/ custom DMA
+obj-$(CONFIG_PDC_ADMA)          += pdc_adma.o
+obj-$(CONFIG_PATA_MPC52xx)      += pata_mpc52xx.o
+obj-$(CONFIG_PATA_OCTEON_CF)    += pata_octeon_cf.o
+obj-$(CONFIG_SATA_QSTOR)        += sata_qstor.o
+obj-$(CONFIG_SATA_SX4)          += sata_sx4.o
+
+# SFF SATA w/ BMDMA
 obj-$(CONFIG_ATA_PIIX)          += ata_piix.o
+obj-$(CONFIG_SATA_MV)           += sata_mv.o
+obj-$(CONFIG_SATA_NV)           += sata_nv.o
 obj-$(CONFIG_SATA_PROMISE)      += sata_promise.o
-obj-$(CONFIG_SATA_QSTOR)        += sata_qstor.o
 obj-$(CONFIG_SATA_SIL)          += sata_sil.o
-obj-$(CONFIG_SATA_SIL24)        += sata_sil24.o
-obj-$(CONFIG_SATA_VIA)          += sata_via.o
-obj-$(CONFIG_SATA_VITESSE)      += sata_vsc.o
 obj-$(CONFIG_SATA_SIS)          += sata_sis.o
-obj-$(CONFIG_SATA_SX4)          += sata_sx4.o
-obj-$(CONFIG_SATA_NV)           += sata_nv.o
+obj-$(CONFIG_SATA_SVW)          += sata_svw.o
 obj-$(CONFIG_SATA_ULI)          += sata_uli.o
-obj-$(CONFIG_SATA_MV)           += sata_mv.o
-obj-$(CONFIG_SATA_INIC162X)     += sata_inic162x.o
-obj-$(CONFIG_PDC_ADMA)          += pdc_adma.o
-obj-$(CONFIG_SATA_FSL)          += sata_fsl.o
-obj-$(CONFIG_PATA_MACIO)        += pata_macio.o
+obj-$(CONFIG_SATA_VIA)          += sata_via.o
+obj-$(CONFIG_SATA_VITESSE)      += sata_vsc.o
 
+# SFF PATA w/ BMDMA
 obj-$(CONFIG_PATA_ALI)          += pata_ali.o
 obj-$(CONFIG_PATA_AMD)          += pata_amd.o
 obj-$(CONFIG_PATA_ARTOP)        += pata_artop.o
-obj-$(CONFIG_PATA_ATP867X)      += pata_atp867x.o
-obj-$(CONFIG_PATA_AT32)         += pata_at32.o
 obj-$(CONFIG_PATA_ATIIXP)       += pata_atiixp.o
-obj-$(CONFIG_PATA_CMD640_PCI)   += pata_cmd640.o
+obj-$(CONFIG_PATA_ATP867X)      += pata_atp867x.o
+obj-$(CONFIG_PATA_BF54X)        += pata_bf54x.o
 obj-$(CONFIG_PATA_CMD64X)       += pata_cmd64x.o
 obj-$(CONFIG_PATA_CS5520)       += pata_cs5520.o
 obj-$(CONFIG_PATA_CS5530)       += pata_cs5530.o
@@ -38,47 +46,52 @@ obj-$(CONFIG_PATA_HPT366)	+= pata_hpt366.o
 obj-$(CONFIG_PATA_HPT37X)       += pata_hpt37x.o
 obj-$(CONFIG_PATA_HPT3X2N)      += pata_hpt3x2n.o
 obj-$(CONFIG_PATA_HPT3X3)       += pata_hpt3x3.o
-obj-$(CONFIG_PATA_ISAPNP)       += pata_isapnp.o
-obj-$(CONFIG_PATA_IT821X)       += pata_it821x.o
+obj-$(CONFIG_PATA_ICSIDE)       += pata_icside.o
 obj-$(CONFIG_PATA_IT8213)       += pata_it8213.o
+obj-$(CONFIG_PATA_IT821X)       += pata_it821x.o
 obj-$(CONFIG_PATA_JMICRON)      += pata_jmicron.o
+obj-$(CONFIG_PATA_MACIO)        += pata_macio.o
+obj-$(CONFIG_PATA_MARVELL)      += pata_marvell.o
 obj-$(CONFIG_PATA_NETCELL)      += pata_netcell.o
 obj-$(CONFIG_PATA_NINJA32)      += pata_ninja32.o
-obj-$(CONFIG_PATA_NS87410)      += pata_ns87410.o
 obj-$(CONFIG_PATA_NS87415)      += pata_ns87415.o
-obj-$(CONFIG_PATA_OPTI)         += pata_opti.o
-obj-$(CONFIG_PATA_OPTIDMA)      += pata_optidma.o
-obj-$(CONFIG_PATA_MPC52xx)      += pata_mpc52xx.o
-obj-$(CONFIG_PATA_MARVELL)      += pata_marvell.o
-obj-$(CONFIG_PATA_MPIIX)        += pata_mpiix.o
 obj-$(CONFIG_PATA_OLDPIIX)      += pata_oldpiix.o
-obj-$(CONFIG_PATA_PALMLD)       += pata_palmld.o
-obj-$(CONFIG_PATA_PCMCIA)       += pata_pcmcia.o
+obj-$(CONFIG_PATA_OPTIDMA)      += pata_optidma.o
 obj-$(CONFIG_PATA_PDC2027X)     += pata_pdc2027x.o
 obj-$(CONFIG_PATA_PDC_OLD)      += pata_pdc202xx_old.o
-obj-$(CONFIG_PATA_QDI)          += pata_qdi.o
 obj-$(CONFIG_PATA_RADISYS)      += pata_radisys.o
-obj-$(CONFIG_PATA_RB532)        += pata_rb532_cf.o
 obj-$(CONFIG_PATA_RDC)          += pata_rdc.o
-obj-$(CONFIG_PATA_RZ1000)       += pata_rz1000.o
 obj-$(CONFIG_PATA_SC1200)       += pata_sc1200.o
+obj-$(CONFIG_PATA_SCC)          += pata_scc.o
+obj-$(CONFIG_PATA_SCH)          += pata_sch.o
 obj-$(CONFIG_PATA_SERVERWORKS)  += pata_serverworks.o
 obj-$(CONFIG_PATA_SIL680)       += pata_sil680.o
+obj-$(CONFIG_PATA_SIS)          += pata_sis.o
 obj-$(CONFIG_PATA_TOSHIBA)      += pata_piccolo.o
+obj-$(CONFIG_PATA_TRIFLEX)      += pata_triflex.o
 obj-$(CONFIG_PATA_VIA)          += pata_via.o
 obj-$(CONFIG_PATA_WINBOND)      += pata_sl82c105.o
-obj-$(CONFIG_PATA_WINBOND_VLB)  += pata_winbond.o
-obj-$(CONFIG_PATA_SIS)          += pata_sis.o
-obj-$(CONFIG_PATA_TRIFLEX)      += pata_triflex.o
+
+# SFF PIO only
+obj-$(CONFIG_PATA_AT32)         += pata_at32.o
+obj-$(CONFIG_PATA_AT91)         += pata_at91.o
+obj-$(CONFIG_PATA_CMD640_PCI)   += pata_cmd640.o
+obj-$(CONFIG_PATA_ISAPNP)       += pata_isapnp.o
 obj-$(CONFIG_PATA_IXP4XX_CF)    += pata_ixp4xx_cf.o
-obj-$(CONFIG_PATA_SCC)          += pata_scc.o
-obj-$(CONFIG_PATA_SCH)          += pata_sch.o
-obj-$(CONFIG_PATA_BF54X)        += pata_bf54x.o
-obj-$(CONFIG_PATA_OCTEON_CF)    += pata_octeon_cf.o
+obj-$(CONFIG_PATA_MPIIX)        += pata_mpiix.o
+obj-$(CONFIG_PATA_NS87410)      += pata_ns87410.o
+obj-$(CONFIG_PATA_OPTI)         += pata_opti.o
+obj-$(CONFIG_PATA_PCMCIA)       += pata_pcmcia.o
+obj-$(CONFIG_PATA_PALMLD)       += pata_palmld.o
 obj-$(CONFIG_PATA_PLATFORM)     += pata_platform.o
-obj-$(CONFIG_PATA_AT91) += pata_at91.o
 obj-$(CONFIG_PATA_OF_PLATFORM)  += pata_of_platform.o
-obj-$(CONFIG_PATA_ICSIDE)       += pata_icside.o
+obj-$(CONFIG_PATA_QDI)          += pata_qdi.o
+obj-$(CONFIG_PATA_RB532)        += pata_rb532_cf.o
+obj-$(CONFIG_PATA_RZ1000)       += pata_rz1000.o
+obj-$(CONFIG_PATA_SAMSUNG_CF)   += pata_samsung_cf.o
+
+obj-$(CONFIG_PATA_PXA)          += pata_pxa.o
+
 # Should be last but two libata driver
 obj-$(CONFIG_PATA_ACPI)         += pata_acpi.o
 # Should be last but one libata driver
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 5326af28a410..99d0e5a51148 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -46,402 +46,52 @@
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_cmnd.h>
 #include <linux/libata.h>
+#include "ahci.h"
 
 #define DRV_NAME        "ahci"
 #define DRV_VERSION     "3.0"
 
-/* Enclosure Management Control */
-#define EM_CTRL_MSG_TYPE              0x000f0000
-
-/* Enclosure Management LED Message Type */
-#define EM_MSG_LED_HBA_PORT           0x0000000f
-#define EM_MSG_LED_PMP_SLOT           0x0000ff00
-#define EM_MSG_LED_VALUE              0xffff0000
-#define EM_MSG_LED_VALUE_ACTIVITY     0x00070000
-#define EM_MSG_LED_VALUE_OFF          0xfff80000
-#define EM_MSG_LED_VALUE_ON           0x00010000
-
-static int ahci_skip_host_reset;
-static int ahci_ignore_sss;
-
-module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
-MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
-
-module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
-MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
-
-static int ahci_enable_alpm(struct ata_port *ap,
-                enum link_pm policy);
-static void ahci_disable_alpm(struct ata_port *ap);
-static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
-static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
-                              size_t size);
-static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
-                                        ssize_t size);
-
 enum {
         AHCI_PCI_BAR            = 5,
-        AHCI_MAX_PORTS          = 32,
-        AHCI_MAX_SG             = 168, /* hardware max is 64K */
-        AHCI_DMA_BOUNDARY       = 0xffffffff,
-        AHCI_MAX_CMDS           = 32,
-        AHCI_CMD_SZ             = 32,
-        AHCI_CMD_SLOT_SZ        = AHCI_MAX_CMDS * AHCI_CMD_SZ,
-        AHCI_RX_FIS_SZ          = 256,
-        AHCI_CMD_TBL_CDB        = 0x40,
-        AHCI_CMD_TBL_HDR_SZ     = 0x80,
-        AHCI_CMD_TBL_SZ         = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
-        AHCI_CMD_TBL_AR_SZ      = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
-        AHCI_PORT_PRIV_DMA_SZ   = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
-                                  AHCI_RX_FIS_SZ,
-        AHCI_PORT_PRIV_FBS_DMA_SZ       = AHCI_CMD_SLOT_SZ +
-                                          AHCI_CMD_TBL_AR_SZ +
-                                          (AHCI_RX_FIS_SZ * 16),
-        AHCI_IRQ_ON_SG          = (1 << 31),
-        AHCI_CMD_ATAPI          = (1 << 5),
-        AHCI_CMD_WRITE          = (1 << 6),
-        AHCI_CMD_PREFETCH       = (1 << 7),
-        AHCI_CMD_RESET          = (1 << 8),
-        AHCI_CMD_CLR_BUSY       = (1 << 10),
-
-        RX_FIS_D2H_REG          = 0x40, /* offset of D2H Register FIS data */
-        RX_FIS_SDB              = 0x58, /* offset of SDB FIS data */
-        RX_FIS_UNK              = 0x60, /* offset of Unknown FIS data */
-
-        board_ahci              = 0,
-        board_ahci_vt8251       = 1,
-        board_ahci_ign_iferr    = 2,
-        board_ahci_sb600        = 3,
-        board_ahci_mv           = 4,
-        board_ahci_sb700        = 5, /* for SB700 and SB800 */
-        board_ahci_mcp65        = 6,
-        board_ahci_nopmp        = 7,
-        board_ahci_yesncq       = 8,
-        board_ahci_nosntf       = 9,
-
-        /* global controller registers */
-        HOST_CAP                = 0x00, /* host capabilities */
-        HOST_CTL                = 0x04, /* global host control */
-        HOST_IRQ_STAT           = 0x08, /* interrupt status */
-        HOST_PORTS_IMPL         = 0x0c, /* bitmap of implemented ports */
-        HOST_VERSION            = 0x10, /* AHCI spec. version compliancy */
-        HOST_EM_LOC             = 0x1c, /* Enclosure Management location */
-        HOST_EM_CTL             = 0x20, /* Enclosure Management Control */
-        HOST_CAP2               = 0x24, /* host capabilities, extended */
-
-        /* HOST_CTL bits */
-        HOST_RESET              = (1 << 0),  /* reset controller; self-clear */
-        HOST_IRQ_EN             = (1 << 1),  /* global IRQ enable */
-        HOST_AHCI_EN            = (1 << 31), /* AHCI enabled */
-
-        /* HOST_CAP bits */
-        HOST_CAP_SXS            = (1 << 5),  /* Supports External SATA */
-        HOST_CAP_EMS            = (1 << 6),  /* Enclosure Management support */
-        HOST_CAP_CCC            = (1 << 7),  /* Command Completion Coalescing */
-        HOST_CAP_PART           = (1 << 13), /* Partial state capable */
-        HOST_CAP_SSC            = (1 << 14), /* Slumber state capable */
-        HOST_CAP_PIO_MULTI      = (1 << 15), /* PIO multiple DRQ support */
-        HOST_CAP_FBS            = (1 << 16), /* FIS-based switching support */
-        HOST_CAP_PMP            = (1 << 17), /* Port Multiplier support */
-        HOST_CAP_ONLY           = (1 << 18), /* Supports AHCI mode only */
-        HOST_CAP_CLO            = (1 << 24), /* Command List Override support */
-        HOST_CAP_LED            = (1 << 25), /* Supports activity LED */
-        HOST_CAP_ALPM           = (1 << 26), /* Aggressive Link PM support */
-        HOST_CAP_SSS            = (1 << 27), /* Staggered Spin-up */
-        HOST_CAP_MPS            = (1 << 28), /* Mechanical presence switch */
-        HOST_CAP_SNTF           = (1 << 29), /* SNotification register */
-        HOST_CAP_NCQ            = (1 << 30), /* Native Command Queueing */
-        HOST_CAP_64             = (1 << 31), /* PCI DAC (64-bit DMA) support */
-
-        /* HOST_CAP2 bits */
-        HOST_CAP2_BOH           = (1 << 0),  /* BIOS/OS handoff supported */
-        HOST_CAP2_NVMHCI        = (1 << 1),  /* NVMHCI supported */
-        HOST_CAP2_APST          = (1 << 2),  /* Automatic partial to slumber */
-
-        /* registers for each SATA port */
-        PORT_LST_ADDR           = 0x00, /* command list DMA addr */
-        PORT_LST_ADDR_HI        = 0x04, /* command list DMA addr hi */
-        PORT_FIS_ADDR           = 0x08, /* FIS rx buf addr */
-        PORT_FIS_ADDR_HI        = 0x0c, /* FIS rx buf addr hi */
-        PORT_IRQ_STAT           = 0x10, /* interrupt status */
-        PORT_IRQ_MASK           = 0x14, /* interrupt enable/disable mask */
-        PORT_CMD                = 0x18, /* port command */
-        PORT_TFDATA             = 0x20, /* taskfile data */
-        PORT_SIG                = 0x24, /* device TF signature */
-        PORT_CMD_ISSUE          = 0x38, /* command issue */
-        PORT_SCR_STAT           = 0x28, /* SATA phy register: SStatus */
-        PORT_SCR_CTL            = 0x2c, /* SATA phy register: SControl */
-        PORT_SCR_ERR            = 0x30, /* SATA phy register: SError */
-        PORT_SCR_ACT            = 0x34, /* SATA phy register: SActive */
-        PORT_SCR_NTF            = 0x3c, /* SATA phy register: SNotification */
-        PORT_FBS                = 0x40, /* FIS-based Switching */
-
-        /* PORT_IRQ_{STAT,MASK} bits */
-        PORT_IRQ_COLD_PRES      = (1 << 31), /* cold presence detect */
-        PORT_IRQ_TF_ERR         = (1 << 30), /* task file error */
-        PORT_IRQ_HBUS_ERR       = (1 << 29), /* host bus fatal error */
-        PORT_IRQ_HBUS_DATA_ERR  = (1 << 28), /* host bus data error */
-        PORT_IRQ_IF_ERR         = (1 << 27), /* interface fatal error */
-        PORT_IRQ_IF_NONFATAL    = (1 << 26), /* interface non-fatal error */
-        PORT_IRQ_OVERFLOW       = (1 << 24), /* xfer exhausted available S/G */
-        PORT_IRQ_BAD_PMP        = (1 << 23), /* incorrect port multiplier */
-
-        PORT_IRQ_PHYRDY         = (1 << 22), /* PhyRdy changed */
-        PORT_IRQ_DEV_ILCK       = (1 << 7), /* device interlock */
-        PORT_IRQ_CONNECT        = (1 << 6), /* port connect change status */
-        PORT_IRQ_SG_DONE        = (1 << 5), /* descriptor processed */
-        PORT_IRQ_UNK_FIS        = (1 << 4), /* unknown FIS rx'd */
-        PORT_IRQ_SDB_FIS        = (1 << 3), /* Set Device Bits FIS rx'd */
-        PORT_IRQ_DMAS_FIS       = (1 << 2), /* DMA Setup FIS rx'd */
-        PORT_IRQ_PIOS_FIS       = (1 << 1), /* PIO Setup FIS rx'd */
-        PORT_IRQ_D2H_REG_FIS    = (1 << 0), /* D2H Register FIS rx'd */
-
-        PORT_IRQ_FREEZE         = PORT_IRQ_HBUS_ERR |
-                                  PORT_IRQ_IF_ERR |
-                                  PORT_IRQ_CONNECT |
-                                  PORT_IRQ_PHYRDY |
-                                  PORT_IRQ_UNK_FIS |
-                                  PORT_IRQ_BAD_PMP,
-        PORT_IRQ_ERROR          = PORT_IRQ_FREEZE |
-                                  PORT_IRQ_TF_ERR |
-                                  PORT_IRQ_HBUS_DATA_ERR,
-        DEF_PORT_IRQ            = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
-                                  PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
-                                  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
-
-        /* PORT_CMD bits */
-        PORT_CMD_ASP            = (1 << 27), /* Aggressive Slumber/Partial */
-        PORT_CMD_ALPE           = (1 << 26), /* Aggressive Link PM enable */
-        PORT_CMD_ATAPI          = (1 << 24), /* Device is ATAPI */
-        PORT_CMD_FBSCP          = (1 << 22), /* FBS Capable Port */
-        PORT_CMD_PMP            = (1 << 17), /* PMP attached */
-        PORT_CMD_LIST_ON        = (1 << 15), /* cmd list DMA engine running */
-        PORT_CMD_FIS_ON         = (1 << 14), /* FIS DMA engine running */
-        PORT_CMD_FIS_RX         = (1 << 4), /* Enable FIS receive DMA engine */
-        PORT_CMD_CLO            = (1 << 3), /* Command list override */
-        PORT_CMD_POWER_ON       = (1 << 2), /* Power up device */
-        PORT_CMD_SPIN_UP        = (1 << 1), /* Spin up device */
-        PORT_CMD_START          = (1 << 0), /* Enable port DMA engine */
-
-        PORT_CMD_ICC_MASK       = (0xf << 28), /* i/f ICC state mask */
-        PORT_CMD_ICC_ACTIVE     = (0x1 << 28), /* Put i/f in active state */
-        PORT_CMD_ICC_PARTIAL    = (0x2 << 28), /* Put i/f in partial state */
-        PORT_CMD_ICC_SLUMBER    = (0x6 << 28), /* Put i/f in slumber state */
-
-        PORT_FBS_DWE_OFFSET     = 16, /* FBS device with error offset */
-        PORT_FBS_ADO_OFFSET     = 12, /* FBS active dev optimization offset */
-        PORT_FBS_DEV_OFFSET     = 8,  /* FBS device to issue offset */
-        PORT_FBS_DEV_MASK       = (0xf << PORT_FBS_DEV_OFFSET),  /* FBS.DEV */
-        PORT_FBS_SDE            = (1 << 2), /* FBS single device error */
-        PORT_FBS_DEC            = (1 << 1), /* FBS device error clear */
-        PORT_FBS_EN             = (1 << 0), /* Enable FBS */
-
-        /* hpriv->flags bits */
-        AHCI_HFLAG_NO_NCQ               = (1 << 0),
-        AHCI_HFLAG_IGN_IRQ_IF_ERR       = (1 << 1), /* ignore IRQ_IF_ERR */
-        AHCI_HFLAG_IGN_SERR_INTERNAL    = (1 << 2), /* ignore SERR_INTERNAL */
-        AHCI_HFLAG_32BIT_ONLY           = (1 << 3), /* force 32bit */
-        AHCI_HFLAG_MV_PATA              = (1 << 4), /* PATA port */
-        AHCI_HFLAG_NO_MSI               = (1 << 5), /* no PCI MSI */
-        AHCI_HFLAG_NO_PMP               = (1 << 6), /* no PMP */
-        AHCI_HFLAG_NO_HOTPLUG           = (1 << 7), /* ignore PxSERR.DIAG.N */
-        AHCI_HFLAG_SECT255              = (1 << 8), /* max 255 sectors */
-        AHCI_HFLAG_YES_NCQ              = (1 << 9), /* force NCQ cap on */
-        AHCI_HFLAG_NO_SUSPEND           = (1 << 10), /* don't suspend */
-        AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
-                                                        link offline */
-        AHCI_HFLAG_NO_SNTF              = (1 << 12), /* no sntf */
-
-        /* ap->flags bits */
-
-        AHCI_FLAG_COMMON                = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
-                                          ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
-                                          ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
-                                          ATA_FLAG_IPM,
-
-        ICH_MAP                         = 0x90, /* ICH MAP register */
-
-        /* em constants */
-        EM_MAX_SLOTS                    = 8,
-        EM_MAX_RETRY                    = 5,
-
-        /* em_ctl bits */
-        EM_CTL_RST                      = (1 << 9), /* Reset */
-        EM_CTL_TM                       = (1 << 8), /* Transmit Message */
-        EM_CTL_ALHD                     = (1 << 26), /* Activity LED */
-};
-
-struct ahci_cmd_hdr {
-        __le32                  opts;
-        __le32                  status;
-        __le32                  tbl_addr;
-        __le32                  tbl_addr_hi;
-        __le32                  reserved[4];
-};
-
-struct ahci_sg {
-        __le32                  addr;
-        __le32                  addr_hi;
-        __le32                  reserved;
-        __le32                  flags_size;
-};
-
-struct ahci_em_priv {
-        enum sw_activity blink_policy;
-        struct timer_list timer;
-        unsigned long saved_activity;
-        unsigned long activity;
-        unsigned long led_state;
-};
-
-struct ahci_host_priv {
-        unsigned int            flags;          /* AHCI_HFLAG_* */
-        u32                     cap;            /* cap to use */
-        u32                     cap2;           /* cap2 to use */
-        u32                     port_map;       /* port map to use */
-        u32                     saved_cap;      /* saved initial cap */
-        u32                     saved_cap2;     /* saved initial cap2 */
-        u32                     saved_port_map; /* saved initial port_map */
-        u32                     em_loc; /* enclosure management location */
 };
 
-struct ahci_port_priv {
-        struct ata_link         *active_link;
-        struct ahci_cmd_hdr     *cmd_slot;
-        dma_addr_t              cmd_slot_dma;
-        void                    *cmd_tbl;
-        dma_addr_t              cmd_tbl_dma;
-        void                    *rx_fis;
-        dma_addr_t              rx_fis_dma;
-        /* for NCQ spurious interrupt analysis */
-        unsigned int            ncq_saw_d2h:1;
-        unsigned int            ncq_saw_dmas:1;
-        unsigned int            ncq_saw_sdb:1;
-        u32                     intr_mask;      /* interrupts to enable */
-        bool                    fbs_supported;  /* set iff FBS is supported */
-        bool                    fbs_enabled;    /* set iff FBS is enabled */
-        int                     fbs_last_dev;   /* save FBS.DEV of last FIS */
-        /* enclosure management info per PM slot */
-        struct ahci_em_priv     em_priv[EM_MAX_SLOTS];
+enum board_ids {
+        /* board IDs by feature in alphabetical order */
+        board_ahci,
+        board_ahci_ign_iferr,
+        board_ahci_nosntf,
+        board_ahci_yes_fbs,
+
+        /* board IDs for specific chipsets in alphabetical order */
+        board_ahci_mcp65,
+        board_ahci_mcp77,
+        board_ahci_mcp89,
+        board_ahci_mv,
+        board_ahci_sb600,
+        board_ahci_sb700,       /* for SB700 and SB800 */
+        board_ahci_vt8251,
+
+        /* aliases */
+        board_ahci_mcp_linux    = board_ahci_mcp65,
+        board_ahci_mcp67        = board_ahci_mcp65,
+        board_ahci_mcp73        = board_ahci_mcp65,
+        board_ahci_mcp79        = board_ahci_mcp77,
 };
 
-static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
-static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
-static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
-static int ahci_port_start(struct ata_port *ap);
-static void ahci_port_stop(struct ata_port *ap);
-static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
-static void ahci_qc_prep(struct ata_queued_cmd *qc);
-static void ahci_freeze(struct ata_port *ap);
-static void ahci_thaw(struct ata_port *ap);
-static void ahci_enable_fbs(struct ata_port *ap);
-static void ahci_disable_fbs(struct ata_port *ap);
-static void ahci_pmp_attach(struct ata_port *ap);
-static void ahci_pmp_detach(struct ata_port *ap);
-static int ahci_softreset(struct ata_link *link, unsigned int *class,
-                          unsigned long deadline);
 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
                           unsigned long deadline);
-static int ahci_hardreset(struct ata_link *link, unsigned int *class,
-                          unsigned long deadline);
 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
                                  unsigned long deadline);
 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
                                 unsigned long deadline);
-static void ahci_postreset(struct ata_link *link, unsigned int *class);
-static void ahci_error_handler(struct ata_port *ap);
-static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
-static int ahci_port_resume(struct ata_port *ap);
-static void ahci_dev_config(struct ata_device *dev);
-static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
-                               u32 opts);
 #ifdef CONFIG_PM
-static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
 static int ahci_pci_device_resume(struct pci_dev *pdev);
 #endif
-static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
-static ssize_t ahci_activity_store(struct ata_device *dev,
-                                   enum sw_activity val);
-static void ahci_init_sw_activity(struct ata_link *link);
-
-static ssize_t ahci_show_host_caps(struct device *dev,
-                                   struct device_attribute *attr, char *buf);
-static ssize_t ahci_show_host_cap2(struct device *dev,
-                                   struct device_attribute *attr, char *buf);
-static ssize_t ahci_show_host_version(struct device *dev,
-                                      struct device_attribute *attr, char *buf);
-static ssize_t ahci_show_port_cmd(struct device *dev,
-                                  struct device_attribute *attr, char *buf);
-
-static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
-static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
-static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
-static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
-
-static struct device_attribute *ahci_shost_attrs[] = {
-        &dev_attr_link_power_management_policy,
-        &dev_attr_em_message_type,
-        &dev_attr_em_message,
-        &dev_attr_ahci_host_caps,
-        &dev_attr_ahci_host_cap2,
-        &dev_attr_ahci_host_version,
-        &dev_attr_ahci_port_cmd,
-        NULL
-};
-
-static struct device_attribute *ahci_sdev_attrs[] = {
-        &dev_attr_sw_activity,
-        &dev_attr_unload_heads,
-        NULL
-};
 
 static struct scsi_host_template ahci_sht = {
-        ATA_NCQ_SHT(DRV_NAME),
-        .can_queue              = AHCI_MAX_CMDS - 1,
-        .sg_tablesize           = AHCI_MAX_SG,
-        .dma_boundary           = AHCI_DMA_BOUNDARY,
-        .shost_attrs            = ahci_shost_attrs,
-        .sdev_attrs             = ahci_sdev_attrs,
-};
-
-static struct ata_port_operations ahci_ops = {
-        .inherits               = &sata_pmp_port_ops,
-
-        .qc_defer               = ahci_pmp_qc_defer,
-        .qc_prep                = ahci_qc_prep,
-        .qc_issue               = ahci_qc_issue,
-        .qc_fill_rtf            = ahci_qc_fill_rtf,
-
-        .freeze                 = ahci_freeze,
-        .thaw                   = ahci_thaw,
-        .softreset              = ahci_softreset,
-        .hardreset              = ahci_hardreset,
-        .postreset              = ahci_postreset,
-        .pmp_softreset          = ahci_softreset,
-        .error_handler          = ahci_error_handler,
-        .post_internal_cmd      = ahci_post_internal_cmd,
-        .dev_config             = ahci_dev_config,
-
-        .scr_read               = ahci_scr_read,
-        .scr_write              = ahci_scr_write,
-        .pmp_attach             = ahci_pmp_attach,
-        .pmp_detach             = ahci_pmp_detach,
-
-        .enable_pm              = ahci_enable_alpm,
-        .disable_pm             = ahci_disable_alpm,
-        .em_show                = ahci_led_show,
-        .em_store               = ahci_led_store,
-        .sw_activity_show       = ahci_activity_show,
-        .sw_activity_store      = ahci_activity_store,
-#ifdef CONFIG_PM
-        .port_suspend           = ahci_port_suspend,
-        .port_resume            = ahci_port_resume,
-#endif
-        .port_start             = ahci_port_start,
-        .port_stop              = ahci_port_stop,
+        AHCI_SHT("ahci"),
 };
 
 static struct ata_port_operations ahci_vt8251_ops = {
@@ -463,6 +113,7 @@ static struct ata_port_operations ahci_sb600_ops = {
 #define AHCI_HFLAGS(flags)      .private_data   = (void *)(flags)
 
 static const struct ata_port_info ahci_port_info[] = {
+        /* by features */
         [board_ahci] =
         {
                 .flags          = AHCI_FLAG_COMMON,
@@ -470,81 +121,91 @@ static const struct ata_port_info ahci_port_info[] = {
                 .udma_mask      = ATA_UDMA6,
                 .port_ops       = &ahci_ops,
         },
-        [board_ahci_vt8251] =
+        [board_ahci_ign_iferr] =
         {
-                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
+                AHCI_HFLAGS     (AHCI_HFLAG_IGN_IRQ_IF_ERR),
                 .flags          = AHCI_FLAG_COMMON,
                 .pio_mask       = ATA_PIO4,
                 .udma_mask      = ATA_UDMA6,
-                .port_ops       = &ahci_vt8251_ops,
+                .port_ops       = &ahci_ops,
         },
-        [board_ahci_ign_iferr] =
+        [board_ahci_nosntf] =
         {
-                AHCI_HFLAGS     (AHCI_HFLAG_IGN_IRQ_IF_ERR),
+                AHCI_HFLAGS     (AHCI_HFLAG_NO_SNTF),
                 .flags          = AHCI_FLAG_COMMON,
                 .pio_mask       = ATA_PIO4,
                 .udma_mask      = ATA_UDMA6,
                 .port_ops       = &ahci_ops,
         },
-        [board_ahci_sb600] =
+        [board_ahci_yes_fbs] =
         {
-                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL |
-                                 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
-                                 AHCI_HFLAG_32BIT_ONLY),
+                AHCI_HFLAGS     (AHCI_HFLAG_YES_FBS),
                 .flags          = AHCI_FLAG_COMMON,
                 .pio_mask       = ATA_PIO4,
                 .udma_mask      = ATA_UDMA6,
-                .port_ops       = &ahci_sb600_ops,
+                .port_ops       = &ahci_ops,
         },
-        [board_ahci_mv] =
+        /* by chipsets */
+        [board_ahci_mcp65] =
         {
-                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
-                                 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
-                .flags          = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
-                                  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
+                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
+                                 AHCI_HFLAG_YES_NCQ),
+                .flags          = AHCI_FLAG_COMMON,
                 .pio_mask       = ATA_PIO4,
                 .udma_mask      = ATA_UDMA6,
                 .port_ops       = &ahci_ops,
         },
-        [board_ahci_sb700] =    /* for SB700 and SB800 */
+        [board_ahci_mcp77] =
         {
-                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL),
+                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
                 .flags          = AHCI_FLAG_COMMON,
                 .pio_mask       = ATA_PIO4,
                 .udma_mask      = ATA_UDMA6,
-                .port_ops       = &ahci_sb600_ops,
+                .port_ops       = &ahci_ops,
         },
-        [board_ahci_mcp65] =
+        [board_ahci_mcp89] =
         {
-                AHCI_HFLAGS     (AHCI_HFLAG_YES_NCQ),
+                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA),
                 .flags          = AHCI_FLAG_COMMON,
                 .pio_mask       = ATA_PIO4,
                 .udma_mask      = ATA_UDMA6,
                 .port_ops       = &ahci_ops,
         },
-        [board_ahci_nopmp] =
+        [board_ahci_mv] =
         {
-                AHCI_HFLAGS     (AHCI_HFLAG_NO_PMP),
-                .flags          = AHCI_FLAG_COMMON,
+                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
+                                 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
+                .flags          = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
+                                  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
                 .pio_mask       = ATA_PIO4,
                 .udma_mask      = ATA_UDMA6,
                 .port_ops       = &ahci_ops,
         },
-        [board_ahci_yesncq] =
+        [board_ahci_sb600] =
         {
-                AHCI_HFLAGS     (AHCI_HFLAG_YES_NCQ),
+                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL |
+                                 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
+                                 AHCI_HFLAG_32BIT_ONLY),
                 .flags          = AHCI_FLAG_COMMON,
                 .pio_mask       = ATA_PIO4,
                 .udma_mask      = ATA_UDMA6,
-                .port_ops       = &ahci_ops,
+                .port_ops       = &ahci_sb600_ops,
         },
-        [board_ahci_nosntf] =
+        [board_ahci_sb700] =    /* for SB700 and SB800 */
         {
-                AHCI_HFLAGS     (AHCI_HFLAG_NO_SNTF),
+                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL),
                 .flags          = AHCI_FLAG_COMMON,
                 .pio_mask       = ATA_PIO4,
                 .udma_mask      = ATA_UDMA6,
-                .port_ops       = &ahci_ops,
+                .port_ops       = &ahci_sb600_ops,
+        },
+        [board_ahci_vt8251] =
+        {
+                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
+                .flags          = AHCI_FLAG_COMMON,
+                .pio_mask       = ATA_PIO4,
+                .udma_mask      = ATA_UDMA6,
+                .port_ops       = &ahci_vt8251_ops,
         },
 };
 
@@ -596,6 +257,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
         { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
         { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
         { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
+        { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
+        { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
+        { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
 
         /* JMicron 360/1/3/5/6, match class to avoid IDE function */
         { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
@@ -629,82 +293,82 @@ static const struct pci_device_id ahci_pci_tbl[] = {
         { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },      /* MCP65 */
         { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },      /* MCP65 */
         { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },      /* MCP65 */
-        { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq },     /* MCP67 */
-        { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq },     /* MCP67 */
-        { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq },     /* MCP67 */
-        { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq },     /* MCP67 */
-        { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq },     /* MCP67 */
-        { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq },     /* MCP67 */
-        { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq },     /* MCP67 */
-        { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq },     /* MCP67 */
-        { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq },     /* MCP67 */
-        { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq },     /* MCP67 */
-        { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq },     /* MCP67 */
-        { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq },     /* MCP67 */
-        { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_yesncq },     /* Linux ID */
-        { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq },     /* MCP73 */
-        { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq },     /* MCP73 */
-        { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq },     /* MCP73 */
-        { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq },     /* MCP73 */
-        { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq },     /* MCP73 */
-        { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq },     /* MCP73 */
-        { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq },     /* MCP73 */
-        { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq },     /* MCP73 */
-        { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq },     /* MCP73 */
-        { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq },     /* MCP73 */
-        { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq },     /* MCP73 */
-        { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq },     /* MCP73 */
-        { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci },            /* MCP77 */
-        { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci },            /* MCP77 */
-        { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci },            /* MCP77 */
-        { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci },            /* MCP77 */
-        { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci },            /* MCP77 */
-        { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci },            /* MCP77 */
-        { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci },            /* MCP77 */
-        { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci },            /* MCP77 */
-        { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci },            /* MCP77 */
-        { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci },            /* MCP77 */
-        { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci },            /* MCP77 */
-        { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci },            /* MCP77 */
-        { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci },            /* MCP79 */
-        { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci },            /* MCP79 */
-        { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci },            /* MCP79 */
-        { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci },            /* MCP79 */
-        { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci },            /* MCP79 */
-        { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci },            /* MCP79 */
-        { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci },            /* MCP79 */
-        { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci },            /* MCP79 */
-        { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci },            /* MCP79 */
-        { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci },            /* MCP79 */
-        { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci },            /* MCP79 */
-        { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci },            /* MCP79 */
-        { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci },            /* MCP89 */
-        { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci },            /* MCP89 */
-        { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci },            /* MCP89 */
-        { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci },            /* MCP89 */
-        { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci },            /* MCP89 */
-        { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci },            /* MCP89 */
-        { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci },            /* MCP89 */
-        { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci },            /* MCP89 */
-        { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci },            /* MCP89 */
-        { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci },            /* MCP89 */
-        { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci },            /* MCP89 */
-        { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci },            /* MCP89 */
+        { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },      /* MCP67 */
+        { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },      /* MCP67 */
+        { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },      /* MCP67 */
+        { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },      /* MCP67 */
+        { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },      /* MCP67 */
+        { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },      /* MCP67 */
+        { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },      /* MCP67 */
+        { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },      /* MCP67 */
+        { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },      /* MCP67 */
+        { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },      /* MCP67 */
+        { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },      /* MCP67 */
+        { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },      /* MCP67 */
+        { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },  /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },      /* MCP73 */
+        { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },      /* MCP73 */
+        { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },      /* MCP73 */
+        { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },      /* MCP73 */
+        { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },      /* MCP73 */
+        { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },      /* MCP73 */
+        { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },      /* MCP73 */
+        { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },      /* MCP73 */
+        { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },      /* MCP73 */
+        { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },      /* MCP73 */
+        { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },      /* MCP73 */
+        { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },      /* MCP73 */
+        { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },      /* MCP77 */
+        { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },      /* MCP77 */
+        { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },      /* MCP77 */
+        { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },      /* MCP77 */
+        { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },      /* MCP77 */
+        { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },      /* MCP77 */
+        { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },      /* MCP77 */
+        { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },      /* MCP77 */
+        { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },      /* MCP77 */
+        { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },      /* MCP77 */
+        { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },      /* MCP77 */
+        { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },      /* MCP77 */
+        { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },      /* MCP79 */
+        { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },      /* MCP79 */
+        { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },      /* MCP79 */
+        { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },      /* MCP79 */
+        { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },      /* MCP79 */
+        { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },      /* MCP79 */
+        { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },      /* MCP79 */
+        { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },      /* MCP79 */
+        { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },      /* MCP79 */
+        { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },      /* MCP79 */
+        { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },      /* MCP79 */
+        { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },      /* MCP79 */
+        { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },      /* MCP89 */
+        { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },      /* MCP89 */
+        { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },      /* MCP89 */
+        { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },      /* MCP89 */
+        { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },      /* MCP89 */
+        { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },      /* MCP89 */
+        { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },      /* MCP89 */
+        { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },      /* MCP89 */
+        { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },      /* MCP89 */
+        { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },      /* MCP89 */
+        { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },      /* MCP89 */
+        { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },      /* MCP89 */
 
         /* SiS */
         { PCI_VDEVICE(SI, 0x1184), board_ahci },                /* SiS 966 */
@@ -714,6 +378,8 @@ static const struct pci_device_id ahci_pci_tbl[] = {
         /* Marvell */
         { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
         { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },        /* 6121 */
+        { PCI_DEVICE(0x1b4b, 0x9123),
+          .driver_data = board_ahci_yes_fbs },                  /* 88se9128 */
 
         /* Promise */
         { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },   /* PDC42819 */
@@ -737,12 +403,6 @@ static struct pci_driver ahci_pci_driver = {
 #endif
 };
 
-static int ahci_em_messages = 1;
-module_param(ahci_em_messages, int, 0444);
-/* add other LED protocol types when they become supported */
-MODULE_PARM_DESC(ahci_em_messages,
-        "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
-
 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
 static int marvell_enable;
 #else
@@ -752,166 +412,15 @@ module_param(marvell_enable, int, 0644);
 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
 
 
-static inline int ahci_nr_ports(u32 cap)
-{
-        return (cap & 0x1f) + 1;
-}
-
-static inline void __iomem *__ahci_port_base(struct ata_host *host,
-                                             unsigned int port_no)
+static void ahci_pci_save_initial_config(struct pci_dev *pdev,
+                                         struct ahci_host_priv *hpriv)
 {
-        void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-
-        return mmio + 0x100 + (port_no * 0x80);
-}
-
-static inline void __iomem *ahci_port_base(struct ata_port *ap)
-{
-        return __ahci_port_base(ap->host, ap->port_no);
-}
-
-static void ahci_enable_ahci(void __iomem *mmio)
-{
-        int i;
-        u32 tmp;
+        unsigned int force_port_map = 0;
+        unsigned int mask_port_map = 0;
 
-        /* turn on AHCI_EN */
-        tmp = readl(mmio + HOST_CTL);
-        if (tmp & HOST_AHCI_EN)
-                return;
-
-        /* Some controllers need AHCI_EN to be written multiple times.
-         * Try a few times before giving up.
-         */
-        for (i = 0; i < 5; i++) {
-                tmp |= HOST_AHCI_EN;
-                writel(tmp, mmio + HOST_CTL);
-                tmp = readl(mmio + HOST_CTL);   /* flush && sanity check */
-                if (tmp & HOST_AHCI_EN)
-                        return;
-                msleep(10);
-        }
-
-        WARN_ON(1);
-}
-
-static ssize_t ahci_show_host_caps(struct device *dev,
-                                   struct device_attribute *attr, char *buf)
-{
-        struct Scsi_Host *shost = class_to_shost(dev);
-        struct ata_port *ap = ata_shost_to_port(shost);
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-
-        return sprintf(buf, "%x\n", hpriv->cap);
-}
-
-static ssize_t ahci_show_host_cap2(struct device *dev,
-                                   struct device_attribute *attr, char *buf)
-{
-        struct Scsi_Host *shost = class_to_shost(dev);
-        struct ata_port *ap = ata_shost_to_port(shost);
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-
-        return sprintf(buf, "%x\n", hpriv->cap2);
-}
-
-static ssize_t ahci_show_host_version(struct device *dev,
-                                   struct device_attribute *attr, char *buf)
-{
-        struct Scsi_Host *shost = class_to_shost(dev);
-        struct ata_port *ap = ata_shost_to_port(shost);
-        void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
-
-        return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
-}
-
-static ssize_t ahci_show_port_cmd(struct device *dev,
-                                  struct device_attribute *attr, char *buf)
-{
-        struct Scsi_Host *shost = class_to_shost(dev);
-        struct ata_port *ap = ata_shost_to_port(shost);
-        void __iomem *port_mmio = ahci_port_base(ap);
-
-        return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
-}
-
-/**
- *      ahci_save_initial_config - Save and fixup initial config values
- *      @pdev: target PCI device
- *      @hpriv: host private area to store config values
- *
- *      Some registers containing configuration info might be setup by
- *      BIOS and might be cleared on reset.  This function saves the
- *      initial values of those registers into @hpriv such that they
- *      can be restored after controller reset.
- *
- *      If inconsistent, config values are fixed up by this function.
- *
- *      LOCKING:
- *      None.
- */
-static void ahci_save_initial_config(struct pci_dev *pdev,
-                                     struct ahci_host_priv *hpriv)
-{
-        void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
-        u32 cap, cap2, vers, port_map;
-        int i;
-        int mv;
-
-        /* make sure AHCI mode is enabled before accessing CAP */
-        ahci_enable_ahci(mmio);
-
-        /* Values prefixed with saved_ are written back to host after
-         * reset.  Values without are used for driver operation.
-         */
-        hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
-        hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
-
-        /* CAP2 register is only defined for AHCI 1.2 and later */
-        vers = readl(mmio + HOST_VERSION);
-        if ((vers >> 16) > 1 ||
-           ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
-                hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
-        else
-                hpriv->saved_cap2 = cap2 = 0;
-
-        /* some chips have errata preventing 64bit use */
-        if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
-                dev_printk(KERN_INFO, &pdev->dev,
-                           "controller can't do 64bit DMA, forcing 32bit\n");
-                cap &= ~HOST_CAP_64;
-        }
-
-        if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
-                dev_printk(KERN_INFO, &pdev->dev,
-                           "controller can't do NCQ, turning off CAP_NCQ\n");
-                cap &= ~HOST_CAP_NCQ;
-        }
-
-        if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
-                dev_printk(KERN_INFO, &pdev->dev,
-                           "controller can do NCQ, turning on CAP_NCQ\n");
-                cap |= HOST_CAP_NCQ;
-        }
-
-        if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
-                dev_printk(KERN_INFO, &pdev->dev,
-                           "controller can't do PMP, turning off CAP_PMP\n");
-                cap &= ~HOST_CAP_PMP;
-        }
-
-        if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
-                dev_printk(KERN_INFO, &pdev->dev,
-                           "controller can't do SNTF, turning off CAP_SNTF\n");
-                cap &= ~HOST_CAP_SNTF;
-        }
-
-        if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
-            port_map != 1) {
-                dev_printk(KERN_INFO, &pdev->dev,
-                           "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
-                           port_map, 1);
-                port_map = 1;
+        if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
+                dev_info(&pdev->dev, "JMB361 has only one port\n");
+                force_port_map = 1;
         }
 
         /*
@@ -921,469 +430,25 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
          */
         if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
                 if (pdev->device == 0x6121)
-                        mv = 0x3;
+                        mask_port_map = 0x3;
                 else
-                        mv = 0xf;
-                dev_printk(KERN_ERR, &pdev->dev,
-                           "MV_AHCI HACK: port_map %x -> %x\n",
-                           port_map,
-                           port_map & mv);
-                dev_printk(KERN_ERR, &pdev->dev,
+                        mask_port_map = 0xf;
+                dev_info(&pdev->dev,
                           "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
-
-                port_map &= mv;
-        }
-
-        /* cross check port_map and cap.n_ports */
-        if (port_map) {
-                int map_ports = 0;
-
-                for (i = 0; i < AHCI_MAX_PORTS; i++)
-                        if (port_map & (1 << i))
-                                map_ports++;
-
-                /* If PI has more ports than n_ports, whine, clear
-                 * port_map and let it be generated from n_ports.
-                 */
-                if (map_ports > ahci_nr_ports(cap)) {
-                        dev_printk(KERN_WARNING, &pdev->dev,
-                                   "implemented port map (0x%x) contains more "
-                                   "ports than nr_ports (%u), using nr_ports\n",
-                                   port_map, ahci_nr_ports(cap));
-                        port_map = 0;
-                }
-        }
-
-        /* fabricate port_map from cap.nr_ports */
-        if (!port_map) {
-                port_map = (1 << ahci_nr_ports(cap)) - 1;
-                dev_printk(KERN_WARNING, &pdev->dev,
-                           "forcing PORTS_IMPL to 0x%x\n", port_map);
-
-                /* write the fixed up value to the PI register */
-                hpriv->saved_port_map = port_map;
-        }
-
-        /* record values to use during operation */
-        hpriv->cap = cap;
-        hpriv->cap2 = cap2;
-        hpriv->port_map = port_map;
-}
-
-/**
- *      ahci_restore_initial_config - Restore initial config
- *      @host: target ATA host
- *
- *      Restore initial config stored by ahci_save_initial_config().
- *
- *      LOCKING:
- *      None.
- */
-static void ahci_restore_initial_config(struct ata_host *host)
-{
-        struct ahci_host_priv *hpriv = host->private_data;
-        void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-
-        writel(hpriv->saved_cap, mmio + HOST_CAP);
-        if (hpriv->saved_cap2)
-                writel(hpriv->saved_cap2, mmio + HOST_CAP2);
-        writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
-        (void) readl(mmio + HOST_PORTS_IMPL);   /* flush */
-}
-
-static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
-{
-        static const int offset[] = {
-                [SCR_STATUS]            = PORT_SCR_STAT,
-                [SCR_CONTROL]           = PORT_SCR_CTL,
-                [SCR_ERROR]             = PORT_SCR_ERR,
-                [SCR_ACTIVE]            = PORT_SCR_ACT,
-                [SCR_NOTIFICATION]      = PORT_SCR_NTF,
-        };
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-
-        if (sc_reg < ARRAY_SIZE(offset) &&
-            (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
-                return offset[sc_reg];
-        return 0;
-}
-
-static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
-{
-        void __iomem *port_mmio = ahci_port_base(link->ap);
-        int offset = ahci_scr_offset(link->ap, sc_reg);
-
-        if (offset) {
-                *val = readl(port_mmio + offset);
-                return 0;
-        }
-        return -EINVAL;
-}
-
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
-{
-        void __iomem *port_mmio = ahci_port_base(link->ap);
-        int offset = ahci_scr_offset(link->ap, sc_reg);
-
-        if (offset) {
-                writel(val, port_mmio + offset);
-                return 0;
-        }
-        return -EINVAL;
-}
-
-static void ahci_start_engine(struct ata_port *ap)
-{
-        void __iomem *port_mmio = ahci_port_base(ap);
-        u32 tmp;
-
-        /* start DMA */
-        tmp = readl(port_mmio + PORT_CMD);
-        tmp |= PORT_CMD_START;
-        writel(tmp, port_mmio + PORT_CMD);
-        readl(port_mmio + PORT_CMD); /* flush */
-}
-
-static int ahci_stop_engine(struct ata_port *ap)
-{
-        void __iomem *port_mmio = ahci_port_base(ap);
-        u32 tmp;
-
-        tmp = readl(port_mmio + PORT_CMD);
-
-        /* check if the HBA is idle */
-        if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
-                return 0;
-
-        /* setting HBA to idle */
-        tmp &= ~PORT_CMD_START;
-        writel(tmp, port_mmio + PORT_CMD);
-
-        /* wait for engine to stop. This could be as long as 500 msec */
-        tmp = ata_wait_register(port_mmio + PORT_CMD,
-                                PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
-        if (tmp & PORT_CMD_LIST_ON)
-                return -EIO;
-
-        return 0;
-}
-
-static void ahci_start_fis_rx(struct ata_port *ap)
-{
-        void __iomem *port_mmio = ahci_port_base(ap);
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-        struct ahci_port_priv *pp = ap->private_data;
-        u32 tmp;
-
-        /* set FIS registers */
-        if (hpriv->cap & HOST_CAP_64)
-                writel((pp->cmd_slot_dma >> 16) >> 16,
-                       port_mmio + PORT_LST_ADDR_HI);
-        writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
-
-        if (hpriv->cap & HOST_CAP_64)
-                writel((pp->rx_fis_dma >> 16) >> 16,
-                       port_mmio + PORT_FIS_ADDR_HI);
-        writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
-
-        /* enable FIS reception */
-        tmp = readl(port_mmio + PORT_CMD);
-        tmp |= PORT_CMD_FIS_RX;
-        writel(tmp, port_mmio + PORT_CMD);
-
-        /* flush */
-        readl(port_mmio + PORT_CMD);
-}
-
-static int ahci_stop_fis_rx(struct ata_port *ap)
-{
-        void __iomem *port_mmio = ahci_port_base(ap);
-        u32 tmp;
-
-        /* disable FIS reception */
-        tmp = readl(port_mmio + PORT_CMD);
-        tmp &= ~PORT_CMD_FIS_RX;
-        writel(tmp, port_mmio + PORT_CMD);
-
-        /* wait for completion, spec says 500ms, give it 1000 */
-        tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
-                                PORT_CMD_FIS_ON, 10, 1000);
-        if (tmp & PORT_CMD_FIS_ON)
-                return -EBUSY;
-
-        return 0;
-}
-
-static void ahci_power_up(struct ata_port *ap)
-{
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-        void __iomem *port_mmio = ahci_port_base(ap);
-        u32 cmd;
-
-        cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
-
-        /* spin up device */
-        if (hpriv->cap & HOST_CAP_SSS) {
-                cmd |= PORT_CMD_SPIN_UP;
-                writel(cmd, port_mmio + PORT_CMD);
-        }
-
-        /* wake up link */
-        writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
-}
-
-static void ahci_disable_alpm(struct ata_port *ap)
-{
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-        void __iomem *port_mmio = ahci_port_base(ap);
-        u32 cmd;
-        struct ahci_port_priv *pp = ap->private_data;
-
-        /* IPM bits should be disabled by libata-core */
-        /* get the existing command bits */
-        cmd = readl(port_mmio + PORT_CMD);
-
-        /* disable ALPM and ASP */
-        cmd &= ~PORT_CMD_ASP;
-        cmd &= ~PORT_CMD_ALPE;
-
-        /* force the interface back to active */
-        cmd |= PORT_CMD_ICC_ACTIVE;
-
-        /* write out new cmd value */
-        writel(cmd, port_mmio + PORT_CMD);
-        cmd = readl(port_mmio + PORT_CMD);
-
-        /* wait 10ms to be sure we've come out of any low power state */
-        msleep(10);
-
-        /* clear out any PhyRdy stuff from interrupt status */
-        writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
-
-        /* go ahead and clean out PhyRdy Change from Serror too */
-        ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
-
-        /*
-         * Clear flag to indicate that we should ignore all PhyRdy
-         * state changes
-         */
-        hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
-
-        /*
-         * Enable interrupts on Phy Ready.
-         */
-        pp->intr_mask |= PORT_IRQ_PHYRDY;
-        writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-
-        /*
-         * don't change the link pm policy - we can be called
-         * just to turn of link pm temporarily
-         */
-}
-
-static int ahci_enable_alpm(struct ata_port *ap,
-        enum link_pm policy)
-{
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-        void __iomem *port_mmio = ahci_port_base(ap);
-        u32 cmd;
-        struct ahci_port_priv *pp = ap->private_data;
-        u32 asp;
-
-        /* Make sure the host is capable of link power management */
-        if (!(hpriv->cap & HOST_CAP_ALPM))
-                return -EINVAL;
-
-        switch (policy) {
-        case MAX_PERFORMANCE:
-        case NOT_AVAILABLE:
-                /*
-                 * if we came here with NOT_AVAILABLE,
-                 * it just means this is the first time we
-                 * have tried to enable - default to max performance,
-                 * and let the user go to lower power modes on request.
-                 */
-                ahci_disable_alpm(ap);
-                return 0;
-        case MIN_POWER:
-                /* configure HBA to enter SLUMBER */
-                asp = PORT_CMD_ASP;
-                break;
-        case MEDIUM_POWER:
-                /* configure HBA to enter PARTIAL */
-                asp = 0;
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        /*
-         * Disable interrupts on Phy Ready. This keeps us from
-         * getting woken up due to spurious phy ready interrupts
-         * TBD - Hot plug should be done via polling now, is
-         * that even supported?
-         */
-        pp->intr_mask &= ~PORT_IRQ_PHYRDY;
-        writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-
-        /*
-         * Set a flag to indicate that we should ignore all PhyRdy
-         * state changes since these can happen now whenever we
-         * change link state
-         */
-        hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
-
-        /* get the existing command bits */
-        cmd = readl(port_mmio + PORT_CMD);
-
-        /*
-         * Set ASP based on Policy
-         */
-        cmd |= asp;
-
-        /*
-         * Setting this bit will instruct the HBA to aggressively
-         * enter a lower power link state when it's appropriate and
-         * based on the value set above for ASP
-         */
-        cmd |= PORT_CMD_ALPE;
-
-        /* write out new cmd value */
-        writel(cmd, port_mmio + PORT_CMD);
-        cmd = readl(port_mmio + PORT_CMD);
-
-        /* IPM bits should be set by libata-core */
-        return 0;
-}
-
-#ifdef CONFIG_PM
-static void ahci_power_down(struct ata_port *ap)
-{
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-        void __iomem *port_mmio = ahci_port_base(ap);
-        u32 cmd, scontrol;
-
-        if (!(hpriv->cap & HOST_CAP_SSS))
-                return;
-
-        /* put device into listen mode, first set PxSCTL.DET to 0 */
-        scontrol = readl(port_mmio + PORT_SCR_CTL);
-        scontrol &= ~0xf;
-        writel(scontrol, port_mmio + PORT_SCR_CTL);
-
-        /* then set PxCMD.SUD to 0 */
-        cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
-        cmd &= ~PORT_CMD_SPIN_UP;
-        writel(cmd, port_mmio + PORT_CMD);
-}
-#endif
-
-static void ahci_start_port(struct ata_port *ap)
-{
-        struct ahci_port_priv *pp = ap->private_data;
-        struct ata_link *link;
-        struct ahci_em_priv *emp;
-        ssize_t rc;
-        int i;
-
-        /* enable FIS reception */
-        ahci_start_fis_rx(ap);
-
-        /* enable DMA */
-        ahci_start_engine(ap);
-
-        /* turn on LEDs */
-        if (ap->flags & ATA_FLAG_EM) {
-                ata_for_each_link(link, ap, EDGE) {
-                        emp = &pp->em_priv[link->pmp];
-
-                        /* EM Transmit bit maybe busy during init */
-                        for (i = 0; i < EM_MAX_RETRY; i++) {
-                                rc = ahci_transmit_led_message(ap,
-                                                               emp->led_state,
-                                                               4);
-                                if (rc == -EBUSY)
-                                        msleep(1);
-                                else
-                                        break;
-                        }
-                }
         }
 
-        if (ap->flags & ATA_FLAG_SW_ACTIVITY)
-                ata_for_each_link(link, ap, EDGE)
-                        ahci_init_sw_activity(link);
-
+        ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
+                                 mask_port_map);
 }
 
-static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
-{
-        int rc;
-
-        /* disable DMA */
-        rc = ahci_stop_engine(ap);
-        if (rc) {
-                *emsg = "failed to stop engine";
-                return rc;
-        }
-
-        /* disable FIS reception */
-        rc = ahci_stop_fis_rx(ap);
-        if (rc) {
-                *emsg = "failed stop FIS RX";
-                return rc;
-        }
-
-        return 0;
-}
-
-static int ahci_reset_controller(struct ata_host *host)
+static int ahci_pci_reset_controller(struct ata_host *host)
 {
         struct pci_dev *pdev = to_pci_dev(host->dev);
-        struct ahci_host_priv *hpriv = host->private_data;
-        void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-        u32 tmp;
 
-        /* we must be in AHCI mode, before using anything
-         * AHCI-specific, such as HOST_RESET.
-         */
-        ahci_enable_ahci(mmio);
-
-        /* global controller reset */
-        if (!ahci_skip_host_reset) {
-                tmp = readl(mmio + HOST_CTL);
-                if ((tmp & HOST_RESET) == 0) {
-                        writel(tmp | HOST_RESET, mmio + HOST_CTL);
-                        readl(mmio + HOST_CTL); /* flush */
-                }
-
-                /*
-                 * to perform host reset, OS should set HOST_RESET
-                 * and poll until this bit is read to be "0".
-                 * reset must complete within 1 second, or
-                 * the hardware should be considered fried.
-                 */
-                tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
-                                        HOST_RESET, 10, 1000);
-
-                if (tmp & HOST_RESET) {
-                        dev_printk(KERN_ERR, host->dev,
-                                   "controller reset failed (0x%x)\n", tmp);
-                        return -EIO;
-                }
-
-                /* turn on AHCI mode */
-                ahci_enable_ahci(mmio);
-
-                /* Some registers might be cleared on reset.  Restore
-                 * initial values.
-                 */
-                ahci_restore_initial_config(host);
-        } else
-                dev_printk(KERN_INFO, host->dev,
-                           "skipping global host reset\n");
+        ahci_reset_controller(host);
 
         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
+                struct ahci_host_priv *hpriv = host->private_data;
                 u16 tmp16;
 
                 /* configure PCS */
@@ -1397,267 +462,10 @@ static int ahci_reset_controller(struct ata_host *host)
         return 0;
 }
 
-static void ahci_sw_activity(struct ata_link *link)
-{
-        struct ata_port *ap = link->ap;
-        struct ahci_port_priv *pp = ap->private_data;
-        struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-
-        if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
-                return;
-
-        emp->activity++;
-        if (!timer_pending(&emp->timer))
-                mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
-}
-
-static void ahci_sw_activity_blink(unsigned long arg)
-{
-        struct ata_link *link = (struct ata_link *)arg;
-        struct ata_port *ap = link->ap;
-        struct ahci_port_priv *pp = ap->private_data;
-        struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-        unsigned long led_message = emp->led_state;
-        u32 activity_led_state;
-        unsigned long flags;
-
-        led_message &= EM_MSG_LED_VALUE;
-        led_message |= ap->port_no | (link->pmp << 8);
-
-        /* check to see if we've had activity.  If so,
-         * toggle state of LED and reset timer.  If not,
-         * turn LED to desired idle state.
-         */
-        spin_lock_irqsave(ap->lock, flags);
-        if (emp->saved_activity != emp->activity) {
-                emp->saved_activity = emp->activity;
-                /* get the current LED state */
-                activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
-
-                if (activity_led_state)
-                        activity_led_state = 0;
-                else
-                        activity_led_state = 1;
-
-                /* clear old state */
-                led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
-
-                /* toggle state */
-                led_message |= (activity_led_state << 16);
-                mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
-        } else {
-                /* switch to idle */
-                led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
-                if (emp->blink_policy == BLINK_OFF)
-                        led_message |= (1 << 16);
-        }
-        spin_unlock_irqrestore(ap->lock, flags);
-        ahci_transmit_led_message(ap, led_message, 4);
-}
-
-static void ahci_init_sw_activity(struct ata_link *link)
-{
-        struct ata_port *ap = link->ap;
-        struct ahci_port_priv *pp = ap->private_data;
-        struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-
-        /* init activity stats, setup timer */
-        emp->saved_activity = emp->activity = 0;
-        setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
-
-        /* check our blink policy and set flag for link if it's enabled */
-        if (emp->blink_policy)
-                link->flags |= ATA_LFLAG_SW_ACTIVITY;
-}
-
-static int ahci_reset_em(struct ata_host *host)
-{
-        void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-        u32 em_ctl;
-
-        em_ctl = readl(mmio + HOST_EM_CTL);
-        if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
-                return -EINVAL;
-
-        writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
-        return 0;
-}
-
-static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
-                                        ssize_t size)
-{
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-        struct ahci_port_priv *pp = ap->private_data;
-        void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
-        u32 em_ctl;
-        u32 message[] = {0, 0};
-        unsigned long flags;
-        int pmp;
-        struct ahci_em_priv *emp;
-
-        /* get the slot number from the message */
-        pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
-        if (pmp < EM_MAX_SLOTS)
-                emp = &pp->em_priv[pmp];
-        else
-                return -EINVAL;
-
-        spin_lock_irqsave(ap->lock, flags);
-
-        /*
-         * if we are still busy transmitting a previous message,
-         * do not allow
-         */
-        em_ctl = readl(mmio + HOST_EM_CTL);
-        if (em_ctl & EM_CTL_TM) {
-                spin_unlock_irqrestore(ap->lock, flags);
-                return -EBUSY;
-        }
-
-        /*
-         * create message header - this is all zero except for
-         * the message size, which is 4 bytes.
-         */
-        message[0] |= (4 << 8);
-
-        /* ignore 0:4 of byte zero, fill in port info yourself */
-        message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
-
-        /* write message to EM_LOC */
-        writel(message[0], mmio + hpriv->em_loc);
-        writel(message[1], mmio + hpriv->em_loc+4);
-
-        /* save off new led state for port/slot */
-        emp->led_state = state;
-
-        /*
-         * tell hardware to transmit the message
-         */
-        writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
-
-        spin_unlock_irqrestore(ap->lock, flags);
-        return size;
-}
-
-static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
-{
-        struct ahci_port_priv *pp = ap->private_data;
-        struct ata_link *link;
-        struct ahci_em_priv *emp;
-        int rc = 0;
-
-        ata_for_each_link(link, ap, EDGE) {
-                emp = &pp->em_priv[link->pmp];
-                rc += sprintf(buf, "%lx\n", emp->led_state);
-        }
-        return rc;
-}
-
-static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
-                                size_t size)
-{
-        int state;
-        int pmp;
-        struct ahci_port_priv *pp = ap->private_data;
-        struct ahci_em_priv *emp;
-
-        state = simple_strtoul(buf, NULL, 0);
-
-        /* get the slot number from the message */
-        pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
-        if (pmp < EM_MAX_SLOTS)
-                emp = &pp->em_priv[pmp];
-        else
-                return -EINVAL;
-
-        /* mask off the activity bits if we are in sw_activity
-         * mode, user should turn off sw_activity before setting
-         * activity led through em_message
-         */
-        if (emp->blink_policy)
-                state &= ~EM_MSG_LED_VALUE_ACTIVITY;
-
-        return ahci_transmit_led_message(ap, state, size);
-}
-
-static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
-{
-        struct ata_link *link = dev->link;
-        struct ata_port *ap = link->ap;
-        struct ahci_port_priv *pp = ap->private_data;
-        struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-        u32 port_led_state = emp->led_state;
-
-        /* save the desired Activity LED behavior */
-        if (val == OFF) {
-                /* clear LFLAG */
-                link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
-
-                /* set the LED to OFF */
-                port_led_state &= EM_MSG_LED_VALUE_OFF;
-                port_led_state |= (ap->port_no | (link->pmp << 8));
-                ahci_transmit_led_message(ap, port_led_state, 4);
-        } else {
-                link->flags |= ATA_LFLAG_SW_ACTIVITY;
-                if (val == BLINK_OFF) {
-                        /* set LED to ON for idle */
-                        port_led_state &= EM_MSG_LED_VALUE_OFF;
-                        port_led_state |= (ap->port_no | (link->pmp << 8));
-                        port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
-                        ahci_transmit_led_message(ap, port_led_state, 4);
-                }
-        }
-        emp->blink_policy = val;
-        return 0;
-}
-
-static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
-{
-        struct ata_link *link = dev->link;
-        struct ata_port *ap = link->ap;
-        struct ahci_port_priv *pp = ap->private_data;
-        struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-
-        /* display the saved value of activity behavior for this
-         * disk.
-         */
-        return sprintf(buf, "%d\n", emp->blink_policy);
-}
-
-static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
-                           int port_no, void __iomem *mmio,
-                           void __iomem *port_mmio)
-{
-        const char *emsg = NULL;
-        int rc;
-        u32 tmp;
-
-        /* make sure port is not active */
-        rc = ahci_deinit_port(ap, &emsg);
-        if (rc)
-                dev_printk(KERN_WARNING, &pdev->dev,
-                           "%s (%d)\n", emsg, rc);
-
-        /* clear SError */
-        tmp = readl(port_mmio + PORT_SCR_ERR);
-        VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
-        writel(tmp, port_mmio + PORT_SCR_ERR);
-
-        /* clear port IRQ */
-        tmp = readl(port_mmio + PORT_IRQ_STAT);
-        VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
-        if (tmp)
-                writel(tmp, port_mmio + PORT_IRQ_STAT);
-
-        writel(1 << port_no, mmio + HOST_IRQ_STAT);
-}
-
-static void ahci_init_controller(struct ata_host *host)
+static void ahci_pci_init_controller(struct ata_host *host)
 {
         struct ahci_host_priv *hpriv = host->private_data;
         struct pci_dev *pdev = to_pci_dev(host->dev);
-        void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-        int i;
         void __iomem *port_mmio;
         u32 tmp;
         int mv;
@@ -1678,220 +486,7 @@ static void ahci_init_controller(struct ata_host *host)
                         writel(tmp, port_mmio + PORT_IRQ_STAT);
         }
 
-        for (i = 0; i < host->n_ports; i++) {
-                struct ata_port *ap = host->ports[i];
-
-                port_mmio = ahci_port_base(ap);
-                if (ata_port_is_dummy(ap))
-                        continue;
-
-                ahci_port_init(pdev, ap, i, mmio, port_mmio);
-        }
-
-        tmp = readl(mmio + HOST_CTL);
-        VPRINTK("HOST_CTL 0x%x\n", tmp);
-        writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
-        tmp = readl(mmio + HOST_CTL);
-        VPRINTK("HOST_CTL 0x%x\n", tmp);
-}
-
-static void ahci_dev_config(struct ata_device *dev)
-{
-        struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
-
-        if (hpriv->flags & AHCI_HFLAG_SECT255) {
-                dev->max_sectors = 255;
-                ata_dev_printk(dev, KERN_INFO,
-                               "SB600 AHCI: limiting to 255 sectors per cmd\n");
-        }
-}
-
-static unsigned int ahci_dev_classify(struct ata_port *ap)
-{
-        void __iomem *port_mmio = ahci_port_base(ap);
-        struct ata_taskfile tf;
-        u32 tmp;
-
-        tmp = readl(port_mmio + PORT_SIG);
-        tf.lbah         = (tmp >> 24)   & 0xff;
-        tf.lbam         = (tmp >> 16)   & 0xff;
-        tf.lbal         = (tmp >> 8)    & 0xff;
-        tf.nsect        = (tmp)         & 0xff;
-
-        return ata_dev_classify(&tf);
-}
-
-static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
-                               u32 opts)
-{
-        dma_addr_t cmd_tbl_dma;
-
-        cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
-
-        pp->cmd_slot[tag].opts = cpu_to_le32(opts);
-        pp->cmd_slot[tag].status = 0;
-        pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
-        pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
-}
-
-static int ahci_kick_engine(struct ata_port *ap)
-{
-        void __iomem *port_mmio = ahci_port_base(ap);
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-        u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
-        u32 tmp;
-        int busy, rc;
-
-        /* stop engine */
-        rc = ahci_stop_engine(ap);
-        if (rc)
-                goto out_restart;
-
-        /* need to do CLO?
-         * always do CLO if PMP is attached (AHCI-1.3 9.2)
-         */
-        busy = status & (ATA_BUSY | ATA_DRQ);
-        if (!busy && !sata_pmp_attached(ap)) {
-                rc = 0;
-                goto out_restart;
-        }
-
-        if (!(hpriv->cap & HOST_CAP_CLO)) {
-                rc = -EOPNOTSUPP;
-                goto out_restart;
-        }
-
-        /* perform CLO */
-        tmp = readl(port_mmio + PORT_CMD);
-        tmp |= PORT_CMD_CLO;
-        writel(tmp, port_mmio + PORT_CMD);
-
-        rc = 0;
-        tmp = ata_wait_register(port_mmio + PORT_CMD,
-                                PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
-        if (tmp & PORT_CMD_CLO)
-                rc = -EIO;
-
-        /* restart engine */
- out_restart:
-        ahci_start_engine(ap);
-        return rc;
-}
-
-static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
-                                struct ata_taskfile *tf, int is_cmd, u16 flags,
-                                unsigned long timeout_msec)
-{
-        const u32 cmd_fis_len = 5; /* five dwords */
-        struct ahci_port_priv *pp = ap->private_data;
-        void __iomem *port_mmio = ahci_port_base(ap);
-        u8 *fis = pp->cmd_tbl;
-        u32 tmp;
-
-        /* prep the command */
-        ata_tf_to_fis(tf, pmp, is_cmd, fis);
-        ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
-
-        /* issue & wait */
-        writel(1, port_mmio + PORT_CMD_ISSUE);
-
-        if (timeout_msec) {
-                tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
-                                        1, timeout_msec);
-                if (tmp & 0x1) {
-                        ahci_kick_engine(ap);
-                        return -EBUSY;
-                }
-        } else
-                readl(port_mmio + PORT_CMD_ISSUE);      /* flush */
-
-        return 0;
-}
-
-static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
-                             int pmp, unsigned long deadline,
-                             int (*check_ready)(struct ata_link *link))
-{
-        struct ata_port *ap = link->ap;
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-        const char *reason = NULL;
-        unsigned long now, msecs;
-        struct ata_taskfile tf;
-        int rc;
-
-        DPRINTK("ENTER\n");
-
-        /* prepare for SRST (AHCI-1.1 10.4.1) */
-        rc = ahci_kick_engine(ap);
-        if (rc && rc != -EOPNOTSUPP)
-                ata_link_printk(link, KERN_WARNING,
-                                "failed to reset engine (errno=%d)\n", rc);
-
-        ata_tf_init(link->device, &tf);
-
-        /* issue the first D2H Register FIS */
-        msecs = 0;
-        now = jiffies;
-        if (time_after(now, deadline))
-                msecs = jiffies_to_msecs(deadline - now);
-
-        tf.ctl |= ATA_SRST;
-        if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
-                                 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
-                rc = -EIO;
-                reason = "1st FIS failed";
-                goto fail;
-        }
-
-        /* spec says at least 5us, but be generous and sleep for 1ms */
-        msleep(1);
-
-        /* issue the second D2H Register FIS */
-        tf.ctl &= ~ATA_SRST;
-        ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
-
-        /* wait for link to become ready */
-        rc = ata_wait_after_reset(link, deadline, check_ready);
-        if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
-                /*
-                 * Workaround for cases where link online status can't
-                 * be trusted.  Treat device readiness timeout as link
-                 * offline.
-                 */
-                ata_link_printk(link, KERN_INFO,
-                                "device not ready, treating as offline\n");
-                *class = ATA_DEV_NONE;
-        } else if (rc) {
-                /* link occupied, -ENODEV too is an error */
-                reason = "device not ready";
-                goto fail;
-        } else
-                *class = ahci_dev_classify(ap);
-
-        DPRINTK("EXIT, class=%u\n", *class);
-        return 0;
-
- fail:
-        ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
-        return rc;
-}
-
-static int ahci_check_ready(struct ata_link *link)
-{
-        void __iomem *port_mmio = ahci_port_base(link->ap);
-        u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
-
-        return ata_check_ready(status);
-}
-
-static int ahci_softreset(struct ata_link *link, unsigned int *class,
-                          unsigned long deadline)
-{
-        int pmp = sata_srst_pmp(link);
-
-        DPRINTK("ENTER\n");
-
-        return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
+        ahci_init_controller(host);
 }
 
 static int ahci_sb600_check_ready(struct ata_link *link)
@@ -1943,38 +538,6 @@ static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
         return rc;
 }
 
-static int ahci_hardreset(struct ata_link *link, unsigned int *class,
-                          unsigned long deadline)
-{
-        const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
-        struct ata_port *ap = link->ap;
-        struct ahci_port_priv *pp = ap->private_data;
-        u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
-        struct ata_taskfile tf;
-        bool online;
-        int rc;
-
-        DPRINTK("ENTER\n");
-
-        ahci_stop_engine(ap);
-
-        /* clear D2H reception area to properly wait for D2H FIS */
-        ata_tf_init(link->device, &tf);
-        tf.command = 0x80;
-        ata_tf_to_fis(&tf, 0, 0, d2h_fis);
-
-        rc = sata_link_hardreset(link, timing, deadline, &online,
-                                 ahci_check_ready);
-
-        ahci_start_engine(ap);
-
-        if (online)
-                *class = ahci_dev_classify(ap);
-
-        DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
-        return rc;
-}
-
 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
                                  unsigned long deadline)
 {
@@ -2043,605 +606,12 @@ static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
         return rc;
 }
 
-static void ahci_postreset(struct ata_link *link, unsigned int *class)
-{
-        struct ata_port *ap = link->ap;
-        void __iomem *port_mmio = ahci_port_base(ap);
-        u32 new_tmp, tmp;
-
-        ata_std_postreset(link, class);
-
-        /* Make sure port's ATAPI bit is set appropriately */
-        new_tmp = tmp = readl(port_mmio + PORT_CMD);
-        if (*class == ATA_DEV_ATAPI)
-                new_tmp |= PORT_CMD_ATAPI;
-        else
-                new_tmp &= ~PORT_CMD_ATAPI;
-        if (new_tmp != tmp) {
-                writel(new_tmp, port_mmio + PORT_CMD);
-                readl(port_mmio + PORT_CMD); /* flush */
-        }
-}
-
-static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
-{
-        struct scatterlist *sg;
-        struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
-        unsigned int si;
-
-        VPRINTK("ENTER\n");
-
-        /*
-         * Next, the S/G list.
-         */
-        for_each_sg(qc->sg, sg, qc->n_elem, si) {
-                dma_addr_t addr = sg_dma_address(sg);
-                u32 sg_len = sg_dma_len(sg);
-
-                ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
-                ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
-                ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
-        }
-
-        return si;
-}
-
-static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
-{
-        struct ata_port *ap = qc->ap;
-        struct ahci_port_priv *pp = ap->private_data;
-
-        if (!sata_pmp_attached(ap) || pp->fbs_enabled)
-                return ata_std_qc_defer(qc);
-        else
-                return sata_pmp_qc_defer_cmd_switch(qc);
-}
-
-static void ahci_qc_prep(struct ata_queued_cmd *qc)
-{
-        struct ata_port *ap = qc->ap;
-        struct ahci_port_priv *pp = ap->private_data;
-        int is_atapi = ata_is_atapi(qc->tf.protocol);
-        void *cmd_tbl;
-        u32 opts;
-        const u32 cmd_fis_len = 5; /* five dwords */
-        unsigned int n_elem;
-
-        /*
-         * Fill in command table information.  First, the header,
-         * a SATA Register - Host to Device command FIS.
-         */
-        cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
-
-        ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
-        if (is_atapi) {
-                memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
-                memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
-        }
-
-        n_elem = 0;
-        if (qc->flags & ATA_QCFLAG_DMAMAP)
-                n_elem = ahci_fill_sg(qc, cmd_tbl);
-
-        /*
-         * Fill in command slot information.
-         */
-        opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
-        if (qc->tf.flags & ATA_TFLAG_WRITE)
-                opts |= AHCI_CMD_WRITE;
-        if (is_atapi)
-                opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
-
-        ahci_fill_cmd_slot(pp, qc->tag, opts);
-}
-
-static void ahci_fbs_dec_intr(struct ata_port *ap)
-{
-        struct ahci_port_priv *pp = ap->private_data;
-        void __iomem *port_mmio = ahci_port_base(ap);
-        u32 fbs = readl(port_mmio + PORT_FBS);
-        int retries = 3;
-
-        DPRINTK("ENTER\n");
-        BUG_ON(!pp->fbs_enabled);
-
-        /* time to wait for DEC is not specified by AHCI spec,
-         * add a retry loop for safety.
-         */
-        writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
-        fbs = readl(port_mmio + PORT_FBS);
-        while ((fbs & PORT_FBS_DEC) && retries--) {
-                udelay(1);
-                fbs = readl(port_mmio + PORT_FBS);
-        }
-
-        if (fbs & PORT_FBS_DEC)
-                dev_printk(KERN_ERR, ap->host->dev,
-                           "failed to clear device error\n");
-}
-
-static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
-{
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-        struct ahci_port_priv *pp = ap->private_data;
-        struct ata_eh_info *host_ehi = &ap->link.eh_info;
-        struct ata_link *link = NULL;
-        struct ata_queued_cmd *active_qc;
-        struct ata_eh_info *active_ehi;
-        bool fbs_need_dec = false;
-        u32 serror;
-
-        /* determine active link with error */
-        if (pp->fbs_enabled) {
-                void __iomem *port_mmio = ahci_port_base(ap);
-                u32 fbs = readl(port_mmio + PORT_FBS);
-                int pmp = fbs >> PORT_FBS_DWE_OFFSET;
-
-                if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
-                    ata_link_online(&ap->pmp_link[pmp])) {
-                        link = &ap->pmp_link[pmp];
-                        fbs_need_dec = true;
-                }
-
-        } else
-                ata_for_each_link(link, ap, EDGE)
-                        if (ata_link_active(link))
-                                break;
-
-        if (!link)
-                link = &ap->link;
-
-        active_qc = ata_qc_from_tag(ap, link->active_tag);
-        active_ehi = &link->eh_info;
-
-        /* record irq stat */
-        ata_ehi_clear_desc(host_ehi);
-        ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
-
-        /* AHCI needs SError cleared; otherwise, it might lock up */
-        ahci_scr_read(&ap->link, SCR_ERROR, &serror);
-        ahci_scr_write(&ap->link, SCR_ERROR, serror);
-        host_ehi->serror |= serror;
-
-        /* some controllers set IRQ_IF_ERR on device errors, ignore it */
-        if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
-                irq_stat &= ~PORT_IRQ_IF_ERR;
-
-        if (irq_stat & PORT_IRQ_TF_ERR) {
-                /* If qc is active, charge it; otherwise, the active
-                 * link.  There's no active qc on NCQ errors.  It will
-                 * be determined by EH by reading log page 10h.
-                 */
-                if (active_qc)
-                        active_qc->err_mask |= AC_ERR_DEV;
-                else
-                        active_ehi->err_mask |= AC_ERR_DEV;
-
-                if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
-                        host_ehi->serror &= ~SERR_INTERNAL;
-        }
-
-        if (irq_stat & PORT_IRQ_UNK_FIS) {
-                u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
-
-                active_ehi->err_mask |= AC_ERR_HSM;
-                active_ehi->action |= ATA_EH_RESET;
-                ata_ehi_push_desc(active_ehi,
-                                  "unknown FIS %08x %08x %08x %08x" ,
-                                  unk[0], unk[1], unk[2], unk[3]);
-        }
-
-        if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
-                active_ehi->err_mask |= AC_ERR_HSM;
-                active_ehi->action |= ATA_EH_RESET;
-                ata_ehi_push_desc(active_ehi, "incorrect PMP");
-        }
-
-        if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
-                host_ehi->err_mask |= AC_ERR_HOST_BUS;
-                host_ehi->action |= ATA_EH_RESET;
-                ata_ehi_push_desc(host_ehi, "host bus error");
-        }
-
-        if (irq_stat & PORT_IRQ_IF_ERR) {
-                if (fbs_need_dec)
-                        active_ehi->err_mask |= AC_ERR_DEV;
-                else {
-                        host_ehi->err_mask |= AC_ERR_ATA_BUS;
-                        host_ehi->action |= ATA_EH_RESET;
-                }
-
-                ata_ehi_push_desc(host_ehi, "interface fatal error");
-        }
-
-        if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
-                ata_ehi_hotplugged(host_ehi);
-                ata_ehi_push_desc(host_ehi, "%s",
-                        irq_stat & PORT_IRQ_CONNECT ?
-                        "connection status changed" : "PHY RDY changed");
-        }
-
-        /* okay, let's hand over to EH */
-
-        if (irq_stat & PORT_IRQ_FREEZE)
-                ata_port_freeze(ap);
-        else if (fbs_need_dec) {
-                ata_link_abort(link);
-                ahci_fbs_dec_intr(ap);
-        } else
-                ata_port_abort(ap);
-}
-
-static void ahci_port_intr(struct ata_port *ap)
-{
-        void __iomem *port_mmio = ahci_port_base(ap);
-        struct ata_eh_info *ehi = &ap->link.eh_info;
-        struct ahci_port_priv *pp = ap->private_data;
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-        int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
-        u32 status, qc_active = 0;
-        int rc;
-
-        status = readl(port_mmio + PORT_IRQ_STAT);
-        writel(status, port_mmio + PORT_IRQ_STAT);
-
-        /* ignore BAD_PMP while resetting */
-        if (unlikely(resetting))
-                status &= ~PORT_IRQ_BAD_PMP;
-
-        /* If we are getting PhyRdy, this is
-         * just a power state change, we should
-         * clear out this, plus the PhyRdy/Comm
-         * Wake bits from Serror
-         */
-        if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
-                (status & PORT_IRQ_PHYRDY)) {
-                status &= ~PORT_IRQ_PHYRDY;
-                ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
-        }
-
-        if (unlikely(status & PORT_IRQ_ERROR)) {
-                ahci_error_intr(ap, status);
-                return;
-        }
-
-        if (status & PORT_IRQ_SDB_FIS) {
-                /* If SNotification is available, leave notification
-                 * handling to sata_async_notification().  If not,
-                 * emulate it by snooping SDB FIS RX area.
-                 *
-                 * Snooping FIS RX area is probably cheaper than
-                 * poking SNotification but some constrollers which
-                 * implement SNotification, ICH9 for example, don't
-                 * store AN SDB FIS into receive area.
-                 */
-                if (hpriv->cap & HOST_CAP_SNTF)
-                        sata_async_notification(ap);
-                else {
-                        /* If the 'N' bit in word 0 of the FIS is set,
-                         * we just received asynchronous notification.
-                         * Tell libata about it.
-                         *
-                         * Lack of SNotification should not appear in
-                         * ahci 1.2, so the workaround is unnecessary
-                         * when FBS is enabled.
-                         */
-                        if (pp->fbs_enabled)
-                                WARN_ON_ONCE(1);
-                        else {
-                                const __le32 *f = pp->rx_fis + RX_FIS_SDB;
-                                u32 f0 = le32_to_cpu(f[0]);
-                                if (f0 & (1 << 15))
-                                        sata_async_notification(ap);
-                        }
-                }
-        }
-
-        /* pp->active_link is not reliable once FBS is enabled, both
-         * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
-         * NCQ and non-NCQ commands may be in flight at the same time.
-         */
-        if (pp->fbs_enabled) {
-                if (ap->qc_active) {
-                        qc_active = readl(port_mmio + PORT_SCR_ACT);
-                        qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
-                }
-        } else {
-                /* pp->active_link is valid iff any command is in flight */
-                if (ap->qc_active && pp->active_link->sactive)
-                        qc_active = readl(port_mmio + PORT_SCR_ACT);
-                else
-                        qc_active = readl(port_mmio + PORT_CMD_ISSUE);
-        }
-
-        rc = ata_qc_complete_multiple(ap, qc_active);
-
-        /* while resetting, invalid completions are expected */
-        if (unlikely(rc < 0 && !resetting)) {
-                ehi->err_mask |= AC_ERR_HSM;
-                ehi->action |= ATA_EH_RESET;
-                ata_port_freeze(ap);
-        }
-}
-
-static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
-{
-        struct ata_host *host = dev_instance;
-        struct ahci_host_priv *hpriv;
-        unsigned int i, handled = 0;
-        void __iomem *mmio;
-        u32 irq_stat, irq_masked;
-
-        VPRINTK("ENTER\n");
-
-        hpriv = host->private_data;
-        mmio = host->iomap[AHCI_PCI_BAR];
-
-        /* sigh.  0xffffffff is a valid return from h/w */
-        irq_stat = readl(mmio + HOST_IRQ_STAT);
-        if (!irq_stat)
-                return IRQ_NONE;
-
-        irq_masked = irq_stat & hpriv->port_map;
-
-        spin_lock(&host->lock);
-
-        for (i = 0; i < host->n_ports; i++) {
-                struct ata_port *ap;
-
-                if (!(irq_masked & (1 << i)))
-                        continue;
-
-                ap = host->ports[i];
-                if (ap) {
-                        ahci_port_intr(ap);
-                        VPRINTK("port %u\n", i);
-                } else {
-                        VPRINTK("port %u (no irq)\n", i);
-                        if (ata_ratelimit())
-                                dev_printk(KERN_WARNING, host->dev,
-                                        "interrupt on disabled port %u\n", i);
-                }
-
-                handled = 1;
-        }
-
-        /* HOST_IRQ_STAT behaves as level triggered latch meaning that
-         * it should be cleared after all the port events are cleared;
-         * otherwise, it will raise a spurious interrupt after each
-         * valid one.  Please read section 10.6.2 of ahci 1.1 for more
-         * information.
-         *
-         * Also, use the unmasked value to clear interrupt as spurious
-         * pending event on a dummy port might cause screaming IRQ.
-         */
-        writel(irq_stat, mmio + HOST_IRQ_STAT);
-
-        spin_unlock(&host->lock);
-
-        VPRINTK("EXIT\n");
-
-        return IRQ_RETVAL(handled);
-}
-
-static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
-{
-        struct ata_port *ap = qc->ap;
-        void __iomem *port_mmio = ahci_port_base(ap);
-        struct ahci_port_priv *pp = ap->private_data;
-
-        /* Keep track of the currently active link.  It will be used
-         * in completion path to determine whether NCQ phase is in
-         * progress.
-         */
-        pp->active_link = qc->dev->link;
-
-        if (qc->tf.protocol == ATA_PROT_NCQ)
-                writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
-
-        if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
-                u32 fbs = readl(port_mmio + PORT_FBS);
-                fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
-                fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
-                writel(fbs, port_mmio + PORT_FBS);
-                pp->fbs_last_dev = qc->dev->link->pmp;
-        }
-
-        writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
-
-        ahci_sw_activity(qc->dev->link);
-
-        return 0;
-}
-
-static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
-{
-        struct ahci_port_priv *pp = qc->ap->private_data;
-        u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
-
-        if (pp->fbs_enabled)
-                d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
-
-        ata_tf_from_fis(d2h_fis, &qc->result_tf);
-        return true;
-}
-
-static void ahci_freeze(struct ata_port *ap)
-{
-        void __iomem *port_mmio = ahci_port_base(ap);
-
-        /* turn IRQ off */
-        writel(0, port_mmio + PORT_IRQ_MASK);
-}
-
-static void ahci_thaw(struct ata_port *ap)
-{
-        void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
-        void __iomem *port_mmio = ahci_port_base(ap);
-        u32 tmp;
-        struct ahci_port_priv *pp = ap->private_data;
-
-        /* clear IRQ */
-        tmp = readl(port_mmio + PORT_IRQ_STAT);
-        writel(tmp, port_mmio + PORT_IRQ_STAT);
-        writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
-
-        /* turn IRQ back on */
-        writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-}
-
-static void ahci_error_handler(struct ata_port *ap)
-{
-        if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
-                /* restart engine */
-                ahci_stop_engine(ap);
-                ahci_start_engine(ap);
-        }
-
-        sata_pmp_error_handler(ap);
-}
-
-static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
-{
-        struct ata_port *ap = qc->ap;
-
-        /* make DMA engine forget about the failed command */
-        if (qc->flags & ATA_QCFLAG_FAILED)
-                ahci_kick_engine(ap);
-}
-
-static void ahci_enable_fbs(struct ata_port *ap)
-{
-        struct ahci_port_priv *pp = ap->private_data;
-        void __iomem *port_mmio = ahci_port_base(ap);
-        u32 fbs;
-        int rc;
-
-        if (!pp->fbs_supported)
-                return;
-
-        fbs = readl(port_mmio + PORT_FBS);
-        if (fbs & PORT_FBS_EN) {
-                pp->fbs_enabled = true;
-                pp->fbs_last_dev = -1; /* initialization */
-                return;
-        }
-
-        rc = ahci_stop_engine(ap);
-        if (rc)
-                return;
-
-        writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
-        fbs = readl(port_mmio + PORT_FBS);
-        if (fbs & PORT_FBS_EN) {
-                dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
-                pp->fbs_enabled = true;
-                pp->fbs_last_dev = -1; /* initialization */
-        } else
-                dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
-
-        ahci_start_engine(ap);
-}
-
-static void ahci_disable_fbs(struct ata_port *ap)
-{
-        struct ahci_port_priv *pp = ap->private_data;
-        void __iomem *port_mmio = ahci_port_base(ap);
-        u32 fbs;
-        int rc;
-
-        if (!pp->fbs_supported)
-                return;
-
-        fbs = readl(port_mmio + PORT_FBS);
-        if ((fbs & PORT_FBS_EN) == 0) {
-                pp->fbs_enabled = false;
-                return;
-        }
-
-        rc = ahci_stop_engine(ap);
-        if (rc)
-                return;
-
-        writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
-        fbs = readl(port_mmio + PORT_FBS);
-        if (fbs & PORT_FBS_EN)
-                dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
-        else {
-                dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
-                pp->fbs_enabled = false;
-        }
-
-        ahci_start_engine(ap);
-}
-
-static void ahci_pmp_attach(struct ata_port *ap)
-{
-        void __iomem *port_mmio = ahci_port_base(ap);
-        struct ahci_port_priv *pp = ap->private_data;
-        u32 cmd;
-
-        cmd = readl(port_mmio + PORT_CMD);
-        cmd |= PORT_CMD_PMP;
-        writel(cmd, port_mmio + PORT_CMD);
-
-        ahci_enable_fbs(ap);
-
-        pp->intr_mask |= PORT_IRQ_BAD_PMP;
-        writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-}
-
-static void ahci_pmp_detach(struct ata_port *ap)
-{
-        void __iomem *port_mmio = ahci_port_base(ap);
-        struct ahci_port_priv *pp = ap->private_data;
-        u32 cmd;
-
-        ahci_disable_fbs(ap);
-
-        cmd = readl(port_mmio + PORT_CMD);
-        cmd &= ~PORT_CMD_PMP;
-        writel(cmd, port_mmio + PORT_CMD);
-
-        pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
-        writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-}
-
-static int ahci_port_resume(struct ata_port *ap)
-{
-        ahci_power_up(ap);
-        ahci_start_port(ap);
-
-        if (sata_pmp_attached(ap))
-                ahci_pmp_attach(ap);
-        else
-                ahci_pmp_detach(ap);
-
-        return 0;
-}
-
 #ifdef CONFIG_PM
-static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
-{
-        const char *emsg = NULL;
-        int rc;
-
-        rc = ahci_deinit_port(ap, &emsg);
-        if (rc == 0)
-                ahci_power_down(ap);
-        else {
-                ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
-                ahci_start_port(ap);
-        }
-
-        return rc;
-}
-
 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 {
         struct ata_host *host = dev_get_drvdata(&pdev->dev);
         struct ahci_host_priv *hpriv = host->private_data;
-        void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
+        void __iomem *mmio = hpriv->mmio;
         u32 ctl;
 
         if (mesg.event & PM_EVENT_SUSPEND &&
@@ -2675,11 +645,11 @@ static int ahci_pci_device_resume(struct pci_dev *pdev)
                 return rc;
 
         if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
-                rc = ahci_reset_controller(host);
+                rc = ahci_pci_reset_controller(host);
                 if (rc)
                         return rc;
 
-                ahci_init_controller(host);
+                ahci_pci_init_controller(host);
         }
 
         ata_host_resume(host);
@@ -2688,92 +658,6 @@ static int ahci_pci_device_resume(struct pci_dev *pdev)
 }
 #endif
 
-static int ahci_port_start(struct ata_port *ap)
-{
-        struct ahci_host_priv *hpriv = ap->host->private_data;
-        struct device *dev = ap->host->dev;
-        struct ahci_port_priv *pp;
-        void *mem;
-        dma_addr_t mem_dma;
-        size_t dma_sz, rx_fis_sz;
-
-        pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
-        if (!pp)
-                return -ENOMEM;
-
-        /* check FBS capability */
-        if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
-                void __iomem *port_mmio = ahci_port_base(ap);
-                u32 cmd = readl(port_mmio + PORT_CMD);
-                if (cmd & PORT_CMD_FBSCP)
-                        pp->fbs_supported = true;
-                else
-                        dev_printk(KERN_WARNING, dev,
-                                   "The port is not capable of FBS\n");
-        }
-
-        if (pp->fbs_supported) {
-                dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
-                rx_fis_sz = AHCI_RX_FIS_SZ * 16;
-        } else {
-                dma_sz = AHCI_PORT_PRIV_DMA_SZ;
-                rx_fis_sz = AHCI_RX_FIS_SZ;
-        }
-
-        mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
-        if (!mem)
-                return -ENOMEM;
-        memset(mem, 0, dma_sz);
-
-        /*
-         * First item in chunk of DMA memory: 32-slot command table,
-         * 32 bytes each in size
-         */
-        pp->cmd_slot = mem;
-        pp->cmd_slot_dma = mem_dma;
-
-        mem += AHCI_CMD_SLOT_SZ;
-        mem_dma += AHCI_CMD_SLOT_SZ;
-
-        /*
-         * Second item: Received-FIS area
-         */
-        pp->rx_fis = mem;
-        pp->rx_fis_dma = mem_dma;
-
-        mem += rx_fis_sz;
-        mem_dma += rx_fis_sz;
-
-        /*
-         * Third item: data area for storing a single command
-         * and its scatter-gather table
-         */
-        pp->cmd_tbl = mem;
-        pp->cmd_tbl_dma = mem_dma;
-
-        /*
-         * Save off initial list of interrupts to be enabled.
-         * This could be changed later
-         */
-        pp->intr_mask = DEF_PORT_IRQ;
-
-        ap->private_data = pp;
-
-        /* engage engines, captain */
-        return ahci_port_resume(ap);
-}
-
-static void ahci_port_stop(struct ata_port *ap)
-{
-        const char *emsg = NULL;
-        int rc;
-
-        /* de-initialize port */
-        rc = ahci_deinit_port(ap, &emsg);
-        if (rc)
-                ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
-}
-
 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 {
         int rc;
@@ -2806,31 +690,12 @@ static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
         return 0;
 }
 
-static void ahci_print_info(struct ata_host *host)
+static void ahci_pci_print_info(struct ata_host *host)
 {
-        struct ahci_host_priv *hpriv = host->private_data;
         struct pci_dev *pdev = to_pci_dev(host->dev);
-        void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-        u32 vers, cap, cap2, impl, speed;
-        const char *speed_s;
         u16 cc;
         const char *scc_s;
 
-        vers = readl(mmio + HOST_VERSION);
-        cap = hpriv->cap;
-        cap2 = hpriv->cap2;
-        impl = hpriv->port_map;
-
-        speed = (cap >> 20) & 0xf;
-        if (speed == 1)
-                speed_s = "1.5";
-        else if (speed == 2)
-                speed_s = "3";
-        else if (speed == 3)
-                speed_s = "6";
-        else
-                speed_s = "?";
-
         pci_read_config_word(pdev, 0x0a, &cc);
         if (cc == PCI_CLASS_STORAGE_IDE)
                 scc_s = "IDE";
@@ -2841,50 +706,7 @@ static void ahci_print_info(struct ata_host *host)
         else
                 scc_s = "unknown";
 
-        dev_printk(KERN_INFO, &pdev->dev,
-                "AHCI %02x%02x.%02x%02x "
-                "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
-                ,
-
-                (vers >> 24) & 0xff,
-                (vers >> 16) & 0xff,
-                (vers >> 8) & 0xff,
-                vers & 0xff,
-
-                ((cap >> 8) & 0x1f) + 1,
-                (cap & 0x1f) + 1,
-                speed_s,
-                impl,
-                scc_s);
-
-        dev_printk(KERN_INFO, &pdev->dev,
-                "flags: "
-                "%s%s%s%s%s%s%s"
-                "%s%s%s%s%s%s%s"
-                "%s%s%s%s%s%s\n"
-                ,
-
-                cap & HOST_CAP_64 ? "64bit " : "",
-                cap & HOST_CAP_NCQ ? "ncq " : "",
-                cap & HOST_CAP_SNTF ? "sntf " : "",
-                cap & HOST_CAP_MPS ? "ilck " : "",
-                cap & HOST_CAP_SSS ? "stag " : "",
-                cap & HOST_CAP_ALPM ? "pm " : "",
-                cap & HOST_CAP_LED ? "led " : "",
-                cap & HOST_CAP_CLO ? "clo " : "",
-                cap & HOST_CAP_ONLY ? "only " : "",
-                cap & HOST_CAP_PMP ? "pmp " : "",
-                cap & HOST_CAP_FBS ? "fbs " : "",
-                cap & HOST_CAP_PIO_MULTI ? "pio " : "",
-                cap & HOST_CAP_SSC ? "slum " : "",
-                cap & HOST_CAP_PART ? "part " : "",
-                cap & HOST_CAP_CCC ? "ccc " : "",
-                cap & HOST_CAP_EMS ? "ems " : "",
-                cap & HOST_CAP_SXS ? "sxs " : "",
-                cap2 & HOST_CAP2_APST ? "apst " : "",
-                cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
-                cap2 & HOST_CAP2_BOH ? "boh " : ""
-                );
+        ahci_print_info(host, scc_s);
 }
 
 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
@@ -3238,7 +1060,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         VPRINTK("ENTER\n");
 
-        WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
+        WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
 
         if (!printed_version++)
                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
@@ -3249,6 +1071,16 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
                 return -ENODEV;
 
+        /*
+         * For some reason, MCP89 on MacBook 7,1 doesn't work with
+         * ahci, use ata_generic instead.
+         */
+        if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
+            pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
+            pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
+            pdev->subsystem_device == 0xcb89)
+                return -ENODEV;
+
         /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
          * At the moment, we can only use the AHCI mode. Let the users know
          * that for SAS drives they're out of luck.
@@ -3308,41 +1140,28 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
                 pci_intx(pdev, 1);
 
+        hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
+
         /* save initial config */
-        ahci_save_initial_config(pdev, hpriv);
+        ahci_pci_save_initial_config(pdev, hpriv);
 
         /* prepare host */
         if (hpriv->cap & HOST_CAP_NCQ) {
                 pi.flags |= ATA_FLAG_NCQ;
-                /* Auto-activate optimization is supposed to be supported on
-                   all AHCI controllers indicating NCQ support, but it seems
-                   to be broken at least on some NVIDIA MCP79 chipsets.
-                   Until we get info on which NVIDIA chipsets don't have this
-                   issue, if any, disable AA on all NVIDIA AHCIs. */
-                if (pdev->vendor != PCI_VENDOR_ID_NVIDIA)
+                /*
+                 * Auto-activate optimization is supposed to be
+                 * supported on all AHCI controllers indicating NCQ
+                 * capability, but it seems to be broken on some
+                 * chipsets including NVIDIAs.
+                 */
+                if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
                         pi.flags |= ATA_FLAG_FPDMA_AA;
         }
 
         if (hpriv->cap & HOST_CAP_PMP)
                 pi.flags |= ATA_FLAG_PMP;
 
-        if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
-                u8 messages;
-                void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
-                u32 em_loc = readl(mmio + HOST_EM_LOC);
-                u32 em_ctl = readl(mmio + HOST_EM_CTL);
-
-                messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
-
-                /* we only support LED message type right now */
-                if ((messages & 0x01) && (ahci_em_messages == 1)) {
-                        /* store em_loc */
-                        hpriv->em_loc = ((em_loc >> 16) * 4);
-                        pi.flags |= ATA_FLAG_EM;
-                        if (!(em_ctl & EM_CTL_ALHD))
-                                pi.flags |= ATA_FLAG_SW_ACTIVITY;
-                }
-        }
+        ahci_set_em_messages(hpriv, &pi);
 
         if (ahci_broken_system_poweroff(pdev)) {
                 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
@@ -3372,7 +1191,6 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
         if (!host)
                 return -ENOMEM;
-        host->iomap = pcim_iomap_table(pdev);
         host->private_data = hpriv;
 
         if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
@@ -3395,7 +1213,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 
                 /* set enclosure management message type */
                 if (ap->flags & ATA_FLAG_EM)
-                        ap->em_message_type = ahci_em_messages;
+                        ap->em_message_type = hpriv->em_msg_type;
 
 
                 /* disabled/not-implemented port */
@@ -3414,12 +1232,12 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         if (rc)
                 return rc;
 
-        rc = ahci_reset_controller(host);
+        rc = ahci_pci_reset_controller(host);
         if (rc)
                 return rc;
 
-        ahci_init_controller(host);
-        ahci_print_info(host);
+        ahci_pci_init_controller(host);
+        ahci_pci_print_info(host);
 
         pci_set_master(pdev);
         return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
new file mode 100644
index 000000000000..e5fdeebf9ef0
--- /dev/null
+++ b/drivers/ata/ahci.h
@@ -0,0 +1,354 @@
+/*
+ *  ahci.h - Common AHCI SATA definitions and declarations
+ *
+ *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *                  Please ALWAYS copy linux-ide@vger.kernel.org
+ *                  on emails.
+ *
+ *  Copyright 2004-2005 Red Hat, Inc.
+ *
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * libata documentation is available via 'make {ps|pdf}docs',
+ * as Documentation/DocBook/libata.*
+ *
+ * AHCI hardware documentation:
+ * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
+ * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
+ *
+ */
+
+#ifndef _AHCI_H
+#define _AHCI_H
+
+#include <linux/libata.h>
+
+/* Enclosure Management Control */
+#define EM_CTRL_MSG_TYPE              0x000f0000
+
+/* Enclosure Management LED Message Type */
+#define EM_MSG_LED_HBA_PORT           0x0000000f
+#define EM_MSG_LED_PMP_SLOT           0x0000ff00
+#define EM_MSG_LED_VALUE              0xffff0000
+#define EM_MSG_LED_VALUE_ACTIVITY     0x00070000
+#define EM_MSG_LED_VALUE_OFF          0xfff80000
+#define EM_MSG_LED_VALUE_ON           0x00010000
+
+enum {
+        AHCI_MAX_PORTS          = 32,
+        AHCI_MAX_SG             = 168, /* hardware max is 64K */
+        AHCI_DMA_BOUNDARY       = 0xffffffff,
+        AHCI_MAX_CMDS           = 32,
+        AHCI_CMD_SZ             = 32,
+        AHCI_CMD_SLOT_SZ        = AHCI_MAX_CMDS * AHCI_CMD_SZ,
+        AHCI_RX_FIS_SZ          = 256,
+        AHCI_CMD_TBL_CDB        = 0x40,
+        AHCI_CMD_TBL_HDR_SZ     = 0x80,
+        AHCI_CMD_TBL_SZ         = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
+        AHCI_CMD_TBL_AR_SZ      = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
+        AHCI_PORT_PRIV_DMA_SZ   = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
+                                  AHCI_RX_FIS_SZ,
+        AHCI_PORT_PRIV_FBS_DMA_SZ       = AHCI_CMD_SLOT_SZ +
+                                          AHCI_CMD_TBL_AR_SZ +
+                                          (AHCI_RX_FIS_SZ * 16),
+        AHCI_IRQ_ON_SG          = (1 << 31),
+        AHCI_CMD_ATAPI          = (1 << 5),
+        AHCI_CMD_WRITE          = (1 << 6),
+        AHCI_CMD_PREFETCH       = (1 << 7),
+        AHCI_CMD_RESET          = (1 << 8),
+        AHCI_CMD_CLR_BUSY       = (1 << 10),
+
+        RX_FIS_D2H_REG          = 0x40, /* offset of D2H Register FIS data */
+        RX_FIS_SDB              = 0x58, /* offset of SDB FIS data */
+        RX_FIS_UNK              = 0x60, /* offset of Unknown FIS data */
+
+        /* global controller registers */
+        HOST_CAP                = 0x00, /* host capabilities */
+        HOST_CTL                = 0x04, /* global host control */
+        HOST_IRQ_STAT           = 0x08, /* interrupt status */
+        HOST_PORTS_IMPL         = 0x0c, /* bitmap of implemented ports */
+        HOST_VERSION            = 0x10, /* AHCI spec. version compliancy */
+        HOST_EM_LOC             = 0x1c, /* Enclosure Management location */
+        HOST_EM_CTL             = 0x20, /* Enclosure Management Control */
+        HOST_CAP2               = 0x24, /* host capabilities, extended */
+
+        /* HOST_CTL bits */
+        HOST_RESET              = (1 << 0),  /* reset controller; self-clear */
+        HOST_IRQ_EN             = (1 << 1),  /* global IRQ enable */
+        HOST_AHCI_EN            = (1 << 31), /* AHCI enabled */
+
+        /* HOST_CAP bits */
+        HOST_CAP_SXS            = (1 << 5),  /* Supports External SATA */
+        HOST_CAP_EMS            = (1 << 6),  /* Enclosure Management support */
+        HOST_CAP_CCC            = (1 << 7),  /* Command Completion Coalescing */
+        HOST_CAP_PART           = (1 << 13), /* Partial state capable */
+        HOST_CAP_SSC            = (1 << 14), /* Slumber state capable */
+        HOST_CAP_PIO_MULTI      = (1 << 15), /* PIO multiple DRQ support */
+        HOST_CAP_FBS            = (1 << 16), /* FIS-based switching support */
+        HOST_CAP_PMP            = (1 << 17), /* Port Multiplier support */
+        HOST_CAP_ONLY           = (1 << 18), /* Supports AHCI mode only */
+        HOST_CAP_CLO            = (1 << 24), /* Command List Override support */
+        HOST_CAP_LED            = (1 << 25), /* Supports activity LED */
+        HOST_CAP_ALPM           = (1 << 26), /* Aggressive Link PM support */
+        HOST_CAP_SSS            = (1 << 27), /* Staggered Spin-up */
+        HOST_CAP_MPS            = (1 << 28), /* Mechanical presence switch */
+        HOST_CAP_SNTF           = (1 << 29), /* SNotification register */
+        HOST_CAP_NCQ            = (1 << 30), /* Native Command Queueing */
+        HOST_CAP_64             = (1 << 31), /* PCI DAC (64-bit DMA) support */
+
+        /* HOST_CAP2 bits */
+        HOST_CAP2_BOH           = (1 << 0),  /* BIOS/OS handoff supported */
+        HOST_CAP2_NVMHCI        = (1 << 1),  /* NVMHCI supported */
+        HOST_CAP2_APST          = (1 << 2),  /* Automatic partial to slumber */
+
+        /* registers for each SATA port */
+        PORT_LST_ADDR           = 0x00, /* command list DMA addr */
+        PORT_LST_ADDR_HI        = 0x04, /* command list DMA addr hi */
+        PORT_FIS_ADDR           = 0x08, /* FIS rx buf addr */
+        PORT_FIS_ADDR_HI        = 0x0c, /* FIS rx buf addr hi */
+        PORT_IRQ_STAT           = 0x10, /* interrupt status */
+        PORT_IRQ_MASK           = 0x14, /* interrupt enable/disable mask */
+        PORT_CMD                = 0x18, /* port command */
+        PORT_TFDATA             = 0x20, /* taskfile data */
+        PORT_SIG                = 0x24, /* device TF signature */
+        PORT_CMD_ISSUE          = 0x38, /* command issue */
+        PORT_SCR_STAT           = 0x28, /* SATA phy register: SStatus */
+        PORT_SCR_CTL            = 0x2c, /* SATA phy register: SControl */
+        PORT_SCR_ERR            = 0x30, /* SATA phy register: SError */
+        PORT_SCR_ACT            = 0x34, /* SATA phy register: SActive */
+        PORT_SCR_NTF            = 0x3c, /* SATA phy register: SNotification */
+        PORT_FBS                = 0x40, /* FIS-based Switching */
+
+        /* PORT_IRQ_{STAT,MASK} bits */
+        PORT_IRQ_COLD_PRES      = (1 << 31), /* cold presence detect */
+        PORT_IRQ_TF_ERR         = (1 << 30), /* task file error */
+        PORT_IRQ_HBUS_ERR       = (1 << 29), /* host bus fatal error */
+        PORT_IRQ_HBUS_DATA_ERR  = (1 << 28), /* host bus data error */
+        PORT_IRQ_IF_ERR         = (1 << 27), /* interface fatal error */
+        PORT_IRQ_IF_NONFATAL    = (1 << 26), /* interface non-fatal error */
+        PORT_IRQ_OVERFLOW       = (1 << 24), /* xfer exhausted available S/G */
+        PORT_IRQ_BAD_PMP        = (1 << 23), /* incorrect port multiplier */
+
+        PORT_IRQ_PHYRDY         = (1 << 22), /* PhyRdy changed */
+        PORT_IRQ_DEV_ILCK       = (1 << 7), /* device interlock */
+        PORT_IRQ_CONNECT        = (1 << 6), /* port connect change status */
+        PORT_IRQ_SG_DONE        = (1 << 5), /* descriptor processed */
+        PORT_IRQ_UNK_FIS        = (1 << 4), /* unknown FIS rx'd */
+        PORT_IRQ_SDB_FIS        = (1 << 3), /* Set Device Bits FIS rx'd */
+        PORT_IRQ_DMAS_FIS       = (1 << 2), /* DMA Setup FIS rx'd */
+        PORT_IRQ_PIOS_FIS       = (1 << 1), /* PIO Setup FIS rx'd */
+        PORT_IRQ_D2H_REG_FIS    = (1 << 0), /* D2H Register FIS rx'd */
+
+        PORT_IRQ_FREEZE         = PORT_IRQ_HBUS_ERR |
+                                  PORT_IRQ_IF_ERR |
+                                  PORT_IRQ_CONNECT |
+                                  PORT_IRQ_PHYRDY |
+                                  PORT_IRQ_UNK_FIS |
+                                  PORT_IRQ_BAD_PMP,
+        PORT_IRQ_ERROR          = PORT_IRQ_FREEZE |
+                                  PORT_IRQ_TF_ERR |
+                                  PORT_IRQ_HBUS_DATA_ERR,
+        DEF_PORT_IRQ            = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
+                                  PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
+                                  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
+
+        /* PORT_CMD bits */
+        PORT_CMD_ASP            = (1 << 27), /* Aggressive Slumber/Partial */
+        PORT_CMD_ALPE           = (1 << 26), /* Aggressive Link PM enable */
+        PORT_CMD_ATAPI          = (1 << 24), /* Device is ATAPI */
+        PORT_CMD_FBSCP          = (1 << 22), /* FBS Capable Port */
+        PORT_CMD_PMP            = (1 << 17), /* PMP attached */
+        PORT_CMD_LIST_ON        = (1 << 15), /* cmd list DMA engine running */
+        PORT_CMD_FIS_ON         = (1 << 14), /* FIS DMA engine running */
+        PORT_CMD_FIS_RX         = (1 << 4), /* Enable FIS receive DMA engine */
+        PORT_CMD_CLO            = (1 << 3), /* Command list override */
+        PORT_CMD_POWER_ON       = (1 << 2), /* Power up device */
+        PORT_CMD_SPIN_UP        = (1 << 1), /* Spin up device */
+        PORT_CMD_START          = (1 << 0), /* Enable port DMA engine */
+
+        PORT_CMD_ICC_MASK       = (0xf << 28), /* i/f ICC state mask */
+        PORT_CMD_ICC_ACTIVE     = (0x1 << 28), /* Put i/f in active state */
+        PORT_CMD_ICC_PARTIAL    = (0x2 << 28), /* Put i/f in partial state */
+        PORT_CMD_ICC_SLUMBER    = (0x6 << 28), /* Put i/f in slumber state */
+
+        PORT_FBS_DWE_OFFSET     = 16, /* FBS device with error offset */
+        PORT_FBS_ADO_OFFSET     = 12, /* FBS active dev optimization offset */
+        PORT_FBS_DEV_OFFSET     = 8,  /* FBS device to issue offset */
+        PORT_FBS_DEV_MASK       = (0xf << PORT_FBS_DEV_OFFSET),  /* FBS.DEV */
+        PORT_FBS_SDE            = (1 << 2), /* FBS single device error */
+        PORT_FBS_DEC            = (1 << 1), /* FBS device error clear */
+        PORT_FBS_EN             = (1 << 0), /* Enable FBS */
+
+        /* hpriv->flags bits */
+        AHCI_HFLAG_NO_NCQ               = (1 << 0),
+        AHCI_HFLAG_IGN_IRQ_IF_ERR       = (1 << 1), /* ignore IRQ_IF_ERR */
+        AHCI_HFLAG_IGN_SERR_INTERNAL    = (1 << 2), /* ignore SERR_INTERNAL */
+        AHCI_HFLAG_32BIT_ONLY           = (1 << 3), /* force 32bit */
+        AHCI_HFLAG_MV_PATA              = (1 << 4), /* PATA port */
+        AHCI_HFLAG_NO_MSI               = (1 << 5), /* no PCI MSI */
+        AHCI_HFLAG_NO_PMP               = (1 << 6), /* no PMP */
+        AHCI_HFLAG_NO_HOTPLUG           = (1 << 7), /* ignore PxSERR.DIAG.N */
+        AHCI_HFLAG_SECT255              = (1 << 8), /* max 255 sectors */
+        AHCI_HFLAG_YES_NCQ              = (1 << 9), /* force NCQ cap on */
+        AHCI_HFLAG_NO_SUSPEND           = (1 << 10), /* don't suspend */
+        AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
+                                                        link offline */
+        AHCI_HFLAG_NO_SNTF              = (1 << 12), /* no sntf */
+        AHCI_HFLAG_NO_FPDMA_AA          = (1 << 13), /* no FPDMA AA */
+        AHCI_HFLAG_YES_FBS              = (1 << 14), /* force FBS cap on */
+
+        /* ap->flags bits */
+
+        AHCI_FLAG_COMMON                = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
+                                          ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
+                                          ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
+                                          ATA_FLAG_IPM,
+
+        ICH_MAP                         = 0x90, /* ICH MAP register */
+
+        /* em constants */
+        EM_MAX_SLOTS                    = 8,
+        EM_MAX_RETRY                    = 5,
+
+        /* em_ctl bits */
+        EM_CTL_RST              = (1 << 9), /* Reset */
+        EM_CTL_TM               = (1 << 8), /* Transmit Message */
+        EM_CTL_MR               = (1 << 0), /* Message Recieved */
+        EM_CTL_ALHD             = (1 << 26), /* Activity LED */
+        EM_CTL_XMT              = (1 << 25), /* Transmit Only */
+        EM_CTL_SMB              = (1 << 24), /* Single Message Buffer */
+
+        /* em message type */
+        EM_MSG_TYPE_LED         = (1 << 0), /* LED */
+        EM_MSG_TYPE_SAFTE       = (1 << 1), /* SAF-TE */
+        EM_MSG_TYPE_SES2        = (1 << 2), /* SES-2 */
+        EM_MSG_TYPE_SGPIO       = (1 << 3), /* SGPIO */
+};
+
+struct ahci_cmd_hdr {
+        __le32                  opts;
+        __le32                  status;
+        __le32                  tbl_addr;
+        __le32                  tbl_addr_hi;
+        __le32                  reserved[4];
+};
+
+struct ahci_sg {
+        __le32                  addr;
+        __le32                  addr_hi;
+        __le32                  reserved;
+        __le32                  flags_size;
+};
+
+struct ahci_em_priv {
+        enum sw_activity blink_policy;
+        struct timer_list timer;
+        unsigned long saved_activity;
+        unsigned long activity;
+        unsigned long led_state;
+};
+
+struct ahci_port_priv {
+        struct ata_link         *active_link;
+        struct ahci_cmd_hdr     *cmd_slot;
+        dma_addr_t              cmd_slot_dma;
+        void                    *cmd_tbl;
+        dma_addr_t              cmd_tbl_dma;
+        void                    *rx_fis;
+        dma_addr_t              rx_fis_dma;
+        /* for NCQ spurious interrupt analysis */
+        unsigned int            ncq_saw_d2h:1;
+        unsigned int            ncq_saw_dmas:1;
+        unsigned int            ncq_saw_sdb:1;
+        u32                     intr_mask;      /* interrupts to enable */
+        bool                    fbs_supported;  /* set iff FBS is supported */
+        bool                    fbs_enabled;    /* set iff FBS is enabled */
+        int                     fbs_last_dev;   /* save FBS.DEV of last FIS */
+        /* enclosure management info per PM slot */
+        struct ahci_em_priv     em_priv[EM_MAX_SLOTS];
+};
+
+struct ahci_host_priv {
+        void __iomem *          mmio;           /* bus-independant mem map */
+        unsigned int            flags;          /* AHCI_HFLAG_* */
+        u32                     cap;            /* cap to use */
+        u32                     cap2;           /* cap2 to use */
+        u32                     port_map;       /* port map to use */
+        u32                     saved_cap;      /* saved initial cap */
+        u32                     saved_cap2;     /* saved initial cap2 */
+        u32                     saved_port_map; /* saved initial port_map */
+        u32                     em_loc; /* enclosure management location */
+        u32                     em_buf_sz;      /* EM buffer size in byte */
+        u32                     em_msg_type;    /* EM message type */
+};
+
+extern int ahci_ignore_sss;
+
+extern struct device_attribute *ahci_shost_attrs[];
+extern struct device_attribute *ahci_sdev_attrs[];
+
+#define AHCI_SHT(drv_name)                                              \
+        ATA_NCQ_SHT(drv_name),                                          \
+        .can_queue              = AHCI_MAX_CMDS - 1,                    \
+        .sg_tablesize           = AHCI_MAX_SG,                          \
+        .dma_boundary           = AHCI_DMA_BOUNDARY,                    \
+        .shost_attrs            = ahci_shost_attrs,                     \
+        .sdev_attrs             = ahci_sdev_attrs
+
+extern struct ata_port_operations ahci_ops;
+
+void ahci_save_initial_config(struct device *dev,
+                              struct ahci_host_priv *hpriv,
+                              unsigned int force_port_map,
+                              unsigned int mask_port_map);
+void ahci_init_controller(struct ata_host *host);
+int ahci_reset_controller(struct ata_host *host);
+
+int ahci_do_softreset(struct ata_link *link, unsigned int *class,
+                      int pmp, unsigned long deadline,
+                      int (*check_ready)(struct ata_link *link));
+
+int ahci_stop_engine(struct ata_port *ap);
+void ahci_start_engine(struct ata_port *ap);
+int ahci_check_ready(struct ata_link *link);
+int ahci_kick_engine(struct ata_port *ap);
+void ahci_set_em_messages(struct ahci_host_priv *hpriv,
+                          struct ata_port_info *pi);
+int ahci_reset_em(struct ata_host *host);
+irqreturn_t ahci_interrupt(int irq, void *dev_instance);
+void ahci_print_info(struct ata_host *host, const char *scc_s);
+
+static inline void __iomem *__ahci_port_base(struct ata_host *host,
+                                             unsigned int port_no)
+{
+        struct ahci_host_priv *hpriv = host->private_data;
+        void __iomem *mmio = hpriv->mmio;
+
+        return mmio + 0x100 + (port_no * 0x80);
+}
+
+static inline void __iomem *ahci_port_base(struct ata_port *ap)
+{
+        return __ahci_port_base(ap->host, ap->port_no);
+}
+
+static inline int ahci_nr_ports(u32 cap)
+{
+        return (cap & 0x1f) + 1;
+}
+
+#endif /* _AHCI_H */
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
new file mode 100644
index 000000000000..84b643270e7a
--- /dev/null
+++ b/drivers/ata/ahci_platform.c
@@ -0,0 +1,200 @@
+/*
+ * AHCI SATA platform driver
+ *
+ * Copyright 2004-2005  Red Hat, Inc.
+ *   Jeff Garzik <jgarzik@pobox.com>
+ * Copyright 2010  MontaVista Software, LLC.
+ *   Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/gfp.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/libata.h>
+#include <linux/ahci_platform.h>
+#include "ahci.h"
+
+static struct scsi_host_template ahci_platform_sht = {
+        AHCI_SHT("ahci_platform"),
+};
+
+static int __init ahci_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct ahci_platform_data *pdata = dev->platform_data;
+        struct ata_port_info pi = {
+                .flags          = AHCI_FLAG_COMMON,
+                .pio_mask       = ATA_PIO4,
+                .udma_mask      = ATA_UDMA6,
+                .port_ops       = &ahci_ops,
+        };
+        const struct ata_port_info *ppi[] = { &pi, NULL };
+        struct ahci_host_priv *hpriv;
+        struct ata_host *host;
+        struct resource *mem;
+        int irq;
+        int n_ports;
+        int i;
+        int rc;
+
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!mem) {
+                dev_err(dev, "no mmio space\n");
+                return -EINVAL;
+        }
+
+        irq = platform_get_irq(pdev, 0);
+        if (irq <= 0) {
+                dev_err(dev, "no irq\n");
+                return -EINVAL;
+        }
+
+        if (pdata && pdata->ata_port_info)
+                pi = *pdata->ata_port_info;
+
+        hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
+        if (!hpriv) {
+                dev_err(dev, "can't alloc ahci_host_priv\n");
+                return -ENOMEM;
+        }
+
+        hpriv->flags |= (unsigned long)pi.private_data;
+
+        hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
+        if (!hpriv->mmio) {
+                dev_err(dev, "can't map %pR\n", mem);
+                return -ENOMEM;
+        }
+
+        /*
+         * Some platforms might need to prepare for mmio region access,
+         * which could be done in the following init call. So, the mmio
+         * region shouldn't be accessed before init (if provided) has
+         * returned successfully.
+         */
+        if (pdata && pdata->init) {
+                rc = pdata->init(dev, hpriv->mmio);
+                if (rc)
+                        return rc;
+        }
+
+        ahci_save_initial_config(dev, hpriv,
+                pdata ? pdata->force_port_map : 0,
+                pdata ? pdata->mask_port_map  : 0);
+
+        /* prepare host */
+        if (hpriv->cap & HOST_CAP_NCQ)
+                pi.flags |= ATA_FLAG_NCQ;
+
+        if (hpriv->cap & HOST_CAP_PMP)
+                pi.flags |= ATA_FLAG_PMP;
+
+        ahci_set_em_messages(hpriv, &pi);
+
+        /* CAP.NP sometimes indicate the index of the last enabled
+         * port, at other times, that of the last possible port, so
+         * determining the maximum port number requires looking at
+         * both CAP.NP and port_map.
+         */
+        n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
+
+        host = ata_host_alloc_pinfo(dev, ppi, n_ports);
+        if (!host) {
+                rc = -ENOMEM;
+                goto err0;
+        }
+
+        host->private_data = hpriv;
+
+        if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
+                host->flags |= ATA_HOST_PARALLEL_SCAN;
+        else
+                printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
+
+        if (pi.flags & ATA_FLAG_EM)
+                ahci_reset_em(host);
+
+        for (i = 0; i < host->n_ports; i++) {
+                struct ata_port *ap = host->ports[i];
+
+                ata_port_desc(ap, "mmio %pR", mem);
+                ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
+
+                /* set initial link pm policy */
+                ap->pm_policy = NOT_AVAILABLE;
+
+                /* set enclosure management message type */
+                if (ap->flags & ATA_FLAG_EM)
+                        ap->em_message_type = hpriv->em_msg_type;
+
+                /* disabled/not-implemented port */
+                if (!(hpriv->port_map & (1 << i)))
+                        ap->ops = &ata_dummy_port_ops;
+        }
+
+        rc = ahci_reset_controller(host);
+        if (rc)
+                goto err0;
+
+        ahci_init_controller(host);
+        ahci_print_info(host, "platform");
+
+        rc = ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED,
+                               &ahci_platform_sht);
+        if (rc)
+                goto err0;
+
+        return 0;
+err0:
+        if (pdata && pdata->exit)
+                pdata->exit(dev);
+        return rc;
+}
+
+static int __devexit ahci_remove(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct ahci_platform_data *pdata = dev->platform_data;
+        struct ata_host *host = dev_get_drvdata(dev);
+
+        ata_host_detach(host);
+
+        if (pdata && pdata->exit)
+                pdata->exit(dev);
+
+        return 0;
+}
+
+static struct platform_driver ahci_driver = {
+        .remove = __devexit_p(ahci_remove),
+        .driver = {
+                .name = "ahci",
+                .owner = THIS_MODULE,
+        },
+};
+
+static int __init ahci_init(void)
+{
+        return platform_driver_probe(&ahci_driver, ahci_probe);
+}
+module_init(ahci_init);
+
+static void __exit ahci_exit(void)
+{
+        platform_driver_unregister(&ahci_driver);
+}
+module_exit(ahci_exit);
+
+MODULE_DESCRIPTION("AHCI SATA platform driver");
+MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ahci");
diff --git a/drivers/ata/ata_generic.c b/drivers/ata/ata_generic.c
index 33fb614f9784..cc5f7726bde7 100644
--- a/drivers/ata/ata_generic.c
+++ b/drivers/ata/ata_generic.c
@@ -32,6 +32,11 @@
  *      A generic parallel ATA driver using libata
  */
 
+enum {
+        ATA_GEN_CLASS_MATCH             = (1 << 0),
+        ATA_GEN_FORCE_DMA               = (1 << 1),
+};
+
 /**
  *      generic_set_mode        -       mode setting
  *      @link: link to set up
@@ -46,16 +51,16 @@
 static int generic_set_mode(struct ata_link *link, struct ata_device **unused)
 {
         struct ata_port *ap = link->ap;
+        const struct pci_device_id *id = ap->host->private_data;
         int dma_enabled = 0;
         struct ata_device *dev;
-        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 
-        /* Bits 5 and 6 indicate if DMA is active on master/slave */
-        if (ap->ioaddr.bmdma_addr)
+        if (id->driver_data & ATA_GEN_FORCE_DMA) {
+                dma_enabled = 0xff;
+        } else if (ap->ioaddr.bmdma_addr) {
+                /* Bits 5 and 6 indicate if DMA is active on master/slave */
                 dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
-
-        if (pdev->vendor == PCI_VENDOR_ID_CENATEK)
-                dma_enabled = 0xFF;
+        }
 
         ata_for_each_dev(dev, link, ENABLED) {
                 /* We don't really care */
@@ -126,7 +131,7 @@ static int ata_generic_init_one(struct pci_dev *dev, const struct pci_device_id
         const struct ata_port_info *ppi[] = { &info, NULL };
 
         /* Don't use the generic entry unless instructed to do so */
-        if (id->driver_data == 1 && all_generic_ide == 0)
+        if ((id->driver_data & ATA_GEN_CLASS_MATCH) && all_generic_ide == 0)
                 return -ENODEV;
 
         /* Devices that need care */
@@ -155,7 +160,7 @@ static int ata_generic_init_one(struct pci_dev *dev, const struct pci_device_id
                         return rc;
                 pcim_pin_device(dev);
         }
-        return ata_pci_sff_init_one(dev, ppi, &generic_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(dev, ppi, &generic_sht, (void *)id, 0);
 }
 
 static struct pci_device_id ata_generic[] = {
@@ -167,7 +172,15 @@ static struct pci_device_id ata_generic[] = {
         { PCI_DEVICE(PCI_VENDOR_ID_HINT,   PCI_DEVICE_ID_HINT_VXPROII_IDE), },
         { PCI_DEVICE(PCI_VENDOR_ID_VIA,    PCI_DEVICE_ID_VIA_82C561), },
         { PCI_DEVICE(PCI_VENDOR_ID_OPTI,   PCI_DEVICE_ID_OPTI_82C558), },
-        { PCI_DEVICE(PCI_VENDOR_ID_CENATEK,PCI_DEVICE_ID_CENATEK_IDE), },
+        { PCI_DEVICE(PCI_VENDOR_ID_CENATEK,PCI_DEVICE_ID_CENATEK_IDE),
+          .driver_data = ATA_GEN_FORCE_DMA },
+        /*
+         * For some reason, MCP89 on MacBook 7,1 doesn't work with
+         * ahci, use ata_generic instead.
+         */
+        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA,
+          PCI_VENDOR_ID_APPLE, 0xcb89,
+          .driver_data = ATA_GEN_FORCE_DMA },
 #if !defined(CONFIG_PATA_TOSHIBA) && !defined(CONFIG_PATA_TOSHIBA_MODULE)
         { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), },
         { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2),  },
@@ -175,7 +188,8 @@ static struct pci_device_id ata_generic[] = {
         { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_5),  },
 #endif  
         /* Must come last. If you add entries adjust this table appropriately */
-        { PCI_ANY_ID,           PCI_ANY_ID,                        PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL, 1},
+        { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL),
+          .driver_data = ATA_GEN_CLASS_MATCH },
         { 0, },
 };
 
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index 83bc49fac9bb..d712675d0a96 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -43,7 +43,7 @@
  * driver the list of errata that are relevant is below, going back to
  * PIIX4. Older device documentation is now a bit tricky to find.
  *
- * The chipsets all follow very much the same design. The orginal Triton
+ * The chipsets all follow very much the same design. The original Triton
  * series chipsets do _not_ support independant device timings, but this
  * is fixed in Triton II. With the odd mobile exception the chips then
  * change little except in gaining more modes until SATA arrives. This
@@ -158,6 +158,7 @@ struct piix_map_db {
 struct piix_host_priv {
         const int *map;
         u32 saved_iocfg;
+        spinlock_t sidpr_lock;  /* FIXME: remove once locking in EH is fixed */
         void __iomem *sidpr;
 };
 
@@ -301,6 +302,10 @@ static const struct pci_device_id piix_pci_tbl[] = {
         { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
         /* SATA Controller IDE (CPT) */
         { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
+        /* SATA Controller IDE (PBG) */
+        { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
+        /* SATA Controller IDE (PBG) */
+        { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
         { }     /* terminate list */
 };
 
@@ -951,12 +956,15 @@ static int piix_sidpr_scr_read(struct ata_link *link,
                                unsigned int reg, u32 *val)
 {
         struct piix_host_priv *hpriv = link->ap->host->private_data;
+        unsigned long flags;
 
         if (reg >= ARRAY_SIZE(piix_sidx_map))
                 return -EINVAL;
 
+        spin_lock_irqsave(&hpriv->sidpr_lock, flags);
         piix_sidpr_sel(link, reg);
         *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
+        spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
         return 0;
 }
 
@@ -964,12 +972,15 @@ static int piix_sidpr_scr_write(struct ata_link *link,
                                 unsigned int reg, u32 val)
 {
         struct piix_host_priv *hpriv = link->ap->host->private_data;
+        unsigned long flags;
 
         if (reg >= ARRAY_SIZE(piix_sidx_map))
                 return -EINVAL;
 
+        spin_lock_irqsave(&hpriv->sidpr_lock, flags);
         piix_sidpr_sel(link, reg);
         iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
+        spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
         return 0;
 }
 
@@ -1566,6 +1577,7 @@ static int __devinit piix_init_one(struct pci_dev *pdev,
         hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
         if (!hpriv)
                 return -ENOMEM;
+        spin_lock_init(&hpriv->sidpr_lock);
 
         /* Save IOCFG, this will be used for cable detection, quirk
          * detection and restoration on detach.  This is necessary
@@ -1589,7 +1601,7 @@ static int __devinit piix_init_one(struct pci_dev *pdev,
                 hpriv->map = piix_init_sata_map(pdev, port_info,
                                         piix_map_db_table[ent->driver_data]);
 
-        rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
+        rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
         if (rc)
                 return rc;
         host->private_data = hpriv;
@@ -1626,7 +1638,7 @@ static int __devinit piix_init_one(struct pci_dev *pdev,
         host->flags |= ATA_HOST_PARALLEL_SCAN;
 
         pci_set_master(pdev);
-        return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht);
+        return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &piix_sht);
 }
 
 static void piix_remove_one(struct pci_dev *pdev)
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
new file mode 100644
index 000000000000..8eea309ea212
--- /dev/null
+++ b/drivers/ata/libahci.c
@@ -0,0 +1,2206 @@
+/*
+ *  libahci.c - Common AHCI SATA low-level routines
+ *
+ *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *                  Please ALWAYS copy linux-ide@vger.kernel.org
+ *                  on emails.
+ *
+ *  Copyright 2004-2005 Red Hat, Inc.
+ *
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * libata documentation is available via 'make {ps|pdf}docs',
+ * as Documentation/DocBook/libata.*
+ *
+ * AHCI hardware documentation:
+ * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
+ * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/gfp.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <scsi/scsi_host.h>
+#include <scsi/scsi_cmnd.h>
+#include <linux/libata.h>
+#include "ahci.h"
+
+static int ahci_skip_host_reset;
+int ahci_ignore_sss;
+EXPORT_SYMBOL_GPL(ahci_ignore_sss);
+
+module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
+MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
+
+module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
+MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
+
+static int ahci_enable_alpm(struct ata_port *ap,
+                enum link_pm policy);
+static void ahci_disable_alpm(struct ata_port *ap);
+static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
+static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
+                              size_t size);
+static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
+                                        ssize_t size);
+
+
+
+static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
+static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
+static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
+static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
+static int ahci_port_start(struct ata_port *ap);
+static void ahci_port_stop(struct ata_port *ap);
+static void ahci_qc_prep(struct ata_queued_cmd *qc);
+static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
+static void ahci_freeze(struct ata_port *ap);
+static void ahci_thaw(struct ata_port *ap);
+static void ahci_enable_fbs(struct ata_port *ap);
+static void ahci_disable_fbs(struct ata_port *ap);
+static void ahci_pmp_attach(struct ata_port *ap);
+static void ahci_pmp_detach(struct ata_port *ap);
+static int ahci_softreset(struct ata_link *link, unsigned int *class,
+                          unsigned long deadline);
+static int ahci_hardreset(struct ata_link *link, unsigned int *class,
+                          unsigned long deadline);
+static void ahci_postreset(struct ata_link *link, unsigned int *class);
+static void ahci_error_handler(struct ata_port *ap);
+static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
+static int ahci_port_resume(struct ata_port *ap);
+static void ahci_dev_config(struct ata_device *dev);
+static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
+                               u32 opts);
+#ifdef CONFIG_PM
+static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
+#endif
+static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
+static ssize_t ahci_activity_store(struct ata_device *dev,
+                                   enum sw_activity val);
+static void ahci_init_sw_activity(struct ata_link *link);
+
+static ssize_t ahci_show_host_caps(struct device *dev,
+                                   struct device_attribute *attr, char *buf);
+static ssize_t ahci_show_host_cap2(struct device *dev,
+                                   struct device_attribute *attr, char *buf);
+static ssize_t ahci_show_host_version(struct device *dev,
+                                      struct device_attribute *attr, char *buf);
+static ssize_t ahci_show_port_cmd(struct device *dev,
+                                  struct device_attribute *attr, char *buf);
+static ssize_t ahci_read_em_buffer(struct device *dev,
+                                   struct device_attribute *attr, char *buf);
+static ssize_t ahci_store_em_buffer(struct device *dev,
+                                    struct device_attribute *attr,
+                                    const char *buf, size_t size);
+
+static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
+static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
+static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
+static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
+static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
+                   ahci_read_em_buffer, ahci_store_em_buffer);
+
+struct device_attribute *ahci_shost_attrs[] = {
+        &dev_attr_link_power_management_policy,
+        &dev_attr_em_message_type,
+        &dev_attr_em_message,
+        &dev_attr_ahci_host_caps,
+        &dev_attr_ahci_host_cap2,
+        &dev_attr_ahci_host_version,
+        &dev_attr_ahci_port_cmd,
+        &dev_attr_em_buffer,
+        NULL
+};
+EXPORT_SYMBOL_GPL(ahci_shost_attrs);
+
+struct device_attribute *ahci_sdev_attrs[] = {
+        &dev_attr_sw_activity,
+        &dev_attr_unload_heads,
+        NULL
+};
+EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
+
+struct ata_port_operations ahci_ops = {
+        .inherits               = &sata_pmp_port_ops,
+
+        .qc_defer               = ahci_pmp_qc_defer,
+        .qc_prep                = ahci_qc_prep,
+        .qc_issue               = ahci_qc_issue,
+        .qc_fill_rtf            = ahci_qc_fill_rtf,
+
+        .freeze                 = ahci_freeze,
+        .thaw                   = ahci_thaw,
+        .softreset              = ahci_softreset,
+        .hardreset              = ahci_hardreset,
+        .postreset              = ahci_postreset,
+        .pmp_softreset          = ahci_softreset,
+        .error_handler          = ahci_error_handler,
+        .post_internal_cmd      = ahci_post_internal_cmd,
+        .dev_config             = ahci_dev_config,
+
+        .scr_read               = ahci_scr_read,
+        .scr_write              = ahci_scr_write,
+        .pmp_attach             = ahci_pmp_attach,
+        .pmp_detach             = ahci_pmp_detach,
+
+        .enable_pm              = ahci_enable_alpm,
+        .disable_pm             = ahci_disable_alpm,
+        .em_show                = ahci_led_show,
+        .em_store               = ahci_led_store,
+        .sw_activity_show       = ahci_activity_show,
+        .sw_activity_store      = ahci_activity_store,
+#ifdef CONFIG_PM
+        .port_suspend           = ahci_port_suspend,
+        .port_resume            = ahci_port_resume,
+#endif
+        .port_start             = ahci_port_start,
+        .port_stop              = ahci_port_stop,
+};
+EXPORT_SYMBOL_GPL(ahci_ops);
+
+int ahci_em_messages = 1;
+EXPORT_SYMBOL_GPL(ahci_em_messages);
+module_param(ahci_em_messages, int, 0444);
+/* add other LED protocol types when they become supported */
+MODULE_PARM_DESC(ahci_em_messages,
+        "AHCI Enclosure Management Message control (0 = off, 1 = on)");
+
+static void ahci_enable_ahci(void __iomem *mmio)
+{
+        int i;
+        u32 tmp;
+
+        /* turn on AHCI_EN */
+        tmp = readl(mmio + HOST_CTL);
+        if (tmp & HOST_AHCI_EN)
+                return;
+
+        /* Some controllers need AHCI_EN to be written multiple times.
+         * Try a few times before giving up.
+         */
+        for (i = 0; i < 5; i++) {
+                tmp |= HOST_AHCI_EN;
+                writel(tmp, mmio + HOST_CTL);
+                tmp = readl(mmio + HOST_CTL);   /* flush && sanity check */
+                if (tmp & HOST_AHCI_EN)
+                        return;
+                msleep(10);
+        }
+
+        WARN_ON(1);
+}
+
+static ssize_t ahci_show_host_caps(struct device *dev,
+                                   struct device_attribute *attr, char *buf)
+{
+        struct Scsi_Host *shost = class_to_shost(dev);
+        struct ata_port *ap = ata_shost_to_port(shost);
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+
+        return sprintf(buf, "%x\n", hpriv->cap);
+}
+
+static ssize_t ahci_show_host_cap2(struct device *dev,
+                                   struct device_attribute *attr, char *buf)
+{
+        struct Scsi_Host *shost = class_to_shost(dev);
+        struct ata_port *ap = ata_shost_to_port(shost);
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+
+        return sprintf(buf, "%x\n", hpriv->cap2);
+}
+
+static ssize_t ahci_show_host_version(struct device *dev,
+                                   struct device_attribute *attr, char *buf)
+{
+        struct Scsi_Host *shost = class_to_shost(dev);
+        struct ata_port *ap = ata_shost_to_port(shost);
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        void __iomem *mmio = hpriv->mmio;
+
+        return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
+}
+
+static ssize_t ahci_show_port_cmd(struct device *dev,
+                                  struct device_attribute *attr, char *buf)
+{
+        struct Scsi_Host *shost = class_to_shost(dev);
+        struct ata_port *ap = ata_shost_to_port(shost);
+        void __iomem *port_mmio = ahci_port_base(ap);
+
+        return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
+}
+
+static ssize_t ahci_read_em_buffer(struct device *dev,
+                                   struct device_attribute *attr, char *buf)
+{
+        struct Scsi_Host *shost = class_to_shost(dev);
+        struct ata_port *ap = ata_shost_to_port(shost);
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        void __iomem *mmio = hpriv->mmio;
+        void __iomem *em_mmio = mmio + hpriv->em_loc;
+        u32 em_ctl, msg;
+        unsigned long flags;
+        size_t count;
+        int i;
+
+        spin_lock_irqsave(ap->lock, flags);
+
+        em_ctl = readl(mmio + HOST_EM_CTL);
+        if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
+            !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
+                spin_unlock_irqrestore(ap->lock, flags);
+                return -EINVAL;
+        }
+
+        if (!(em_ctl & EM_CTL_MR)) {
+                spin_unlock_irqrestore(ap->lock, flags);
+                return -EAGAIN;
+        }
+
+        if (!(em_ctl & EM_CTL_SMB))
+                em_mmio += hpriv->em_buf_sz;
+
+        count = hpriv->em_buf_sz;
+
+        /* the count should not be larger than PAGE_SIZE */
+        if (count > PAGE_SIZE) {
+                if (printk_ratelimit())
+                        ata_port_printk(ap, KERN_WARNING,
+                                        "EM read buffer size too large: "
+                                        "buffer size %u, page size %lu\n",
+                                        hpriv->em_buf_sz, PAGE_SIZE);
+                count = PAGE_SIZE;
+        }
+
+        for (i = 0; i < count; i += 4) {
+                msg = readl(em_mmio + i);
+                buf[i] = msg & 0xff;
+                buf[i + 1] = (msg >> 8) & 0xff;
+                buf[i + 2] = (msg >> 16) & 0xff;
+                buf[i + 3] = (msg >> 24) & 0xff;
+        }
+
+        spin_unlock_irqrestore(ap->lock, flags);
+
+        return i;
+}
+
+static ssize_t ahci_store_em_buffer(struct device *dev,
+                                    struct device_attribute *attr,
+                                    const char *buf, size_t size)
+{
+        struct Scsi_Host *shost = class_to_shost(dev);
+        struct ata_port *ap = ata_shost_to_port(shost);
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        void __iomem *mmio = hpriv->mmio;
+        void __iomem *em_mmio = mmio + hpriv->em_loc;
+        const unsigned char *msg_buf = buf;
+        u32 em_ctl, msg;
+        unsigned long flags;
+        int i;
+
+        /* check size validity */
+        if (!(ap->flags & ATA_FLAG_EM) ||
+            !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
+            size % 4 || size > hpriv->em_buf_sz)
+                return -EINVAL;
+
+        spin_lock_irqsave(ap->lock, flags);
+
+        em_ctl = readl(mmio + HOST_EM_CTL);
+        if (em_ctl & EM_CTL_TM) {
+                spin_unlock_irqrestore(ap->lock, flags);
+                return -EBUSY;
+        }
+
+        for (i = 0; i < size; i += 4) {
+                msg = msg_buf[i] | msg_buf[i + 1] << 8 |
+                      msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
+                writel(msg, em_mmio + i);
+        }
+
+        writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
+
+        spin_unlock_irqrestore(ap->lock, flags);
+
+        return size;
+}
+
+/**
+ *      ahci_save_initial_config - Save and fixup initial config values
+ *      @dev: target AHCI device
+ *      @hpriv: host private area to store config values
+ *      @force_port_map: force port map to a specified value
+ *      @mask_port_map: mask out particular bits from port map
+ *
+ *      Some registers containing configuration info might be setup by
+ *      BIOS and might be cleared on reset.  This function saves the
+ *      initial values of those registers into @hpriv such that they
+ *      can be restored after controller reset.
+ *
+ *      If inconsistent, config values are fixed up by this function.
+ *
+ *      LOCKING:
+ *      None.
+ */
+void ahci_save_initial_config(struct device *dev,
+                              struct ahci_host_priv *hpriv,
+                              unsigned int force_port_map,
+                              unsigned int mask_port_map)
+{
+        void __iomem *mmio = hpriv->mmio;
+        u32 cap, cap2, vers, port_map;
+        int i;
+
+        /* make sure AHCI mode is enabled before accessing CAP */
+        ahci_enable_ahci(mmio);
+
+        /* Values prefixed with saved_ are written back to host after
+         * reset.  Values without are used for driver operation.
+         */
+        hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
+        hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
+
+        /* CAP2 register is only defined for AHCI 1.2 and later */
+        vers = readl(mmio + HOST_VERSION);
+        if ((vers >> 16) > 1 ||
+           ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
+                hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
+        else
+                hpriv->saved_cap2 = cap2 = 0;
+
+        /* some chips have errata preventing 64bit use */
+        if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
+                dev_printk(KERN_INFO, dev,
+                           "controller can't do 64bit DMA, forcing 32bit\n");
+                cap &= ~HOST_CAP_64;
+        }
+
+        if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
+                dev_printk(KERN_INFO, dev,
+                           "controller can't do NCQ, turning off CAP_NCQ\n");
+                cap &= ~HOST_CAP_NCQ;
+        }
+
+        if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
+                dev_printk(KERN_INFO, dev,
+                           "controller can do NCQ, turning on CAP_NCQ\n");
+                cap |= HOST_CAP_NCQ;
+        }
+
+        if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
+                dev_printk(KERN_INFO, dev,
+                           "controller can't do PMP, turning off CAP_PMP\n");
+                cap &= ~HOST_CAP_PMP;
+        }
+
+        if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
+                dev_printk(KERN_INFO, dev,
+                           "controller can't do SNTF, turning off CAP_SNTF\n");
+                cap &= ~HOST_CAP_SNTF;
+        }
+
+        if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
+                dev_printk(KERN_INFO, dev,
+                           "controller can do FBS, turning on CAP_FBS\n");
+                cap |= HOST_CAP_FBS;
+        }
+
+        if (force_port_map && port_map != force_port_map) {
+                dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
+                           port_map, force_port_map);
+                port_map = force_port_map;
+        }
+
+        if (mask_port_map) {
+                dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
+                           port_map,
+                           port_map & mask_port_map);
+                port_map &= mask_port_map;
+        }
+
+        /* cross check port_map and cap.n_ports */
+        if (port_map) {
+                int map_ports = 0;
+
+                for (i = 0; i < AHCI_MAX_PORTS; i++)
+                        if (port_map & (1 << i))
+                                map_ports++;
+
+                /* If PI has more ports than n_ports, whine, clear
+                 * port_map and let it be generated from n_ports.
+                 */
+                if (map_ports > ahci_nr_ports(cap)) {
+                        dev_printk(KERN_WARNING, dev,
+                                   "implemented port map (0x%x) contains more "
+                                   "ports than nr_ports (%u), using nr_ports\n",
+                                   port_map, ahci_nr_ports(cap));
+                        port_map = 0;
+                }
+        }
+
+        /* fabricate port_map from cap.nr_ports */
+        if (!port_map) {
+                port_map = (1 << ahci_nr_ports(cap)) - 1;
+                dev_printk(KERN_WARNING, dev,
+                           "forcing PORTS_IMPL to 0x%x\n", port_map);
+
+                /* write the fixed up value to the PI register */
+                hpriv->saved_port_map = port_map;
+        }
+
+        /* record values to use during operation */
+        hpriv->cap = cap;
+        hpriv->cap2 = cap2;
+        hpriv->port_map = port_map;
+}
+EXPORT_SYMBOL_GPL(ahci_save_initial_config);
+
+/**
+ *      ahci_restore_initial_config - Restore initial config
+ *      @host: target ATA host
+ *
+ *      Restore initial config stored by ahci_save_initial_config().
+ *
+ *      LOCKING:
+ *      None.
+ */
+static void ahci_restore_initial_config(struct ata_host *host)
+{
+        struct ahci_host_priv *hpriv = host->private_data;
+        void __iomem *mmio = hpriv->mmio;
+
+        writel(hpriv->saved_cap, mmio + HOST_CAP);
+        if (hpriv->saved_cap2)
+                writel(hpriv->saved_cap2, mmio + HOST_CAP2);
+        writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
+        (void) readl(mmio + HOST_PORTS_IMPL);   /* flush */
+}
+
+static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
+{
+        static const int offset[] = {
+                [SCR_STATUS]            = PORT_SCR_STAT,
+                [SCR_CONTROL]           = PORT_SCR_CTL,
+                [SCR_ERROR]             = PORT_SCR_ERR,
+                [SCR_ACTIVE]            = PORT_SCR_ACT,
+                [SCR_NOTIFICATION]      = PORT_SCR_NTF,
+        };
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+
+        if (sc_reg < ARRAY_SIZE(offset) &&
+            (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
+                return offset[sc_reg];
+        return 0;
+}
+
+static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
+{
+        void __iomem *port_mmio = ahci_port_base(link->ap);
+        int offset = ahci_scr_offset(link->ap, sc_reg);
+
+        if (offset) {
+                *val = readl(port_mmio + offset);
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
+{
+        void __iomem *port_mmio = ahci_port_base(link->ap);
+        int offset = ahci_scr_offset(link->ap, sc_reg);
+
+        if (offset) {
+                writel(val, port_mmio + offset);
+                return 0;
+        }
+        return -EINVAL;
+}
+
+void ahci_start_engine(struct ata_port *ap)
+{
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 tmp;
+
+        /* start DMA */
+        tmp = readl(port_mmio + PORT_CMD);
+        tmp |= PORT_CMD_START;
+        writel(tmp, port_mmio + PORT_CMD);
+        readl(port_mmio + PORT_CMD); /* flush */
+}
+EXPORT_SYMBOL_GPL(ahci_start_engine);
+
+int ahci_stop_engine(struct ata_port *ap)
+{
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 tmp;
+
+        tmp = readl(port_mmio + PORT_CMD);
+
+        /* check if the HBA is idle */
+        if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
+                return 0;
+
+        /* setting HBA to idle */
+        tmp &= ~PORT_CMD_START;
+        writel(tmp, port_mmio + PORT_CMD);
+
+        /* wait for engine to stop. This could be as long as 500 msec */
+        tmp = ata_wait_register(port_mmio + PORT_CMD,
+                                PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
+        if (tmp & PORT_CMD_LIST_ON)
+                return -EIO;
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(ahci_stop_engine);
+
+static void ahci_start_fis_rx(struct ata_port *ap)
+{
+        void __iomem *port_mmio = ahci_port_base(ap);
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        struct ahci_port_priv *pp = ap->private_data;
+        u32 tmp;
+
+        /* set FIS registers */
+        if (hpriv->cap & HOST_CAP_64)
+                writel((pp->cmd_slot_dma >> 16) >> 16,
+                       port_mmio + PORT_LST_ADDR_HI);
+        writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
+
+        if (hpriv->cap & HOST_CAP_64)
+                writel((pp->rx_fis_dma >> 16) >> 16,
+                       port_mmio + PORT_FIS_ADDR_HI);
+        writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
+
+        /* enable FIS reception */
+        tmp = readl(port_mmio + PORT_CMD);
+        tmp |= PORT_CMD_FIS_RX;
+        writel(tmp, port_mmio + PORT_CMD);
+
+        /* flush */
+        readl(port_mmio + PORT_CMD);
+}
+
+static int ahci_stop_fis_rx(struct ata_port *ap)
+{
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 tmp;
+
+        /* disable FIS reception */
+        tmp = readl(port_mmio + PORT_CMD);
+        tmp &= ~PORT_CMD_FIS_RX;
+        writel(tmp, port_mmio + PORT_CMD);
+
+        /* wait for completion, spec says 500ms, give it 1000 */
+        tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
+                                PORT_CMD_FIS_ON, 10, 1000);
+        if (tmp & PORT_CMD_FIS_ON)
+                return -EBUSY;
+
+        return 0;
+}
+
+static void ahci_power_up(struct ata_port *ap)
+{
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 cmd;
+
+        cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
+
+        /* spin up device */
+        if (hpriv->cap & HOST_CAP_SSS) {
+                cmd |= PORT_CMD_SPIN_UP;
+                writel(cmd, port_mmio + PORT_CMD);
+        }
+
+        /* wake up link */
+        writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
+}
+
+static void ahci_disable_alpm(struct ata_port *ap)
+{
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 cmd;
+        struct ahci_port_priv *pp = ap->private_data;
+
+        /* IPM bits should be disabled by libata-core */
+        /* get the existing command bits */
+        cmd = readl(port_mmio + PORT_CMD);
+
+        /* disable ALPM and ASP */
+        cmd &= ~PORT_CMD_ASP;
+        cmd &= ~PORT_CMD_ALPE;
+
+        /* force the interface back to active */
+        cmd |= PORT_CMD_ICC_ACTIVE;
+
+        /* write out new cmd value */
+        writel(cmd, port_mmio + PORT_CMD);
+        cmd = readl(port_mmio + PORT_CMD);
+
+        /* wait 10ms to be sure we've come out of any low power state */
+        msleep(10);
+
+        /* clear out any PhyRdy stuff from interrupt status */
+        writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
+
+        /* go ahead and clean out PhyRdy Change from Serror too */
+        ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
+
+        /*
+         * Clear flag to indicate that we should ignore all PhyRdy
+         * state changes
+         */
+        hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
+
+        /*
+         * Enable interrupts on Phy Ready.
+         */
+        pp->intr_mask |= PORT_IRQ_PHYRDY;
+        writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+
+        /*
+         * don't change the link pm policy - we can be called
+         * just to turn of link pm temporarily
+         */
+}
+
+static int ahci_enable_alpm(struct ata_port *ap,
+        enum link_pm policy)
+{
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 cmd;
+        struct ahci_port_priv *pp = ap->private_data;
+        u32 asp;
+
+        /* Make sure the host is capable of link power management */
+        if (!(hpriv->cap & HOST_CAP_ALPM))
+                return -EINVAL;
+
+        switch (policy) {
+        case MAX_PERFORMANCE:
+        case NOT_AVAILABLE:
+                /*
+                 * if we came here with NOT_AVAILABLE,
+                 * it just means this is the first time we
+                 * have tried to enable - default to max performance,
+                 * and let the user go to lower power modes on request.
+                 */
+                ahci_disable_alpm(ap);
+                return 0;
+        case MIN_POWER:
+                /* configure HBA to enter SLUMBER */
+                asp = PORT_CMD_ASP;
+                break;
+        case MEDIUM_POWER:
+                /* configure HBA to enter PARTIAL */
+                asp = 0;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /*
+         * Disable interrupts on Phy Ready. This keeps us from
+         * getting woken up due to spurious phy ready interrupts
+         * TBD - Hot plug should be done via polling now, is
+         * that even supported?
+         */
+        pp->intr_mask &= ~PORT_IRQ_PHYRDY;
+        writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+
+        /*
+         * Set a flag to indicate that we should ignore all PhyRdy
+         * state changes since these can happen now whenever we
+         * change link state
+         */
+        hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
+
+        /* get the existing command bits */
+        cmd = readl(port_mmio + PORT_CMD);
+
+        /*
+         * Set ASP based on Policy
+         */
+        cmd |= asp;
+
+        /*
+         * Setting this bit will instruct the HBA to aggressively
+         * enter a lower power link state when it's appropriate and
+         * based on the value set above for ASP
+         */
+        cmd |= PORT_CMD_ALPE;
+
+        /* write out new cmd value */
+        writel(cmd, port_mmio + PORT_CMD);
+        cmd = readl(port_mmio + PORT_CMD);
+
+        /* IPM bits should be set by libata-core */
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static void ahci_power_down(struct ata_port *ap)
+{
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 cmd, scontrol;
+
+        if (!(hpriv->cap & HOST_CAP_SSS))
+                return;
+
+        /* put device into listen mode, first set PxSCTL.DET to 0 */
+        scontrol = readl(port_mmio + PORT_SCR_CTL);
+        scontrol &= ~0xf;
+        writel(scontrol, port_mmio + PORT_SCR_CTL);
+
+        /* then set PxCMD.SUD to 0 */
+        cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
+        cmd &= ~PORT_CMD_SPIN_UP;
+        writel(cmd, port_mmio + PORT_CMD);
+}
+#endif
+
+static void ahci_start_port(struct ata_port *ap)
+{
+        struct ahci_port_priv *pp = ap->private_data;
+        struct ata_link *link;
+        struct ahci_em_priv *emp;
+        ssize_t rc;
+        int i;
+
+        /* enable FIS reception */
+        ahci_start_fis_rx(ap);
+
+        /* enable DMA */
+        ahci_start_engine(ap);
+
+        /* turn on LEDs */
+        if (ap->flags & ATA_FLAG_EM) {
+                ata_for_each_link(link, ap, EDGE) {
+                        emp = &pp->em_priv[link->pmp];
+
+                        /* EM Transmit bit maybe busy during init */
+                        for (i = 0; i < EM_MAX_RETRY; i++) {
+                                rc = ahci_transmit_led_message(ap,
+                                                               emp->led_state,
+                                                               4);
+                                if (rc == -EBUSY)
+                                        msleep(1);
+                                else
+                                        break;
+                        }
+                }
+        }
+
+        if (ap->flags & ATA_FLAG_SW_ACTIVITY)
+                ata_for_each_link(link, ap, EDGE)
+                        ahci_init_sw_activity(link);
+
+}
+
+static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
+{
+        int rc;
+
+        /* disable DMA */
+        rc = ahci_stop_engine(ap);
+        if (rc) {
+                *emsg = "failed to stop engine";
+                return rc;
+        }
+
+        /* disable FIS reception */
+        rc = ahci_stop_fis_rx(ap);
+        if (rc) {
+                *emsg = "failed stop FIS RX";
+                return rc;
+        }
+
+        return 0;
+}
+
+int ahci_reset_controller(struct ata_host *host)
+{
+        struct ahci_host_priv *hpriv = host->private_data;
+        void __iomem *mmio = hpriv->mmio;
+        u32 tmp;
+
+        /* we must be in AHCI mode, before using anything
+         * AHCI-specific, such as HOST_RESET.
+         */
+        ahci_enable_ahci(mmio);
+
+        /* global controller reset */
+        if (!ahci_skip_host_reset) {
+                tmp = readl(mmio + HOST_CTL);
+                if ((tmp & HOST_RESET) == 0) {
+                        writel(tmp | HOST_RESET, mmio + HOST_CTL);
+                        readl(mmio + HOST_CTL); /* flush */
+                }
+
+                /*
+                 * to perform host reset, OS should set HOST_RESET
+                 * and poll until this bit is read to be "0".
+                 * reset must complete within 1 second, or
+                 * the hardware should be considered fried.
+                 */
+                tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
+                                        HOST_RESET, 10, 1000);
+
+                if (tmp & HOST_RESET) {
+                        dev_printk(KERN_ERR, host->dev,
+                                   "controller reset failed (0x%x)\n", tmp);
+                        return -EIO;
+                }
+
+                /* turn on AHCI mode */
+                ahci_enable_ahci(mmio);
+
+                /* Some registers might be cleared on reset.  Restore
+                 * initial values.
+                 */
+                ahci_restore_initial_config(host);
+        } else
+                dev_printk(KERN_INFO, host->dev,
+                           "skipping global host reset\n");
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(ahci_reset_controller);
+
+static void ahci_sw_activity(struct ata_link *link)
+{
+        struct ata_port *ap = link->ap;
+        struct ahci_port_priv *pp = ap->private_data;
+        struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+
+        if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
+                return;
+
+        emp->activity++;
+        if (!timer_pending(&emp->timer))
+                mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
+}
+
+static void ahci_sw_activity_blink(unsigned long arg)
+{
+        struct ata_link *link = (struct ata_link *)arg;
+        struct ata_port *ap = link->ap;
+        struct ahci_port_priv *pp = ap->private_data;
+        struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+        unsigned long led_message = emp->led_state;
+        u32 activity_led_state;
+        unsigned long flags;
+
+        led_message &= EM_MSG_LED_VALUE;
+        led_message |= ap->port_no | (link->pmp << 8);
+
+        /* check to see if we've had activity.  If so,
+         * toggle state of LED and reset timer.  If not,
+         * turn LED to desired idle state.
+         */
+        spin_lock_irqsave(ap->lock, flags);
+        if (emp->saved_activity != emp->activity) {
+                emp->saved_activity = emp->activity;
+                /* get the current LED state */
+                activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
+
+                if (activity_led_state)
+                        activity_led_state = 0;
+                else
+                        activity_led_state = 1;
+
+                /* clear old state */
+                led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
+
+                /* toggle state */
+                led_message |= (activity_led_state << 16);
+                mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
+        } else {
+                /* switch to idle */
+                led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
+                if (emp->blink_policy == BLINK_OFF)
+                        led_message |= (1 << 16);
+        }
+        spin_unlock_irqrestore(ap->lock, flags);
+        ahci_transmit_led_message(ap, led_message, 4);
+}
+
+static void ahci_init_sw_activity(struct ata_link *link)
+{
+        struct ata_port *ap = link->ap;
+        struct ahci_port_priv *pp = ap->private_data;
+        struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+
+        /* init activity stats, setup timer */
+        emp->saved_activity = emp->activity = 0;
+        setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
+
+        /* check our blink policy and set flag for link if it's enabled */
+        if (emp->blink_policy)
+                link->flags |= ATA_LFLAG_SW_ACTIVITY;
+}
+
+int ahci_reset_em(struct ata_host *host)
+{
+        struct ahci_host_priv *hpriv = host->private_data;
+        void __iomem *mmio = hpriv->mmio;
+        u32 em_ctl;
+
+        em_ctl = readl(mmio + HOST_EM_CTL);
+        if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
+                return -EINVAL;
+
+        writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(ahci_reset_em);
+
+static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
+                                        ssize_t size)
+{
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        struct ahci_port_priv *pp = ap->private_data;
+        void __iomem *mmio = hpriv->mmio;
+        u32 em_ctl;
+        u32 message[] = {0, 0};
+        unsigned long flags;
+        int pmp;
+        struct ahci_em_priv *emp;
+
+        /* get the slot number from the message */
+        pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
+        if (pmp < EM_MAX_SLOTS)
+                emp = &pp->em_priv[pmp];
+        else
+                return -EINVAL;
+
+        spin_lock_irqsave(ap->lock, flags);
+
+        /*
+         * if we are still busy transmitting a previous message,
+         * do not allow
+         */
+        em_ctl = readl(mmio + HOST_EM_CTL);
+        if (em_ctl & EM_CTL_TM) {
+                spin_unlock_irqrestore(ap->lock, flags);
+                return -EBUSY;
+        }
+
+        if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
+                /*
+                 * create message header - this is all zero except for
+                 * the message size, which is 4 bytes.
+                 */
+                message[0] |= (4 << 8);
+
+                /* ignore 0:4 of byte zero, fill in port info yourself */
+                message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
+
+                /* write message to EM_LOC */
+                writel(message[0], mmio + hpriv->em_loc);
+                writel(message[1], mmio + hpriv->em_loc+4);
+
+                /*
+                 * tell hardware to transmit the message
+                 */
+                writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
+        }
+
+        /* save off new led state for port/slot */
+        emp->led_state = state;
+
+        spin_unlock_irqrestore(ap->lock, flags);
+        return size;
+}
+
+static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
+{
+        struct ahci_port_priv *pp = ap->private_data;
+        struct ata_link *link;
+        struct ahci_em_priv *emp;
+        int rc = 0;
+
+        ata_for_each_link(link, ap, EDGE) {
+                emp = &pp->em_priv[link->pmp];
+                rc += sprintf(buf, "%lx\n", emp->led_state);
+        }
+        return rc;
+}
+
+static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
+                                size_t size)
+{
+        int state;
+        int pmp;
+        struct ahci_port_priv *pp = ap->private_data;
+        struct ahci_em_priv *emp;
+
+        state = simple_strtoul(buf, NULL, 0);
+
+        /* get the slot number from the message */
+        pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
+        if (pmp < EM_MAX_SLOTS)
+                emp = &pp->em_priv[pmp];
+        else
+                return -EINVAL;
+
+        /* mask off the activity bits if we are in sw_activity
+         * mode, user should turn off sw_activity before setting
+         * activity led through em_message
+         */
+        if (emp->blink_policy)
+                state &= ~EM_MSG_LED_VALUE_ACTIVITY;
+
+        return ahci_transmit_led_message(ap, state, size);
+}
+
+static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
+{
+        struct ata_link *link = dev->link;
+        struct ata_port *ap = link->ap;
+        struct ahci_port_priv *pp = ap->private_data;
+        struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+        u32 port_led_state = emp->led_state;
+
+        /* save the desired Activity LED behavior */
+        if (val == OFF) {
+                /* clear LFLAG */
+                link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
+
+                /* set the LED to OFF */
+                port_led_state &= EM_MSG_LED_VALUE_OFF;
+                port_led_state |= (ap->port_no | (link->pmp << 8));
+                ahci_transmit_led_message(ap, port_led_state, 4);
+        } else {
+                link->flags |= ATA_LFLAG_SW_ACTIVITY;
+                if (val == BLINK_OFF) {
+                        /* set LED to ON for idle */
+                        port_led_state &= EM_MSG_LED_VALUE_OFF;
+                        port_led_state |= (ap->port_no | (link->pmp << 8));
+                        port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
+                        ahci_transmit_led_message(ap, port_led_state, 4);
+                }
+        }
+        emp->blink_policy = val;
+        return 0;
+}
+
+static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
+{
+        struct ata_link *link = dev->link;
+        struct ata_port *ap = link->ap;
+        struct ahci_port_priv *pp = ap->private_data;
+        struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+
+        /* display the saved value of activity behavior for this
+         * disk.
+         */
+        return sprintf(buf, "%d\n", emp->blink_policy);
+}
+
+static void ahci_port_init(struct device *dev, struct ata_port *ap,
+                           int port_no, void __iomem *mmio,
+                           void __iomem *port_mmio)
+{
+        const char *emsg = NULL;
+        int rc;
+        u32 tmp;
+
+        /* make sure port is not active */
+        rc = ahci_deinit_port(ap, &emsg);
+        if (rc)
+                dev_warn(dev, "%s (%d)\n", emsg, rc);
+
+        /* clear SError */
+        tmp = readl(port_mmio + PORT_SCR_ERR);
+        VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
+        writel(tmp, port_mmio + PORT_SCR_ERR);
+
+        /* clear port IRQ */
+        tmp = readl(port_mmio + PORT_IRQ_STAT);
+        VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
+        if (tmp)
+                writel(tmp, port_mmio + PORT_IRQ_STAT);
+
+        writel(1 << port_no, mmio + HOST_IRQ_STAT);
+}
+
+void ahci_init_controller(struct ata_host *host)
+{
+        struct ahci_host_priv *hpriv = host->private_data;
+        void __iomem *mmio = hpriv->mmio;
+        int i;
+        void __iomem *port_mmio;
+        u32 tmp;
+
+        for (i = 0; i < host->n_ports; i++) {
+                struct ata_port *ap = host->ports[i];
+
+                port_mmio = ahci_port_base(ap);
+                if (ata_port_is_dummy(ap))
+                        continue;
+
+                ahci_port_init(host->dev, ap, i, mmio, port_mmio);
+        }
+
+        tmp = readl(mmio + HOST_CTL);
+        VPRINTK("HOST_CTL 0x%x\n", tmp);
+        writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
+        tmp = readl(mmio + HOST_CTL);
+        VPRINTK("HOST_CTL 0x%x\n", tmp);
+}
+EXPORT_SYMBOL_GPL(ahci_init_controller);
+
+static void ahci_dev_config(struct ata_device *dev)
+{
+        struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
+
+        if (hpriv->flags & AHCI_HFLAG_SECT255) {
+                dev->max_sectors = 255;
+                ata_dev_printk(dev, KERN_INFO,
+                               "SB600 AHCI: limiting to 255 sectors per cmd\n");
+        }
+}
+
+static unsigned int ahci_dev_classify(struct ata_port *ap)
+{
+        void __iomem *port_mmio = ahci_port_base(ap);
+        struct ata_taskfile tf;
+        u32 tmp;
+
+        tmp = readl(port_mmio + PORT_SIG);
+        tf.lbah         = (tmp >> 24)   & 0xff;
+        tf.lbam         = (tmp >> 16)   & 0xff;
+        tf.lbal         = (tmp >> 8)    & 0xff;
+        tf.nsect        = (tmp)         & 0xff;
+
+        return ata_dev_classify(&tf);
+}
+
+static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
+                               u32 opts)
+{
+        dma_addr_t cmd_tbl_dma;
+
+        cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
+
+        pp->cmd_slot[tag].opts = cpu_to_le32(opts);
+        pp->cmd_slot[tag].status = 0;
+        pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
+        pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
+}
+
+int ahci_kick_engine(struct ata_port *ap)
+{
+        void __iomem *port_mmio = ahci_port_base(ap);
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
+        u32 tmp;
+        int busy, rc;
+
+        /* stop engine */
+        rc = ahci_stop_engine(ap);
+        if (rc)
+                goto out_restart;
+
+        /* need to do CLO?
+         * always do CLO if PMP is attached (AHCI-1.3 9.2)
+         */
+        busy = status & (ATA_BUSY | ATA_DRQ);
+        if (!busy && !sata_pmp_attached(ap)) {
+                rc = 0;
+                goto out_restart;
+        }
+
+        if (!(hpriv->cap & HOST_CAP_CLO)) {
+                rc = -EOPNOTSUPP;
+                goto out_restart;
+        }
+
+        /* perform CLO */
+        tmp = readl(port_mmio + PORT_CMD);
+        tmp |= PORT_CMD_CLO;
+        writel(tmp, port_mmio + PORT_CMD);
+
+        rc = 0;
+        tmp = ata_wait_register(port_mmio + PORT_CMD,
+                                PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
+        if (tmp & PORT_CMD_CLO)
+                rc = -EIO;
+
+        /* restart engine */
+ out_restart:
+        ahci_start_engine(ap);
+        return rc;
+}
+EXPORT_SYMBOL_GPL(ahci_kick_engine);
+
+static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
+                                struct ata_taskfile *tf, int is_cmd, u16 flags,
+                                unsigned long timeout_msec)
+{
+        const u32 cmd_fis_len = 5; /* five dwords */
+        struct ahci_port_priv *pp = ap->private_data;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u8 *fis = pp->cmd_tbl;
+        u32 tmp;
+
+        /* prep the command */
+        ata_tf_to_fis(tf, pmp, is_cmd, fis);
+        ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
+
+        /* issue & wait */
+        writel(1, port_mmio + PORT_CMD_ISSUE);
+
+        if (timeout_msec) {
+                tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
+                                        1, timeout_msec);
+                if (tmp & 0x1) {
+                        ahci_kick_engine(ap);
+                        return -EBUSY;
+                }
+        } else
+                readl(port_mmio + PORT_CMD_ISSUE);      /* flush */
+
+        return 0;
+}
+
+int ahci_do_softreset(struct ata_link *link, unsigned int *class,
+                      int pmp, unsigned long deadline,
+                      int (*check_ready)(struct ata_link *link))
+{
+        struct ata_port *ap = link->ap;
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        const char *reason = NULL;
+        unsigned long now, msecs;
+        struct ata_taskfile tf;
+        int rc;
+
+        DPRINTK("ENTER\n");
+
+        /* prepare for SRST (AHCI-1.1 10.4.1) */
+        rc = ahci_kick_engine(ap);
+        if (rc && rc != -EOPNOTSUPP)
+                ata_link_printk(link, KERN_WARNING,
+                                "failed to reset engine (errno=%d)\n", rc);
+
+        ata_tf_init(link->device, &tf);
+
+        /* issue the first D2H Register FIS */
+        msecs = 0;
+        now = jiffies;
+        if (time_after(deadline, now))
+                msecs = jiffies_to_msecs(deadline - now);
+
+        tf.ctl |= ATA_SRST;
+        if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
+                                 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
+                rc = -EIO;
+                reason = "1st FIS failed";
+                goto fail;
+        }
+
+        /* spec says at least 5us, but be generous and sleep for 1ms */
+        msleep(1);
+
+        /* issue the second D2H Register FIS */
+        tf.ctl &= ~ATA_SRST;
+        ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
+
+        /* wait for link to become ready */
+        rc = ata_wait_after_reset(link, deadline, check_ready);
+        if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
+                /*
+                 * Workaround for cases where link online status can't
+                 * be trusted.  Treat device readiness timeout as link
+                 * offline.
+                 */
+                ata_link_printk(link, KERN_INFO,
+                                "device not ready, treating as offline\n");
+                *class = ATA_DEV_NONE;
+        } else if (rc) {
+                /* link occupied, -ENODEV too is an error */
+                reason = "device not ready";
+                goto fail;
+        } else
+                *class = ahci_dev_classify(ap);
+
+        DPRINTK("EXIT, class=%u\n", *class);
+        return 0;
+
+ fail:
+        ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
+        return rc;
+}
+
+int ahci_check_ready(struct ata_link *link)
+{
+        void __iomem *port_mmio = ahci_port_base(link->ap);
+        u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
+
+        return ata_check_ready(status);
+}
+EXPORT_SYMBOL_GPL(ahci_check_ready);
+
+static int ahci_softreset(struct ata_link *link, unsigned int *class,
+                          unsigned long deadline)
+{
+        int pmp = sata_srst_pmp(link);
+
+        DPRINTK("ENTER\n");
+
+        return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
+}
+EXPORT_SYMBOL_GPL(ahci_do_softreset);
+
+static int ahci_hardreset(struct ata_link *link, unsigned int *class,
+                          unsigned long deadline)
+{
+        const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
+        struct ata_port *ap = link->ap;
+        struct ahci_port_priv *pp = ap->private_data;
+        u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
+        struct ata_taskfile tf;
+        bool online;
+        int rc;
+
+        DPRINTK("ENTER\n");
+
+        ahci_stop_engine(ap);
+
+        /* clear D2H reception area to properly wait for D2H FIS */
+        ata_tf_init(link->device, &tf);
+        tf.command = 0x80;
+        ata_tf_to_fis(&tf, 0, 0, d2h_fis);
+
+        rc = sata_link_hardreset(link, timing, deadline, &online,
+                                 ahci_check_ready);
+
+        ahci_start_engine(ap);
+
+        if (online)
+                *class = ahci_dev_classify(ap);
+
+        DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
+        return rc;
+}
+
+static void ahci_postreset(struct ata_link *link, unsigned int *class)
+{
+        struct ata_port *ap = link->ap;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 new_tmp, tmp;
+
+        ata_std_postreset(link, class);
+
+        /* Make sure port's ATAPI bit is set appropriately */
+        new_tmp = tmp = readl(port_mmio + PORT_CMD);
+        if (*class == ATA_DEV_ATAPI)
+                new_tmp |= PORT_CMD_ATAPI;
+        else
+                new_tmp &= ~PORT_CMD_ATAPI;
+        if (new_tmp != tmp) {
+                writel(new_tmp, port_mmio + PORT_CMD);
+                readl(port_mmio + PORT_CMD); /* flush */
+        }
+}
+
+static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
+{
+        struct scatterlist *sg;
+        struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
+        unsigned int si;
+
+        VPRINTK("ENTER\n");
+
+        /*
+         * Next, the S/G list.
+         */
+        for_each_sg(qc->sg, sg, qc->n_elem, si) {
+                dma_addr_t addr = sg_dma_address(sg);
+                u32 sg_len = sg_dma_len(sg);
+
+                ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
+                ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
+                ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
+        }
+
+        return si;
+}
+
+static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
+{
+        struct ata_port *ap = qc->ap;
+        struct ahci_port_priv *pp = ap->private_data;
+
+        if (!sata_pmp_attached(ap) || pp->fbs_enabled)
+                return ata_std_qc_defer(qc);
+        else
+                return sata_pmp_qc_defer_cmd_switch(qc);
+}
+
+static void ahci_qc_prep(struct ata_queued_cmd *qc)
+{
+        struct ata_port *ap = qc->ap;
+        struct ahci_port_priv *pp = ap->private_data;
+        int is_atapi = ata_is_atapi(qc->tf.protocol);
+        void *cmd_tbl;
+        u32 opts;
+        const u32 cmd_fis_len = 5; /* five dwords */
+        unsigned int n_elem;
+
+        /*
+         * Fill in command table information.  First, the header,
+         * a SATA Register - Host to Device command FIS.
+         */
+        cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
+
+        ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
+        if (is_atapi) {
+                memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
+                memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
+        }
+
+        n_elem = 0;
+        if (qc->flags & ATA_QCFLAG_DMAMAP)
+                n_elem = ahci_fill_sg(qc, cmd_tbl);
+
+        /*
+         * Fill in command slot information.
+         */
+        opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
+        if (qc->tf.flags & ATA_TFLAG_WRITE)
+                opts |= AHCI_CMD_WRITE;
+        if (is_atapi)
+                opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
+
+        ahci_fill_cmd_slot(pp, qc->tag, opts);
+}
+
+static void ahci_fbs_dec_intr(struct ata_port *ap)
+{
+        struct ahci_port_priv *pp = ap->private_data;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 fbs = readl(port_mmio + PORT_FBS);
+        int retries = 3;
+
+        DPRINTK("ENTER\n");
+        BUG_ON(!pp->fbs_enabled);
+
+        /* time to wait for DEC is not specified by AHCI spec,
+         * add a retry loop for safety.
+         */
+        writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
+        fbs = readl(port_mmio + PORT_FBS);
+        while ((fbs & PORT_FBS_DEC) && retries--) {
+                udelay(1);
+                fbs = readl(port_mmio + PORT_FBS);
+        }
+
+        if (fbs & PORT_FBS_DEC)
+                dev_printk(KERN_ERR, ap->host->dev,
+                           "failed to clear device error\n");
+}
+
+static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
+{
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        struct ahci_port_priv *pp = ap->private_data;
+        struct ata_eh_info *host_ehi = &ap->link.eh_info;
+        struct ata_link *link = NULL;
+        struct ata_queued_cmd *active_qc;
+        struct ata_eh_info *active_ehi;
+        bool fbs_need_dec = false;
+        u32 serror;
+
+        /* determine active link with error */
+        if (pp->fbs_enabled) {
+                void __iomem *port_mmio = ahci_port_base(ap);
+                u32 fbs = readl(port_mmio + PORT_FBS);
+                int pmp = fbs >> PORT_FBS_DWE_OFFSET;
+
+                if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
+                    ata_link_online(&ap->pmp_link[pmp])) {
+                        link = &ap->pmp_link[pmp];
+                        fbs_need_dec = true;
+                }
+
+        } else
+                ata_for_each_link(link, ap, EDGE)
+                        if (ata_link_active(link))
+                                break;
+
+        if (!link)
+                link = &ap->link;
+
+        active_qc = ata_qc_from_tag(ap, link->active_tag);
+        active_ehi = &link->eh_info;
+
+        /* record irq stat */
+        ata_ehi_clear_desc(host_ehi);
+        ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
+
+        /* AHCI needs SError cleared; otherwise, it might lock up */
+        ahci_scr_read(&ap->link, SCR_ERROR, &serror);
+        ahci_scr_write(&ap->link, SCR_ERROR, serror);
+        host_ehi->serror |= serror;
+
+        /* some controllers set IRQ_IF_ERR on device errors, ignore it */
+        if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
+                irq_stat &= ~PORT_IRQ_IF_ERR;
+
+        if (irq_stat & PORT_IRQ_TF_ERR) {
+                /* If qc is active, charge it; otherwise, the active
+                 * link.  There's no active qc on NCQ errors.  It will
+                 * be determined by EH by reading log page 10h.
+                 */
+                if (active_qc)
+                        active_qc->err_mask |= AC_ERR_DEV;
+                else
+                        active_ehi->err_mask |= AC_ERR_DEV;
+
+                if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
+                        host_ehi->serror &= ~SERR_INTERNAL;
+        }
+
+        if (irq_stat & PORT_IRQ_UNK_FIS) {
+                u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
+
+                active_ehi->err_mask |= AC_ERR_HSM;
+                active_ehi->action |= ATA_EH_RESET;
+                ata_ehi_push_desc(active_ehi,
+                                  "unknown FIS %08x %08x %08x %08x" ,
+                                  unk[0], unk[1], unk[2], unk[3]);
+        }
+
+        if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
+                active_ehi->err_mask |= AC_ERR_HSM;
+                active_ehi->action |= ATA_EH_RESET;
+                ata_ehi_push_desc(active_ehi, "incorrect PMP");
+        }
+
+        if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
+                host_ehi->err_mask |= AC_ERR_HOST_BUS;
+                host_ehi->action |= ATA_EH_RESET;
+                ata_ehi_push_desc(host_ehi, "host bus error");
+        }
+
+        if (irq_stat & PORT_IRQ_IF_ERR) {
+                if (fbs_need_dec)
+                        active_ehi->err_mask |= AC_ERR_DEV;
+                else {
+                        host_ehi->err_mask |= AC_ERR_ATA_BUS;
+                        host_ehi->action |= ATA_EH_RESET;
+                }
+
+                ata_ehi_push_desc(host_ehi, "interface fatal error");
+        }
+
+        if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
+                ata_ehi_hotplugged(host_ehi);
+                ata_ehi_push_desc(host_ehi, "%s",
+                        irq_stat & PORT_IRQ_CONNECT ?
+                        "connection status changed" : "PHY RDY changed");
+        }
+
+        /* okay, let's hand over to EH */
+
+        if (irq_stat & PORT_IRQ_FREEZE)
+                ata_port_freeze(ap);
+        else if (fbs_need_dec) {
+                ata_link_abort(link);
+                ahci_fbs_dec_intr(ap);
+        } else
+                ata_port_abort(ap);
+}
+
+static void ahci_port_intr(struct ata_port *ap)
+{
+        void __iomem *port_mmio = ahci_port_base(ap);
+        struct ata_eh_info *ehi = &ap->link.eh_info;
+        struct ahci_port_priv *pp = ap->private_data;
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
+        u32 status, qc_active = 0;
+        int rc;
+
+        status = readl(port_mmio + PORT_IRQ_STAT);
+        writel(status, port_mmio + PORT_IRQ_STAT);
+
+        /* ignore BAD_PMP while resetting */
+        if (unlikely(resetting))
+                status &= ~PORT_IRQ_BAD_PMP;
+
+        /* If we are getting PhyRdy, this is
+         * just a power state change, we should
+         * clear out this, plus the PhyRdy/Comm
+         * Wake bits from Serror
+         */
+        if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
+                (status & PORT_IRQ_PHYRDY)) {
+                status &= ~PORT_IRQ_PHYRDY;
+                ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
+        }
+
+        if (unlikely(status & PORT_IRQ_ERROR)) {
+                ahci_error_intr(ap, status);
+                return;
+        }
+
+        if (status & PORT_IRQ_SDB_FIS) {
+                /* If SNotification is available, leave notification
+                 * handling to sata_async_notification().  If not,
+                 * emulate it by snooping SDB FIS RX area.
+                 *
+                 * Snooping FIS RX area is probably cheaper than
+                 * poking SNotification but some constrollers which
+                 * implement SNotification, ICH9 for example, don't
+                 * store AN SDB FIS into receive area.
+                 */
+                if (hpriv->cap & HOST_CAP_SNTF)
+                        sata_async_notification(ap);
+                else {
+                        /* If the 'N' bit in word 0 of the FIS is set,
+                         * we just received asynchronous notification.
+                         * Tell libata about it.
+                         *
+                         * Lack of SNotification should not appear in
+                         * ahci 1.2, so the workaround is unnecessary
+                         * when FBS is enabled.
+                         */
+                        if (pp->fbs_enabled)
+                                WARN_ON_ONCE(1);
+                        else {
+                                const __le32 *f = pp->rx_fis + RX_FIS_SDB;
+                                u32 f0 = le32_to_cpu(f[0]);
+                                if (f0 & (1 << 15))
+                                        sata_async_notification(ap);
+                        }
+                }
+        }
+
+        /* pp->active_link is not reliable once FBS is enabled, both
+         * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
+         * NCQ and non-NCQ commands may be in flight at the same time.
+         */
+        if (pp->fbs_enabled) {
+                if (ap->qc_active) {
+                        qc_active = readl(port_mmio + PORT_SCR_ACT);
+                        qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
+                }
+        } else {
+                /* pp->active_link is valid iff any command is in flight */
+                if (ap->qc_active && pp->active_link->sactive)
+                        qc_active = readl(port_mmio + PORT_SCR_ACT);
+                else
+                        qc_active = readl(port_mmio + PORT_CMD_ISSUE);
+        }
+
+
+        rc = ata_qc_complete_multiple(ap, qc_active);
+
+        /* while resetting, invalid completions are expected */
+        if (unlikely(rc < 0 && !resetting)) {
+                ehi->err_mask |= AC_ERR_HSM;
+                ehi->action |= ATA_EH_RESET;
+                ata_port_freeze(ap);
+        }
+}
+
+irqreturn_t ahci_interrupt(int irq, void *dev_instance)
+{
+        struct ata_host *host = dev_instance;
+        struct ahci_host_priv *hpriv;
+        unsigned int i, handled = 0;
+        void __iomem *mmio;
+        u32 irq_stat, irq_masked;
+
+        VPRINTK("ENTER\n");
+
+        hpriv = host->private_data;
+        mmio = hpriv->mmio;
+
+        /* sigh.  0xffffffff is a valid return from h/w */
+        irq_stat = readl(mmio + HOST_IRQ_STAT);
+        if (!irq_stat)
+                return IRQ_NONE;
+
+        irq_masked = irq_stat & hpriv->port_map;
+
+        spin_lock(&host->lock);
+
+        for (i = 0; i < host->n_ports; i++) {
+                struct ata_port *ap;
+
+                if (!(irq_masked & (1 << i)))
+                        continue;
+
+                ap = host->ports[i];
+                if (ap) {
+                        ahci_port_intr(ap);
+                        VPRINTK("port %u\n", i);
+                } else {
+                        VPRINTK("port %u (no irq)\n", i);
+                        if (ata_ratelimit())
+                                dev_printk(KERN_WARNING, host->dev,
+                                        "interrupt on disabled port %u\n", i);
+                }
+
+                handled = 1;
+        }
+
+        /* HOST_IRQ_STAT behaves as level triggered latch meaning that
+         * it should be cleared after all the port events are cleared;
+         * otherwise, it will raise a spurious interrupt after each
+         * valid one.  Please read section 10.6.2 of ahci 1.1 for more
+         * information.
+         *
+         * Also, use the unmasked value to clear interrupt as spurious
+         * pending event on a dummy port might cause screaming IRQ.
+         */
+        writel(irq_stat, mmio + HOST_IRQ_STAT);
+
+        spin_unlock(&host->lock);
+
+        VPRINTK("EXIT\n");
+
+        return IRQ_RETVAL(handled);
+}
+EXPORT_SYMBOL_GPL(ahci_interrupt);
+
+static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
+{
+        struct ata_port *ap = qc->ap;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        struct ahci_port_priv *pp = ap->private_data;
+
+        /* Keep track of the currently active link.  It will be used
+         * in completion path to determine whether NCQ phase is in
+         * progress.
+         */
+        pp->active_link = qc->dev->link;
+
+        if (qc->tf.protocol == ATA_PROT_NCQ)
+                writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
+
+        if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
+                u32 fbs = readl(port_mmio + PORT_FBS);
+                fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
+                fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
+                writel(fbs, port_mmio + PORT_FBS);
+                pp->fbs_last_dev = qc->dev->link->pmp;
+        }
+
+        writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
+
+        ahci_sw_activity(qc->dev->link);
+
+        return 0;
+}
+
+static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
+{
+        struct ahci_port_priv *pp = qc->ap->private_data;
+        u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
+
+        if (pp->fbs_enabled)
+                d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
+
+        ata_tf_from_fis(d2h_fis, &qc->result_tf);
+        return true;
+}
+
+static void ahci_freeze(struct ata_port *ap)
+{
+        void __iomem *port_mmio = ahci_port_base(ap);
+
+        /* turn IRQ off */
+        writel(0, port_mmio + PORT_IRQ_MASK);
+}
+
+static void ahci_thaw(struct ata_port *ap)
+{
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        void __iomem *mmio = hpriv->mmio;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 tmp;
+        struct ahci_port_priv *pp = ap->private_data;
+
+        /* clear IRQ */
+        tmp = readl(port_mmio + PORT_IRQ_STAT);
+        writel(tmp, port_mmio + PORT_IRQ_STAT);
+        writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
+
+        /* turn IRQ back on */
+        writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+}
+
+static void ahci_error_handler(struct ata_port *ap)
+{
+        if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
+                /* restart engine */
+                ahci_stop_engine(ap);
+                ahci_start_engine(ap);
+        }
+
+        sata_pmp_error_handler(ap);
+
+        if (!ata_dev_enabled(ap->link.device))
+                ahci_stop_engine(ap);
+}
+
+static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
+{
+        struct ata_port *ap = qc->ap;
+
+        /* make DMA engine forget about the failed command */
+        if (qc->flags & ATA_QCFLAG_FAILED)
+                ahci_kick_engine(ap);
+}
+
+static void ahci_enable_fbs(struct ata_port *ap)
+{
+        struct ahci_port_priv *pp = ap->private_data;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 fbs;
+        int rc;
+
+        if (!pp->fbs_supported)
+                return;
+
+        fbs = readl(port_mmio + PORT_FBS);
+        if (fbs & PORT_FBS_EN) {
+                pp->fbs_enabled = true;
+                pp->fbs_last_dev = -1; /* initialization */
+                return;
+        }
+
+        rc = ahci_stop_engine(ap);
+        if (rc)
+                return;
+
+        writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
+        fbs = readl(port_mmio + PORT_FBS);
+        if (fbs & PORT_FBS_EN) {
+                dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
+                pp->fbs_enabled = true;
+                pp->fbs_last_dev = -1; /* initialization */
+        } else
+                dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
+
+        ahci_start_engine(ap);
+}
+
+static void ahci_disable_fbs(struct ata_port *ap)
+{
+        struct ahci_port_priv *pp = ap->private_data;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 fbs;
+        int rc;
+
+        if (!pp->fbs_supported)
+                return;
+
+        fbs = readl(port_mmio + PORT_FBS);
+        if ((fbs & PORT_FBS_EN) == 0) {
+                pp->fbs_enabled = false;
+                return;
+        }
+
+        rc = ahci_stop_engine(ap);
+        if (rc)
+                return;
+
+        writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
+        fbs = readl(port_mmio + PORT_FBS);
+        if (fbs & PORT_FBS_EN)
+                dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
+        else {
+                dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
+                pp->fbs_enabled = false;
+        }
+
+        ahci_start_engine(ap);
+}
+
+static void ahci_pmp_attach(struct ata_port *ap)
+{
+        void __iomem *port_mmio = ahci_port_base(ap);
+        struct ahci_port_priv *pp = ap->private_data;
+        u32 cmd;
+
+        cmd = readl(port_mmio + PORT_CMD);
+        cmd |= PORT_CMD_PMP;
+        writel(cmd, port_mmio + PORT_CMD);
+
+        ahci_enable_fbs(ap);
+
+        pp->intr_mask |= PORT_IRQ_BAD_PMP;
+        writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+}
+
+static void ahci_pmp_detach(struct ata_port *ap)
+{
+        void __iomem *port_mmio = ahci_port_base(ap);
+        struct ahci_port_priv *pp = ap->private_data;
+        u32 cmd;
+
+        ahci_disable_fbs(ap);
+
+        cmd = readl(port_mmio + PORT_CMD);
+        cmd &= ~PORT_CMD_PMP;
+        writel(cmd, port_mmio + PORT_CMD);
+
+        pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
+        writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+}
+
+static int ahci_port_resume(struct ata_port *ap)
+{
+        ahci_power_up(ap);
+        ahci_start_port(ap);
+
+        if (sata_pmp_attached(ap))
+                ahci_pmp_attach(ap);
+        else
+                ahci_pmp_detach(ap);
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
+{
+        const char *emsg = NULL;
+        int rc;
+
+        rc = ahci_deinit_port(ap, &emsg);
+        if (rc == 0)
+                ahci_power_down(ap);
+        else {
+                ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
+                ahci_start_port(ap);
+        }
+
+        return rc;
+}
+#endif
+
+static int ahci_port_start(struct ata_port *ap)
+{
+        struct ahci_host_priv *hpriv = ap->host->private_data;
+        struct device *dev = ap->host->dev;
+        struct ahci_port_priv *pp;
+        void *mem;
+        dma_addr_t mem_dma;
+        size_t dma_sz, rx_fis_sz;
+
+        pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
+        if (!pp)
+                return -ENOMEM;
+
+        /* check FBS capability */
+        if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
+                void __iomem *port_mmio = ahci_port_base(ap);
+                u32 cmd = readl(port_mmio + PORT_CMD);
+                if (cmd & PORT_CMD_FBSCP)
+                        pp->fbs_supported = true;
+                else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
+                        dev_printk(KERN_INFO, dev,
+                                   "port %d can do FBS, forcing FBSCP\n",
+                                   ap->port_no);
+                        pp->fbs_supported = true;
+                } else
+                        dev_printk(KERN_WARNING, dev,
+                                   "port %d is not capable of FBS\n",
+                                   ap->port_no);
+        }
+
+        if (pp->fbs_supported) {
+                dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
+                rx_fis_sz = AHCI_RX_FIS_SZ * 16;
+        } else {
+                dma_sz = AHCI_PORT_PRIV_DMA_SZ;
+                rx_fis_sz = AHCI_RX_FIS_SZ;
+        }
+
+        mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
+        if (!mem)
+                return -ENOMEM;
+        memset(mem, 0, dma_sz);
+
+        /*
+         * First item in chunk of DMA memory: 32-slot command table,
+         * 32 bytes each in size
+         */
+        pp->cmd_slot = mem;
+        pp->cmd_slot_dma = mem_dma;
+
+        mem += AHCI_CMD_SLOT_SZ;
+        mem_dma += AHCI_CMD_SLOT_SZ;
+
+        /*
+         * Second item: Received-FIS area
+         */
+        pp->rx_fis = mem;
+        pp->rx_fis_dma = mem_dma;
+
+        mem += rx_fis_sz;
+        mem_dma += rx_fis_sz;
+
+        /*
+         * Third item: data area for storing a single command
+         * and its scatter-gather table
+         */
+        pp->cmd_tbl = mem;
+        pp->cmd_tbl_dma = mem_dma;
+
+        /*
+         * Save off initial list of interrupts to be enabled.
+         * This could be changed later
+         */
+        pp->intr_mask = DEF_PORT_IRQ;
+
+        ap->private_data = pp;
+
+        /* engage engines, captain */
+        return ahci_port_resume(ap);
+}
+
+static void ahci_port_stop(struct ata_port *ap)
+{
+        const char *emsg = NULL;
+        int rc;
+
+        /* de-initialize port */
+        rc = ahci_deinit_port(ap, &emsg);
+        if (rc)
+                ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
+}
+
+void ahci_print_info(struct ata_host *host, const char *scc_s)
+{
+        struct ahci_host_priv *hpriv = host->private_data;
+        void __iomem *mmio = hpriv->mmio;
+        u32 vers, cap, cap2, impl, speed;
+        const char *speed_s;
+
+        vers = readl(mmio + HOST_VERSION);
+        cap = hpriv->cap;
+        cap2 = hpriv->cap2;
+        impl = hpriv->port_map;
+
+        speed = (cap >> 20) & 0xf;
+        if (speed == 1)
+                speed_s = "1.5";
+        else if (speed == 2)
+                speed_s = "3";
+        else if (speed == 3)
+                speed_s = "6";
+        else
+                speed_s = "?";
+
+        dev_info(host->dev,
+                "AHCI %02x%02x.%02x%02x "
+                "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
+                ,
+
+                (vers >> 24) & 0xff,
+                (vers >> 16) & 0xff,
+                (vers >> 8) & 0xff,
+                vers & 0xff,
+
+                ((cap >> 8) & 0x1f) + 1,
+                (cap & 0x1f) + 1,
+                speed_s,
+                impl,
+                scc_s);
+
+        dev_info(host->dev,
+                "flags: "
+                "%s%s%s%s%s%s%s"
+                "%s%s%s%s%s%s%s"
+                "%s%s%s%s%s%s\n"
+                ,
+
+                cap & HOST_CAP_64 ? "64bit " : "",
+                cap & HOST_CAP_NCQ ? "ncq " : "",
+                cap & HOST_CAP_SNTF ? "sntf " : "",
+                cap & HOST_CAP_MPS ? "ilck " : "",
+                cap & HOST_CAP_SSS ? "stag " : "",
+                cap & HOST_CAP_ALPM ? "pm " : "",
+                cap & HOST_CAP_LED ? "led " : "",
+                cap & HOST_CAP_CLO ? "clo " : "",
+                cap & HOST_CAP_ONLY ? "only " : "",
+                cap & HOST_CAP_PMP ? "pmp " : "",
+                cap & HOST_CAP_FBS ? "fbs " : "",
+                cap & HOST_CAP_PIO_MULTI ? "pio " : "",
+                cap & HOST_CAP_SSC ? "slum " : "",
+                cap & HOST_CAP_PART ? "part " : "",
+                cap & HOST_CAP_CCC ? "ccc " : "",
+                cap & HOST_CAP_EMS ? "ems " : "",
+                cap & HOST_CAP_SXS ? "sxs " : "",
+                cap2 & HOST_CAP2_APST ? "apst " : "",
+                cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
+                cap2 & HOST_CAP2_BOH ? "boh " : ""
+                );
+}
+EXPORT_SYMBOL_GPL(ahci_print_info);
+
+void ahci_set_em_messages(struct ahci_host_priv *hpriv,
+                          struct ata_port_info *pi)
+{
+        u8 messages;
+        void __iomem *mmio = hpriv->mmio;
+        u32 em_loc = readl(mmio + HOST_EM_LOC);
+        u32 em_ctl = readl(mmio + HOST_EM_CTL);
+
+        if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
+                return;
+
+        messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
+
+        if (messages) {
+                /* store em_loc */
+                hpriv->em_loc = ((em_loc >> 16) * 4);
+                hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
+                hpriv->em_msg_type = messages;
+                pi->flags |= ATA_FLAG_EM;
+                if (!(em_ctl & EM_CTL_ALHD))
+                        pi->flags |= ATA_FLAG_SW_ACTIVITY;
+        }
+}
+EXPORT_SYMBOL_GPL(ahci_set_em_messages);
+
+MODULE_AUTHOR("Jeff Garzik");
+MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
+MODULE_LICENSE("GPL");
diff --git a/drivers/ata/libata-acpi.c b/drivers/ata/libata-acpi.c
index 7b5eea7e01dc..8b5ea399a4f4 100644
--- a/drivers/ata/libata-acpi.c
+++ b/drivers/ata/libata-acpi.c
@@ -145,12 +145,6 @@ static void ata_acpi_handle_hotplug(struct ata_port *ap, struct ata_device *dev,
         struct ata_eh_info *ehi = &ap->link.eh_info;
         int wait = 0;
         unsigned long flags;
-        acpi_handle handle;
-
-        if (dev)
-                handle = dev->acpi_handle;
-        else
-                handle = ap->acpi_handle;
 
         spin_lock_irqsave(ap->lock, flags);
         /*
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 49cffb6094a3..932eaee50245 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -65,6 +65,7 @@
 #include <linux/libata.h>
 #include <asm/byteorder.h>
 #include <linux/cdrom.h>
+#include <linux/ratelimit.h>
 
 #include "libata.h"
 
@@ -96,9 +97,6 @@ static void ata_dev_xfermask(struct ata_device *dev);
 static unsigned long ata_dev_blacklisted(const struct ata_device *dev);
 
 unsigned int ata_print_id = 1;
-static struct workqueue_struct *ata_wq;
-
-struct workqueue_struct *ata_aux_wq;
 
 struct ata_force_param {
         const char      *name;
@@ -160,6 +158,10 @@ int libata_allow_tpm = 0;
 module_param_named(allow_tpm, libata_allow_tpm, int, 0444);
 MODULE_PARM_DESC(allow_tpm, "Permit the use of TPM commands (0=off [default], 1=on)");
 
+static int atapi_an;
+module_param(atapi_an, int, 0444);
+MODULE_PARM_DESC(atapi_an, "Enable ATAPI AN media presence notification (0=0ff [default], 1=on)");
+
 MODULE_AUTHOR("Jeff Garzik");
 MODULE_DESCRIPTION("Library module for ATA devices");
 MODULE_LICENSE("GPL");
@@ -1685,52 +1687,6 @@ unsigned long ata_id_xfermask(const u16 *id)
         return ata_pack_xfermask(pio_mask, mwdma_mask, udma_mask);
 }
 
-/**
- *      ata_pio_queue_task - Queue port_task
- *      @ap: The ata_port to queue port_task for
- *      @data: data for @fn to use
- *      @delay: delay time in msecs for workqueue function
- *
- *      Schedule @fn(@data) for execution after @delay jiffies using
- *      port_task.  There is one port_task per port and it's the
- *      user(low level driver)'s responsibility to make sure that only
- *      one task is active at any given time.
- *
- *      libata core layer takes care of synchronization between
- *      port_task and EH.  ata_pio_queue_task() may be ignored for EH
- *      synchronization.
- *
- *      LOCKING:
- *      Inherited from caller.
- */
-void ata_pio_queue_task(struct ata_port *ap, void *data, unsigned long delay)
-{
-        ap->port_task_data = data;
-
-        /* may fail if ata_port_flush_task() in progress */
-        queue_delayed_work(ata_wq, &ap->port_task, msecs_to_jiffies(delay));
-}
-
-/**
- *      ata_port_flush_task - Flush port_task
- *      @ap: The ata_port to flush port_task for
- *
- *      After this function completes, port_task is guranteed not to
- *      be running or scheduled.
- *
- *      LOCKING:
- *      Kernel thread context (may sleep)
- */
-void ata_port_flush_task(struct ata_port *ap)
-{
-        DPRINTK("ENTER\n");
-
-        cancel_rearming_delayed_work(&ap->port_task);
-
-        if (ata_msg_ctl(ap))
-                ata_port_printk(ap, KERN_DEBUG, "%s: EXIT\n", __func__);
-}
-
 static void ata_qc_complete_internal(struct ata_queued_cmd *qc)
 {
         struct completion *waiting = qc->private_data;
@@ -1852,7 +1808,7 @@ unsigned ata_exec_internal_sg(struct ata_device *dev,
 
         rc = wait_for_completion_timeout(&wait, msecs_to_jiffies(timeout));
 
-        ata_port_flush_task(ap);
+        ata_sff_flush_pio_task(ap);
 
         if (!rc) {
                 spin_lock_irqsave(ap->lock, flags);
@@ -1906,22 +1862,6 @@ unsigned ata_exec_internal_sg(struct ata_device *dev,
         ap->qc_active = preempted_qc_active;
         ap->nr_active_links = preempted_nr_active_links;
 
-        /* XXX - Some LLDDs (sata_mv) disable port on command failure.
-         * Until those drivers are fixed, we detect the condition
-         * here, fail the command with AC_ERR_SYSTEM and reenable the
-         * port.
-         *
-         * Note that this doesn't change any behavior as internal
-         * command failure results in disabling the device in the
-         * higher layer for LLDDs without new reset/EH callbacks.
-         *
-         * Kill the following code as soon as those drivers are fixed.
-         */
-        if (ap->flags & ATA_FLAG_DISABLED) {
-                err_mask |= AC_ERR_SYSTEM;
-                ata_port_probe(ap);
-        }
-
         spin_unlock_irqrestore(ap->lock, flags);
 
         if ((err_mask & AC_ERR_TIMEOUT) && auto_timeout)
@@ -2184,6 +2124,14 @@ retry:
                 goto err_out;
         }
 
+        if (dev->horkage & ATA_HORKAGE_DUMP_ID) {
+                ata_dev_printk(dev, KERN_DEBUG, "dumping IDENTIFY data, "
+                               "class=%d may_fallback=%d tried_spinup=%d\n",
+                               class, may_fallback, tried_spinup);
+                print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET,
+                               16, 2, id, ATA_ID_WORDS * sizeof(*id), true);
+        }
+
         /* Falling back doesn't make sense if ID data was read
          * successfully at least once.
          */
@@ -2572,7 +2520,8 @@ int ata_dev_configure(struct ata_device *dev)
                  * to enable ATAPI AN to discern between PHY status
                  * changed notifications and ATAPI ANs.
                  */
-                if ((ap->flags & ATA_FLAG_AN) && ata_id_has_atapi_AN(id) &&
+                if (atapi_an &&
+                    (ap->flags & ATA_FLAG_AN) && ata_id_has_atapi_AN(id) &&
                     (!sata_pmp_attached(ap) ||
                      sata_scr_read(&ap->link, SCR_NOTIFICATION, &sntf) == 0)) {
                         unsigned int err_mask;
@@ -2767,8 +2716,6 @@ int ata_bus_probe(struct ata_port *ap)
         int rc;
         struct ata_device *dev;
 
-        ata_port_probe(ap);
-
         ata_for_each_dev(dev, &ap->link, ALL)
                 tries[dev->devno] = ATA_PROBE_MAX_TRIES;
 
@@ -2796,8 +2743,7 @@ int ata_bus_probe(struct ata_port *ap)
         ap->ops->phy_reset(ap);
 
         ata_for_each_dev(dev, &ap->link, ALL) {
-                if (!(ap->flags & ATA_FLAG_DISABLED) &&
-                    dev->class != ATA_DEV_UNKNOWN)
+                if (dev->class != ATA_DEV_UNKNOWN)
                         classes[dev->devno] = dev->class;
                 else
                         classes[dev->devno] = ATA_DEV_NONE;
@@ -2805,8 +2751,6 @@ int ata_bus_probe(struct ata_port *ap)
                 dev->class = ATA_DEV_UNKNOWN;
         }
 
-        ata_port_probe(ap);
-
         /* read IDENTIFY page and configure devices. We have to do the identify
            specific sequence bass-ackwards so that PDIAG- is released by
            the slave device */
@@ -2856,8 +2800,6 @@ int ata_bus_probe(struct ata_port *ap)
         ata_for_each_dev(dev, &ap->link, ENABLED)
                 return 0;
 
-        /* no device present, disable port */
-        ata_port_disable(ap);
         return -ENODEV;
 
  fail:
@@ -2889,22 +2831,6 @@ int ata_bus_probe(struct ata_port *ap)
 }
 
 /**
- *      ata_port_probe - Mark port as enabled
- *      @ap: Port for which we indicate enablement
- *
- *      Modify @ap data structure such that the system
- *      thinks that the entire port is enabled.
- *
- *      LOCKING: host lock, or some other form of
- *      serialization.
- */
-
-void ata_port_probe(struct ata_port *ap)
-{
-        ap->flags &= ~ATA_FLAG_DISABLED;
-}
-
-/**
  *      sata_print_link_status - Print SATA link status
  *      @link: SATA link to printk link status about
  *
@@ -2951,26 +2877,6 @@ struct ata_device *ata_dev_pair(struct ata_device *adev)
 }
 
 /**
- *      ata_port_disable - Disable port.
- *      @ap: Port to be disabled.
- *
- *      Modify @ap data structure such that the system
- *      thinks that the entire port is disabled, and should
- *      never attempt to probe or communicate with devices
- *      on this port.
- *
- *      LOCKING: host lock, or some other form of
- *      serialization.
- */
-
-void ata_port_disable(struct ata_port *ap)
-{
-        ap->link.device[0].class = ATA_DEV_NONE;
-        ap->link.device[1].class = ATA_DEV_NONE;
-        ap->flags |= ATA_FLAG_DISABLED;
-}
-
-/**
  *      sata_down_spd_limit - adjust SATA spd limit downward
  *      @link: Link to adjust SATA spd limit for
  *      @spd_limit: Additional limit
@@ -3631,9 +3537,15 @@ int ata_wait_ready(struct ata_link *link, unsigned long deadline,
                    int (*check_ready)(struct ata_link *link))
 {
         unsigned long start = jiffies;
-        unsigned long nodev_deadline = ata_deadline(start, ATA_TMOUT_FF_WAIT);
+        unsigned long nodev_deadline;
         int warned = 0;
 
+        /* choose which 0xff timeout to use, read comment in libata.h */
+        if (link->ap->host->flags & ATA_HOST_PARALLEL_SCAN)
+                nodev_deadline = ata_deadline(start, ATA_TMOUT_FF_WAIT_LONG);
+        else
+                nodev_deadline = ata_deadline(start, ATA_TMOUT_FF_WAIT);
+
         /* Slave readiness can't be tested separately from master.  On
          * M/S emulation configuration, this function should be called
          * only on the master and it will handle both master and slave.
@@ -3651,12 +3563,12 @@ int ata_wait_ready(struct ata_link *link, unsigned long deadline,
                 if (ready > 0)
                         return 0;
 
-                /* -ENODEV could be transient.  Ignore -ENODEV if link
+                /*
+                 * -ENODEV could be transient.  Ignore -ENODEV if link
                  * is online.  Also, some SATA devices take a long
-                 * time to clear 0xff after reset.  For example,
-                 * HHD424020F7SV00 iVDR needs >= 800ms while Quantum
-                 * GoVault needs even more than that.  Wait for
-                 * ATA_TMOUT_FF_WAIT on -ENODEV if link isn't offline.
+                 * time to clear 0xff after reset.  Wait for
+                 * ATA_TMOUT_FF_WAIT[_LONG] on -ENODEV if link isn't
+                 * offline.
                  *
                  * Note that some PATA controllers (pata_ali) explode
                  * if status register is read more than once when
@@ -4205,9 +4117,8 @@ int ata_dev_revalidate(struct ata_device *dev, unsigned int new_class,
             dev->n_sectors > n_sectors && dev->n_sectors == n_native_sectors) {
                 ata_dev_printk(dev, KERN_WARNING,
                                "new n_sectors matches native, probably "
-                               "late HPA unlock, continuing\n");
-                /* keep using the old n_sectors */
-                dev->n_sectors = n_sectors;
+                               "late HPA unlock, n_sectors updated\n");
+                /* use the larger n_sectors */
                 return 0;
         }
 
@@ -4254,15 +4165,13 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
         { "WDC AC23200L",       "21.10N21",     ATA_HORKAGE_NODMA },
         { "Compaq CRD-8241B",   NULL,           ATA_HORKAGE_NODMA },
         { "CRD-8400B",          NULL,           ATA_HORKAGE_NODMA },
-        { "CRD-8480B",          NULL,           ATA_HORKAGE_NODMA },
-        { "CRD-8482B",          NULL,           ATA_HORKAGE_NODMA },
+        { "CRD-848[02]B",       NULL,           ATA_HORKAGE_NODMA },
         { "CRD-84",             NULL,           ATA_HORKAGE_NODMA },
         { "SanDisk SDP3B",      NULL,           ATA_HORKAGE_NODMA },
         { "SanDisk SDP3B-64",   NULL,           ATA_HORKAGE_NODMA },
         { "SANYO CD-ROM CRD",   NULL,           ATA_HORKAGE_NODMA },
         { "HITACHI CDR-8",      NULL,           ATA_HORKAGE_NODMA },
-        { "HITACHI CDR-8335",   NULL,           ATA_HORKAGE_NODMA },
-        { "HITACHI CDR-8435",   NULL,           ATA_HORKAGE_NODMA },
+        { "HITACHI CDR-8[34]35",NULL,           ATA_HORKAGE_NODMA },
         { "Toshiba CD-ROM XM-6202B", NULL,      ATA_HORKAGE_NODMA },
         { "TOSHIBA CD-ROM XM-1702BC", NULL,     ATA_HORKAGE_NODMA },
         { "CD-532E-A",          NULL,           ATA_HORKAGE_NODMA },
@@ -4298,70 +4207,16 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
         { "OCZ CORE_SSD",       "02.10104",     ATA_HORKAGE_NONCQ },
 
         /* Seagate NCQ + FLUSH CACHE firmware bug */
-        { "ST31500341AS",       "SD15",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST31500341AS",       "SD16",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST31500341AS",       "SD17",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST31500341AS",       "SD18",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST31500341AS",       "SD19",         ATA_HORKAGE_NONCQ |
+        { "ST31500341AS",       "SD1[5-9]",     ATA_HORKAGE_NONCQ |
                                                 ATA_HORKAGE_FIRMWARE_WARN },
 
-        { "ST31000333AS",       "SD15",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST31000333AS",       "SD16",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST31000333AS",       "SD17",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST31000333AS",       "SD18",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST31000333AS",       "SD19",         ATA_HORKAGE_NONCQ |
+        { "ST31000333AS",       "SD1[5-9]",     ATA_HORKAGE_NONCQ |
                                                 ATA_HORKAGE_FIRMWARE_WARN },
 
-        { "ST3640623AS",        "SD15",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3640623AS",        "SD16",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3640623AS",        "SD17",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3640623AS",        "SD18",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3640623AS",        "SD19",         ATA_HORKAGE_NONCQ |
+        { "ST3640[36]23AS",     "SD1[5-9]",     ATA_HORKAGE_NONCQ |
                                                 ATA_HORKAGE_FIRMWARE_WARN },
 
-        { "ST3640323AS",        "SD15",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3640323AS",        "SD16",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3640323AS",        "SD17",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3640323AS",        "SD18",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3640323AS",        "SD19",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-
-        { "ST3320813AS",        "SD15",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3320813AS",        "SD16",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3320813AS",        "SD17",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3320813AS",        "SD18",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3320813AS",        "SD19",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-
-        { "ST3320613AS",        "SD15",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3320613AS",        "SD16",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3320613AS",        "SD17",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3320613AS",        "SD18",         ATA_HORKAGE_NONCQ |
-                                                ATA_HORKAGE_FIRMWARE_WARN },
-        { "ST3320613AS",        "SD19",         ATA_HORKAGE_NONCQ |
+        { "ST3320[68]13AS",     "SD1[5-9]",     ATA_HORKAGE_NONCQ |
                                                 ATA_HORKAGE_FIRMWARE_WARN },
 
         /* Blacklist entries taken from Silicon Image 3124/3132
@@ -4390,12 +4245,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
         /* Devices which get the IVB wrong */
         { "QUANTUM FIREBALLlct10 05", "A03.0900", ATA_HORKAGE_IVB, },
         /* Maybe we should just blacklist TSSTcorp... */
-        { "TSSTcorp CDDVDW SH-S202H", "SB00",     ATA_HORKAGE_IVB, },
-        { "TSSTcorp CDDVDW SH-S202H", "SB01",     ATA_HORKAGE_IVB, },
-        { "TSSTcorp CDDVDW SH-S202J", "SB00",     ATA_HORKAGE_IVB, },
-        { "TSSTcorp CDDVDW SH-S202J", "SB01",     ATA_HORKAGE_IVB, },
-        { "TSSTcorp CDDVDW SH-S202N", "SB00",     ATA_HORKAGE_IVB, },
-        { "TSSTcorp CDDVDW SH-S202N", "SB01",     ATA_HORKAGE_IVB, },
+        { "TSSTcorp CDDVDW SH-S202[HJN]", "SB0[01]",  ATA_HORKAGE_IVB, },
 
         /* Devices that do not need bridging limits applied */
         { "MTRON MSP-SATA*",            NULL,   ATA_HORKAGE_BRIDGE_OK, },
@@ -4413,29 +4263,73 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
         { }
 };
 
-static int strn_pattern_cmp(const char *patt, const char *name, int wildchar)
+/**
+ *      glob_match - match a text string against a glob-style pattern
+ *      @text: the string to be examined
+ *      @pattern: the glob-style pattern to be matched against
+ *
+ *      Either/both of text and pattern can be empty strings.
+ *
+ *      Match text against a glob-style pattern, with wildcards and simple sets:
+ *
+ *              ?       matches any single character.
+ *              *       matches any run of characters.
+ *              [xyz]   matches a single character from the set: x, y, or z.
+ *              [a-d]   matches a single character from the range: a, b, c, or d.
+ *              [a-d0-9] matches a single character from either range.
+ *
+ *      The special characters ?, [, -, or *, can be matched using a set, eg. [*]
+ *      Behaviour with malformed patterns is undefined, though generally reasonable.
+ *
+ *      Sample patterns:  "SD1?",  "SD1[0-5]",  "*R0",  "SD*1?[012]*xx"
+ *
+ *      This function uses one level of recursion per '*' in pattern.
+ *      Since it calls _nothing_ else, and has _no_ explicit local variables,
+ *      this will not cause stack problems for any reasonable use here.
+ *
+ *      RETURNS:
+ *      0 on match, 1 otherwise.
+ */
+static int glob_match (const char *text, const char *pattern)
 {
-        const char *p;
-        int len;
-
-        /*
-         * check for trailing wildcard: *\0
-         */
-        p = strchr(patt, wildchar);
-        if (p && ((*(p + 1)) == 0))
-                len = p - patt;
-        else {
-                len = strlen(name);
-                if (!len) {
-                        if (!*patt)
-                                return 0;
-                        return -1;
+        do {
+                /* Match single character or a '?' wildcard */
+                if (*text == *pattern || *pattern == '?') {
+                        if (!*pattern++)
+                                return 0;  /* End of both strings: match */
+                } else {
+                        /* Match single char against a '[' bracketed ']' pattern set */
+                        if (!*text || *pattern != '[')
+                                break;  /* Not a pattern set */
+                        while (*++pattern && *pattern != ']' && *text != *pattern) {
+                                if (*pattern == '-' && *(pattern - 1) != '[')
+                                        if (*text > *(pattern - 1) && *text < *(pattern + 1)) {
+                                                ++pattern;
+                                                break;
+                                        }
+                        }
+                        if (!*pattern || *pattern == ']')
+                                return 1;  /* No match */
+                        while (*pattern && *pattern++ != ']');
+                }
+        } while (*++text && *pattern);
+
+        /* Match any run of chars against a '*' wildcard */
+        if (*pattern == '*') {
+                if (!*++pattern)
+                        return 0;  /* Match: avoid recursion at end of pattern */
+                /* Loop to handle additional pattern chars after the wildcard */
+                while (*text) {
+                        if (glob_match(text, pattern) == 0)
+                                return 0;  /* Remainder matched */
+                        ++text;  /* Absorb (match) this char and try again */
                 }
         }
-
-        return strncmp(patt, name, len);
+        if (!*text && !*pattern)
+                return 0;  /* End of both strings: match */
+        return 1;  /* No match */
 }
-
+ 
 static unsigned long ata_dev_blacklisted(const struct ata_device *dev)
 {
         unsigned char model_num[ATA_ID_PROD_LEN + 1];
@@ -4446,10 +4340,10 @@ static unsigned long ata_dev_blacklisted(const struct ata_device *dev)
         ata_id_c_string(dev->id, model_rev, ATA_ID_FW_REV, sizeof(model_rev));
 
         while (ad->model_num) {
-                if (!strn_pattern_cmp(ad->model_num, model_num, '*')) {
+                if (!glob_match(model_num, ad->model_num)) {
                         if (ad->model_rev == NULL)
                                 return ad->horkage;
-                        if (!strn_pattern_cmp(ad->model_rev, model_rev, '*'))
+                        if (!glob_match(model_rev, ad->model_rev))
                                 return ad->horkage;
                 }
                 ad++;
@@ -5217,15 +5111,18 @@ void ata_qc_issue(struct ata_queued_cmd *qc)
         qc->flags |= ATA_QCFLAG_ACTIVE;
         ap->qc_active |= 1 << qc->tag;
 
-        /* We guarantee to LLDs that they will have at least one
+        /*
+         * We guarantee to LLDs that they will have at least one
          * non-zero sg if the command is a data command.
          */
-        BUG_ON(ata_is_data(prot) && (!qc->sg || !qc->n_elem || !qc->nbytes));
+        if (WARN_ON_ONCE(ata_is_data(prot) &&
+                         (!qc->sg || !qc->n_elem || !qc->nbytes)))
+                goto sys_err;
 
         if (ata_is_dma(prot) || (ata_is_pio(prot) &&
                                  (ap->flags & ATA_FLAG_PIO_DMA)))
                 if (ata_sg_setup(qc))
-                        goto sg_err;
+                        goto sys_err;
 
         /* if device is sleeping, schedule reset and abort the link */
         if (unlikely(qc->dev->flags & ATA_DFLAG_SLEEPING)) {
@@ -5242,7 +5139,7 @@ void ata_qc_issue(struct ata_queued_cmd *qc)
                 goto err;
         return;
 
-sg_err:
+sys_err:
         qc->err_mask |= AC_ERR_SYSTEM;
 err:
         ata_qc_complete(qc);
@@ -5521,6 +5418,7 @@ static int ata_host_request_pm(struct ata_host *host, pm_message_t mesg,
  */
 int ata_host_suspend(struct ata_host *host, pm_message_t mesg)
 {
+        unsigned int ehi_flags = ATA_EHI_QUIET;
         int rc;
 
         /*
@@ -5529,7 +5427,18 @@ int ata_host_suspend(struct ata_host *host, pm_message_t mesg)
          */
         ata_lpm_enable(host);
 
-        rc = ata_host_request_pm(host, mesg, 0, ATA_EHI_QUIET, 1);
+        /*
+         * On some hardware, device fails to respond after spun down
+         * for suspend.  As the device won't be used before being
+         * resumed, we don't need to touch the device.  Ask EH to skip
+         * the usual stuff and proceed directly to suspend.
+         *
+         * http://thread.gmane.org/gmane.linux.ide/46764
+         */
+        if (mesg.event == PM_EVENT_SUSPEND)
+                ehi_flags |= ATA_EHI_NO_AUTOPSY | ATA_EHI_NO_RECOVERY;
+
+        rc = ata_host_request_pm(host, mesg, 0, ehi_flags, 1);
         if (rc == 0)
                 host->dev->power.power_state = mesg;
         return rc;
@@ -5558,30 +5467,6 @@ void ata_host_resume(struct ata_host *host)
 #endif
 
 /**
- *      ata_port_start - Set port up for dma.
- *      @ap: Port to initialize
- *
- *      Called just after data structures for each port are
- *      initialized.  Allocates space for PRD table.
- *
- *      May be used as the port_start() entry in ata_port_operations.
- *
- *      LOCKING:
- *      Inherited from caller.
- */
-int ata_port_start(struct ata_port *ap)
-{
-        struct device *dev = ap->dev;
-
-        ap->prd = dmam_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma,
-                                      GFP_KERNEL);
-        if (!ap->prd)
-                return -ENOMEM;
-
-        return 0;
-}
-
-/**
  *      ata_dev_init - Initialize an ata_device structure
  *      @dev: Device structure to initialize
  *
@@ -5709,12 +5594,9 @@ struct ata_port *ata_port_alloc(struct ata_host *host)
 
         ap->pflags |= ATA_PFLAG_INITIALIZING;
         ap->lock = &host->lock;
-        ap->flags = ATA_FLAG_DISABLED;
         ap->print_id = -1;
-        ap->ctl = ATA_DEVCTL_OBS;
         ap->host = host;
         ap->dev = host->dev;
-        ap->last_ctl = 0xFF;
 
 #if defined(ATA_VERBOSE_DEBUG)
         /* turn on all debugging levels */
@@ -5725,11 +5607,7 @@ struct ata_port *ata_port_alloc(struct ata_host *host)
         ap->msg_enable = ATA_MSG_DRV | ATA_MSG_ERR | ATA_MSG_WARN;
 #endif
 
-#ifdef CONFIG_ATA_SFF
-        INIT_DELAYED_WORK(&ap->port_task, ata_pio_task);
-#else
-        INIT_DELAYED_WORK(&ap->port_task, NULL);
-#endif
+        mutex_init(&ap->scsi_scan_mutex);
         INIT_DELAYED_WORK(&ap->hotplug_task, ata_scsi_hotplug);
         INIT_WORK(&ap->scsi_rescan_task, ata_scsi_dev_rescan);
         INIT_LIST_HEAD(&ap->eh_done_q);
@@ -5747,6 +5625,8 @@ struct ata_port *ata_port_alloc(struct ata_host *host)
         ap->stats.unhandled_irq = 1;
         ap->stats.idle_irq = 1;
 #endif
+        ata_sff_port_init(ap);
+
         return ap;
 }
 
@@ -6138,8 +6018,6 @@ static void async_port_probe(void *data, async_cookie_t cookie)
                 struct ata_eh_info *ehi = &ap->link.eh_info;
                 unsigned long flags;
 
-                ata_port_probe(ap);
-
                 /* kick EH for boot probing */
                 spin_lock_irqsave(ap->lock, flags);
 
@@ -6503,6 +6381,7 @@ static int __init ata_parse_force_one(char **cur,
                 { "3.0Gbps",    .spd_limit      = 2 },
                 { "noncq",      .horkage_on     = ATA_HORKAGE_NONCQ },
                 { "ncq",        .horkage_off    = ATA_HORKAGE_NONCQ },
+                { "dump_id",    .horkage_on     = ATA_HORKAGE_DUMP_ID },
                 { "pio0",       .xfer_mask      = 1 << (ATA_SHIFT_PIO + 0) },
                 { "pio1",       .xfer_mask      = 1 << (ATA_SHIFT_PIO + 1) },
                 { "pio2",       .xfer_mask      = 1 << (ATA_SHIFT_PIO + 2) },
@@ -6663,62 +6542,34 @@ static void __init ata_parse_force_param(void)
 
 static int __init ata_init(void)
 {
-        ata_parse_force_param();
+        int rc = -ENOMEM;
 
-        /*
-         * FIXME: In UP case, there is only one workqueue thread and if you
-         * have more than one PIO device, latency is bloody awful, with
-         * occasional multi-second "hiccups" as one PIO device waits for
-         * another.  It's an ugly wart that users DO occasionally complain
-         * about; luckily most users have at most one PIO polled device.
-         */
-        ata_wq = create_workqueue("ata");
-        if (!ata_wq)
-                goto free_force_tbl;
+        ata_parse_force_param();
 
-        ata_aux_wq = create_singlethread_workqueue("ata_aux");
-        if (!ata_aux_wq)
-                goto free_wq;
+        rc = ata_sff_init();
+        if (rc) {
+                kfree(ata_force_tbl);
+                return rc;
+        }
 
         printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
         return 0;
-
-free_wq:
-        destroy_workqueue(ata_wq);
-free_force_tbl:
-        kfree(ata_force_tbl);
-        return -ENOMEM;
 }
 
 static void __exit ata_exit(void)
 {
+        ata_sff_exit();
         kfree(ata_force_tbl);
-        destroy_workqueue(ata_wq);
-        destroy_workqueue(ata_aux_wq);
 }
 
 subsys_initcall(ata_init);
 module_exit(ata_exit);
 
-static unsigned long ratelimit_time;
-static DEFINE_SPINLOCK(ata_ratelimit_lock);
+static DEFINE_RATELIMIT_STATE(ratelimit, HZ / 5, 1);
 
 int ata_ratelimit(void)
 {
-        int rc;
-        unsigned long flags;
-
-        spin_lock_irqsave(&ata_ratelimit_lock, flags);
-
-        if (time_after(jiffies, ratelimit_time)) {
-                rc = 1;
-                ratelimit_time = jiffies + (HZ/5);
-        } else
-                rc = 0;
-
-        spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
-
-        return rc;
+        return __ratelimit(&ratelimit);
 }
 
 /**
@@ -6805,6 +6656,7 @@ EXPORT_SYMBOL_GPL(ata_dummy_port_info);
 EXPORT_SYMBOL_GPL(ata_link_next);
 EXPORT_SYMBOL_GPL(ata_dev_next);
 EXPORT_SYMBOL_GPL(ata_std_bios_param);
+EXPORT_SYMBOL_GPL(ata_scsi_unlock_native_capacity);
 EXPORT_SYMBOL_GPL(ata_host_init);
 EXPORT_SYMBOL_GPL(ata_host_alloc);
 EXPORT_SYMBOL_GPL(ata_host_alloc_pinfo);
@@ -6826,11 +6678,9 @@ EXPORT_SYMBOL_GPL(ata_xfer_mode2mask);
 EXPORT_SYMBOL_GPL(ata_xfer_mode2shift);
 EXPORT_SYMBOL_GPL(ata_mode_string);
 EXPORT_SYMBOL_GPL(ata_id_xfermask);
-EXPORT_SYMBOL_GPL(ata_port_start);
 EXPORT_SYMBOL_GPL(ata_do_set_mode);
 EXPORT_SYMBOL_GPL(ata_std_qc_defer);
 EXPORT_SYMBOL_GPL(ata_noop_qc_prep);
-EXPORT_SYMBOL_GPL(ata_port_probe);
 EXPORT_SYMBOL_GPL(ata_dev_disable);
 EXPORT_SYMBOL_GPL(sata_set_spd);
 EXPORT_SYMBOL_GPL(ata_wait_after_reset);
@@ -6842,7 +6692,6 @@ EXPORT_SYMBOL_GPL(sata_std_hardreset);
 EXPORT_SYMBOL_GPL(ata_std_postreset);
 EXPORT_SYMBOL_GPL(ata_dev_classify);
 EXPORT_SYMBOL_GPL(ata_dev_pair);
-EXPORT_SYMBOL_GPL(ata_port_disable);
 EXPORT_SYMBOL_GPL(ata_ratelimit);
 EXPORT_SYMBOL_GPL(ata_wait_register);
 EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
@@ -6864,7 +6713,6 @@ EXPORT_SYMBOL_GPL(ata_id_c_string);
 EXPORT_SYMBOL_GPL(ata_do_dev_read_id);
 EXPORT_SYMBOL_GPL(ata_scsi_simulate);
 
-EXPORT_SYMBOL_GPL(ata_pio_queue_task);
 EXPORT_SYMBOL_GPL(ata_pio_need_iordy);
 EXPORT_SYMBOL_GPL(ata_timing_find_mode);
 EXPORT_SYMBOL_GPL(ata_timing_compute);
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index 228740f356c9..e48302eae55f 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -550,8 +550,8 @@ void ata_scsi_error(struct Scsi_Host *host)
 
         DPRINTK("ENTER\n");
 
-        /* synchronize with port task */
-        ata_port_flush_task(ap);
+        /* make sure sff pio task is not running */
+        ata_sff_flush_pio_task(ap);
 
         /* synchronize with host lock and sort out timeouts */
 
@@ -727,7 +727,7 @@ void ata_scsi_error(struct Scsi_Host *host)
         if (ap->pflags & ATA_PFLAG_LOADING)
                 ap->pflags &= ~ATA_PFLAG_LOADING;
         else if (ap->pflags & ATA_PFLAG_SCSI_HOTPLUG)
-                queue_delayed_work(ata_aux_wq, &ap->hotplug_task, 0);
+                schedule_delayed_work(&ap->hotplug_task, 0);
 
         if (ap->pflags & ATA_PFLAG_RECOVERED)
                 ata_port_printk(ap, KERN_INFO, "EH complete\n");
@@ -2214,6 +2214,7 @@ const char *ata_get_cmd_descript(u8 command)
                 { ATA_CMD_SMART,                "SMART" },
                 { ATA_CMD_MEDIA_LOCK,           "DOOR LOCK" },
                 { ATA_CMD_MEDIA_UNLOCK,         "DOOR UNLOCK" },
+                { ATA_CMD_DSM,                  "DATA SET MANAGEMENT" },
                 { ATA_CMD_CHK_MED_CRD_TYP,      "CHECK MEDIA CARD TYPE" },
                 { ATA_CMD_CFA_REQ_EXT_ERR,      "CFA REQUEST EXTENDED ERROR" },
                 { ATA_CMD_CFA_WRITE_NE,         "CFA WRITE SECTORS WITHOUT ERASE" },
@@ -2944,7 +2945,7 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
                         ehc->i.flags |= ATA_EHI_SETMODE;
 
                         /* schedule the scsi_rescan_device() here */
-                        queue_work(ata_aux_wq, &(ap->scsi_rescan_task));
+                        schedule_work(&(ap->scsi_rescan_task));
                 } else if (dev->class == ATA_DEV_UNKNOWN &&
                            ehc->tries[dev->devno] &&
                            ata_class_enabled(ehc->classes[dev->devno])) {
@@ -3234,6 +3235,10 @@ static int ata_eh_skip_recovery(struct ata_link *link)
         if (link->flags & ATA_LFLAG_DISABLED)
                 return 1;
 
+        /* skip if explicitly requested */
+        if (ehc->i.flags & ATA_EHI_NO_RECOVERY)
+                return 1;
+
         /* thaw frozen port and recover failed devices */
         if ((ap->pflags & ATA_PFLAG_FROZEN) || ata_link_nr_enabled(link))
                 return 0;
@@ -3684,7 +3689,7 @@ void ata_std_error_handler(struct ata_port *ap)
         ata_reset_fn_t hardreset = ops->hardreset;
 
         /* ignore built-in hardreset if SCR access is not available */
-        if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link))
+        if (hardreset == sata_std_hardreset && !sata_scr_valid(&ap->link))
                 hardreset = NULL;
 
         ata_do_eh(ap, ops->prereset, ops->softreset, hardreset, ops->postreset);
diff --git a/drivers/ata/libata-pmp.c b/drivers/ata/libata-pmp.c
index 00305f41ed86..224faabd7b7e 100644
--- a/drivers/ata/libata-pmp.c
+++ b/drivers/ata/libata-pmp.c
@@ -231,10 +231,14 @@ static const char *sata_pmp_spec_rev_str(const u32 *gscr)
         return "<unknown>";
 }
 
+#define PMP_GSCR_SII_POL 129
+
 static int sata_pmp_configure(struct ata_device *dev, int print_info)
 {
         struct ata_port *ap = dev->link->ap;
         u32 *gscr = dev->gscr;
+        u16 vendor = sata_pmp_gscr_vendor(gscr);
+        u16 devid = sata_pmp_gscr_devid(gscr);
         unsigned int err_mask = 0;
         const char *reason;
         int nr_ports, rc;
@@ -260,12 +264,34 @@ static int sata_pmp_configure(struct ata_device *dev, int print_info)
                 goto fail;
         }
 
+        /* Disable sending Early R_OK.
+         * With "cached read" HDD testing and multiple ports busy on a SATA
+         * host controller, 3726 PMP will very rarely drop a deferred
+         * R_OK that was intended for the host. Symptom will be all
+         * 5 drives under test will timeout, get reset, and recover.
+         */
+        if (vendor == 0x1095 && devid == 0x3726) {
+                u32 reg;
+
+                err_mask = sata_pmp_read(&ap->link, PMP_GSCR_SII_POL, &reg);
+                if (err_mask) {
+                        rc = -EIO;
+                        reason = "failed to read Sil3726 Private Register";
+                        goto fail;
+                }
+                reg &= ~0x1;
+                err_mask = sata_pmp_write(&ap->link, PMP_GSCR_SII_POL, reg);
+                if (err_mask) {
+                        rc = -EIO;
+                        reason = "failed to write Sil3726 Private Register";
+                        goto fail;
+                }
+        }
+
         if (print_info) {
                 ata_dev_printk(dev, KERN_INFO, "Port Multiplier %s, "
                                "0x%04x:0x%04x r%d, %d ports, feat 0x%x/0x%x\n",
-                               sata_pmp_spec_rev_str(gscr),
-                               sata_pmp_gscr_vendor(gscr),
-                               sata_pmp_gscr_devid(gscr),
+                               sata_pmp_spec_rev_str(gscr), vendor, devid,
                                sata_pmp_gscr_rev(gscr),
                                nr_ports, gscr[SATA_PMP_GSCR_FEAT_EN],
                                gscr[SATA_PMP_GSCR_FEAT]);
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index 0088cdeb0b1e..a89172c100f5 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -415,6 +415,35 @@ int ata_std_bios_param(struct scsi_device *sdev, struct block_device *bdev,
 }
 
 /**
+ *      ata_scsi_unlock_native_capacity - unlock native capacity
+ *      @sdev: SCSI device to adjust device capacity for
+ *
+ *      This function is called if a partition on @sdev extends beyond
+ *      the end of the device.  It requests EH to unlock HPA.
+ *
+ *      LOCKING:
+ *      Defined by the SCSI layer.  Might sleep.
+ */
+void ata_scsi_unlock_native_capacity(struct scsi_device *sdev)
+{
+        struct ata_port *ap = ata_shost_to_port(sdev->host);
+        struct ata_device *dev;
+        unsigned long flags;
+
+        spin_lock_irqsave(ap->lock, flags);
+
+        dev = ata_scsi_find_dev(ap, sdev);
+        if (dev && dev->n_sectors < dev->n_native_sectors) {
+                dev->flags |= ATA_DFLAG_UNLOCK_HPA;
+                dev->link->eh_info.action |= ATA_EH_RESET;
+                ata_port_schedule_eh(ap);
+        }
+
+        spin_unlock_irqrestore(ap->lock, flags);
+        ata_port_wait_eh(ap);
+}
+
+/**
  *      ata_get_identity - Handler for HDIO_GET_IDENTITY ioctl
  *      @ap: target port
  *      @sdev: SCSI device to get identify data for
@@ -1082,10 +1111,10 @@ static void ata_scsi_sdev_config(struct scsi_device *sdev)
  */
 static int atapi_drain_needed(struct request *rq)
 {
-        if (likely(!blk_pc_request(rq)))
+        if (likely(rq->cmd_type != REQ_TYPE_BLOCK_PC))
                 return 0;
 
-        if (!blk_rq_bytes(rq) || (rq->cmd_flags & REQ_RW))
+        if (!blk_rq_bytes(rq) || (rq->cmd_flags & REQ_WRITE))
                 return 0;
 
         return atapi_cmd_type(rq->cmd[0]) == ATAPI_MISC;
@@ -3345,9 +3374,6 @@ void ata_scsi_scan_host(struct ata_port *ap, int sync)
         struct ata_link *link;
         struct ata_device *dev;
 
-        if (ap->flags & ATA_FLAG_DISABLED)
-                return;
-
  repeat:
         ata_for_each_link(link, ap, EDGE) {
                 ata_for_each_dev(dev, link, ENABLED) {
@@ -3409,7 +3435,7 @@ void ata_scsi_scan_host(struct ata_port *ap, int sync)
                                 "                  switching to async\n");
         }
 
-        queue_delayed_work(ata_aux_wq, &ap->hotplug_task,
+        queue_delayed_work(system_long_wq, &ap->hotplug_task,
                            round_jiffies_relative(HZ));
 }
 
@@ -3556,6 +3582,7 @@ void ata_scsi_hotplug(struct work_struct *work)
         }
 
         DPRINTK("ENTER\n");
+        mutex_lock(&ap->scsi_scan_mutex);
 
         /* Unplug detached devices.  We cannot use link iterator here
          * because PMP links have to be scanned even if PMP is
@@ -3569,6 +3596,7 @@ void ata_scsi_hotplug(struct work_struct *work)
         /* scan for new ones */
         ata_scsi_scan_host(ap, 0);
 
+        mutex_unlock(&ap->scsi_scan_mutex);
         DPRINTK("EXIT\n");
 }
 
@@ -3647,9 +3675,7 @@ static int ata_scsi_user_scan(struct Scsi_Host *shost, unsigned int channel,
  *      @work: Pointer to ATA port to perform scsi_rescan_device()
  *
  *      After ATA pass thru (SAT) commands are executed successfully,
- *      libata need to propagate the changes to SCSI layer.  This
- *      function must be executed from ata_aux_wq such that sdev
- *      attach/detach don't race with rescan.
+ *      libata need to propagate the changes to SCSI layer.
  *
  *      LOCKING:
  *      Kernel thread context (may sleep).
@@ -3662,6 +3688,7 @@ void ata_scsi_dev_rescan(struct work_struct *work)
         struct ata_device *dev;
         unsigned long flags;
 
+        mutex_lock(&ap->scsi_scan_mutex);
         spin_lock_irqsave(ap->lock, flags);
 
         ata_for_each_link(link, ap, EDGE) {
@@ -3681,6 +3708,7 @@ void ata_scsi_dev_rescan(struct work_struct *work)
         }
 
         spin_unlock_irqrestore(ap->lock, flags);
+        mutex_unlock(&ap->scsi_scan_mutex);
 }
 
 /**
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c
index e3877b6843c9..e30c537cce32 100644
--- a/drivers/ata/libata-sff.c
+++ b/drivers/ata/libata-sff.c
@@ -40,10 +40,12 @@
 
 #include "libata.h"
 
+static struct workqueue_struct *ata_sff_wq;
+
 const struct ata_port_operations ata_sff_port_ops = {
         .inherits               = &ata_base_port_ops,
 
-        .qc_prep                = ata_sff_qc_prep,
+        .qc_prep                = ata_noop_qc_prep,
         .qc_issue               = ata_sff_qc_issue,
         .qc_fill_rtf            = ata_sff_qc_fill_rtf,
 
@@ -53,9 +55,7 @@ const struct ata_port_operations ata_sff_port_ops = {
         .softreset              = ata_sff_softreset,
         .hardreset              = sata_sff_hardreset,
         .postreset              = ata_sff_postreset,
-        .drain_fifo             = ata_sff_drain_fifo,
         .error_handler          = ata_sff_error_handler,
-        .post_internal_cmd      = ata_sff_post_internal_cmd,
 
         .sff_dev_select         = ata_sff_dev_select,
         .sff_check_status       = ata_sff_check_status,
@@ -63,178 +63,12 @@ const struct ata_port_operations ata_sff_port_ops = {
         .sff_tf_read            = ata_sff_tf_read,
         .sff_exec_command       = ata_sff_exec_command,
         .sff_data_xfer          = ata_sff_data_xfer,
-        .sff_irq_on             = ata_sff_irq_on,
-        .sff_irq_clear          = ata_sff_irq_clear,
+        .sff_drain_fifo         = ata_sff_drain_fifo,
 
         .lost_interrupt         = ata_sff_lost_interrupt,
-
-        .port_start             = ata_sff_port_start,
 };
 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
 
-const struct ata_port_operations ata_bmdma_port_ops = {
-        .inherits               = &ata_sff_port_ops,
-
-        .mode_filter            = ata_bmdma_mode_filter,
-
-        .bmdma_setup            = ata_bmdma_setup,
-        .bmdma_start            = ata_bmdma_start,
-        .bmdma_stop             = ata_bmdma_stop,
-        .bmdma_status           = ata_bmdma_status,
-};
-EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
-
-const struct ata_port_operations ata_bmdma32_port_ops = {
-        .inherits               = &ata_bmdma_port_ops,
-
-        .sff_data_xfer          = ata_sff_data_xfer32,
-        .port_start             = ata_sff_port_start32,
-};
-EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
-
-/**
- *      ata_fill_sg - Fill PCI IDE PRD table
- *      @qc: Metadata associated with taskfile to be transferred
- *
- *      Fill PCI IDE PRD (scatter-gather) table with segments
- *      associated with the current disk command.
- *
- *      LOCKING:
- *      spin_lock_irqsave(host lock)
- *
- */
-static void ata_fill_sg(struct ata_queued_cmd *qc)
-{
-        struct ata_port *ap = qc->ap;
-        struct scatterlist *sg;
-        unsigned int si, pi;
-
-        pi = 0;
-        for_each_sg(qc->sg, sg, qc->n_elem, si) {
-                u32 addr, offset;
-                u32 sg_len, len;
-
-                /* determine if physical DMA addr spans 64K boundary.
-                 * Note h/w doesn't support 64-bit, so we unconditionally
-                 * truncate dma_addr_t to u32.
-                 */
-                addr = (u32) sg_dma_address(sg);
-                sg_len = sg_dma_len(sg);
-
-                while (sg_len) {
-                        offset = addr & 0xffff;
-                        len = sg_len;
-                        if ((offset + sg_len) > 0x10000)
-                                len = 0x10000 - offset;
-
-                        ap->prd[pi].addr = cpu_to_le32(addr);
-                        ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
-                        VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
-
-                        pi++;
-                        sg_len -= len;
-                        addr += len;
-                }
-        }
-
-        ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
-}
-
-/**
- *      ata_fill_sg_dumb - Fill PCI IDE PRD table
- *      @qc: Metadata associated with taskfile to be transferred
- *
- *      Fill PCI IDE PRD (scatter-gather) table with segments
- *      associated with the current disk command. Perform the fill
- *      so that we avoid writing any length 64K records for
- *      controllers that don't follow the spec.
- *
- *      LOCKING:
- *      spin_lock_irqsave(host lock)
- *
- */
-static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
-{
-        struct ata_port *ap = qc->ap;
-        struct scatterlist *sg;
-        unsigned int si, pi;
-
-        pi = 0;
-        for_each_sg(qc->sg, sg, qc->n_elem, si) {
-                u32 addr, offset;
-                u32 sg_len, len, blen;
-
-                /* determine if physical DMA addr spans 64K boundary.
-                 * Note h/w doesn't support 64-bit, so we unconditionally
-                 * truncate dma_addr_t to u32.
-                 */
-                addr = (u32) sg_dma_address(sg);
-                sg_len = sg_dma_len(sg);
-
-                while (sg_len) {
-                        offset = addr & 0xffff;
-                        len = sg_len;
-                        if ((offset + sg_len) > 0x10000)
-                                len = 0x10000 - offset;
-
-                        blen = len & 0xffff;
-                        ap->prd[pi].addr = cpu_to_le32(addr);
-                        if (blen == 0) {
-                                /* Some PATA chipsets like the CS5530 can't
-                                   cope with 0x0000 meaning 64K as the spec
-                                   says */
-                                ap->prd[pi].flags_len = cpu_to_le32(0x8000);
-                                blen = 0x8000;
-                                ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
-                        }
-                        ap->prd[pi].flags_len = cpu_to_le32(blen);
-                        VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
-
-                        pi++;
-                        sg_len -= len;
-                        addr += len;
-                }
-        }
-
-        ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
-}
-
-/**
- *      ata_sff_qc_prep - Prepare taskfile for submission
- *      @qc: Metadata associated with taskfile to be prepared
- *
- *      Prepare ATA taskfile for submission.
- *
- *      LOCKING:
- *      spin_lock_irqsave(host lock)
- */
-void ata_sff_qc_prep(struct ata_queued_cmd *qc)
-{
-        if (!(qc->flags & ATA_QCFLAG_DMAMAP))
-                return;
-
-        ata_fill_sg(qc);
-}
-EXPORT_SYMBOL_GPL(ata_sff_qc_prep);
-
-/**
- *      ata_sff_dumb_qc_prep - Prepare taskfile for submission
- *      @qc: Metadata associated with taskfile to be prepared
- *
- *      Prepare ATA taskfile for submission.
- *
- *      LOCKING:
- *      spin_lock_irqsave(host lock)
- */
-void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc)
-{
-        if (!(qc->flags & ATA_QCFLAG_DMAMAP))
-                return;
-
-        ata_fill_sg_dumb(qc);
-}
-EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep);
-
 /**
  *      ata_sff_check_status - Read device status reg & clear interrupt
  *      @ap: port where the device is
@@ -446,6 +280,27 @@ int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
 
 /**
+ *      ata_sff_set_devctl - Write device control reg
+ *      @ap: port where the device is
+ *      @ctl: value to write
+ *
+ *      Writes ATA taskfile device control register.
+ *
+ *      Note: may NOT be used as the sff_set_devctl() entry in
+ *      ata_port_operations.
+ *
+ *      LOCKING:
+ *      Inherited from caller.
+ */
+static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
+{
+        if (ap->ops->sff_set_devctl)
+                ap->ops->sff_set_devctl(ap, ctl);
+        else
+                iowrite8(ctl, ap->ioaddr.ctl_addr);
+}
+
+/**
  *      ata_sff_dev_select - Select device 0/1 on ATA bus
  *      @ap: ATA channel to manipulate
  *      @device: ATA device (numbered from zero) to select
@@ -491,7 +346,7 @@ EXPORT_SYMBOL_GPL(ata_sff_dev_select);
  *      LOCKING:
  *      caller.
  */
-void ata_dev_select(struct ata_port *ap, unsigned int device,
+static void ata_dev_select(struct ata_port *ap, unsigned int device,
                            unsigned int wait, unsigned int can_sleep)
 {
         if (ata_msg_probe(ap))
@@ -517,50 +372,34 @@ void ata_dev_select(struct ata_port *ap, unsigned int device,
  *      Enable interrupts on a legacy IDE device using MMIO or PIO,
  *      wait for idle, clear any pending interrupts.
  *
+ *      Note: may NOT be used as the sff_irq_on() entry in
+ *      ata_port_operations.
+ *
  *      LOCKING:
  *      Inherited from caller.
  */
-u8 ata_sff_irq_on(struct ata_port *ap)
+void ata_sff_irq_on(struct ata_port *ap)
 {
         struct ata_ioports *ioaddr = &ap->ioaddr;
-        u8 tmp;
+
+        if (ap->ops->sff_irq_on) {
+                ap->ops->sff_irq_on(ap);
+                return;
+        }
 
         ap->ctl &= ~ATA_NIEN;
         ap->last_ctl = ap->ctl;
 
-        if (ioaddr->ctl_addr)
-                iowrite8(ap->ctl, ioaddr->ctl_addr);
-        tmp = ata_wait_idle(ap);
-
-        ap->ops->sff_irq_clear(ap);
+        if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
+                ata_sff_set_devctl(ap, ap->ctl);
+        ata_wait_idle(ap);
 
-        return tmp;
+        if (ap->ops->sff_irq_clear)
+                ap->ops->sff_irq_clear(ap);
 }
 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
 
 /**
- *      ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt.
- *      @ap: Port associated with this ATA transaction.
- *
- *      Clear interrupt and error flags in DMA status register.
- *
- *      May be used as the irq_clear() entry in ata_port_operations.
- *
- *      LOCKING:
- *      spin_lock_irqsave(host lock)
- */
-void ata_sff_irq_clear(struct ata_port *ap)
-{
-        void __iomem *mmio = ap->ioaddr.bmdma_addr;
-
-        if (!mmio)
-                return;
-
-        iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
-}
-EXPORT_SYMBOL_GPL(ata_sff_irq_clear);
-
-/**
  *      ata_sff_tf_load - send taskfile registers to host controller
  *      @ap: Port to which output is sent
  *      @tf: ATA taskfile register set
@@ -894,7 +733,7 @@ static void ata_pio_sector(struct ata_queued_cmd *qc)
                                        do_write);
         }
 
-        if (!do_write)
+        if (!do_write && !PageSlab(page))
                 flush_dcache_page(page);
 
         qc->curbytes += qc->sect_size;
@@ -962,11 +801,15 @@ static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
         case ATAPI_PROT_NODATA:
                 ap->hsm_task_state = HSM_ST_LAST;
                 break;
+#ifdef CONFIG_ATA_BMDMA
         case ATAPI_PROT_DMA:
                 ap->hsm_task_state = HSM_ST_LAST;
                 /* initiate bmdma */
                 ap->ops->bmdma_start(qc);
                 break;
+#endif /* CONFIG_ATA_BMDMA */
+        default:
+                BUG();
         }
 }
 
@@ -1165,7 +1008,7 @@ static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
                         qc = ata_qc_from_tag(ap, qc->tag);
                         if (qc) {
                                 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
-                                        ap->ops->sff_irq_on(ap);
+                                        ata_sff_irq_on(ap);
                                         ata_qc_complete(qc);
                                 } else
                                         ata_port_freeze(ap);
@@ -1181,7 +1024,7 @@ static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
         } else {
                 if (in_wq) {
                         spin_lock_irqsave(ap->lock, flags);
-                        ap->ops->sff_irq_on(ap);
+                        ata_sff_irq_on(ap);
                         ata_qc_complete(qc);
                         spin_unlock_irqrestore(ap->lock, flags);
                 } else
@@ -1202,7 +1045,8 @@ static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
                      u8 status, int in_wq)
 {
-        struct ata_eh_info *ehi = &ap->link.eh_info;
+        struct ata_link *link = qc->dev->link;
+        struct ata_eh_info *ehi = &link->eh_info;
         unsigned long flags = 0;
         int poll_next;
 
@@ -1293,7 +1137,7 @@ fsm_start:
                 if (in_wq)
                         spin_unlock_irqrestore(ap->lock, flags);
 
-                /* if polling, ata_pio_task() handles the rest.
+                /* if polling, ata_sff_pio_task() handles the rest.
                  * otherwise, interrupt handler takes over from here.
                  */
                 break;
@@ -1458,14 +1302,48 @@ fsm_start:
 }
 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
 
-void ata_pio_task(struct work_struct *work)
+void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
+{
+        struct ata_port *ap = link->ap;
+
+        WARN_ON((ap->sff_pio_task_link != NULL) &&
+                (ap->sff_pio_task_link != link));
+        ap->sff_pio_task_link = link;
+
+        /* may fail if ata_sff_flush_pio_task() in progress */
+        queue_delayed_work(ata_sff_wq, &ap->sff_pio_task,
+                           msecs_to_jiffies(delay));
+}
+EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
+
+void ata_sff_flush_pio_task(struct ata_port *ap)
+{
+        DPRINTK("ENTER\n");
+
+        cancel_rearming_delayed_work(&ap->sff_pio_task);
+        ap->hsm_task_state = HSM_ST_IDLE;
+
+        if (ata_msg_ctl(ap))
+                ata_port_printk(ap, KERN_DEBUG, "%s: EXIT\n", __func__);
+}
+
+static void ata_sff_pio_task(struct work_struct *work)
 {
         struct ata_port *ap =
-                container_of(work, struct ata_port, port_task.work);
-        struct ata_queued_cmd *qc = ap->port_task_data;
+                container_of(work, struct ata_port, sff_pio_task.work);
+        struct ata_link *link = ap->sff_pio_task_link;
+        struct ata_queued_cmd *qc;
         u8 status;
         int poll_next;
 
+        BUG_ON(ap->sff_pio_task_link == NULL); 
+        /* qc can be NULL if timeout occurred */
+        qc = ata_qc_from_tag(ap, link->active_tag);
+        if (!qc) {
+                ap->sff_pio_task_link = NULL;
+                return;
+        }
+
 fsm_start:
         WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
 
@@ -1481,11 +1359,16 @@ fsm_start:
                 msleep(2);
                 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
                 if (status & ATA_BUSY) {
-                        ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
+                        ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
                         return;
                 }
         }
 
+        /*
+         * hsm_move() may trigger another command to be processed.
+         * clean the link beforehand.
+         */
+        ap->sff_pio_task_link = NULL;
         /* move the HSM */
         poll_next = ata_sff_hsm_move(ap, qc, status, 1);
 
@@ -1497,15 +1380,11 @@ fsm_start:
 }
 
 /**
- *      ata_sff_qc_issue - issue taskfile to device in proto-dependent manner
+ *      ata_sff_qc_issue - issue taskfile to a SFF controller
  *      @qc: command to issue to device
  *
- *      Using various libata functions and hooks, this function
- *      starts an ATA command.  ATA commands are grouped into
- *      classes called "protocols", and issuing each type of protocol
- *      is slightly different.
- *
- *      May be used as the qc_issue() entry in ata_port_operations.
+ *      This function issues a PIO or NODATA command to a SFF
+ *      controller.
  *
  *      LOCKING:
  *      spin_lock_irqsave(host lock)
@@ -1516,27 +1395,13 @@ fsm_start:
 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
 {
         struct ata_port *ap = qc->ap;
+        struct ata_link *link = qc->dev->link;
 
         /* Use polling pio if the LLD doesn't handle
          * interrupt driven pio and atapi CDB interrupt.
          */
-        if (ap->flags & ATA_FLAG_PIO_POLLING) {
-                switch (qc->tf.protocol) {
-                case ATA_PROT_PIO:
-                case ATA_PROT_NODATA:
-                case ATAPI_PROT_PIO:
-                case ATAPI_PROT_NODATA:
-                        qc->tf.flags |= ATA_TFLAG_POLLING;
-                        break;
-                case ATAPI_PROT_DMA:
-                        if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
-                                /* see ata_dma_blacklisted() */
-                                BUG();
-                        break;
-                default:
-                        break;
-                }
-        }
+        if (ap->flags & ATA_FLAG_PIO_POLLING)
+                qc->tf.flags |= ATA_TFLAG_POLLING;
 
         /* select the device */
         ata_dev_select(ap, qc->dev->devno, 1, 0);
@@ -1551,17 +1416,8 @@ unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
                 ap->hsm_task_state = HSM_ST_LAST;
 
                 if (qc->tf.flags & ATA_TFLAG_POLLING)
-                        ata_pio_queue_task(ap, qc, 0);
-
-                break;
-
-        case ATA_PROT_DMA:
-                WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
+                        ata_sff_queue_pio_task(link, 0);
 
-                ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
-                ap->ops->bmdma_setup(qc);           /* set up bmdma */
-                ap->ops->bmdma_start(qc);           /* initiate bmdma */
-                ap->hsm_task_state = HSM_ST_LAST;
                 break;
 
         case ATA_PROT_PIO:
@@ -1573,20 +1429,21 @@ unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
                 if (qc->tf.flags & ATA_TFLAG_WRITE) {
                         /* PIO data out protocol */
                         ap->hsm_task_state = HSM_ST_FIRST;
-                        ata_pio_queue_task(ap, qc, 0);
+                        ata_sff_queue_pio_task(link, 0);
 
-                        /* always send first data block using
-                         * the ata_pio_task() codepath.
+                        /* always send first data block using the
+                         * ata_sff_pio_task() codepath.
                          */
                 } else {
                         /* PIO data in protocol */
                         ap->hsm_task_state = HSM_ST;
 
                         if (qc->tf.flags & ATA_TFLAG_POLLING)
-                                ata_pio_queue_task(ap, qc, 0);
+                                ata_sff_queue_pio_task(link, 0);
 
-                        /* if polling, ata_pio_task() handles the rest.
-                         * otherwise, interrupt handler takes over from here.
+                        /* if polling, ata_sff_pio_task() handles the
+                         * rest.  otherwise, interrupt handler takes
+                         * over from here.
                          */
                 }
 
@@ -1604,19 +1461,7 @@ unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
                 /* send cdb by polling if no cdb interrupt */
                 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
                     (qc->tf.flags & ATA_TFLAG_POLLING))
-                        ata_pio_queue_task(ap, qc, 0);
-                break;
-
-        case ATAPI_PROT_DMA:
-                WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
-
-                ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
-                ap->ops->bmdma_setup(qc);           /* set up bmdma */
-                ap->hsm_task_state = HSM_ST_FIRST;
-
-                /* send cdb by polling if no cdb interrupt */
-                if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
-                        ata_pio_queue_task(ap, qc, 0);
+                        ata_sff_queue_pio_task(link, 0);
                 break;
 
         default:
@@ -1648,27 +1493,27 @@ bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
 }
 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
 
-/**
- *      ata_sff_host_intr - Handle host interrupt for given (port, task)
- *      @ap: Port on which interrupt arrived (possibly...)
- *      @qc: Taskfile currently active in engine
- *
- *      Handle host interrupt for given queued command.  Currently,
- *      only DMA interrupts are handled.  All other commands are
- *      handled via polling with interrupts disabled (nIEN bit).
- *
- *      LOCKING:
- *      spin_lock_irqsave(host lock)
- *
- *      RETURNS:
- *      One if interrupt was handled, zero if not (shared irq).
- */
-unsigned int ata_sff_host_intr(struct ata_port *ap,
-                                      struct ata_queued_cmd *qc)
+static unsigned int ata_sff_idle_irq(struct ata_port *ap)
 {
-        struct ata_eh_info *ehi = &ap->link.eh_info;
-        u8 status, host_stat = 0;
-        bool bmdma_stopped = false;
+        ap->stats.idle_irq++;
+
+#ifdef ATA_IRQ_TRAP
+        if ((ap->stats.idle_irq % 1000) == 0) {
+                ap->ops->sff_check_status(ap);
+                if (ap->ops->sff_irq_clear)
+                        ap->ops->sff_irq_clear(ap);
+                ata_port_printk(ap, KERN_WARNING, "irq trap\n");
+                return 1;
+        }
+#endif
+        return 0;       /* irq not handled */
+}
+
+static unsigned int __ata_sff_port_intr(struct ata_port *ap,
+                                        struct ata_queued_cmd *qc,
+                                        bool hsmv_on_idle)
+{
+        u8 status;
 
         VPRINTK("ata%u: protocol %d task_state %d\n",
                 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
@@ -1685,90 +1530,56 @@ unsigned int ata_sff_host_intr(struct ata_port *ap,
                  * need to check ata_is_atapi(qc->tf.protocol) again.
                  */
                 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
-                        goto idle_irq;
-                break;
-        case HSM_ST_LAST:
-                if (qc->tf.protocol == ATA_PROT_DMA ||
-                    qc->tf.protocol == ATAPI_PROT_DMA) {
-                        /* check status of DMA engine */
-                        host_stat = ap->ops->bmdma_status(ap);
-                        VPRINTK("ata%u: host_stat 0x%X\n",
-                                ap->print_id, host_stat);
-
-                        /* if it's not our irq... */
-                        if (!(host_stat & ATA_DMA_INTR))
-                                goto idle_irq;
-
-                        /* before we do anything else, clear DMA-Start bit */
-                        ap->ops->bmdma_stop(qc);
-                        bmdma_stopped = true;
-
-                        if (unlikely(host_stat & ATA_DMA_ERR)) {
-                                /* error when transfering data to/from memory */
-                                qc->err_mask |= AC_ERR_HOST_BUS;
-                                ap->hsm_task_state = HSM_ST_ERR;
-                        }
-                }
+                        return ata_sff_idle_irq(ap);
                 break;
         case HSM_ST:
+        case HSM_ST_LAST:
                 break;
         default:
-                goto idle_irq;
+                return ata_sff_idle_irq(ap);
         }
 
-
         /* check main status, clearing INTRQ if needed */
         status = ata_sff_irq_status(ap);
         if (status & ATA_BUSY) {
-                if (bmdma_stopped) {
+                if (hsmv_on_idle) {
                         /* BMDMA engine is already stopped, we're screwed */
                         qc->err_mask |= AC_ERR_HSM;
                         ap->hsm_task_state = HSM_ST_ERR;
                 } else
-                        goto idle_irq;
+                        return ata_sff_idle_irq(ap);
         }
 
-        /* ack bmdma irq events */
-        ap->ops->sff_irq_clear(ap);
+        /* clear irq events */
+        if (ap->ops->sff_irq_clear)
+                ap->ops->sff_irq_clear(ap);
 
         ata_sff_hsm_move(ap, qc, status, 0);
 
-        if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
-                                       qc->tf.protocol == ATAPI_PROT_DMA))
-                ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
-
         return 1;       /* irq handled */
-
-idle_irq:
-        ap->stats.idle_irq++;
-
-#ifdef ATA_IRQ_TRAP
-        if ((ap->stats.idle_irq % 1000) == 0) {
-                ap->ops->sff_check_status(ap);
-                ap->ops->sff_irq_clear(ap);
-                ata_port_printk(ap, KERN_WARNING, "irq trap\n");
-                return 1;
-        }
-#endif
-        return 0;       /* irq not handled */
 }
-EXPORT_SYMBOL_GPL(ata_sff_host_intr);
 
 /**
- *      ata_sff_interrupt - Default ATA host interrupt handler
- *      @irq: irq line (unused)
- *      @dev_instance: pointer to our ata_host information structure
+ *      ata_sff_port_intr - Handle SFF port interrupt
+ *      @ap: Port on which interrupt arrived (possibly...)
+ *      @qc: Taskfile currently active in engine
  *
- *      Default interrupt handler for PCI IDE devices.  Calls
- *      ata_sff_host_intr() for each port that is not disabled.
+ *      Handle port interrupt for given queued command.
  *
  *      LOCKING:
- *      Obtains host lock during operation.
+ *      spin_lock_irqsave(host lock)
  *
  *      RETURNS:
- *      IRQ_NONE or IRQ_HANDLED.
+ *      One if interrupt was handled, zero if not (shared irq).
  */
-irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
+unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
+{
+        return __ata_sff_port_intr(ap, qc, false);
+}
+EXPORT_SYMBOL_GPL(ata_sff_port_intr);
+
+static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
+        unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
 {
         struct ata_host *host = dev_instance;
         bool retried = false;
@@ -1785,13 +1596,10 @@ retry:
                 struct ata_port *ap = host->ports[i];
                 struct ata_queued_cmd *qc;
 
-                if (unlikely(ap->flags & ATA_FLAG_DISABLED))
-                        continue;
-
                 qc = ata_qc_from_tag(ap, ap->link.active_tag);
                 if (qc) {
                         if (!(qc->tf.flags & ATA_TFLAG_POLLING))
-                                handled |= ata_sff_host_intr(ap, qc);
+                                handled |= port_intr(ap, qc);
                         else
                                 polling |= 1 << i;
                 } else
@@ -1818,7 +1626,8 @@ retry:
 
                         if (idle & (1 << i)) {
                                 ap->ops->sff_check_status(ap);
-                                ap->ops->sff_irq_clear(ap);
+                                if (ap->ops->sff_irq_clear)
+                                        ap->ops->sff_irq_clear(ap);
                         } else {
                                 /* clear INTRQ and check if BUSY cleared */
                                 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
@@ -1840,6 +1649,25 @@ retry:
 
         return IRQ_RETVAL(handled);
 }
+
+/**
+ *      ata_sff_interrupt - Default SFF ATA host interrupt handler
+ *      @irq: irq line (unused)
+ *      @dev_instance: pointer to our ata_host information structure
+ *
+ *      Default interrupt handler for PCI IDE devices.  Calls
+ *      ata_sff_port_intr() for each port that is not disabled.
+ *
+ *      LOCKING:
+ *      Obtains host lock during operation.
+ *
+ *      RETURNS:
+ *      IRQ_NONE or IRQ_HANDLED.
+ */
+irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
+{
+        return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
+}
 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
 
 /**
@@ -1862,11 +1690,8 @@ void ata_sff_lost_interrupt(struct ata_port *ap)
 
         /* Only one outstanding command per SFF channel */
         qc = ata_qc_from_tag(ap, ap->link.active_tag);
-        /* Check we have a live one.. */
-        if (qc == NULL ||  !(qc->flags & ATA_QCFLAG_ACTIVE))
-                return;
-        /* We cannot lose an interrupt on a polled command */
-        if (qc->tf.flags & ATA_TFLAG_POLLING)
+        /* We cannot lose an interrupt on a non-existent or polled command */
+        if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
                 return;
         /* See if the controller thinks it is still busy - if so the command
            isn't a lost IRQ but is still in progress */
@@ -1880,7 +1705,7 @@ void ata_sff_lost_interrupt(struct ata_port *ap)
                                                                 status);
         /* Run the host interrupt logic as if the interrupt had not been
            lost */
-        ata_sff_host_intr(ap, qc);
+        ata_sff_port_intr(ap, qc);
 }
 EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
 
@@ -1888,20 +1713,18 @@ EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
  *      ata_sff_freeze - Freeze SFF controller port
  *      @ap: port to freeze
  *
- *      Freeze BMDMA controller port.
+ *      Freeze SFF controller port.
  *
  *      LOCKING:
  *      Inherited from caller.
  */
 void ata_sff_freeze(struct ata_port *ap)
 {
-        struct ata_ioports *ioaddr = &ap->ioaddr;
-
         ap->ctl |= ATA_NIEN;
         ap->last_ctl = ap->ctl;
 
-        if (ioaddr->ctl_addr)
-                iowrite8(ap->ctl, ioaddr->ctl_addr);
+        if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
+                ata_sff_set_devctl(ap, ap->ctl);
 
         /* Under certain circumstances, some controllers raise IRQ on
          * ATA_NIEN manipulation.  Also, many controllers fail to mask
@@ -1909,7 +1732,8 @@ void ata_sff_freeze(struct ata_port *ap)
          */
         ap->ops->sff_check_status(ap);
 
-        ap->ops->sff_irq_clear(ap);
+        if (ap->ops->sff_irq_clear)
+                ap->ops->sff_irq_clear(ap);
 }
 EXPORT_SYMBOL_GPL(ata_sff_freeze);
 
@@ -1926,8 +1750,9 @@ void ata_sff_thaw(struct ata_port *ap)
 {
         /* clear & re-enable interrupts */
         ap->ops->sff_check_status(ap);
-        ap->ops->sff_irq_clear(ap);
-        ap->ops->sff_irq_on(ap);
+        if (ap->ops->sff_irq_clear)
+                ap->ops->sff_irq_clear(ap);
+        ata_sff_irq_on(ap);
 }
 EXPORT_SYMBOL_GPL(ata_sff_thaw);
 
@@ -2301,8 +2126,8 @@ void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
         }
 
         /* set up device control */
-        if (ap->ioaddr.ctl_addr) {
-                iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
+        if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
+                ata_sff_set_devctl(ap, ap->ctl);
                 ap->last_ctl = ap->ctl;
         }
 }
@@ -2342,7 +2167,7 @@ void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
 EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
 
 /**
- *      ata_sff_error_handler - Stock error handler for BMDMA controller
+ *      ata_sff_error_handler - Stock error handler for SFF controller
  *      @ap: port to handle error for
  *
  *      Stock error handler for SFF controller.  It can handle both
@@ -2359,62 +2184,32 @@ void ata_sff_error_handler(struct ata_port *ap)
         ata_reset_fn_t hardreset = ap->ops->hardreset;
         struct ata_queued_cmd *qc;
         unsigned long flags;
-        int thaw = 0;
 
         qc = __ata_qc_from_tag(ap, ap->link.active_tag);
         if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
                 qc = NULL;
 
-        /* reset PIO HSM and stop DMA engine */
         spin_lock_irqsave(ap->lock, flags);
 
-        ap->hsm_task_state = HSM_ST_IDLE;
-
-        if (ap->ioaddr.bmdma_addr &&
-            qc && (qc->tf.protocol == ATA_PROT_DMA ||
-                   qc->tf.protocol == ATAPI_PROT_DMA)) {
-                u8 host_stat;
-
-                host_stat = ap->ops->bmdma_status(ap);
-
-                /* BMDMA controllers indicate host bus error by
-                 * setting DMA_ERR bit and timing out.  As it wasn't
-                 * really a timeout event, adjust error mask and
-                 * cancel frozen state.
-                 */
-                if (qc->err_mask == AC_ERR_TIMEOUT
-                                                && (host_stat & ATA_DMA_ERR)) {
-                        qc->err_mask = AC_ERR_HOST_BUS;
-                        thaw = 1;
-                }
-
-                ap->ops->bmdma_stop(qc);
-        }
-
-        ata_sff_sync(ap);               /* FIXME: We don't need this */
-        ap->ops->sff_check_status(ap);
-        ap->ops->sff_irq_clear(ap);
-        /* We *MUST* do FIFO draining before we issue a reset as several
-         * devices helpfully clear their internal state and will lock solid
-         * if we touch the data port post reset. Pass qc in case anyone wants
-         *  to do different PIO/DMA recovery or has per command fixups
+        /*
+         * We *MUST* do FIFO draining before we issue a reset as
+         * several devices helpfully clear their internal state and
+         * will lock solid if we touch the data port post reset. Pass
+         * qc in case anyone wants to do different PIO/DMA recovery or
+         * has per command fixups
          */
-        if (ap->ops->drain_fifo)
-                ap->ops->drain_fifo(qc);
+        if (ap->ops->sff_drain_fifo)
+                ap->ops->sff_drain_fifo(qc);
 
         spin_unlock_irqrestore(ap->lock, flags);
 
-        if (thaw)
-                ata_eh_thaw_port(ap);
-
-        /* PIO and DMA engines have been stopped, perform recovery */
-
-        /* Ignore ata_sff_softreset if ctl isn't accessible and
-         * built-in hardresets if SCR access isn't available.
-         */
+        /* ignore ata_sff_softreset if ctl isn't accessible */
         if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
                 softreset = NULL;
-        if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link))
+
+        /* ignore built-in hardresets if SCR access is not available */
+        if ((hardreset == sata_std_hardreset ||
+             hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
                 hardreset = NULL;
 
         ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
@@ -2423,73 +2218,6 @@ void ata_sff_error_handler(struct ata_port *ap)
 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
 
 /**
- *      ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller
- *      @qc: internal command to clean up
- *
- *      LOCKING:
- *      Kernel thread context (may sleep)
- */
-void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc)
-{
-        struct ata_port *ap = qc->ap;
-        unsigned long flags;
-
-        spin_lock_irqsave(ap->lock, flags);
-
-        ap->hsm_task_state = HSM_ST_IDLE;
-
-        if (ap->ioaddr.bmdma_addr)
-                ap->ops->bmdma_stop(qc);
-
-        spin_unlock_irqrestore(ap->lock, flags);
-}
-EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd);
-
-/**
- *      ata_sff_port_start - Set port up for dma.
- *      @ap: Port to initialize
- *
- *      Called just after data structures for each port are
- *      initialized.  Allocates space for PRD table if the device
- *      is DMA capable SFF.
- *
- *      May be used as the port_start() entry in ata_port_operations.
- *
- *      LOCKING:
- *      Inherited from caller.
- */
-int ata_sff_port_start(struct ata_port *ap)
-{
-        if (ap->ioaddr.bmdma_addr)
-                return ata_port_start(ap);
-        return 0;
-}
-EXPORT_SYMBOL_GPL(ata_sff_port_start);
-
-/**
- *      ata_sff_port_start32 - Set port up for dma.
- *      @ap: Port to initialize
- *
- *      Called just after data structures for each port are
- *      initialized.  Allocates space for PRD table if the device
- *      is DMA capable SFF.
- *
- *      May be used as the port_start() entry in ata_port_operations for
- *      devices that are capable of 32bit PIO.
- *
- *      LOCKING:
- *      Inherited from caller.
- */
-int ata_sff_port_start32(struct ata_port *ap)
-{
-        ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
-        if (ap->ioaddr.bmdma_addr)
-                return ata_port_start(ap);
-        return 0;
-}
-EXPORT_SYMBOL_GPL(ata_sff_port_start32);
-
-/**
  *      ata_sff_std_ports - initialize ioaddr with standard port offsets.
  *      @ioaddr: IO address structure to be initialized
  *
@@ -2515,302 +2243,8 @@ void ata_sff_std_ports(struct ata_ioports *ioaddr)
 }
 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
 
-unsigned long ata_bmdma_mode_filter(struct ata_device *adev,
-                                    unsigned long xfer_mask)
-{
-        /* Filter out DMA modes if the device has been configured by
-           the BIOS as PIO only */
-
-        if (adev->link->ap->ioaddr.bmdma_addr == NULL)
-                xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
-        return xfer_mask;
-}
-EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter);
-
-/**
- *      ata_bmdma_setup - Set up PCI IDE BMDMA transaction
- *      @qc: Info associated with this ATA transaction.
- *
- *      LOCKING:
- *      spin_lock_irqsave(host lock)
- */
-void ata_bmdma_setup(struct ata_queued_cmd *qc)
-{
-        struct ata_port *ap = qc->ap;
-        unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
-        u8 dmactl;
-
-        /* load PRD table addr. */
-        mb();   /* make sure PRD table writes are visible to controller */
-        iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
-
-        /* specify data direction, triple-check start bit is clear */
-        dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
-        dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
-        if (!rw)
-                dmactl |= ATA_DMA_WR;
-        iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
-
-        /* issue r/w command */
-        ap->ops->sff_exec_command(ap, &qc->tf);
-}
-EXPORT_SYMBOL_GPL(ata_bmdma_setup);
-
-/**
- *      ata_bmdma_start - Start a PCI IDE BMDMA transaction
- *      @qc: Info associated with this ATA transaction.
- *
- *      LOCKING:
- *      spin_lock_irqsave(host lock)
- */
-void ata_bmdma_start(struct ata_queued_cmd *qc)
-{
-        struct ata_port *ap = qc->ap;
-        u8 dmactl;
-
-        /* start host DMA transaction */
-        dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
-        iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
-
-        /* Strictly, one may wish to issue an ioread8() here, to
-         * flush the mmio write.  However, control also passes
-         * to the hardware at this point, and it will interrupt
-         * us when we are to resume control.  So, in effect,
-         * we don't care when the mmio write flushes.
-         * Further, a read of the DMA status register _immediately_
-         * following the write may not be what certain flaky hardware
-         * is expected, so I think it is best to not add a readb()
-         * without first all the MMIO ATA cards/mobos.
-         * Or maybe I'm just being paranoid.
-         *
-         * FIXME: The posting of this write means I/O starts are
-         * unneccessarily delayed for MMIO
-         */
-}
-EXPORT_SYMBOL_GPL(ata_bmdma_start);
-
-/**
- *      ata_bmdma_stop - Stop PCI IDE BMDMA transfer
- *      @qc: Command we are ending DMA for
- *
- *      Clears the ATA_DMA_START flag in the dma control register
- *
- *      May be used as the bmdma_stop() entry in ata_port_operations.
- *
- *      LOCKING:
- *      spin_lock_irqsave(host lock)
- */
-void ata_bmdma_stop(struct ata_queued_cmd *qc)
-{
-        struct ata_port *ap = qc->ap;
-        void __iomem *mmio = ap->ioaddr.bmdma_addr;
-
-        /* clear start/stop bit */
-        iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
-                 mmio + ATA_DMA_CMD);
-
-        /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
-        ata_sff_dma_pause(ap);
-}
-EXPORT_SYMBOL_GPL(ata_bmdma_stop);
-
-/**
- *      ata_bmdma_status - Read PCI IDE BMDMA status
- *      @ap: Port associated with this ATA transaction.
- *
- *      Read and return BMDMA status register.
- *
- *      May be used as the bmdma_status() entry in ata_port_operations.
- *
- *      LOCKING:
- *      spin_lock_irqsave(host lock)
- */
-u8 ata_bmdma_status(struct ata_port *ap)
-{
-        return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
-}
-EXPORT_SYMBOL_GPL(ata_bmdma_status);
-
-/**
- *      ata_bus_reset - reset host port and associated ATA channel
- *      @ap: port to reset
- *
- *      This is typically the first time we actually start issuing
- *      commands to the ATA channel.  We wait for BSY to clear, then
- *      issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
- *      result.  Determine what devices, if any, are on the channel
- *      by looking at the device 0/1 error register.  Look at the signature
- *      stored in each device's taskfile registers, to determine if
- *      the device is ATA or ATAPI.
- *
- *      LOCKING:
- *      PCI/etc. bus probe sem.
- *      Obtains host lock.
- *
- *      SIDE EFFECTS:
- *      Sets ATA_FLAG_DISABLED if bus reset fails.
- *
- *      DEPRECATED:
- *      This function is only for drivers which still use old EH and
- *      will be removed soon.
- */
-void ata_bus_reset(struct ata_port *ap)
-{
-        struct ata_device *device = ap->link.device;
-        struct ata_ioports *ioaddr = &ap->ioaddr;
-        unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
-        u8 err;
-        unsigned int dev0, dev1 = 0, devmask = 0;
-        int rc;
-
-        DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no);
-
-        /* determine if device 0/1 are present */
-        if (ap->flags & ATA_FLAG_SATA_RESET)
-                dev0 = 1;
-        else {
-                dev0 = ata_devchk(ap, 0);
-                if (slave_possible)
-                        dev1 = ata_devchk(ap, 1);
-        }
-
-        if (dev0)
-                devmask |= (1 << 0);
-        if (dev1)
-                devmask |= (1 << 1);
-
-        /* select device 0 again */
-        ap->ops->sff_dev_select(ap, 0);
-
-        /* issue bus reset */
-        if (ap->flags & ATA_FLAG_SRST) {
-                rc = ata_bus_softreset(ap, devmask,
-                                       ata_deadline(jiffies, 40000));
-                if (rc && rc != -ENODEV)
-                        goto err_out;
-        }
-
-        /*
-         * determine by signature whether we have ATA or ATAPI devices
-         */
-        device[0].class = ata_sff_dev_classify(&device[0], dev0, &err);
-        if ((slave_possible) && (err != 0x81))
-                device[1].class = ata_sff_dev_classify(&device[1], dev1, &err);
-
-        /* is double-select really necessary? */
-        if (device[1].class != ATA_DEV_NONE)
-                ap->ops->sff_dev_select(ap, 1);
-        if (device[0].class != ATA_DEV_NONE)
-                ap->ops->sff_dev_select(ap, 0);
-
-        /* if no devices were detected, disable this port */
-        if ((device[0].class == ATA_DEV_NONE) &&
-            (device[1].class == ATA_DEV_NONE))
-                goto err_out;
-
-        if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
-                /* set up device control for ATA_FLAG_SATA_RESET */
-                iowrite8(ap->ctl, ioaddr->ctl_addr);
-                ap->last_ctl = ap->ctl;
-        }
-
-        DPRINTK("EXIT\n");
-        return;
-
-err_out:
-        ata_port_printk(ap, KERN_ERR, "disabling port\n");
-        ata_port_disable(ap);
-
-        DPRINTK("EXIT\n");
-}
-EXPORT_SYMBOL_GPL(ata_bus_reset);
-
 #ifdef CONFIG_PCI
 
-/**
- *      ata_pci_bmdma_clear_simplex -   attempt to kick device out of simplex
- *      @pdev: PCI device
- *
- *      Some PCI ATA devices report simplex mode but in fact can be told to
- *      enter non simplex mode. This implements the necessary logic to
- *      perform the task on such devices. Calling it on other devices will
- *      have -undefined- behaviour.
- */
-int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
-{
-        unsigned long bmdma = pci_resource_start(pdev, 4);
-        u8 simplex;
-
-        if (bmdma == 0)
-                return -ENOENT;
-
-        simplex = inb(bmdma + 0x02);
-        outb(simplex & 0x60, bmdma + 0x02);
-        simplex = inb(bmdma + 0x02);
-        if (simplex & 0x80)
-                return -EOPNOTSUPP;
-        return 0;
-}
-EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
-
-/**
- *      ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
- *      @host: target ATA host
- *
- *      Acquire PCI BMDMA resources and initialize @host accordingly.
- *
- *      LOCKING:
- *      Inherited from calling layer (may sleep).
- *
- *      RETURNS:
- *      0 on success, -errno otherwise.
- */
-int ata_pci_bmdma_init(struct ata_host *host)
-{
-        struct device *gdev = host->dev;
-        struct pci_dev *pdev = to_pci_dev(gdev);
-        int i, rc;
-
-        /* No BAR4 allocation: No DMA */
-        if (pci_resource_start(pdev, 4) == 0)
-                return 0;
-
-        /* TODO: If we get no DMA mask we should fall back to PIO */
-        rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
-        if (rc)
-                return rc;
-        rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
-        if (rc)
-                return rc;
-
-        /* request and iomap DMA region */
-        rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
-        if (rc) {
-                dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
-                return -ENOMEM;
-        }
-        host->iomap = pcim_iomap_table(pdev);
-
-        for (i = 0; i < 2; i++) {
-                struct ata_port *ap = host->ports[i];
-                void __iomem *bmdma = host->iomap[4] + 8 * i;
-
-                if (ata_port_is_dummy(ap))
-                        continue;
-
-                ap->ioaddr.bmdma_addr = bmdma;
-                if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
-                    (ioread8(bmdma + 2) & 0x80))
-                        host->flags |= ATA_HOST_SIMPLEX;
-
-                ata_port_desc(ap, "bmdma 0x%llx",
-                    (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
-        }
-
-        return 0;
-}
-EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
-
 static int ata_resources_present(struct pci_dev *pdev, int port)
 {
         int i;
@@ -2905,13 +2339,13 @@ int ata_pci_sff_init_host(struct ata_host *host)
 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
 
 /**
- *      ata_pci_sff_prepare_host - helper to prepare native PCI ATA host
+ *      ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
  *      @pdev: target PCI device
  *      @ppi: array of port_info, must be enough for two ports
  *      @r_host: out argument for the initialized ATA host
  *
- *      Helper to allocate ATA host for @pdev, acquire all native PCI
- *      resources and initialize it accordingly in one go.
+ *      Helper to allocate PIO-only SFF ATA host for @pdev, acquire
+ *      all PCI resources and initialize it accordingly in one go.
  *
  *      LOCKING:
  *      Inherited from calling layer (may sleep).
@@ -2941,22 +2375,10 @@ int ata_pci_sff_prepare_host(struct pci_dev *pdev,
         if (rc)
                 goto err_out;
 
-        /* init DMA related stuff */
-        rc = ata_pci_bmdma_init(host);
-        if (rc)
-                goto err_bmdma;
-
         devres_remove_group(&pdev->dev, NULL);
         *r_host = host;
         return 0;
 
-err_bmdma:
-        /* This is necessary because PCI and iomap resources are
-         * merged and releasing the top group won't release the
-         * acquired resources if some of those have been acquired
-         * before entering this function.
-         */
-        pcim_iounmap_regions(pdev, 0xf);
 err_out:
         devres_release_group(&pdev->dev, NULL);
         return rc;
@@ -3057,8 +2479,21 @@ out:
 }
 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
 
+static const struct ata_port_info *ata_sff_find_valid_pi(
+                                        const struct ata_port_info * const *ppi)
+{
+        int i;
+
+        /* look up the first valid port_info */
+        for (i = 0; i < 2 && ppi[i]; i++)
+                if (ppi[i]->port_ops != &ata_dummy_port_ops)
+                        return ppi[i];
+
+        return NULL;
+}
+
 /**
- *      ata_pci_sff_init_one - Initialize/register PCI IDE host controller
+ *      ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
  *      @pdev: Controller to be initialized
  *      @ppi: array of port_info, must be enough for two ports
  *      @sht: scsi_host_template to use when registering the host
@@ -3067,11 +2502,7 @@ EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
  *
  *      This is a helper function which can be called from a driver's
  *      xxx_init_one() probe function if the hardware uses traditional
- *      IDE taskfile registers.
- *
- *      This function calls pci_enable_device(), reserves its register
- *      regions, sets the dma mask, enables bus master mode, and calls
- *      ata_device_add()
+ *      IDE taskfile registers and is PIO only.
  *
  *      ASSUMPTION:
  *      Nobody makes a single channel controller that appears solely as
@@ -3088,20 +2519,13 @@ int ata_pci_sff_init_one(struct pci_dev *pdev,
                  struct scsi_host_template *sht, void *host_priv, int hflag)
 {
         struct device *dev = &pdev->dev;
-        const struct ata_port_info *pi = NULL;
+        const struct ata_port_info *pi;
         struct ata_host *host = NULL;
-        int i, rc;
+        int rc;
 
         DPRINTK("ENTER\n");
 
-        /* look up the first valid port_info */
-        for (i = 0; i < 2 && ppi[i]; i++) {
-                if (ppi[i]->port_ops != &ata_dummy_port_ops) {
-                        pi = ppi[i];
-                        break;
-                }
-        }
-
+        pi = ata_sff_find_valid_pi(ppi);
         if (!pi) {
                 dev_printk(KERN_ERR, &pdev->dev,
                            "no valid port_info specified\n");
@@ -3122,7 +2546,6 @@ int ata_pci_sff_init_one(struct pci_dev *pdev,
         host->private_data = host_priv;
         host->flags |= hflag;
 
-        pci_set_master(pdev);
         rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
 out:
         if (rc == 0)
@@ -3135,3 +2558,791 @@ out:
 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
 
 #endif /* CONFIG_PCI */
+
+/*
+ *      BMDMA support
+ */
+
+#ifdef CONFIG_ATA_BMDMA
+
+const struct ata_port_operations ata_bmdma_port_ops = {
+        .inherits               = &ata_sff_port_ops,
+
+        .error_handler          = ata_bmdma_error_handler,
+        .post_internal_cmd      = ata_bmdma_post_internal_cmd,
+
+        .qc_prep                = ata_bmdma_qc_prep,
+        .qc_issue               = ata_bmdma_qc_issue,
+
+        .sff_irq_clear          = ata_bmdma_irq_clear,
+        .bmdma_setup            = ata_bmdma_setup,
+        .bmdma_start            = ata_bmdma_start,
+        .bmdma_stop             = ata_bmdma_stop,
+        .bmdma_status           = ata_bmdma_status,
+
+        .port_start             = ata_bmdma_port_start,
+};
+EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
+
+const struct ata_port_operations ata_bmdma32_port_ops = {
+        .inherits               = &ata_bmdma_port_ops,
+
+        .sff_data_xfer          = ata_sff_data_xfer32,
+        .port_start             = ata_bmdma_port_start32,
+};
+EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
+
+/**
+ *      ata_bmdma_fill_sg - Fill PCI IDE PRD table
+ *      @qc: Metadata associated with taskfile to be transferred
+ *
+ *      Fill PCI IDE PRD (scatter-gather) table with segments
+ *      associated with the current disk command.
+ *
+ *      LOCKING:
+ *      spin_lock_irqsave(host lock)
+ *
+ */
+static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
+{
+        struct ata_port *ap = qc->ap;
+        struct ata_bmdma_prd *prd = ap->bmdma_prd;
+        struct scatterlist *sg;
+        unsigned int si, pi;
+
+        pi = 0;
+        for_each_sg(qc->sg, sg, qc->n_elem, si) {
+                u32 addr, offset;
+                u32 sg_len, len;
+
+                /* determine if physical DMA addr spans 64K boundary.
+                 * Note h/w doesn't support 64-bit, so we unconditionally
+                 * truncate dma_addr_t to u32.
+                 */
+                addr = (u32) sg_dma_address(sg);
+                sg_len = sg_dma_len(sg);
+
+                while (sg_len) {
+                        offset = addr & 0xffff;
+                        len = sg_len;
+                        if ((offset + sg_len) > 0x10000)
+                                len = 0x10000 - offset;
+
+                        prd[pi].addr = cpu_to_le32(addr);
+                        prd[pi].flags_len = cpu_to_le32(len & 0xffff);
+                        VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
+
+                        pi++;
+                        sg_len -= len;
+                        addr += len;
+                }
+        }
+
+        prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
+}
+
+/**
+ *      ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
+ *      @qc: Metadata associated with taskfile to be transferred
+ *
+ *      Fill PCI IDE PRD (scatter-gather) table with segments
+ *      associated with the current disk command. Perform the fill
+ *      so that we avoid writing any length 64K records for
+ *      controllers that don't follow the spec.
+ *
+ *      LOCKING:
+ *      spin_lock_irqsave(host lock)
+ *
+ */
+static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
+{
+        struct ata_port *ap = qc->ap;
+        struct ata_bmdma_prd *prd = ap->bmdma_prd;
+        struct scatterlist *sg;
+        unsigned int si, pi;
+
+        pi = 0;
+        for_each_sg(qc->sg, sg, qc->n_elem, si) {
+                u32 addr, offset;
+                u32 sg_len, len, blen;
+
+                /* determine if physical DMA addr spans 64K boundary.
+                 * Note h/w doesn't support 64-bit, so we unconditionally
+                 * truncate dma_addr_t to u32.
+                 */
+                addr = (u32) sg_dma_address(sg);
+                sg_len = sg_dma_len(sg);
+
+                while (sg_len) {
+                        offset = addr & 0xffff;
+                        len = sg_len;
+                        if ((offset + sg_len) > 0x10000)
+                                len = 0x10000 - offset;
+
+                        blen = len & 0xffff;
+                        prd[pi].addr = cpu_to_le32(addr);
+                        if (blen == 0) {
+                                /* Some PATA chipsets like the CS5530 can't
+                                   cope with 0x0000 meaning 64K as the spec
+                                   says */
+                                prd[pi].flags_len = cpu_to_le32(0x8000);
+                                blen = 0x8000;
+                                prd[++pi].addr = cpu_to_le32(addr + 0x8000);
+                        }
+                        prd[pi].flags_len = cpu_to_le32(blen);
+                        VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
+
+                        pi++;
+                        sg_len -= len;
+                        addr += len;
+                }
+        }
+
+        prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
+}
+
+/**
+ *      ata_bmdma_qc_prep - Prepare taskfile for submission
+ *      @qc: Metadata associated with taskfile to be prepared
+ *
+ *      Prepare ATA taskfile for submission.
+ *
+ *      LOCKING:
+ *      spin_lock_irqsave(host lock)
+ */
+void ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
+{
+        if (!(qc->flags & ATA_QCFLAG_DMAMAP))
+                return;
+
+        ata_bmdma_fill_sg(qc);
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
+
+/**
+ *      ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
+ *      @qc: Metadata associated with taskfile to be prepared
+ *
+ *      Prepare ATA taskfile for submission.
+ *
+ *      LOCKING:
+ *      spin_lock_irqsave(host lock)
+ */
+void ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
+{
+        if (!(qc->flags & ATA_QCFLAG_DMAMAP))
+                return;
+
+        ata_bmdma_fill_sg_dumb(qc);
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
+
+/**
+ *      ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
+ *      @qc: command to issue to device
+ *
+ *      This function issues a PIO, NODATA or DMA command to a
+ *      SFF/BMDMA controller.  PIO and NODATA are handled by
+ *      ata_sff_qc_issue().
+ *
+ *      LOCKING:
+ *      spin_lock_irqsave(host lock)
+ *
+ *      RETURNS:
+ *      Zero on success, AC_ERR_* mask on failure
+ */
+unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
+{
+        struct ata_port *ap = qc->ap;
+        struct ata_link *link = qc->dev->link;
+
+        /* defer PIO handling to sff_qc_issue */
+        if (!ata_is_dma(qc->tf.protocol))
+                return ata_sff_qc_issue(qc);
+
+        /* select the device */
+        ata_dev_select(ap, qc->dev->devno, 1, 0);
+
+        /* start the command */
+        switch (qc->tf.protocol) {
+        case ATA_PROT_DMA:
+                WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
+
+                ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
+                ap->ops->bmdma_setup(qc);           /* set up bmdma */
+                ap->ops->bmdma_start(qc);           /* initiate bmdma */
+                ap->hsm_task_state = HSM_ST_LAST;
+                break;
+
+        case ATAPI_PROT_DMA:
+                WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
+
+                ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
+                ap->ops->bmdma_setup(qc);           /* set up bmdma */
+                ap->hsm_task_state = HSM_ST_FIRST;
+
+                /* send cdb by polling if no cdb interrupt */
+                if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
+                        ata_sff_queue_pio_task(link, 0);
+                break;
+
+        default:
+                WARN_ON(1);
+                return AC_ERR_SYSTEM;
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
+
+/**
+ *      ata_bmdma_port_intr - Handle BMDMA port interrupt
+ *      @ap: Port on which interrupt arrived (possibly...)
+ *      @qc: Taskfile currently active in engine
+ *
+ *      Handle port interrupt for given queued command.
+ *
+ *      LOCKING:
+ *      spin_lock_irqsave(host lock)
+ *
+ *      RETURNS:
+ *      One if interrupt was handled, zero if not (shared irq).
+ */
+unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
+{
+        struct ata_eh_info *ehi = &ap->link.eh_info;
+        u8 host_stat = 0;
+        bool bmdma_stopped = false;
+        unsigned int handled;
+
+        if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
+                /* check status of DMA engine */
+                host_stat = ap->ops->bmdma_status(ap);
+                VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat);
+
+                /* if it's not our irq... */
+                if (!(host_stat & ATA_DMA_INTR))
+                        return ata_sff_idle_irq(ap);
+
+                /* before we do anything else, clear DMA-Start bit */
+                ap->ops->bmdma_stop(qc);
+                bmdma_stopped = true;
+
+                if (unlikely(host_stat & ATA_DMA_ERR)) {
+                        /* error when transfering data to/from memory */
+                        qc->err_mask |= AC_ERR_HOST_BUS;
+                        ap->hsm_task_state = HSM_ST_ERR;
+                }
+        }
+
+        handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
+
+        if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
+                ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
+
+        return handled;
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
+
+/**
+ *      ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
+ *      @irq: irq line (unused)
+ *      @dev_instance: pointer to our ata_host information structure
+ *
+ *      Default interrupt handler for PCI IDE devices.  Calls
+ *      ata_bmdma_port_intr() for each port that is not disabled.
+ *
+ *      LOCKING:
+ *      Obtains host lock during operation.
+ *
+ *      RETURNS:
+ *      IRQ_NONE or IRQ_HANDLED.
+ */
+irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
+{
+        return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
+
+/**
+ *      ata_bmdma_error_handler - Stock error handler for BMDMA controller
+ *      @ap: port to handle error for
+ *
+ *      Stock error handler for BMDMA controller.  It can handle both
+ *      PATA and SATA controllers.  Most BMDMA controllers should be
+ *      able to use this EH as-is or with some added handling before
+ *      and after.
+ *
+ *      LOCKING:
+ *      Kernel thread context (may sleep)
+ */
+void ata_bmdma_error_handler(struct ata_port *ap)
+{
+        struct ata_queued_cmd *qc;
+        unsigned long flags;
+        bool thaw = false;
+
+        qc = __ata_qc_from_tag(ap, ap->link.active_tag);
+        if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
+                qc = NULL;
+
+        /* reset PIO HSM and stop DMA engine */
+        spin_lock_irqsave(ap->lock, flags);
+
+        if (qc && ata_is_dma(qc->tf.protocol)) {
+                u8 host_stat;
+
+                host_stat = ap->ops->bmdma_status(ap);
+
+                /* BMDMA controllers indicate host bus error by
+                 * setting DMA_ERR bit and timing out.  As it wasn't
+                 * really a timeout event, adjust error mask and
+                 * cancel frozen state.
+                 */
+                if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
+                        qc->err_mask = AC_ERR_HOST_BUS;
+                        thaw = true;
+                }
+
+                ap->ops->bmdma_stop(qc);
+
+                /* if we're gonna thaw, make sure IRQ is clear */
+                if (thaw) {
+                        ap->ops->sff_check_status(ap);
+                        if (ap->ops->sff_irq_clear)
+                                ap->ops->sff_irq_clear(ap);
+                }
+        }
+
+        spin_unlock_irqrestore(ap->lock, flags);
+
+        if (thaw)
+                ata_eh_thaw_port(ap);
+
+        ata_sff_error_handler(ap);
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
+
+/**
+ *      ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
+ *      @qc: internal command to clean up
+ *
+ *      LOCKING:
+ *      Kernel thread context (may sleep)
+ */
+void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
+{
+        struct ata_port *ap = qc->ap;
+        unsigned long flags;
+
+        if (ata_is_dma(qc->tf.protocol)) {
+                spin_lock_irqsave(ap->lock, flags);
+                ap->ops->bmdma_stop(qc);
+                spin_unlock_irqrestore(ap->lock, flags);
+        }
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
+
+/**
+ *      ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
+ *      @ap: Port associated with this ATA transaction.
+ *
+ *      Clear interrupt and error flags in DMA status register.
+ *
+ *      May be used as the irq_clear() entry in ata_port_operations.
+ *
+ *      LOCKING:
+ *      spin_lock_irqsave(host lock)
+ */
+void ata_bmdma_irq_clear(struct ata_port *ap)
+{
+        void __iomem *mmio = ap->ioaddr.bmdma_addr;
+
+        if (!mmio)
+                return;
+
+        iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
+
+/**
+ *      ata_bmdma_setup - Set up PCI IDE BMDMA transaction
+ *      @qc: Info associated with this ATA transaction.
+ *
+ *      LOCKING:
+ *      spin_lock_irqsave(host lock)
+ */
+void ata_bmdma_setup(struct ata_queued_cmd *qc)
+{
+        struct ata_port *ap = qc->ap;
+        unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
+        u8 dmactl;
+
+        /* load PRD table addr. */
+        mb();   /* make sure PRD table writes are visible to controller */
+        iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
+
+        /* specify data direction, triple-check start bit is clear */
+        dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
+        dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
+        if (!rw)
+                dmactl |= ATA_DMA_WR;
+        iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
+
+        /* issue r/w command */
+        ap->ops->sff_exec_command(ap, &qc->tf);
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_setup);
+
+/**
+ *      ata_bmdma_start - Start a PCI IDE BMDMA transaction
+ *      @qc: Info associated with this ATA transaction.
+ *
+ *      LOCKING:
+ *      spin_lock_irqsave(host lock)
+ */
+void ata_bmdma_start(struct ata_queued_cmd *qc)
+{
+        struct ata_port *ap = qc->ap;
+        u8 dmactl;
+
+        /* start host DMA transaction */
+        dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
+        iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
+
+        /* Strictly, one may wish to issue an ioread8() here, to
+         * flush the mmio write.  However, control also passes
+         * to the hardware at this point, and it will interrupt
+         * us when we are to resume control.  So, in effect,
+         * we don't care when the mmio write flushes.
+         * Further, a read of the DMA status register _immediately_
+         * following the write may not be what certain flaky hardware
+         * is expected, so I think it is best to not add a readb()
+         * without first all the MMIO ATA cards/mobos.
+         * Or maybe I'm just being paranoid.
+         *
+         * FIXME: The posting of this write means I/O starts are
+         * unneccessarily delayed for MMIO
+         */
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_start);
+
+/**
+ *      ata_bmdma_stop - Stop PCI IDE BMDMA transfer
+ *      @qc: Command we are ending DMA for
+ *
+ *      Clears the ATA_DMA_START flag in the dma control register
+ *
+ *      May be used as the bmdma_stop() entry in ata_port_operations.
+ *
+ *      LOCKING:
+ *      spin_lock_irqsave(host lock)
+ */
+void ata_bmdma_stop(struct ata_queued_cmd *qc)
+{
+        struct ata_port *ap = qc->ap;
+        void __iomem *mmio = ap->ioaddr.bmdma_addr;
+
+        /* clear start/stop bit */
+        iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
+                 mmio + ATA_DMA_CMD);
+
+        /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
+        ata_sff_dma_pause(ap);
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_stop);
+
+/**
+ *      ata_bmdma_status - Read PCI IDE BMDMA status
+ *      @ap: Port associated with this ATA transaction.
+ *
+ *      Read and return BMDMA status register.
+ *
+ *      May be used as the bmdma_status() entry in ata_port_operations.
+ *
+ *      LOCKING:
+ *      spin_lock_irqsave(host lock)
+ */
+u8 ata_bmdma_status(struct ata_port *ap)
+{
+        return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_status);
+
+
+/**
+ *      ata_bmdma_port_start - Set port up for bmdma.
+ *      @ap: Port to initialize
+ *
+ *      Called just after data structures for each port are
+ *      initialized.  Allocates space for PRD table.
+ *
+ *      May be used as the port_start() entry in ata_port_operations.
+ *
+ *      LOCKING:
+ *      Inherited from caller.
+ */
+int ata_bmdma_port_start(struct ata_port *ap)
+{
+        if (ap->mwdma_mask || ap->udma_mask) {
+                ap->bmdma_prd =
+                        dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
+                                            &ap->bmdma_prd_dma, GFP_KERNEL);
+                if (!ap->bmdma_prd)
+                        return -ENOMEM;
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
+
+/**
+ *      ata_bmdma_port_start32 - Set port up for dma.
+ *      @ap: Port to initialize
+ *
+ *      Called just after data structures for each port are
+ *      initialized.  Enables 32bit PIO and allocates space for PRD
+ *      table.
+ *
+ *      May be used as the port_start() entry in ata_port_operations for
+ *      devices that are capable of 32bit PIO.
+ *
+ *      LOCKING:
+ *      Inherited from caller.
+ */
+int ata_bmdma_port_start32(struct ata_port *ap)
+{
+        ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
+        return ata_bmdma_port_start(ap);
+}
+EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
+
+#ifdef CONFIG_PCI
+
+/**
+ *      ata_pci_bmdma_clear_simplex -   attempt to kick device out of simplex
+ *      @pdev: PCI device
+ *
+ *      Some PCI ATA devices report simplex mode but in fact can be told to
+ *      enter non simplex mode. This implements the necessary logic to
+ *      perform the task on such devices. Calling it on other devices will
+ *      have -undefined- behaviour.
+ */
+int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
+{
+        unsigned long bmdma = pci_resource_start(pdev, 4);
+        u8 simplex;
+
+        if (bmdma == 0)
+                return -ENOENT;
+
+        simplex = inb(bmdma + 0x02);
+        outb(simplex & 0x60, bmdma + 0x02);
+        simplex = inb(bmdma + 0x02);
+        if (simplex & 0x80)
+                return -EOPNOTSUPP;
+        return 0;
+}
+EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
+
+static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
+{
+        int i;
+
+        dev_printk(KERN_ERR, host->dev, "BMDMA: %s, falling back to PIO\n",
+                   reason);
+
+        for (i = 0; i < 2; i++) {
+                host->ports[i]->mwdma_mask = 0;
+                host->ports[i]->udma_mask = 0;
+        }
+}
+
+/**
+ *      ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
+ *      @host: target ATA host
+ *
+ *      Acquire PCI BMDMA resources and initialize @host accordingly.
+ *
+ *      LOCKING:
+ *      Inherited from calling layer (may sleep).
+ */
+void ata_pci_bmdma_init(struct ata_host *host)
+{
+        struct device *gdev = host->dev;
+        struct pci_dev *pdev = to_pci_dev(gdev);
+        int i, rc;
+
+        /* No BAR4 allocation: No DMA */
+        if (pci_resource_start(pdev, 4) == 0) {
+                ata_bmdma_nodma(host, "BAR4 is zero");
+                return;
+        }
+
+        /*
+         * Some controllers require BMDMA region to be initialized
+         * even if DMA is not in use to clear IRQ status via
+         * ->sff_irq_clear method.  Try to initialize bmdma_addr
+         * regardless of dma masks.
+         */
+        rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
+        if (rc)
+                ata_bmdma_nodma(host, "failed to set dma mask");
+        if (!rc) {
+                rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
+                if (rc)
+                        ata_bmdma_nodma(host,
+                                        "failed to set consistent dma mask");
+        }
+
+        /* request and iomap DMA region */
+        rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
+        if (rc) {
+                ata_bmdma_nodma(host, "failed to request/iomap BAR4");
+                return;
+        }
+        host->iomap = pcim_iomap_table(pdev);
+
+        for (i = 0; i < 2; i++) {
+                struct ata_port *ap = host->ports[i];
+                void __iomem *bmdma = host->iomap[4] + 8 * i;
+
+                if (ata_port_is_dummy(ap))
+                        continue;
+
+                ap->ioaddr.bmdma_addr = bmdma;
+                if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
+                    (ioread8(bmdma + 2) & 0x80))
+                        host->flags |= ATA_HOST_SIMPLEX;
+
+                ata_port_desc(ap, "bmdma 0x%llx",
+                    (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
+        }
+}
+EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
+
+/**
+ *      ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
+ *      @pdev: target PCI device
+ *      @ppi: array of port_info, must be enough for two ports
+ *      @r_host: out argument for the initialized ATA host
+ *
+ *      Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
+ *      resources and initialize it accordingly in one go.
+ *
+ *      LOCKING:
+ *      Inherited from calling layer (may sleep).
+ *
+ *      RETURNS:
+ *      0 on success, -errno otherwise.
+ */
+int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
+                               const struct ata_port_info * const * ppi,
+                               struct ata_host **r_host)
+{
+        int rc;
+
+        rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
+        if (rc)
+                return rc;
+
+        ata_pci_bmdma_init(*r_host);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
+
+/**
+ *      ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
+ *      @pdev: Controller to be initialized
+ *      @ppi: array of port_info, must be enough for two ports
+ *      @sht: scsi_host_template to use when registering the host
+ *      @host_priv: host private_data
+ *      @hflags: host flags
+ *
+ *      This function is similar to ata_pci_sff_init_one() but also
+ *      takes care of BMDMA initialization.
+ *
+ *      LOCKING:
+ *      Inherited from PCI layer (may sleep).
+ *
+ *      RETURNS:
+ *      Zero on success, negative on errno-based value on error.
+ */
+int ata_pci_bmdma_init_one(struct pci_dev *pdev,
+                           const struct ata_port_info * const * ppi,
+                           struct scsi_host_template *sht, void *host_priv,
+                           int hflags)
+{
+        struct device *dev = &pdev->dev;
+        const struct ata_port_info *pi;
+        struct ata_host *host = NULL;
+        int rc;
+
+        DPRINTK("ENTER\n");
+
+        pi = ata_sff_find_valid_pi(ppi);
+        if (!pi) {
+                dev_printk(KERN_ERR, &pdev->dev,
+                           "no valid port_info specified\n");
+                return -EINVAL;
+        }
+
+        if (!devres_open_group(dev, NULL, GFP_KERNEL))
+                return -ENOMEM;
+
+        rc = pcim_enable_device(pdev);
+        if (rc)
+                goto out;
+
+        /* prepare and activate BMDMA host */
+        rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
+        if (rc)
+                goto out;
+        host->private_data = host_priv;
+        host->flags |= hflags;
+
+        pci_set_master(pdev);
+        rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
+ out:
+        if (rc == 0)
+                devres_remove_group(&pdev->dev, NULL);
+        else
+                devres_release_group(&pdev->dev, NULL);
+
+        return rc;
+}
+EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
+
+#endif /* CONFIG_PCI */
+#endif /* CONFIG_ATA_BMDMA */
+
+/**
+ *      ata_sff_port_init - Initialize SFF/BMDMA ATA port
+ *      @ap: Port to initialize
+ *
+ *      Called on port allocation to initialize SFF/BMDMA specific
+ *      fields.
+ *
+ *      LOCKING:
+ *      None.
+ */
+void ata_sff_port_init(struct ata_port *ap)
+{
+        INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
+        ap->ctl = ATA_DEVCTL_OBS;
+        ap->last_ctl = 0xFF;
+}
+
+int __init ata_sff_init(void)
+{
+        ata_sff_wq = alloc_workqueue("ata_sff", WQ_RESCUER, WQ_MAX_ACTIVE);
+        if (!ata_sff_wq)
+                return -ENOMEM;
+
+        return 0;
+}
+
+void __exit ata_sff_exit(void)
+{
+        destroy_workqueue(ata_sff_wq);
+}
diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h
index 823e63096362..9ce1ecc63e39 100644
--- a/drivers/ata/libata.h
+++ b/drivers/ata/libata.h
@@ -38,17 +38,6 @@ struct ata_scsi_args {
         void                    (*done)(struct scsi_cmnd *);
 };
 
-static inline int ata_is_builtin_hardreset(ata_reset_fn_t reset)
-{
-        if (reset == sata_std_hardreset)
-                return 1;
-#ifdef CONFIG_ATA_SFF
-        if (reset == sata_sff_hardreset)
-                return 1;
-#endif
-        return 0;
-}
-
 /* libata-core.c */
 enum {
         /* flags for ata_dev_read_id() */
@@ -65,7 +54,6 @@ enum {
 };
 
 extern unsigned int ata_print_id;
-extern struct workqueue_struct *ata_aux_wq;
 extern int atapi_passthru16;
 extern int libata_fua;
 extern int libata_noacpi;
@@ -79,7 +67,6 @@ extern int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev,
                            u64 block, u32 n_block, unsigned int tf_flags,
                            unsigned int tag);
 extern u64 ata_tf_read_block(struct ata_taskfile *tf, struct ata_device *dev);
-extern void ata_port_flush_task(struct ata_port *ap);
 extern unsigned ata_exec_internal(struct ata_device *dev,
                                   struct ata_taskfile *tf, const u8 *cdb,
                                   int dma_dir, void *buf, unsigned int buflen,
@@ -202,10 +189,19 @@ static inline int sata_pmp_attach(struct ata_device *dev)
 
 /* libata-sff.c */
 #ifdef CONFIG_ATA_SFF
-extern void ata_dev_select(struct ata_port *ap, unsigned int device,
-                           unsigned int wait, unsigned int can_sleep);
-extern u8 ata_irq_on(struct ata_port *ap);
-extern void ata_pio_task(struct work_struct *work);
+extern void ata_sff_flush_pio_task(struct ata_port *ap);
+extern void ata_sff_port_init(struct ata_port *ap);
+extern int ata_sff_init(void);
+extern void ata_sff_exit(void);
+#else /* CONFIG_ATA_SFF */
+static inline void ata_sff_flush_pio_task(struct ata_port *ap)
+{ }
+static inline void ata_sff_port_init(struct ata_port *ap)
+{ }
+static inline int ata_sff_init(void)
+{ return 0; }
+static inline void ata_sff_exit(void)
+{ }
 #endif /* CONFIG_ATA_SFF */
 
 #endif /* __LIBATA_H__ */
diff --git a/drivers/ata/pata_acpi.c b/drivers/ata/pata_acpi.c
index 1ea2be0f4b94..c8d47034d5e9 100644
--- a/drivers/ata/pata_acpi.c
+++ b/drivers/ata/pata_acpi.c
@@ -101,7 +101,7 @@ static unsigned long pacpi_discover_modes(struct ata_port *ap, struct ata_device
 static unsigned long pacpi_mode_filter(struct ata_device *adev, unsigned long mask)
 {
         struct pata_acpi *acpi = adev->link->ap->private_data;
-        return ata_bmdma_mode_filter(adev, mask & acpi->mask[adev->devno]);
+        return mask & acpi->mask[adev->devno];
 }
 
 /**
@@ -172,7 +172,7 @@ static unsigned int pacpi_qc_issue(struct ata_queued_cmd *qc)
         struct pata_acpi *acpi = ap->private_data;
 
         if (acpi->gtm.flags & 0x10)
-                return ata_sff_qc_issue(qc);
+                return ata_bmdma_qc_issue(qc);
 
         if (adev != acpi->last) {
                 pacpi_set_piomode(ap, adev);
@@ -180,7 +180,7 @@ static unsigned int pacpi_qc_issue(struct ata_queued_cmd *qc)
                         pacpi_set_dmamode(ap, adev);
                 acpi->last = adev;
         }
-        return ata_sff_qc_issue(qc);
+        return ata_bmdma_qc_issue(qc);
 }
 
 /**
@@ -205,7 +205,7 @@ static int pacpi_port_start(struct ata_port *ap)
                 return -ENOMEM;
         acpi->mask[0] = pacpi_discover_modes(ap, &ap->link.device[0]);
         acpi->mask[1] = pacpi_discover_modes(ap, &ap->link.device[1]);
-        ret = ata_sff_port_start(ap);
+        ret = ata_bmdma_port_start(ap);
         if (ret < 0)
                 return ret;
 
@@ -260,7 +260,7 @@ static int pacpi_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
                         return rc;
                 pcim_pin_device(pdev);
         }
-        return ata_pci_sff_init_one(pdev, ppi, &pacpi_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &pacpi_sht, NULL, 0);
 }
 
 static const struct pci_device_id pacpi_pci_tbl[] = {
diff --git a/drivers/ata/pata_ali.c b/drivers/ata/pata_ali.c
index dc61b72f751c..794ec6e3275d 100644
--- a/drivers/ata/pata_ali.c
+++ b/drivers/ata/pata_ali.c
@@ -124,7 +124,7 @@ static unsigned long ali_20_filter(struct ata_device *adev, unsigned long mask)
         ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
         if (strstr(model_num, "WDC"))
                 return mask &= ~ATA_MASK_UDMA;
-        return ata_bmdma_mode_filter(adev, mask);
+        return mask;
 }
 
 /**
@@ -583,7 +583,10 @@ static int ali_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
                         ppi[0] = &info_20_udma;
         }
 
-        return ata_pci_sff_init_one(pdev, ppi, &ali_sht, NULL, 0);
+        if (!ppi[0]->mwdma_mask && !ppi[0]->udma_mask)
+                return ata_pci_sff_init_one(pdev, ppi, &ali_sht, NULL, 0);
+        else
+                return ata_pci_bmdma_init_one(pdev, ppi, &ali_sht, NULL, 0);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c
index d95eca9c547e..620a07cabe31 100644
--- a/drivers/ata/pata_amd.c
+++ b/drivers/ata/pata_amd.c
@@ -574,7 +574,7 @@ static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
         }
 
         /* And fire it up */
-        return ata_pci_sff_init_one(pdev, ppi, &amd_sht, hpriv, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &amd_sht, hpriv, 0);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/ata/pata_artop.c b/drivers/ata/pata_artop.c
index 4d066d6c30fa..2215632e4b31 100644
--- a/drivers/ata/pata_artop.c
+++ b/drivers/ata/pata_artop.c
@@ -74,7 +74,8 @@ static int artop6260_pre_reset(struct ata_link *link, unsigned long deadline)
         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 
         /* Odd numbered device ids are the units with enable bits (the -R cards) */
-        if (pdev->device % 1 && !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
+        if ((pdev->device & 1) &&
+            !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
                 return -ENOENT;
 
         return ata_sff_prereset(link, deadline);
@@ -421,7 +422,7 @@ static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
 
         BUG_ON(ppi[0] == NULL);
 
-        return ata_pci_sff_init_one(pdev, ppi, &artop_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
 }
 
 static const struct pci_device_id artop_pci_tbl[] = {
diff --git a/drivers/ata/pata_at91.c b/drivers/ata/pata_at91.c
index c6a946aa252c..0da0dcc7dd08 100644
--- a/drivers/ata/pata_at91.c
+++ b/drivers/ata/pata_at91.c
@@ -202,7 +202,6 @@ static struct ata_port_operations pata_at91_port_ops = {
         .sff_data_xfer  = pata_at91_data_xfer_noirq,
         .set_piomode    = pata_at91_set_piomode,
         .cable_detect   = ata_cable_40wire,
-        .port_start     = ATA_OP_NULL,
 };
 
 static int __devinit pata_at91_probe(struct platform_device *pdev)
diff --git a/drivers/ata/pata_atiixp.c b/drivers/ata/pata_atiixp.c
index cbaf2eddac6b..43755616dc5a 100644
--- a/drivers/ata/pata_atiixp.c
+++ b/drivers/ata/pata_atiixp.c
@@ -217,7 +217,7 @@ static struct scsi_host_template atiixp_sht = {
 static struct ata_port_operations atiixp_port_ops = {
         .inherits       = &ata_bmdma_port_ops,
 
-        .qc_prep        = ata_sff_dumb_qc_prep,
+        .qc_prep        = ata_bmdma_dumb_qc_prep,
         .bmdma_start    = atiixp_bmdma_start,
         .bmdma_stop     = atiixp_bmdma_stop,
 
@@ -246,8 +246,8 @@ static int atiixp_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
                 if (!pci_test_config_bits(pdev, &atiixp_enable_bits[i]))
                         ppi[i] = &ata_dummy_port_info;
 
-        return ata_pci_sff_init_one(pdev, ppi, &atiixp_sht, NULL,
-                                                ATA_HOST_PARALLEL_SCAN);
+        return ata_pci_bmdma_init_one(pdev, ppi, &atiixp_sht, NULL,
+                                      ATA_HOST_PARALLEL_SCAN);
 }
 
 static const struct pci_device_id atiixp[] = {
diff --git a/drivers/ata/pata_atp867x.c b/drivers/ata/pata_atp867x.c
index bb6e0746e07d..95295935dd95 100644
--- a/drivers/ata/pata_atp867x.c
+++ b/drivers/ata/pata_atp867x.c
@@ -525,7 +525,7 @@ static int atp867x_init_one(struct pci_dev *pdev,
 
         pci_set_master(pdev);
 
-        rc = ata_host_activate(host, pdev->irq, ata_sff_interrupt,
+        rc = ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
                                 IRQF_SHARED, &atp867x_sht);
         if (rc)
                 dev_printk(KERN_ERR, &pdev->dev, "failed to activate host\n");
diff --git a/drivers/ata/pata_bf54x.c b/drivers/ata/pata_bf54x.c
index 02c81f12c702..9cae65de750e 100644
--- a/drivers/ata/pata_bf54x.c
+++ b/drivers/ata/pata_bf54x.c
@@ -821,6 +821,18 @@ static void bfin_dev_select(struct ata_port *ap, unsigned int device)
 }
 
 /**
+ *      bfin_set_devctl - Write device control reg
+ *      @ap: port where the device is
+ *      @ctl: value to write
+ */
+
+static u8 bfin_set_devctl(struct ata_port *ap, u8 ctl)
+{
+        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
+        write_atapi_register(base, ATA_REG_CTRL, ctl);
+}
+
+/**
  *      bfin_bmdma_setup - Set up IDE DMA transaction
  *      @qc: Info associated with this ATA transaction.
  *
@@ -1202,7 +1214,7 @@ static unsigned int bfin_data_xfer(struct ata_device *dev, unsigned char *buf,
  *      bfin_irq_clear - Clear ATAPI interrupt.
  *      @ap: Port associated with this ATA transaction.
  *
- *      Note: Original code is ata_sff_irq_clear().
+ *      Note: Original code is ata_bmdma_irq_clear().
  */
 
 static void bfin_irq_clear(struct ata_port *ap)
@@ -1216,56 +1228,6 @@ static void bfin_irq_clear(struct ata_port *ap)
 }
 
 /**
- *      bfin_irq_on - Enable interrupts on a port.
- *      @ap: Port on which interrupts are enabled.
- *
- *      Note: Original code is ata_sff_irq_on().
- */
-
-static unsigned char bfin_irq_on(struct ata_port *ap)
-{
-        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
-        u8 tmp;
-
-        dev_dbg(ap->dev, "in atapi irq on\n");
-        ap->ctl &= ~ATA_NIEN;
-        ap->last_ctl = ap->ctl;
-
-        write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
-        tmp = ata_wait_idle(ap);
-
-        bfin_irq_clear(ap);
-
-        return tmp;
-}
-
-/**
- *      bfin_freeze - Freeze DMA controller port
- *      @ap: port to freeze
- *
- *      Note: Original code is ata_sff_freeze().
- */
-
-static void bfin_freeze(struct ata_port *ap)
-{
-        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
-
-        dev_dbg(ap->dev, "in atapi dma freeze\n");
-        ap->ctl |= ATA_NIEN;
-        ap->last_ctl = ap->ctl;
-
-        write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
-
-        /* Under certain circumstances, some controllers raise IRQ on
-         * ATA_NIEN manipulation.  Also, many controllers fail to mask
-         * previously pending IRQ on ATA_NIEN assertion.  Clear it.
-         */
-        ap->ops->sff_check_status(ap);
-
-        bfin_irq_clear(ap);
-}
-
-/**
  *      bfin_thaw - Thaw DMA controller port
  *      @ap: port to thaw
  *
@@ -1276,7 +1238,7 @@ void bfin_thaw(struct ata_port *ap)
 {
         dev_dbg(ap->dev, "in atapi dma thaw\n");
         bfin_check_status(ap);
-        bfin_irq_on(ap);
+        ata_sff_irq_on(ap);
 }
 
 /**
@@ -1293,7 +1255,7 @@ static void bfin_postreset(struct ata_link *link, unsigned int *classes)
         void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
 
         /* re-enable interrupts */
-        bfin_irq_on(ap);
+        ata_sff_irq_on(ap);
 
         /* is double-select really necessary? */
         if (classes[0] != ATA_DEV_NONE)
@@ -1438,18 +1400,12 @@ static irqreturn_t bfin_ata_interrupt(int irq, void *dev_instance)
         spin_lock_irqsave(&host->lock, flags);
 
         for (i = 0; i < host->n_ports; i++) {
-                struct ata_port *ap;
+                struct ata_port *ap = host->ports[i];
+                struct ata_queued_cmd *qc;
 
-                ap = host->ports[i];
-                if (ap &&
-                    !(ap->flags & ATA_FLAG_DISABLED)) {
-                        struct ata_queued_cmd *qc;
-
-                        qc = ata_qc_from_tag(ap, ap->link.active_tag);
-                        if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
-                            (qc->flags & ATA_QCFLAG_ACTIVE))
-                                handled |= bfin_ata_host_intr(ap, qc);
-                }
+                qc = ata_qc_from_tag(ap, ap->link.active_tag);
+                if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
+                        handled |= bfin_ata_host_intr(ap, qc);
         }
 
         spin_unlock_irqrestore(&host->lock, flags);
@@ -1465,7 +1421,7 @@ static struct scsi_host_template bfin_sht = {
 };
 
 static struct ata_port_operations bfin_pata_ops = {
-        .inherits               = &ata_sff_port_ops,
+        .inherits               = &ata_bmdma_port_ops,
 
         .set_piomode            = bfin_set_piomode,
         .set_dmamode            = bfin_set_dmamode,
@@ -1476,6 +1432,7 @@ static struct ata_port_operations bfin_pata_ops = {
         .sff_check_status       = bfin_check_status,
         .sff_check_altstatus    = bfin_check_altstatus,
         .sff_dev_select         = bfin_dev_select,
+        .sff_set_devctl         = bfin_set_devctl,
 
         .bmdma_setup            = bfin_bmdma_setup,
         .bmdma_start            = bfin_bmdma_start,
@@ -1485,13 +1442,11 @@ static struct ata_port_operations bfin_pata_ops = {
 
         .qc_prep                = ata_noop_qc_prep,
 
-        .freeze                 = bfin_freeze,
         .thaw                   = bfin_thaw,
         .softreset              = bfin_softreset,
         .postreset              = bfin_postreset,
 
         .sff_irq_clear          = bfin_irq_clear,
-        .sff_irq_on             = bfin_irq_on,
 
         .port_start             = bfin_port_start,
         .port_stop              = bfin_port_stop,
diff --git a/drivers/ata/pata_cmd640.c b/drivers/ata/pata_cmd640.c
index 45896b3c6538..e5f289f59ca3 100644
--- a/drivers/ata/pata_cmd640.c
+++ b/drivers/ata/pata_cmd640.c
@@ -153,24 +153,20 @@ static int cmd640_port_start(struct ata_port *ap)
         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
         struct cmd640_reg *timing;
 
-        int ret = ata_sff_port_start(ap);
-        if (ret < 0)
-                return ret;
-
         timing = devm_kzalloc(&pdev->dev, sizeof(struct cmd640_reg), GFP_KERNEL);
         if (timing == NULL)
                 return -ENOMEM;
         timing->last = -1;      /* Force a load */
         ap->private_data = timing;
-        return ret;
+        return 0;
 }
 
 static struct scsi_host_template cmd640_sht = {
-        ATA_BMDMA_SHT(DRV_NAME),
+        ATA_PIO_SHT(DRV_NAME),
 };
 
 static struct ata_port_operations cmd640_port_ops = {
-        .inherits       = &ata_bmdma_port_ops,
+        .inherits       = &ata_sff_port_ops,
         /* In theory xfer_noirq is not needed once we kill the prefetcher */
         .sff_data_xfer  = ata_sff_data_xfer_noirq,
         .qc_issue       = cmd640_qc_issue,
@@ -181,13 +177,10 @@ static struct ata_port_operations cmd640_port_ops = {
 
 static void cmd640_hardware_init(struct pci_dev *pdev)
 {
-        u8 r;
         u8 ctrl;
 
         /* CMD640 detected, commiserations */
         pci_write_config_byte(pdev, 0x5B, 0x00);
-        /* Get version info */
-        pci_read_config_byte(pdev, CFR, &r);
         /* PIO0 command cycles */
         pci_write_config_byte(pdev, CMDTIM, 0);
         /* 512 byte bursts (sector) */
diff --git a/drivers/ata/pata_cmd64x.c b/drivers/ata/pata_cmd64x.c
index 4c81a71b8877..905ff76d3cbb 100644
--- a/drivers/ata/pata_cmd64x.c
+++ b/drivers/ata/pata_cmd64x.c
@@ -121,14 +121,8 @@ static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 m
 
                 if (pair) {
                         struct ata_timing tp;
-
                         ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
                         ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
-                        if (pair->dma_mode) {
-                                ata_timing_compute(pair, pair->dma_mode,
-                                                &tp, T, 0);
-                                ata_timing_merge(&tp, &t, &t, ATA_TIMING_SETUP);
-                        }
                 }
         }
 
@@ -367,7 +361,7 @@ static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
         pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
 #endif
 
-        return ata_pci_sff_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/ata/pata_cs5520.c b/drivers/ata/pata_cs5520.c
index 95ebdac517f2..030952f1f97c 100644
--- a/drivers/ata/pata_cs5520.c
+++ b/drivers/ata/pata_cs5520.c
@@ -110,7 +110,7 @@ static struct scsi_host_template cs5520_sht = {
 
 static struct ata_port_operations cs5520_port_ops = {
         .inherits               = &ata_bmdma_port_ops,
-        .qc_prep                = ata_sff_dumb_qc_prep,
+        .qc_prep                = ata_bmdma_dumb_qc_prep,
         .cable_detect           = ata_cable_40wire,
         .set_piomode            = cs5520_set_piomode,
 };
@@ -221,7 +221,7 @@ static int __devinit cs5520_init_one(struct pci_dev *pdev, const struct pci_devi
                         continue;
 
                 rc = devm_request_irq(&pdev->dev, irq[ap->port_no],
-                                      ata_sff_interrupt, 0, DRV_NAME, host);
+                                      ata_bmdma_interrupt, 0, DRV_NAME, host);
                 if (rc)
                         return rc;
 
diff --git a/drivers/ata/pata_cs5530.c b/drivers/ata/pata_cs5530.c
index 738ad2e14a97..f792330f0d8e 100644
--- a/drivers/ata/pata_cs5530.c
+++ b/drivers/ata/pata_cs5530.c
@@ -156,7 +156,7 @@ static unsigned int cs5530_qc_issue(struct ata_queued_cmd *qc)
                         cs5530_set_dmamode(ap, adev);
         }
 
-        return ata_sff_qc_issue(qc);
+        return ata_bmdma_qc_issue(qc);
 }
 
 static struct scsi_host_template cs5530_sht = {
@@ -167,7 +167,7 @@ static struct scsi_host_template cs5530_sht = {
 static struct ata_port_operations cs5530_port_ops = {
         .inherits       = &ata_bmdma_port_ops,
 
-        .qc_prep        = ata_sff_dumb_qc_prep,
+        .qc_prep        = ata_bmdma_dumb_qc_prep,
         .qc_issue       = cs5530_qc_issue,
 
         .cable_detect   = ata_cable_40wire,
@@ -324,7 +324,7 @@ static int cs5530_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
                 ppi[1] = &info_palmax_secondary;
 
         /* Now kick off ATA set up */
-        return ata_pci_sff_init_one(pdev, ppi, &cs5530_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &cs5530_sht, NULL, 0);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/ata/pata_cs5535.c b/drivers/ata/pata_cs5535.c
index a02e6459fdcc..03a93186aa19 100644
--- a/drivers/ata/pata_cs5535.c
+++ b/drivers/ata/pata_cs5535.c
@@ -198,7 +198,7 @@ static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
         rdmsr(ATAC_CH0D1_PIO, timings, dummy);
         if (CS5535_BAD_PIO(timings))
                 wrmsr(ATAC_CH0D1_PIO, 0xF7F4F7F4UL, 0);
-        return ata_pci_sff_init_one(dev, ppi, &cs5535_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(dev, ppi, &cs5535_sht, NULL, 0);
 }
 
 static const struct pci_device_id cs5535[] = {
diff --git a/drivers/ata/pata_cs5536.c b/drivers/ata/pata_cs5536.c
index 914ae3506ff5..21ee23f89e88 100644
--- a/drivers/ata/pata_cs5536.c
+++ b/drivers/ata/pata_cs5536.c
@@ -260,7 +260,7 @@ static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
                 return -ENODEV;
         }
 
-        return ata_pci_sff_init_one(dev, ppi, &cs5536_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(dev, ppi, &cs5536_sht, NULL, 0);
 }
 
 static const struct pci_device_id cs5536[] = {
diff --git a/drivers/ata/pata_cypress.c b/drivers/ata/pata_cypress.c
index 0fcc096b8dac..6d915b063d93 100644
--- a/drivers/ata/pata_cypress.c
+++ b/drivers/ata/pata_cypress.c
@@ -138,7 +138,7 @@ static int cy82c693_init_one(struct pci_dev *pdev, const struct pci_device_id *i
         if (PCI_FUNC(pdev->devfn) != 1)
                 return -ENODEV;
 
-        return ata_pci_sff_init_one(pdev, ppi, &cy82c693_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &cy82c693_sht, NULL, 0);
 }
 
 static const struct pci_device_id cy82c693[] = {
diff --git a/drivers/ata/pata_efar.c b/drivers/ata/pata_efar.c
index 3bac0e079691..a08834758ea2 100644
--- a/drivers/ata/pata_efar.c
+++ b/drivers/ata/pata_efar.c
@@ -277,8 +277,8 @@ static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
                 dev_printk(KERN_DEBUG, &pdev->dev,
                            "version " DRV_VERSION "\n");
 
-        return ata_pci_sff_init_one(pdev, ppi, &efar_sht, NULL,
-                                        ATA_HOST_PARALLEL_SCAN);
+        return ata_pci_bmdma_init_one(pdev, ppi, &efar_sht, NULL,
+                                      ATA_HOST_PARALLEL_SCAN);
 }
 
 static const struct pci_device_id efar_pci_tbl[] = {
diff --git a/drivers/ata/pata_hpt366.c b/drivers/ata/pata_hpt366.c
index af49bfb57247..7688868557b9 100644
--- a/drivers/ata/pata_hpt366.c
+++ b/drivers/ata/pata_hpt366.c
@@ -182,7 +182,7 @@ static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
         } else if (adev->class == ATA_DEV_ATAPI)
                 mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
 
-        return ata_bmdma_mode_filter(adev, mask);
+        return mask;
 }
 
 static int hpt36x_cable_detect(struct ata_port *ap)
@@ -361,7 +361,7 @@ static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
                         break;
         }
         /* Now kick off ATA set up */
-        return ata_pci_sff_init_one(dev, ppi, &hpt36x_sht, hpriv, 0);
+        return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, hpriv, 0);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/ata/pata_hpt37x.c b/drivers/ata/pata_hpt37x.c
index 8839307a64cf..9ae4c0830577 100644
--- a/drivers/ata/pata_hpt37x.c
+++ b/drivers/ata/pata_hpt37x.c
@@ -282,7 +282,7 @@ static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
                 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
                         mask &= ~(0xE0 << ATA_SHIFT_UDMA);
         }
-        return ata_bmdma_mode_filter(adev, mask);
+        return mask;
 }
 
 /**
@@ -298,7 +298,7 @@ static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
                 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
                         mask &= ~(0xE0 << ATA_SHIFT_UDMA);
         }
-        return ata_bmdma_mode_filter(adev, mask);
+        return mask;
 }
 
 /**
@@ -987,7 +987,7 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
         }
 
         /* Now kick off ATA set up */
-        return ata_pci_sff_init_one(dev, ppi, &hpt37x_sht, private_data, 0);
+        return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0);
 }
 
 static const struct pci_device_id hpt37x[] = {
diff --git a/drivers/ata/pata_hpt3x2n.c b/drivers/ata/pata_hpt3x2n.c
index 01457b266f3d..32f3463216b8 100644
--- a/drivers/ata/pata_hpt3x2n.c
+++ b/drivers/ata/pata_hpt3x2n.c
@@ -320,7 +320,7 @@ static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
 
                 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
         }
-        return ata_sff_qc_issue(qc);
+        return ata_bmdma_qc_issue(qc);
 }
 
 static struct scsi_host_template hpt3x2n_sht = {
@@ -548,7 +548,7 @@ static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
                 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
 
         /* Now kick off ATA set up */
-        return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);
+        return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);
 }
 
 static const struct pci_device_id hpt3x2n[] = {
diff --git a/drivers/ata/pata_hpt3x3.c b/drivers/ata/pata_hpt3x3.c
index 727a81ce4c9f..b63d5e2d4628 100644
--- a/drivers/ata/pata_hpt3x3.c
+++ b/drivers/ata/pata_hpt3x3.c
@@ -248,7 +248,7 @@ static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
                 ata_port_pbar_desc(ap, 4, offset_cmd[i], "cmd");
         }
         pci_set_master(pdev);
-        return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
+        return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
                                  IRQF_SHARED, &hpt3x3_sht);
 }
 
diff --git a/drivers/ata/pata_icside.c b/drivers/ata/pata_icside.c
index fa812e206eeb..9f2889fe43b2 100644
--- a/drivers/ata/pata_icside.c
+++ b/drivers/ata/pata_icside.c
@@ -321,7 +321,7 @@ static void pata_icside_postreset(struct ata_link *link, unsigned int *classes)
 }
 
 static struct ata_port_operations pata_icside_port_ops = {
-        .inherits               = &ata_sff_port_ops,
+        .inherits               = &ata_bmdma_port_ops,
         /* no need to build any PRD tables for DMA */
         .qc_prep                = ata_noop_qc_prep,
         .sff_data_xfer          = ata_sff_data_xfer_noirq,
@@ -333,7 +333,8 @@ static struct ata_port_operations pata_icside_port_ops = {
         .cable_detect           = ata_cable_40wire,
         .set_dmamode            = pata_icside_set_dmamode,
         .postreset              = pata_icside_postreset,
-        .post_internal_cmd      = pata_icside_bmdma_stop,
+
+        .port_start             = ATA_OP_NULL,  /* don't need PRD table */
 };
 
 static void __devinit
@@ -469,7 +470,7 @@ static int __devinit pata_icside_add_ports(struct pata_icside_info *info)
                 pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]);
         }
 
-        return ata_host_activate(host, ec->irq, ata_sff_interrupt, 0,
+        return ata_host_activate(host, ec->irq, ata_bmdma_interrupt, 0,
                                  &pata_icside_sht);
 }
 
diff --git a/drivers/ata/pata_it8213.c b/drivers/ata/pata_it8213.c
index f971f0de88e6..4d142a2ab8fd 100644
--- a/drivers/ata/pata_it8213.c
+++ b/drivers/ata/pata_it8213.c
@@ -273,7 +273,7 @@ static int it8213_init_one (struct pci_dev *pdev, const struct pci_device_id *en
                 dev_printk(KERN_DEBUG, &pdev->dev,
                            "version " DRV_VERSION "\n");
 
-        return ata_pci_sff_init_one(pdev, ppi, &it8213_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &it8213_sht, NULL, 0);
 }
 
 static const struct pci_device_id it8213_pci_tbl[] = {
diff --git a/drivers/ata/pata_it821x.c b/drivers/ata/pata_it821x.c
index 5cb286fd839e..bf88f71a21f4 100644
--- a/drivers/ata/pata_it821x.c
+++ b/drivers/ata/pata_it821x.c
@@ -430,7 +430,7 @@ static unsigned int it821x_smart_qc_issue(struct ata_queued_cmd *qc)
                 case 0xFC:      /* Internal 'report rebuild state' */
                 /* Arguably should just no-op this one */
                 case ATA_CMD_SET_FEATURES:
-                        return ata_sff_qc_issue(qc);
+                        return ata_bmdma_qc_issue(qc);
         }
         printk(KERN_DEBUG "it821x: can't process command 0x%02X\n", qc->tf.command);
         return AC_ERR_DEV;
@@ -448,7 +448,7 @@ static unsigned int it821x_smart_qc_issue(struct ata_queued_cmd *qc)
 static unsigned int it821x_passthru_qc_issue(struct ata_queued_cmd *qc)
 {
         it821x_passthru_dev_select(qc->ap, qc->dev->devno);
-        return ata_sff_qc_issue(qc);
+        return ata_bmdma_qc_issue(qc);
 }
 
 /**
@@ -739,7 +739,7 @@ static int it821x_port_start(struct ata_port *ap)
         struct it821x_dev *itdev;
         u8 conf;
 
-        int ret = ata_sff_port_start(ap);
+        int ret = ata_bmdma_port_start(ap);
         if (ret < 0)
                 return ret;
 
@@ -933,7 +933,7 @@ static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
                 else
                         ppi[0] = &info_smart;
         }
-        return ata_pci_sff_init_one(pdev, ppi, &it821x_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &it821x_sht, NULL, 0);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/ata/pata_jmicron.c b/drivers/ata/pata_jmicron.c
index 565e01e6ac7c..cb3babbb7035 100644
--- a/drivers/ata/pata_jmicron.c
+++ b/drivers/ata/pata_jmicron.c
@@ -144,7 +144,7 @@ static int jmicron_init_one (struct pci_dev *pdev, const struct pci_device_id *i
         };
         const struct ata_port_info *ppi[] = { &info, NULL };
 
-        return ata_pci_sff_init_one(pdev, ppi, &jmicron_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &jmicron_sht, NULL, 0);
 }
 
 static const struct pci_device_id jmicron_pci_tbl[] = {
diff --git a/drivers/ata/pata_legacy.c b/drivers/ata/pata_legacy.c
index 9df1ff7e1eaa..eaf194138f21 100644
--- a/drivers/ata/pata_legacy.c
+++ b/drivers/ata/pata_legacy.c
@@ -44,6 +44,9 @@
  *  Specific support is included for the ht6560a/ht6560b/opti82c611a/
  *  opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
  *
+ *  Support for the Winbond 83759A when operating in advanced mode.
+ *  Multichip mode is not currently supported.
+ *
  *  Use the autospeed and pio_mask options with:
  *      Appian ADI/2 aka CLPD7220 or AIC25VL01.
  *  Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
@@ -135,12 +138,18 @@ static int ht6560b;		/* HT 6560A on primary 1, second 2, both 3 */
 static int opti82c611a;         /* Opti82c611A on primary 1, sec 2, both 3 */
 static int opti82c46x;          /* Opti 82c465MV present(pri/sec autodetect) */
 static int qdi;                 /* Set to probe QDI controllers */
-static int winbond;             /* Set to probe Winbond controllers,
-                                        give I/O port if non standard */
 static int autospeed;           /* Chip present which snoops speed changes */
 static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */
 static int iordy_mask = 0xFFFFFFFF;     /* Use iordy if available */
 
+#ifdef PATA_WINBOND_VLB_MODULE
+static int winbond = 1;         /* Set to probe Winbond controllers,
+                                        give I/O port if non standard */
+#else
+static int winbond;             /* Set to probe Winbond controllers,
+                                        give I/O port if non standard */
+#endif
+
 /**
  *      legacy_probe_add        -       Add interface to probe list
  *      @port: Controller port
@@ -1297,6 +1306,7 @@ MODULE_AUTHOR("Alan Cox");
 MODULE_DESCRIPTION("low-level driver for legacy ATA");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(DRV_VERSION);
+MODULE_ALIAS("pata_winbond");
 
 module_param(probe_all, int, 0);
 module_param(autospeed, int, 0);
@@ -1305,6 +1315,7 @@ module_param(ht6560b, int, 0);
 module_param(opti82c611a, int, 0);
 module_param(opti82c46x, int, 0);
 module_param(qdi, int, 0);
+module_param(winbond, int, 0);
 module_param(pio_mask, int, 0);
 module_param(iordy_mask, int, 0);
 
diff --git a/drivers/ata/pata_macio.c b/drivers/ata/pata_macio.c
index 211b6438b3a0..75b49d01780b 100644
--- a/drivers/ata/pata_macio.c
+++ b/drivers/ata/pata_macio.c
@@ -720,6 +720,8 @@ static int pata_macio_port_start(struct ata_port *ap)
         if (priv->dma_table_cpu == NULL) {
                 dev_err(priv->dev, "Unable to allocate DMA command list\n");
                 ap->ioaddr.bmdma_addr = NULL;
+                ap->mwdma_mask = 0;
+                ap->udma_mask = 0;
         }
         return 0;
 }
@@ -917,7 +919,7 @@ static struct scsi_host_template pata_macio_sht = {
 };
 
 static struct ata_port_operations pata_macio_ops = {
-        .inherits               = &ata_sff_port_ops,
+        .inherits               = &ata_bmdma_port_ops,
 
         .freeze                 = pata_macio_freeze,
         .set_piomode            = pata_macio_set_timings,
@@ -925,7 +927,6 @@ static struct ata_port_operations pata_macio_ops = {
         .cable_detect           = pata_macio_cable_detect,
         .sff_dev_select         = pata_macio_dev_select,
         .qc_prep                = pata_macio_qc_prep,
-        .mode_filter            = ata_bmdma_mode_filter,
         .bmdma_setup            = pata_macio_bmdma_setup,
         .bmdma_start            = pata_macio_bmdma_start,
         .bmdma_stop             = pata_macio_bmdma_stop,
@@ -1109,7 +1110,7 @@ static int __devinit pata_macio_common_init(struct pata_macio_priv	*priv,
 
         /* Start it up */
         priv->irq = irq;
-        return ata_host_activate(priv->host, irq, ata_sff_interrupt, 0,
+        return ata_host_activate(priv->host, irq, ata_bmdma_interrupt, 0,
                                  &pata_macio_sht);
 }
 
@@ -1139,7 +1140,7 @@ static int __devinit pata_macio_attach(struct macio_dev *mdev,
                         "Failed to allocate private memory\n");
                 return -ENOMEM;
         }
-        priv->node = of_node_get(mdev->ofdev.node);
+        priv->node = of_node_get(mdev->ofdev.dev.of_node);
         priv->mdev = mdev;
         priv->dev = &mdev->ofdev.dev;
 
@@ -1354,8 +1355,11 @@ static struct of_device_id pata_macio_match[] =
 
 static struct macio_driver pata_macio_driver =
 {
-        .name           = "pata-macio",
-        .match_table    = pata_macio_match,
+        .driver = {
+                .name           = "pata-macio",
+                .owner          = THIS_MODULE,
+                .of_match_table = pata_macio_match,
+        },
         .probe          = pata_macio_attach,
         .remove         = pata_macio_detach,
 #ifdef CONFIG_PM
@@ -1365,9 +1369,6 @@ static struct macio_driver pata_macio_driver =
 #ifdef CONFIG_PMAC_MEDIABAY
         .mediabay_event = pata_macio_mb_event,
 #endif
-        .driver = {
-                .owner          = THIS_MODULE,
-        },
 };
 
 static const struct pci_device_id pata_macio_pci_match[] = {
diff --git a/drivers/ata/pata_marvell.c b/drivers/ata/pata_marvell.c
index e8ca02e5a71d..dd38083dcbeb 100644
--- a/drivers/ata/pata_marvell.c
+++ b/drivers/ata/pata_marvell.c
@@ -153,7 +153,7 @@ static int marvell_init_one (struct pci_dev *pdev, const struct pci_device_id *i
                 return -ENODEV;
         }
 #endif
-        return ata_pci_sff_init_one(pdev, ppi, &marvell_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &marvell_sht, NULL, 0);
 }
 
 static const struct pci_device_id marvell_pci_tbl[] = {
diff --git a/drivers/ata/pata_mpc52xx.c b/drivers/ata/pata_mpc52xx.c
index 9f5b053611dd..8cc536e49a0a 100644
--- a/drivers/ata/pata_mpc52xx.c
+++ b/drivers/ata/pata_mpc52xx.c
@@ -64,13 +64,13 @@ struct mpc52xx_ata_priv {
 
 
 /* ATAPI-4 PIO specs (in ns) */
-static const int ataspec_t0[5]    = {600, 383, 240, 180, 120};
-static const int ataspec_t1[5]    = { 70,  50,  30,  30,  25};
-static const int ataspec_t2_8[5]  = {290, 290, 290,  80,  70};
-static const int ataspec_t2_16[5] = {165, 125, 100,  80,  70};
-static const int ataspec_t2i[5]   = {  0,   0,   0,  70,  25};
-static const int ataspec_t4[5]    = { 30,  20,  15,  10,  10};
-static const int ataspec_ta[5]    = { 35,  35,  35,  35,  35};
+static const u16 ataspec_t0[5]          = {600, 383, 240, 180, 120};
+static const u16 ataspec_t1[5]          = { 70,  50,  30,  30,  25};
+static const u16 ataspec_t2_8[5]        = {290, 290, 290,  80,  70};
+static const u16 ataspec_t2_16[5]       = {165, 125, 100,  80,  70};
+static const u16 ataspec_t2i[5]         = {  0,   0,   0,  70,  25};
+static const u16 ataspec_t4[5]          = { 30,  20,  15,  10,  10};
+static const u16 ataspec_ta[5]          = { 35,  35,  35,  35,  35};
 
 #define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c)))
 
@@ -78,13 +78,13 @@ static const int ataspec_ta[5]    = { 35,  35,  35,  35,  35};
 
 /* ATAPI-4 MDMA specs (in clocks) */
 struct mdmaspec {
-        u32 t0M;
-        u32 td;
-        u32 th;
-        u32 tj;
-        u32 tkw;
-        u32 tm;
-        u32 tn;
+        u8 t0M;
+        u8 td;
+        u8 th;
+        u8 tj;
+        u8 tkw;
+        u8 tm;
+        u8 tn;
 };
 
 static const struct mdmaspec mdmaspec66[3] = {
@@ -101,23 +101,23 @@ static const struct mdmaspec mdmaspec132[3] = {
 
 /* ATAPI-4 UDMA specs (in clocks) */
 struct udmaspec {
-        u32 tcyc;
-        u32 t2cyc;
-        u32 tds;
-        u32 tdh;
-        u32 tdvs;
-        u32 tdvh;
-        u32 tfs;
-        u32 tli;
-        u32 tmli;
-        u32 taz;
-        u32 tzah;
-        u32 tenv;
-        u32 tsr;
-        u32 trfs;
-        u32 trp;
-        u32 tack;
-        u32 tss;
+        u8 tcyc;
+        u8 t2cyc;
+        u8 tds;
+        u8 tdh;
+        u8 tdvs;
+        u8 tdvh;
+        u8 tfs;
+        u8 tli;
+        u8 tmli;
+        u8 taz;
+        u8 tzah;
+        u8 tenv;
+        u8 tsr;
+        u8 trfs;
+        u8 trp;
+        u8 tack;
+        u8 tss;
 };
 
 static const struct udmaspec udmaspec66[6] = {
@@ -270,7 +270,7 @@ mpc52xx_ata_compute_pio_timings(struct mpc52xx_ata_priv *priv, int dev, int pio)
 {
         struct mpc52xx_ata_timings *timing = &priv->timings[dev];
         unsigned int ipb_period = priv->ipb_period;
-        unsigned int t0, t1, t2_8, t2_16, t2i, t4, ta;
+        u32 t0, t1, t2_8, t2_16, t2i, t4, ta;
 
         if ((pio < 0) || (pio > 4))
                 return -EINVAL;
@@ -299,8 +299,8 @@ mpc52xx_ata_compute_mdma_timings(struct mpc52xx_ata_priv *priv, int dev,
         if (speed < 0 || speed > 2)
                 return -EINVAL;
 
-        t->mdma1 = (s->t0M << 24) | (s->td << 16) | (s->tkw << 8) | (s->tm);
-        t->mdma2 = (s->th << 24) | (s->tj << 16) | (s->tn << 8);
+        t->mdma1 = ((u32)s->t0M << 24) | ((u32)s->td << 16) | ((u32)s->tkw << 8) | s->tm;
+        t->mdma2 = ((u32)s->th << 24) | ((u32)s->tj << 16) | ((u32)s->tn << 8);
         t->using_udma = 0;
 
         return 0;
@@ -316,11 +316,11 @@ mpc52xx_ata_compute_udma_timings(struct mpc52xx_ata_priv *priv, int dev,
         if (speed < 0 || speed > 2)
                 return -EINVAL;
 
-        t->udma1 = (s->t2cyc << 24) | (s->tcyc << 16) | (s->tds << 8) | s->tdh;
-        t->udma2 = (s->tdvs << 24) | (s->tdvh << 16) | (s->tfs << 8) | s->tli;
-        t->udma3 = (s->tmli << 24) | (s->taz << 16) | (s->tenv << 8) | s->tsr;
-        t->udma4 = (s->tss << 24) | (s->trfs << 16) | (s->trp << 8) | s->tack;
-        t->udma5 = (s->tzah << 24);
+        t->udma1 = ((u32)s->t2cyc << 24) | ((u32)s->tcyc << 16) | ((u32)s->tds << 8) | s->tdh;
+        t->udma2 = ((u32)s->tdvs << 24) | ((u32)s->tdvh << 16) | ((u32)s->tfs << 8) | s->tli;
+        t->udma3 = ((u32)s->tmli << 24) | ((u32)s->taz << 16) | ((u32)s->tenv << 8) | s->tsr;
+        t->udma4 = ((u32)s->tss << 24) | ((u32)s->trfs << 16) | ((u32)s->trp << 8) | s->tack;
+        t->udma5 = (u32)s->tzah << 24;
         t->using_udma = 1;
 
         return 0;
@@ -659,7 +659,7 @@ mpc52xx_ata_init_one(struct device *dev, struct mpc52xx_ata_priv *priv,
         ata_port_desc(ap, "ata_regs 0x%lx", raw_ata_regs);
 
         /* activate host */
-        return ata_host_activate(host, priv->ata_irq, ata_sff_interrupt, 0,
+        return ata_host_activate(host, priv->ata_irq, ata_bmdma_interrupt, 0,
                                  &mpc52xx_ata_sht);
 }
 
@@ -680,7 +680,7 @@ mpc52xx_ata_remove_one(struct device *dev)
 /* ======================================================================== */
 
 static int __devinit
-mpc52xx_ata_probe(struct of_device *op, const struct of_device_id *match)
+mpc52xx_ata_probe(struct platform_device *op, const struct of_device_id *match)
 {
         unsigned int ipb_freq;
         struct resource res_mem;
@@ -694,7 +694,7 @@ mpc52xx_ata_probe(struct of_device *op, const struct of_device_id *match)
         struct bcom_task *dmatsk = NULL;
 
         /* Get ipb frequency */
-        ipb_freq = mpc5xxx_get_bus_frequency(op->node);
+        ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node);
         if (!ipb_freq) {
                 dev_err(&op->dev, "could not determine IPB bus frequency\n");
                 return -ENODEV;
@@ -702,7 +702,7 @@ mpc52xx_ata_probe(struct of_device *op, const struct of_device_id *match)
 
         /* Get device base address from device tree, request the region
          * and ioremap it. */
-        rv = of_address_to_resource(op->node, 0, &res_mem);
+        rv = of_address_to_resource(op->dev.of_node, 0, &res_mem);
         if (rv) {
                 dev_err(&op->dev, "could not determine device base address\n");
                 return rv;
@@ -735,14 +735,14 @@ mpc52xx_ata_probe(struct of_device *op, const struct of_device_id *match)
          * The MPC5200 ATA controller supports MWDMA modes 0, 1 and 2 and
          * UDMA modes 0, 1 and 2.
          */
-        prop = of_get_property(op->node, "mwdma-mode", &proplen);
+        prop = of_get_property(op->dev.of_node, "mwdma-mode", &proplen);
         if ((prop) && (proplen >= 4))
                 mwdma_mask = ATA_MWDMA2 & ((1 << (*prop + 1)) - 1);
-        prop = of_get_property(op->node, "udma-mode", &proplen);
+        prop = of_get_property(op->dev.of_node, "udma-mode", &proplen);
         if ((prop) && (proplen >= 4))
                 udma_mask = ATA_UDMA2 & ((1 << (*prop + 1)) - 1);
 
-        ata_irq = irq_of_parse_and_map(op->node, 0);
+        ata_irq = irq_of_parse_and_map(op->dev.of_node, 0);
         if (ata_irq == NO_IRQ) {
                 dev_err(&op->dev, "error mapping irq\n");
                 return -EINVAL;
@@ -821,7 +821,7 @@ mpc52xx_ata_probe(struct of_device *op, const struct of_device_id *match)
 }
 
 static int
-mpc52xx_ata_remove(struct of_device *op)
+mpc52xx_ata_remove(struct platform_device *op)
 {
         struct mpc52xx_ata_priv *priv;
         int task_irq;
@@ -848,7 +848,7 @@ mpc52xx_ata_remove(struct of_device *op)
 #ifdef CONFIG_PM
 
 static int
-mpc52xx_ata_suspend(struct of_device *op, pm_message_t state)
+mpc52xx_ata_suspend(struct platform_device *op, pm_message_t state)
 {
         struct ata_host *host = dev_get_drvdata(&op->dev);
 
@@ -856,7 +856,7 @@ mpc52xx_ata_suspend(struct of_device *op, pm_message_t state)
 }
 
 static int
-mpc52xx_ata_resume(struct of_device *op)
+mpc52xx_ata_resume(struct platform_device *op)
 {
         struct ata_host *host = dev_get_drvdata(&op->dev);
         struct mpc52xx_ata_priv *priv = host->private_data;
@@ -884,9 +884,6 @@ static struct of_device_id mpc52xx_ata_of_match[] = {
 
 
 static struct of_platform_driver mpc52xx_ata_of_platform_driver = {
-        .owner          = THIS_MODULE,
-        .name           = DRV_NAME,
-        .match_table    = mpc52xx_ata_of_match,
         .probe          = mpc52xx_ata_probe,
         .remove         = mpc52xx_ata_remove,
 #ifdef CONFIG_PM
@@ -896,6 +893,7 @@ static struct of_platform_driver mpc52xx_ata_of_platform_driver = {
         .driver         = {
                 .name   = DRV_NAME,
                 .owner  = THIS_MODULE,
+                .of_match_table = mpc52xx_ata_of_match,
         },
 };
 
diff --git a/drivers/ata/pata_netcell.c b/drivers/ata/pata_netcell.c
index 94f979a7f4f7..3eb921c746a1 100644
--- a/drivers/ata/pata_netcell.c
+++ b/drivers/ata/pata_netcell.c
@@ -82,7 +82,7 @@ static int netcell_init_one (struct pci_dev *pdev, const struct pci_device_id *e
         ata_pci_bmdma_clear_simplex(pdev);
 
         /* And let the library code do the work */
-        return ata_pci_sff_init_one(pdev, port_info, &netcell_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, port_info, &netcell_sht, NULL, 0);
 }
 
 static const struct pci_device_id netcell_pci_tbl[] = {
diff --git a/drivers/ata/pata_ninja32.c b/drivers/ata/pata_ninja32.c
index dd53a66b19e3..cc50bd09aa26 100644
--- a/drivers/ata/pata_ninja32.c
+++ b/drivers/ata/pata_ninja32.c
@@ -149,7 +149,7 @@ static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 
         ninja32_program(base);
         /* FIXME: Should we disable them at remove ? */
-        return ata_host_activate(host, dev->irq, ata_sff_interrupt,
+        return ata_host_activate(host, dev->irq, ata_bmdma_interrupt,
                                  IRQF_SHARED, &ninja32_sht);
 }
 
diff --git a/drivers/ata/pata_ns87415.c b/drivers/ata/pata_ns87415.c
index 830431f036a1..605f198f958c 100644
--- a/drivers/ata/pata_ns87415.c
+++ b/drivers/ata/pata_ns87415.c
@@ -126,7 +126,7 @@ static void ns87415_bmdma_setup(struct ata_queued_cmd *qc)
 
         /* load PRD table addr. */
         mb();   /* make sure PRD table writes are visible to controller */
-        iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
+        iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
 
         /* specify data direction, triple-check start bit is clear */
         dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
@@ -380,7 +380,7 @@ static int ns87415_init_one (struct pci_dev *pdev, const struct pci_device_id *e
 
         ns87415_fixup(pdev);
 
-        return ata_pci_sff_init_one(pdev, ppi, &ns87415_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &ns87415_sht, NULL, 0);
 }
 
 static const struct pci_device_id ns87415_pci_tbl[] = {
diff --git a/drivers/ata/pata_octeon_cf.c b/drivers/ata/pata_octeon_cf.c
index 005a44483a7b..06ddd91ffeda 100644
--- a/drivers/ata/pata_octeon_cf.c
+++ b/drivers/ata/pata_octeon_cf.c
@@ -489,9 +489,8 @@ static void octeon_cf_exec_command16(struct ata_port *ap,
         ata_wait_idle(ap);
 }
 
-static u8 octeon_cf_irq_on(struct ata_port *ap)
+static void octeon_cf_irq_on(struct ata_port *ap)
 {
-        return 0;
 }
 
 static void octeon_cf_irq_clear(struct ata_port *ap)
@@ -655,9 +654,6 @@ static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance)
                 ap = host->ports[i];
                 ocd = ap->dev->platform_data;
 
-                if (ap->flags & ATA_FLAG_DISABLED)
-                        continue;
-
                 ocd = ap->dev->platform_data;
                 cf_port = ap->private_data;
                 dma_int.u64 =
@@ -667,8 +663,7 @@ static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance)
 
                 qc = ata_qc_from_tag(ap, ap->link.active_tag);
 
-                if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
-                    (qc->flags & ATA_QCFLAG_ACTIVE)) {
+                if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) {
                         if (dma_int.s.done && !dma_cfg.s.en) {
                                 if (!sg_is_last(qc->cursg)) {
                                         qc->cursg = sg_next(qc->cursg);
@@ -738,8 +733,7 @@ static void octeon_cf_delayed_finish(struct work_struct *work)
                 goto out;
         }
         qc = ata_qc_from_tag(ap, ap->link.active_tag);
-        if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
-            (qc->flags & ATA_QCFLAG_ACTIVE))
+        if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
                 octeon_cf_dma_finished(ap, qc);
 out:
         spin_unlock_irqrestore(&host->lock, flags);
@@ -756,20 +750,6 @@ static void octeon_cf_dev_config(struct ata_device *dev)
 }
 
 /*
- * Trap if driver tries to do standard bmdma commands.  They are not
- * supported.
- */
-static void unreachable_qc(struct ata_queued_cmd *qc)
-{
-        BUG();
-}
-
-static u8 unreachable_port(struct ata_port *ap)
-{
-        BUG();
-}
-
-/*
  * We don't do ATAPI DMA so return 0.
  */
 static int octeon_cf_check_atapi_dma(struct ata_queued_cmd *qc)
@@ -810,10 +790,6 @@ static struct ata_port_operations octeon_cf_ops = {
         .sff_dev_select         = octeon_cf_dev_select,
         .sff_irq_on             = octeon_cf_irq_on,
         .sff_irq_clear          = octeon_cf_irq_clear,
-        .bmdma_setup            = unreachable_qc,
-        .bmdma_start            = unreachable_qc,
-        .bmdma_stop             = unreachable_qc,
-        .bmdma_status           = unreachable_port,
         .cable_detect           = ata_cable_40wire,
         .set_piomode            = octeon_cf_set_piomode,
         .set_dmamode            = octeon_cf_set_dmamode,
diff --git a/drivers/ata/pata_of_platform.c b/drivers/ata/pata_of_platform.c
index 1f18ad9e4fe1..480e043ce6b8 100644
--- a/drivers/ata/pata_of_platform.c
+++ b/drivers/ata/pata_of_platform.c
@@ -14,11 +14,11 @@
 #include <linux/of_platform.h>
 #include <linux/ata_platform.h>
 
-static int __devinit pata_of_platform_probe(struct of_device *ofdev,
+static int __devinit pata_of_platform_probe(struct platform_device *ofdev,
                                             const struct of_device_id *match)
 {
         int ret;
-        struct device_node *dn = ofdev->node;
+        struct device_node *dn = ofdev->dev.of_node;
         struct resource io_res;
         struct resource ctl_res;
         struct resource irq_res;
@@ -78,7 +78,7 @@ static int __devinit pata_of_platform_probe(struct of_device *ofdev,
                                      reg_shift, pio_mask);
 }
 
-static int __devexit pata_of_platform_remove(struct of_device *ofdev)
+static int __devexit pata_of_platform_remove(struct platform_device *ofdev)
 {
         return __pata_platform_remove(&ofdev->dev);
 }
@@ -91,8 +91,11 @@ static struct of_device_id pata_of_platform_match[] = {
 MODULE_DEVICE_TABLE(of, pata_of_platform_match);
 
 static struct of_platform_driver pata_of_platform_driver = {
-        .name           = "pata_of_platform",
-        .match_table    = pata_of_platform_match,
+        .driver = {
+                .name = "pata_of_platform",
+                .owner = THIS_MODULE,
+                .of_match_table = pata_of_platform_match,
+        },
         .probe          = pata_of_platform_probe,
         .remove         = __devexit_p(pata_of_platform_remove),
 };
diff --git a/drivers/ata/pata_oldpiix.c b/drivers/ata/pata_oldpiix.c
index 5f6aba7eb0dd..b811c1636204 100644
--- a/drivers/ata/pata_oldpiix.c
+++ b/drivers/ata/pata_oldpiix.c
@@ -200,7 +200,7 @@ static unsigned int oldpiix_qc_issue(struct ata_queued_cmd *qc)
                 if (ata_dma_enabled(adev))
                         oldpiix_set_dmamode(ap, adev);
         }
-        return ata_sff_qc_issue(qc);
+        return ata_bmdma_qc_issue(qc);
 }
 
 
@@ -248,7 +248,7 @@ static int oldpiix_init_one (struct pci_dev *pdev, const struct pci_device_id *e
                 dev_printk(KERN_DEBUG, &pdev->dev,
                            "version " DRV_VERSION "\n");
 
-        return ata_pci_sff_init_one(pdev, ppi, &oldpiix_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &oldpiix_sht, NULL, 0);
 }
 
 static const struct pci_device_id oldpiix_pci_tbl[] = {
diff --git a/drivers/ata/pata_optidma.c b/drivers/ata/pata_optidma.c
index 76b7d12b1e8d..0852cd07de08 100644
--- a/drivers/ata/pata_optidma.c
+++ b/drivers/ata/pata_optidma.c
@@ -429,7 +429,7 @@ static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
         if (optiplus_with_udma(dev))
                 ppi[0] = &info_82c700_udma;
 
-        return ata_pci_sff_init_one(dev, ppi, &optidma_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(dev, ppi, &optidma_sht, NULL, 0);
 }
 
 static const struct pci_device_id optidma[] = {
diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c
index d94b8f0bd743..e944aa0c5517 100644
--- a/drivers/ata/pata_pcmcia.c
+++ b/drivers/ata/pata_pcmcia.c
@@ -34,7 +34,6 @@
 #include <linux/ata.h>
 #include <linux/libata.h>
 
-#include <pcmcia/cs_types.h>
 #include <pcmcia/cs.h>
 #include <pcmcia/cistpl.h>
 #include <pcmcia/ds.h>
@@ -45,16 +44,6 @@
 #define DRV_NAME "pata_pcmcia"
 #define DRV_VERSION "0.3.5"
 
-/*
- *      Private data structure to glue stuff together
- */
-
-struct ata_pcmcia_info {
-        struct pcmcia_device *pdev;
-        int             ndev;
-        dev_node_t      node;
-};
-
 /**
  *      pcmcia_set_mode -       PCMCIA specific mode setup
  *      @link: link
@@ -175,7 +164,7 @@ static struct ata_port_operations pcmcia_8bit_port_ops = {
         .sff_data_xfer  = ata_data_xfer_8bit,
         .cable_detect   = ata_cable_40wire,
         .set_mode       = pcmcia_set_mode_8bit,
-        .drain_fifo     = pcmcia_8bit_drain_fifo,
+        .sff_drain_fifo = pcmcia_8bit_drain_fifo,
 };
 
 
@@ -211,23 +200,25 @@ static int pcmcia_check_one_config(struct pcmcia_device *pdev,
 
         if ((cfg->io.nwin > 0) || (dflt->io.nwin > 0)) {
                 cistpl_io_t *io = (cfg->io.nwin) ? &cfg->io : &dflt->io;
-                pdev->io.BasePort1 = io->win[0].base;
-                pdev->io.IOAddrLines = io->flags & CISTPL_IO_LINES_MASK;
-                if (!(io->flags & CISTPL_IO_16BIT))
-                        pdev->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
+                pdev->io_lines = io->flags & CISTPL_IO_LINES_MASK;
+                pdev->resource[0]->start = io->win[0].base;
+                if (!(io->flags & CISTPL_IO_16BIT)) {
+                        pdev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
+                        pdev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
+                }
                 if (io->nwin == 2) {
-                        pdev->io.NumPorts1 = 8;
-                        pdev->io.BasePort2 = io->win[1].base;
-                        pdev->io.NumPorts2 = (stk->is_kme) ? 2 : 1;
-                        if (pcmcia_request_io(pdev, &pdev->io) != 0)
+                        pdev->resource[0]->end = 8;
+                        pdev->resource[1]->start = io->win[1].base;
+                        pdev->resource[1]->end = (stk->is_kme) ? 2 : 1;
+                        if (pcmcia_request_io(pdev) != 0)
                                 return -ENODEV;
-                        stk->ctl_base = pdev->io.BasePort2;
+                        stk->ctl_base = pdev->resource[1]->start;
                 } else if ((io->nwin == 1) && (io->win[0].len >= 16)) {
-                        pdev->io.NumPorts1 = io->win[0].len;
-                        pdev->io.NumPorts2 = 0;
-                        if (pcmcia_request_io(pdev, &pdev->io) != 0)
+                        pdev->resource[0]->end = io->win[0].len;
+                        pdev->resource[1]->end = 0;
+                        if (pcmcia_request_io(pdev) != 0)
                                 return -ENODEV;
-                        stk->ctl_base = pdev->io.BasePort1 + 0x0e;
+                        stk->ctl_base = pdev->resource[0]->start + 0x0e;
                 } else
                         return -ENODEV;
                 /* If we've got this far, we're done */
@@ -248,7 +239,6 @@ static int pcmcia_init_one(struct pcmcia_device *pdev)
 {
         struct ata_host *host;
         struct ata_port *ap;
-        struct ata_pcmcia_info *info;
         struct pcmcia_config_check *stk = NULL;
         int is_kme = 0, ret = -ENOMEM, p;
         unsigned long io_base, ctl_base;
@@ -256,19 +246,9 @@ static int pcmcia_init_one(struct pcmcia_device *pdev)
         int n_ports = 1;
         struct ata_port_operations *ops = &pcmcia_port_ops;
 
-        info = kzalloc(sizeof(*info), GFP_KERNEL);
-        if (info == NULL)
-                return -ENOMEM;
-
-        /* Glue stuff together. FIXME: We may be able to get rid of info with care */
-        info->pdev = pdev;
-        pdev->priv = info;
-
         /* Set up attributes in order to probe card and get resources */
-        pdev->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
-        pdev->io.Attributes2 = IO_DATA_PATH_WIDTH_8;
-        pdev->io.IOAddrLines = 3;
-        pdev->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING;
+        pdev->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
+        pdev->resource[1]->flags |= IO_DATA_PATH_WIDTH_8;
         pdev->conf.Attributes = CONF_ENABLE_IRQ;
         pdev->conf.IntType = INT_MEMORY_AND_IO;
 
@@ -291,10 +271,9 @@ static int pcmcia_init_one(struct pcmcia_device *pdev)
                 if (pcmcia_loop_config(pdev, pcmcia_check_one_config, stk))
                         goto failed; /* No suitable config found */
         }
-        io_base = pdev->io.BasePort1;
+        io_base = pdev->resource[0]->start;
         ctl_base = stk->ctl_base;
-        ret = pcmcia_request_irq(pdev, &pdev->irq);
-        if (ret)
+        if (!pdev->irq)
                 goto failed;
 
         ret = pcmcia_request_configuration(pdev, &pdev->conf);
@@ -315,7 +294,7 @@ static int pcmcia_init_one(struct pcmcia_device *pdev)
 
         /* FIXME: Could be more ports at base + 0x10 but we only deal with
            one right now */
-        if (pdev->io.NumPorts1 >= 0x20)
+        if (resource_size(pdev->resource[0]) >= 0x20)
                 n_ports = 2;
 
         if (pdev->manf_id == 0x0097 && pdev->card_id == 0x1620)
@@ -344,21 +323,19 @@ static int pcmcia_init_one(struct pcmcia_device *pdev)
         }
 
         /* activate */
-        ret = ata_host_activate(host, pdev->irq.AssignedIRQ, ata_sff_interrupt,
+        ret = ata_host_activate(host, pdev->irq, ata_sff_interrupt,
                                 IRQF_SHARED, &pcmcia_sht);
         if (ret)
                 goto failed;
 
-        info->ndev = 1;
+        pdev->priv = host;
         kfree(stk);
         return 0;
 
 failed:
         kfree(stk);
-        info->ndev = 0;
         pcmcia_disable_device(pdev);
 out1:
-        kfree(info);
         return ret;
 }
 
@@ -372,20 +349,12 @@ out1:
 
 static void pcmcia_remove_one(struct pcmcia_device *pdev)
 {
-        struct ata_pcmcia_info *info = pdev->priv;
-        struct device *dev = &pdev->dev;
-
-        if (info != NULL) {
-                /* If we have attached the device to the ATA layer, detach it */
-                if (info->ndev) {
-                        struct ata_host *host = dev_get_drvdata(dev);
-                        ata_host_detach(host);
-                }
-                info->ndev = 0;
-                pdev->priv = NULL;
-        }
+        struct ata_host *host = pdev->priv;
+
+        if (host)
+                ata_host_detach(host);
+
         pcmcia_disable_device(pdev);
-        kfree(info);
 }
 
 static struct pcmcia_device_id pcmcia_devices[] = {
diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c
index ca5cad0fd80b..b18351122525 100644
--- a/drivers/ata/pata_pdc2027x.c
+++ b/drivers/ata/pata_pdc2027x.c
@@ -265,7 +265,7 @@ static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long
         struct ata_device *pair = ata_dev_pair(adev);
 
         if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
-                return ata_bmdma_mode_filter(adev, mask);
+                return mask;
 
         /* Check for slave of a Maxtor at UDMA6 */
         ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
@@ -274,7 +274,7 @@ static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long
         if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6)
                 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
 
-        return ata_bmdma_mode_filter(adev, mask);
+        return mask;
 }
 
 /**
@@ -754,7 +754,7 @@ static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_de
                 return -EIO;
 
         pci_set_master(pdev);
-        return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
+        return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
                                  IRQF_SHARED, &pdc2027x_sht);
 }
 
diff --git a/drivers/ata/pata_pdc202xx_old.c b/drivers/ata/pata_pdc202xx_old.c
index 9ac0897cf8b0..c39f213e1bbc 100644
--- a/drivers/ata/pata_pdc202xx_old.c
+++ b/drivers/ata/pata_pdc202xx_old.c
@@ -249,7 +249,7 @@ static int pdc2026x_port_start(struct ata_port *ap)
                 u8 burst = ioread8(bmdma + 0x1f);
                 iowrite8(burst | 0x01, bmdma + 0x1f);
         }
-        return ata_sff_port_start(ap);
+        return ata_bmdma_port_start(ap);
 }
 
 /**
@@ -337,7 +337,7 @@ static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id
                                 return -ENODEV;
                 }
         }
-        return ata_pci_sff_init_one(dev, ppi, &pdc202xx_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(dev, ppi, &pdc202xx_sht, NULL, 0);
 }
 
 static const struct pci_device_id pdc202xx[] = {
diff --git a/drivers/ata/pata_piccolo.c b/drivers/ata/pata_piccolo.c
index 981615414849..cb01bf9496fe 100644
--- a/drivers/ata/pata_piccolo.c
+++ b/drivers/ata/pata_piccolo.c
@@ -95,7 +95,7 @@ static int ata_tosh_init_one(struct pci_dev *dev, const struct pci_device_id *id
         };
         const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
         /* Just one port for the moment */
-        return ata_pci_sff_init_one(dev, ppi, &tosh_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(dev, ppi, &tosh_sht, NULL, 0);
 }
 
 static struct pci_device_id ata_tosh[] = {
diff --git a/drivers/ata/pata_platform.c b/drivers/ata/pata_platform.c
index 3f6ebc6c665a..50400fa120fe 100644
--- a/drivers/ata/pata_platform.c
+++ b/drivers/ata/pata_platform.c
@@ -53,7 +53,6 @@ static struct ata_port_operations pata_platform_port_ops = {
         .sff_data_xfer          = ata_sff_data_xfer_noirq,
         .cable_detect           = ata_cable_unknown,
         .set_mode               = pata_platform_set_mode,
-        .port_start             = ATA_OP_NULL,
 };
 
 static void pata_platform_setup_port(struct ata_ioports *ioaddr,
diff --git a/drivers/ata/pata_pxa.c b/drivers/ata/pata_pxa.c
new file mode 100644
index 000000000000..1898c6ed4b4e
--- /dev/null
+++ b/drivers/ata/pata_pxa.c
@@ -0,0 +1,411 @@
+/*
+ * Generic PXA PATA driver
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/ata.h>
+#include <linux/libata.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+#include <linux/completion.h>
+
+#include <scsi/scsi_host.h>
+
+#include <mach/pxa2xx-regs.h>
+#include <mach/pata_pxa.h>
+#include <mach/dma.h>
+
+#define DRV_NAME        "pata_pxa"
+#define DRV_VERSION     "0.1"
+
+struct pata_pxa_data {
+        uint32_t                dma_channel;
+        struct pxa_dma_desc     *dma_desc;
+        dma_addr_t              dma_desc_addr;
+        uint32_t                dma_desc_id;
+
+        /* DMA IO physical address */
+        uint32_t                dma_io_addr;
+        /* PXA DREQ<0:2> pin selector */
+        uint32_t                dma_dreq;
+        /* DMA DCSR register value */
+        uint32_t                dma_dcsr;
+
+        struct completion       dma_done;
+};
+
+/*
+ * Setup the DMA descriptors. The size is transfer capped at 4k per descriptor,
+ * if the transfer is longer, it is split into multiple chained descriptors.
+ */
+static void pxa_load_dmac(struct scatterlist *sg, struct ata_queued_cmd *qc)
+{
+        struct pata_pxa_data *pd = qc->ap->private_data;
+
+        uint32_t cpu_len, seg_len;
+        dma_addr_t cpu_addr;
+
+        cpu_addr = sg_dma_address(sg);
+        cpu_len = sg_dma_len(sg);
+
+        do {
+                seg_len = (cpu_len > 0x1000) ? 0x1000 : cpu_len;
+
+                pd->dma_desc[pd->dma_desc_id].ddadr = pd->dma_desc_addr +
+                        ((pd->dma_desc_id + 1) * sizeof(struct pxa_dma_desc));
+
+                pd->dma_desc[pd->dma_desc_id].dcmd = DCMD_BURST32 |
+                                        DCMD_WIDTH2 | (DCMD_LENGTH & seg_len);
+
+                if (qc->tf.flags & ATA_TFLAG_WRITE) {
+                        pd->dma_desc[pd->dma_desc_id].dsadr = cpu_addr;
+                        pd->dma_desc[pd->dma_desc_id].dtadr = pd->dma_io_addr;
+                        pd->dma_desc[pd->dma_desc_id].dcmd |= DCMD_INCSRCADDR |
+                                                DCMD_FLOWTRG;
+                } else {
+                        pd->dma_desc[pd->dma_desc_id].dsadr = pd->dma_io_addr;
+                        pd->dma_desc[pd->dma_desc_id].dtadr = cpu_addr;
+                        pd->dma_desc[pd->dma_desc_id].dcmd |= DCMD_INCTRGADDR |
+                                                DCMD_FLOWSRC;
+                }
+
+                cpu_len -= seg_len;
+                cpu_addr += seg_len;
+                pd->dma_desc_id++;
+
+        } while (cpu_len);
+
+        /* Should not happen */
+        if (seg_len & 0x1f)
+                DALGN |= (1 << pd->dma_dreq);
+}
+
+/*
+ * Prepare taskfile for submission.
+ */
+static void pxa_qc_prep(struct ata_queued_cmd *qc)
+{
+        struct pata_pxa_data *pd = qc->ap->private_data;
+        int si = 0;
+        struct scatterlist *sg;
+
+        if (!(qc->flags & ATA_QCFLAG_DMAMAP))
+                return;
+
+        pd->dma_desc_id = 0;
+
+        DCSR(pd->dma_channel) = 0;
+        DALGN &= ~(1 << pd->dma_dreq);
+
+        for_each_sg(qc->sg, sg, qc->n_elem, si)
+                pxa_load_dmac(sg, qc);
+
+        pd->dma_desc[pd->dma_desc_id - 1].ddadr = DDADR_STOP;
+
+        /* Fire IRQ only at the end of last block */
+        pd->dma_desc[pd->dma_desc_id - 1].dcmd |= DCMD_ENDIRQEN;
+
+        DDADR(pd->dma_channel) = pd->dma_desc_addr;
+        DRCMR(pd->dma_dreq) = DRCMR_MAPVLD | pd->dma_channel;
+
+}
+
+/*
+ * Configure the DMA controller, load the DMA descriptors, but don't start the
+ * DMA controller yet. Only issue the ATA command.
+ */
+static void pxa_bmdma_setup(struct ata_queued_cmd *qc)
+{
+        qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
+}
+
+/*
+ * Execute the DMA transfer.
+ */
+static void pxa_bmdma_start(struct ata_queued_cmd *qc)
+{
+        struct pata_pxa_data *pd = qc->ap->private_data;
+        init_completion(&pd->dma_done);
+        DCSR(pd->dma_channel) = DCSR_RUN;
+}
+
+/*
+ * Wait until the DMA transfer completes, then stop the DMA controller.
+ */
+static void pxa_bmdma_stop(struct ata_queued_cmd *qc)
+{
+        struct pata_pxa_data *pd = qc->ap->private_data;
+
+        if ((DCSR(pd->dma_channel) & DCSR_RUN) &&
+                wait_for_completion_timeout(&pd->dma_done, HZ))
+                dev_err(qc->ap->dev, "Timeout waiting for DMA completion!");
+
+        DCSR(pd->dma_channel) = 0;
+}
+
+/*
+ * Read DMA status. The bmdma_stop() will take care of properly finishing the
+ * DMA transfer so we always have DMA-complete interrupt here.
+ */
+static unsigned char pxa_bmdma_status(struct ata_port *ap)
+{
+        struct pata_pxa_data *pd = ap->private_data;
+        unsigned char ret = ATA_DMA_INTR;
+
+        if (pd->dma_dcsr & DCSR_BUSERR)
+                ret |= ATA_DMA_ERR;
+
+        return ret;
+}
+
+/*
+ * No IRQ register present so we do nothing.
+ */
+static void pxa_irq_clear(struct ata_port *ap)
+{
+}
+
+/*
+ * Check for ATAPI DMA. ATAPI DMA is unsupported by this driver. It's still
+ * unclear why ATAPI has DMA issues.
+ */
+static int pxa_check_atapi_dma(struct ata_queued_cmd *qc)
+{
+        return -EOPNOTSUPP;
+}
+
+static struct scsi_host_template pxa_ata_sht = {
+        ATA_BMDMA_SHT(DRV_NAME),
+};
+
+static struct ata_port_operations pxa_ata_port_ops = {
+        .inherits               = &ata_bmdma_port_ops,
+        .cable_detect           = ata_cable_40wire,
+
+        .bmdma_setup            = pxa_bmdma_setup,
+        .bmdma_start            = pxa_bmdma_start,
+        .bmdma_stop             = pxa_bmdma_stop,
+        .bmdma_status           = pxa_bmdma_status,
+
+        .check_atapi_dma        = pxa_check_atapi_dma,
+
+        .sff_irq_clear          = pxa_irq_clear,
+
+        .qc_prep                = pxa_qc_prep,
+};
+
+/*
+ * DMA interrupt handler.
+ */
+static void pxa_ata_dma_irq(int dma, void *port)
+{
+        struct ata_port *ap = port;
+        struct pata_pxa_data *pd = ap->private_data;
+
+        pd->dma_dcsr = DCSR(dma);
+        DCSR(dma) = pd->dma_dcsr;
+
+        if (pd->dma_dcsr & DCSR_STOPSTATE)
+                complete(&pd->dma_done);
+}
+
+static int __devinit pxa_ata_probe(struct platform_device *pdev)
+{
+        struct ata_host *host;
+        struct ata_port *ap;
+        struct pata_pxa_data *data;
+        struct resource *cmd_res;
+        struct resource *ctl_res;
+        struct resource *dma_res;
+        struct resource *irq_res;
+        struct pata_pxa_pdata *pdata = pdev->dev.platform_data;
+        int ret = 0;
+
+        /*
+         * Resource validation, three resources are needed:
+         *  - CMD port base address
+         *  - CTL port base address
+         *  - DMA port base address
+         *  - IRQ pin
+         */
+        if (pdev->num_resources != 4) {
+                dev_err(&pdev->dev, "invalid number of resources\n");
+                return -EINVAL;
+        }
+
+        /*
+         * CMD port base address
+         */
+        cmd_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (unlikely(cmd_res == NULL))
+                return -EINVAL;
+
+        /*
+         * CTL port base address
+         */
+        ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        if (unlikely(ctl_res == NULL))
+                return -EINVAL;
+
+        /*
+         * DMA port base address
+         */
+        dma_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+        if (unlikely(dma_res == NULL))
+                return -EINVAL;
+
+        /*
+         * IRQ pin
+         */
+        irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (unlikely(irq_res == NULL))
+                return -EINVAL;
+
+        /*
+         * Allocate the host
+         */
+        host = ata_host_alloc(&pdev->dev, 1);
+        if (!host)
+                return -ENOMEM;
+
+        ap              = host->ports[0];
+        ap->ops         = &pxa_ata_port_ops;
+        ap->pio_mask    = ATA_PIO4;
+        ap->mwdma_mask  = ATA_MWDMA2;
+        ap->flags       = ATA_FLAG_MMIO;
+
+        ap->ioaddr.cmd_addr     = devm_ioremap(&pdev->dev, cmd_res->start,
+                                                resource_size(cmd_res));
+        ap->ioaddr.ctl_addr     = devm_ioremap(&pdev->dev, ctl_res->start,
+                                                resource_size(ctl_res));
+        ap->ioaddr.bmdma_addr   = devm_ioremap(&pdev->dev, dma_res->start,
+                                                resource_size(dma_res));
+
+        /*
+         * Adjust register offsets
+         */
+        ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
+        ap->ioaddr.data_addr    = ap->ioaddr.cmd_addr +
+                                        (ATA_REG_DATA << pdata->reg_shift);
+        ap->ioaddr.error_addr   = ap->ioaddr.cmd_addr +
+                                        (ATA_REG_ERR << pdata->reg_shift);
+        ap->ioaddr.feature_addr = ap->ioaddr.cmd_addr +
+                                        (ATA_REG_FEATURE << pdata->reg_shift);
+        ap->ioaddr.nsect_addr   = ap->ioaddr.cmd_addr +
+                                        (ATA_REG_NSECT << pdata->reg_shift);
+        ap->ioaddr.lbal_addr    = ap->ioaddr.cmd_addr +
+                                        (ATA_REG_LBAL << pdata->reg_shift);
+        ap->ioaddr.lbam_addr    = ap->ioaddr.cmd_addr +
+                                        (ATA_REG_LBAM << pdata->reg_shift);
+        ap->ioaddr.lbah_addr    = ap->ioaddr.cmd_addr +
+                                        (ATA_REG_LBAH << pdata->reg_shift);
+        ap->ioaddr.device_addr  = ap->ioaddr.cmd_addr +
+                                        (ATA_REG_DEVICE << pdata->reg_shift);
+        ap->ioaddr.status_addr  = ap->ioaddr.cmd_addr +
+                                        (ATA_REG_STATUS << pdata->reg_shift);
+        ap->ioaddr.command_addr = ap->ioaddr.cmd_addr +
+                                        (ATA_REG_CMD << pdata->reg_shift);
+
+        /*
+         * Allocate and load driver's internal data structure
+         */
+        data = devm_kzalloc(&pdev->dev, sizeof(struct pata_pxa_data),
+                                                                GFP_KERNEL);
+        if (!data)
+                return -ENOMEM;
+
+        ap->private_data = data;
+        data->dma_dreq = pdata->dma_dreq;
+        data->dma_io_addr = dma_res->start;
+
+        /*
+         * Allocate space for the DMA descriptors
+         */
+        data->dma_desc = dmam_alloc_coherent(&pdev->dev, PAGE_SIZE,
+                                        &data->dma_desc_addr, GFP_KERNEL);
+        if (!data->dma_desc)
+                return -EINVAL;
+
+        /*
+         * Request the DMA channel
+         */
+        data->dma_channel = pxa_request_dma(DRV_NAME, DMA_PRIO_LOW,
+                                                pxa_ata_dma_irq, ap);
+        if (data->dma_channel < 0)
+                return -EBUSY;
+
+        /*
+         * Stop and clear the DMA channel
+         */
+        DCSR(data->dma_channel) = 0;
+
+        /*
+         * Activate the ATA host
+         */
+        ret = ata_host_activate(host, irq_res->start, ata_sff_interrupt,
+                                pdata->irq_flags, &pxa_ata_sht);
+        if (ret)
+                pxa_free_dma(data->dma_channel);
+
+        return ret;
+}
+
+static int __devexit pxa_ata_remove(struct platform_device *pdev)
+{
+        struct ata_host *host = dev_get_drvdata(&pdev->dev);
+        struct pata_pxa_data *data = host->ports[0]->private_data;
+
+        pxa_free_dma(data->dma_channel);
+
+        ata_host_detach(host);
+
+        return 0;
+}
+
+static struct platform_driver pxa_ata_driver = {
+        .probe          = pxa_ata_probe,
+        .remove         = __devexit_p(pxa_ata_remove),
+        .driver         = {
+                .name           = DRV_NAME,
+                .owner          = THIS_MODULE,
+        },
+};
+
+static int __init pxa_ata_init(void)
+{
+        return platform_driver_register(&pxa_ata_driver);
+}
+
+static void __exit pxa_ata_exit(void)
+{
+        platform_driver_unregister(&pxa_ata_driver);
+}
+
+module_init(pxa_ata_init);
+module_exit(pxa_ata_exit);
+
+MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
+MODULE_DESCRIPTION("DMA-capable driver for PATA on PXA CPU");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/drivers/ata/pata_radisys.c b/drivers/ata/pata_radisys.c
index fc9602229acb..8574b31f1773 100644
--- a/drivers/ata/pata_radisys.c
+++ b/drivers/ata/pata_radisys.c
@@ -179,7 +179,7 @@ static unsigned int radisys_qc_issue(struct ata_queued_cmd *qc)
                                 radisys_set_piomode(ap, adev);
                 }
         }
-        return ata_sff_qc_issue(qc);
+        return ata_bmdma_qc_issue(qc);
 }
 
 
@@ -227,7 +227,7 @@ static int radisys_init_one (struct pci_dev *pdev, const struct pci_device_id *e
                 dev_printk(KERN_DEBUG, &pdev->dev,
                            "version " DRV_VERSION "\n");
 
-        return ata_pci_sff_init_one(pdev, ppi, &radisys_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &radisys_sht, NULL, 0);
 }
 
 static const struct pci_device_id radisys_pci_tbl[] = {
diff --git a/drivers/ata/pata_rdc.c b/drivers/ata/pata_rdc.c
index 37092cfd7bc6..5fbe9b166c69 100644
--- a/drivers/ata/pata_rdc.c
+++ b/drivers/ata/pata_rdc.c
@@ -344,7 +344,7 @@ static int __devinit rdc_init_one(struct pci_dev *pdev,
          */
         pci_read_config_dword(pdev, 0x54, &hpriv->saved_iocfg);
 
-        rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
+        rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
         if (rc)
                 return rc;
         host->private_data = hpriv;
@@ -354,7 +354,7 @@ static int __devinit rdc_init_one(struct pci_dev *pdev,
         host->flags |= ATA_HOST_PARALLEL_SCAN;
 
         pci_set_master(pdev);
-        return ata_pci_sff_activate_host(host, ata_sff_interrupt, &rdc_sht);
+        return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &rdc_sht);
 }
 
 static void rdc_remove_one(struct pci_dev *pdev)
diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
new file mode 100644
index 000000000000..6f9cfb24b751
--- /dev/null
+++ b/drivers/ata/pata_samsung_cf.c
@@ -0,0 +1,683 @@
+/*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * PATA driver for Samsung SoCs.
+ * Supports CF Interface in True IDE mode. Currently only PIO mode has been
+ * implemented; UDMA support has to be added.
+ *
+ * Based on:
+ *      PATA driver for AT91SAM9260 Static Memory Controller
+ *      PATA driver for Toshiba SCC controller
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/libata.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <plat/ata.h>
+#include <plat/regs-ata.h>
+
+#define DRV_NAME "pata_samsung_cf"
+#define DRV_VERSION "0.1"
+
+enum s3c_cpu_type {
+        TYPE_S3C64XX,
+        TYPE_S5PC100,
+        TYPE_S5PV210,
+};
+
+/*
+ * struct s3c_ide_info - S3C PATA instance.
+ * @clk: The clock resource for this controller.
+ * @ide_addr: The area mapped for the hardware registers.
+ * @sfr_addr: The area mapped for the special function registers.
+ * @irq: The IRQ number we are using.
+ * @cpu_type: The exact type of this controller.
+ * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
+ */
+struct s3c_ide_info {
+        struct clk *clk;
+        void __iomem *ide_addr;
+        void __iomem *sfr_addr;
+        unsigned int irq;
+        enum s3c_cpu_type cpu_type;
+        unsigned int fifo_status_reg;
+};
+
+static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
+{
+        u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
+        reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
+        writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
+}
+
+static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
+{
+        /* Select true-ide as the internal operating mode */
+        writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
+                s3c_ide_sfrbase + S3C_CFATA_MUX);
+}
+
+static unsigned long
+pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
+{
+        int t1 = ata->setup;
+        int t2 = ata->act8b;
+        int t2i = ata->rec8b;
+        ulong piotime;
+
+        piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
+
+        return piotime;
+}
+
+static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+        struct s3c_ide_info *info = ap->host->private_data;
+        struct ata_timing timing;
+        int cycle_time;
+        ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
+        ulong piotime;
+
+        /* Enables IORDY if mode requires it */
+        if (ata_pio_need_iordy(adev))
+                ata_cfg |= S3C_ATA_CFG_IORDYEN;
+        else
+                ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
+
+        cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
+
+        ata_timing_compute(adev, adev->pio_mode, &timing,
+                                        cycle_time * 1000, 0);
+
+        piotime = pata_s3c_setup_timing(info, &timing);
+
+        writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
+        writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
+}
+
+/*
+ * Waits until the IDE controller is able to perform next read/write
+ * operation to the disk. Needed for 64XX series boards only.
+ */
+static int wait_for_host_ready(struct s3c_ide_info *info)
+{
+        ulong timeout;
+        void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
+
+        /* wait for maximum of 20 msec */
+        timeout = jiffies + msecs_to_jiffies(20);
+        while (time_before(jiffies, timeout)) {
+                if ((readl(fifo_reg) >> 28) == 0)
+                        return 0;
+        }
+        return -EBUSY;
+}
+
+/*
+ * Writes to one of the task file registers.
+ */
+static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
+{
+        struct s3c_ide_info *info = host->private_data;
+
+        wait_for_host_ready(info);
+        writeb(addr, reg);
+}
+
+/*
+ * Reads from one of the task file registers.
+ */
+static u8 ata_inb(struct ata_host *host, void __iomem *reg)
+{
+        struct s3c_ide_info *info = host->private_data;
+        u8 temp;
+
+        wait_for_host_ready(info);
+        (void) readb(reg);
+        wait_for_host_ready(info);
+        temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
+        return temp;
+}
+
+/*
+ * pata_s3c_tf_load - send taskfile registers to host controller
+ */
+static void pata_s3c_tf_load(struct ata_port *ap,
+                                const struct ata_taskfile *tf)
+{
+        struct ata_ioports *ioaddr = &ap->ioaddr;
+        unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
+
+        if (tf->ctl != ap->last_ctl) {
+                ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
+                ap->last_ctl = tf->ctl;
+                ata_wait_idle(ap);
+        }
+
+        if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
+                ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
+                ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
+                ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
+                ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
+                ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
+        }
+
+        if (is_addr) {
+                ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
+                ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
+                ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
+                ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
+                ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
+        }
+
+        if (tf->flags & ATA_TFLAG_DEVICE)
+                ata_outb(ap->host, tf->device, ioaddr->device_addr);
+
+        ata_wait_idle(ap);
+}
+
+/*
+ * pata_s3c_tf_read - input device's ATA taskfile shadow registers
+ */
+static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
+{
+        struct ata_ioports *ioaddr = &ap->ioaddr;
+
+        tf->feature = ata_inb(ap->host, ioaddr->error_addr);
+        tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+        tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+        tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
+        tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
+        tf->device = ata_inb(ap->host, ioaddr->device_addr);
+
+        if (tf->flags & ATA_TFLAG_LBA48) {
+                ata_outb(ap->host, tf->ctl | ATA_HOB, ioaddr->ctl_addr);
+                tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
+                tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+                tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+                tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
+                tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
+                ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
+                ap->last_ctl = tf->ctl;
+        }
+}
+
+/*
+ * pata_s3c_exec_command - issue ATA command to host controller
+ */
+static void pata_s3c_exec_command(struct ata_port *ap,
+                                const struct ata_taskfile *tf)
+{
+        ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
+        ata_sff_pause(ap);
+}
+
+/*
+ * pata_s3c_check_status - Read device status register
+ */
+static u8 pata_s3c_check_status(struct ata_port *ap)
+{
+        return ata_inb(ap->host, ap->ioaddr.status_addr);
+}
+
+/*
+ * pata_s3c_check_altstatus - Read alternate device status register
+ */
+static u8 pata_s3c_check_altstatus(struct ata_port *ap)
+{
+        return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
+}
+
+/*
+ * pata_s3c_data_xfer - Transfer data by PIO
+ */
+unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char *buf,
+                                unsigned int buflen, int rw)
+{
+        struct ata_port *ap = dev->link->ap;
+        struct s3c_ide_info *info = ap->host->private_data;
+        void __iomem *data_addr = ap->ioaddr.data_addr;
+        unsigned int words = buflen >> 1, i;
+        u16 *data_ptr = (u16 *)buf;
+
+        /* Requires wait same as in ata_inb/ata_outb */
+        if (rw == READ)
+                for (i = 0; i < words; i++, data_ptr++) {
+                        wait_for_host_ready(info);
+                        (void) readw(data_addr);
+                        wait_for_host_ready(info);
+                        *data_ptr = readw(info->ide_addr
+                                        + S3C_ATA_PIO_RDATA);
+                }
+        else
+                for (i = 0; i < words; i++, data_ptr++) {
+                        wait_for_host_ready(info);
+                        writew(*data_ptr, data_addr);
+                }
+
+        if (buflen & 0x01)
+                dev_err(ap->dev, "unexpected trailing data\n");
+
+        return words << 1;
+}
+
+/*
+ * pata_s3c_dev_select - Select device on ATA bus
+ */
+static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
+{
+        u8 tmp = ATA_DEVICE_OBS;
+
+        if (device != 0)
+                tmp |= ATA_DEV1;
+
+        ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
+        ata_sff_pause(ap);
+}
+
+/*
+ * pata_s3c_devchk - PATA device presence detection
+ */
+static unsigned int pata_s3c_devchk(struct ata_port *ap,
+                                unsigned int device)
+{
+        struct ata_ioports *ioaddr = &ap->ioaddr;
+        u8 nsect, lbal;
+
+        pata_s3c_dev_select(ap, device);
+
+        ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
+        ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
+
+        ata_outb(ap->host, 0xaa, ioaddr->nsect_addr);
+        ata_outb(ap->host, 0x55, ioaddr->lbal_addr);
+
+        ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
+        ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
+
+        nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+        lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+
+        if ((nsect == 0x55) && (lbal == 0xaa))
+                return 1;       /* we found a device */
+
+        return 0;               /* nothing found */
+}
+
+/*
+ * pata_s3c_wait_after_reset - wait for devices to become ready after reset
+ */
+static int pata_s3c_wait_after_reset(struct ata_link *link,
+                unsigned long deadline)
+{
+        int rc;
+
+        msleep(ATA_WAIT_AFTER_RESET);
+
+        /* always check readiness of the master device */
+        rc = ata_sff_wait_ready(link, deadline);
+        /* -ENODEV means the odd clown forgot the D7 pulldown resistor
+         * and TF status is 0xff, bail out on it too.
+         */
+        if (rc)
+                return rc;
+
+        return 0;
+}
+
+/*
+ * pata_s3c_bus_softreset - PATA device software reset
+ */
+static unsigned int pata_s3c_bus_softreset(struct ata_port *ap,
+                unsigned long deadline)
+{
+        struct ata_ioports *ioaddr = &ap->ioaddr;
+
+        /* software reset.  causes dev0 to be selected */
+        ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
+        udelay(20);
+        ata_outb(ap->host, ap->ctl | ATA_SRST, ioaddr->ctl_addr);
+        udelay(20);
+        ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
+        ap->last_ctl = ap->ctl;
+
+        return pata_s3c_wait_after_reset(&ap->link, deadline);
+}
+
+/*
+ * pata_s3c_softreset - reset host port via ATA SRST
+ */
+static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes,
+                         unsigned long deadline)
+{
+        struct ata_port *ap = link->ap;
+        unsigned int devmask = 0;
+        int rc;
+        u8 err;
+
+        /* determine if device 0 is present */
+        if (pata_s3c_devchk(ap, 0))
+                devmask |= (1 << 0);
+
+        /* select device 0 again */
+        pata_s3c_dev_select(ap, 0);
+
+        /* issue bus reset */
+        rc = pata_s3c_bus_softreset(ap, deadline);
+        /* if link is occupied, -ENODEV too is an error */
+        if (rc && rc != -ENODEV) {
+                ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
+                return rc;
+        }
+
+        /* determine by signature whether we have ATA or ATAPI devices */
+        classes[0] = ata_sff_dev_classify(&ap->link.device[0],
+                                          devmask & (1 << 0), &err);
+
+        return 0;
+}
+
+/*
+ * pata_s3c_set_devctl - Write device control register
+ */
+static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
+{
+        ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
+}
+
+static struct scsi_host_template pata_s3c_sht = {
+        ATA_PIO_SHT(DRV_NAME),
+};
+
+static struct ata_port_operations pata_s3c_port_ops = {
+        .inherits               = &ata_sff_port_ops,
+        .sff_check_status       = pata_s3c_check_status,
+        .sff_check_altstatus    = pata_s3c_check_altstatus,
+        .sff_tf_load            = pata_s3c_tf_load,
+        .sff_tf_read            = pata_s3c_tf_read,
+        .sff_data_xfer          = pata_s3c_data_xfer,
+        .sff_exec_command       = pata_s3c_exec_command,
+        .sff_dev_select         = pata_s3c_dev_select,
+        .sff_set_devctl         = pata_s3c_set_devctl,
+        .softreset              = pata_s3c_softreset,
+        .set_piomode            = pata_s3c_set_piomode,
+};
+
+static struct ata_port_operations pata_s5p_port_ops = {
+        .inherits               = &ata_sff_port_ops,
+        .set_piomode            = pata_s3c_set_piomode,
+};
+
+static void pata_s3c_enable(void *s3c_ide_regbase, bool state)
+{
+        u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
+        temp = state ? (temp | 1) : (temp & ~1);
+        writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
+}
+
+static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
+{
+        struct ata_host *host = dev_instance;
+        struct s3c_ide_info *info = host->private_data;
+        u32 reg;
+
+        reg = readl(info->ide_addr + S3C_ATA_IRQ);
+        writel(reg, info->ide_addr + S3C_ATA_IRQ);
+
+        return ata_sff_interrupt(irq, dev_instance);
+}
+
+static void pata_s3c_hwinit(struct s3c_ide_info *info,
+                                struct s3c_ide_platdata *pdata)
+{
+        switch (info->cpu_type) {
+        case TYPE_S3C64XX:
+                /* Configure as big endian */
+                pata_s3c_cfg_mode(info->sfr_addr);
+                pata_s3c_set_endian(info->ide_addr, 1);
+                pata_s3c_enable(info->ide_addr, true);
+                msleep(100);
+
+                /* Remove IRQ Status */
+                writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
+                writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
+                break;
+
+        case TYPE_S5PC100:
+                pata_s3c_cfg_mode(info->sfr_addr);
+                /* FALLTHROUGH */
+
+        case TYPE_S5PV210:
+                /* Configure as little endian */
+                pata_s3c_set_endian(info->ide_addr, 0);
+                pata_s3c_enable(info->ide_addr, true);
+                msleep(100);
+
+                /* Remove IRQ Status */
+                writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
+                writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
+                break;
+
+        default:
+                BUG();
+        }
+}
+
+static int __init pata_s3c_probe(struct platform_device *pdev)
+{
+        struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
+        struct device *dev = &pdev->dev;
+        struct s3c_ide_info *info;
+        struct resource *res;
+        struct ata_port *ap;
+        struct ata_host *host;
+        enum s3c_cpu_type cpu_type;
+        int ret;
+
+        cpu_type = platform_get_device_id(pdev)->driver_data;
+
+        info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
+        if (!info) {
+                dev_err(dev, "failed to allocate memory for device data\n");
+                return -ENOMEM;
+        }
+
+        info->irq = platform_get_irq(pdev, 0);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res == NULL) {
+                dev_err(dev, "failed to get mem resource\n");
+                return -EINVAL;
+        }
+
+        if (!devm_request_mem_region(dev, res->start,
+                                resource_size(res), DRV_NAME)) {
+                dev_err(dev, "error requesting register region\n");
+                return -EBUSY;
+        }
+
+        info->ide_addr = devm_ioremap(dev, res->start, resource_size(res));
+        if (!info->ide_addr) {
+                dev_err(dev, "failed to map IO base address\n");
+                return -ENOMEM;
+        }
+
+        info->clk = clk_get(&pdev->dev, "cfcon");
+        if (IS_ERR(info->clk)) {
+                dev_err(dev, "failed to get access to cf controller clock\n");
+                ret = PTR_ERR(info->clk);
+                info->clk = NULL;
+                return ret;
+        }
+
+        clk_enable(info->clk);
+
+        /* init ata host */
+        host = ata_host_alloc(dev, 1);
+        if (!host) {
+                dev_err(dev, "failed to allocate ide host\n");
+                ret = -ENOMEM;
+                goto stop_clk;
+        }
+
+        ap = host->ports[0];
+        ap->flags |= ATA_FLAG_MMIO;
+        ap->pio_mask = ATA_PIO4;
+
+        if (cpu_type == TYPE_S3C64XX) {
+                ap->ops = &pata_s3c_port_ops;
+                info->sfr_addr = info->ide_addr + 0x1800;
+                info->ide_addr += 0x1900;
+                info->fifo_status_reg = 0x94;
+        } else if (cpu_type == TYPE_S5PC100) {
+                ap->ops = &pata_s5p_port_ops;
+                info->sfr_addr = info->ide_addr + 0x1800;
+                info->ide_addr += 0x1900;
+                info->fifo_status_reg = 0x84;
+        } else {
+                ap->ops = &pata_s5p_port_ops;
+                info->fifo_status_reg = 0x84;
+        }
+
+        info->cpu_type = cpu_type;
+
+        if (info->irq <= 0) {
+                ap->flags |= ATA_FLAG_PIO_POLLING;
+                info->irq = 0;
+                ata_port_desc(ap, "no IRQ, using PIO polling\n");
+        }
+
+        ap->ioaddr.cmd_addr =  info->ide_addr + S3C_ATA_CMD;
+        ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
+        ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
+        ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
+        ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
+        ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
+        ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
+        ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
+        ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
+        ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
+        ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
+        ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
+        ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
+
+        ata_port_desc(ap, "mmio cmd 0x%llx ",
+                        (unsigned long long)res->start);
+
+        host->private_data = info;
+
+        if (pdata && pdata->setup_gpio)
+                pdata->setup_gpio();
+
+        /* Set endianness and enable the interface */
+        pata_s3c_hwinit(info, pdata);
+
+        platform_set_drvdata(pdev, host);
+
+        return ata_host_activate(host, info->irq,
+                        info->irq ? pata_s3c_irq : NULL,
+                        0, &pata_s3c_sht);
+
+stop_clk:
+        clk_disable(info->clk);
+        clk_put(info->clk);
+        return ret;
+}
+
+static int __exit pata_s3c_remove(struct platform_device *pdev)
+{
+        struct ata_host *host = platform_get_drvdata(pdev);
+        struct s3c_ide_info *info = host->private_data;
+
+        ata_host_detach(host);
+
+        clk_disable(info->clk);
+        clk_put(info->clk);
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int pata_s3c_suspend(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct ata_host *host = platform_get_drvdata(pdev);
+
+        return ata_host_suspend(host, PMSG_SUSPEND);
+}
+
+static int pata_s3c_resume(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct ata_host *host = platform_get_drvdata(pdev);
+        struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
+        struct s3c_ide_info *info = host->private_data;
+
+        pata_s3c_hwinit(info, pdata);
+        ata_host_resume(host);
+
+        return 0;
+}
+
+static const struct dev_pm_ops pata_s3c_pm_ops = {
+        .suspend        = pata_s3c_suspend,
+        .resume         = pata_s3c_resume,
+};
+#endif
+
+/* driver device registration */
+static struct platform_device_id pata_s3c_driver_ids[] = {
+        {
+                .name           = "s3c64xx-pata",
+                .driver_data    = TYPE_S3C64XX,
+        }, {
+                .name           = "s5pc100-pata",
+                .driver_data    = TYPE_S5PC100,
+        }, {
+                .name           = "s5pv210-pata",
+                .driver_data    = TYPE_S5PV210,
+        },
+        { }
+};
+
+MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
+
+static struct platform_driver pata_s3c_driver = {
+        .remove         = __exit_p(pata_s3c_remove),
+        .id_table       = pata_s3c_driver_ids,
+        .driver         = {
+                .name   = DRV_NAME,
+                .owner  = THIS_MODULE,
+#ifdef CONFIG_PM
+                .pm     = &pata_s3c_pm_ops,
+#endif
+        },
+};
+
+static int __init pata_s3c_init(void)
+{
+        return platform_driver_probe(&pata_s3c_driver, pata_s3c_probe);
+}
+
+static void __exit pata_s3c_exit(void)
+{
+        platform_driver_unregister(&pata_s3c_driver);
+}
+
+module_init(pata_s3c_init);
+module_exit(pata_s3c_exit);
+
+MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan@samsung.com>");
+MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/ata/pata_sc1200.c b/drivers/ata/pata_sc1200.c
index dfecc6f964b0..e2c18257adff 100644
--- a/drivers/ata/pata_sc1200.c
+++ b/drivers/ata/pata_sc1200.c
@@ -174,7 +174,7 @@ static unsigned int sc1200_qc_issue(struct ata_queued_cmd *qc)
                         sc1200_set_dmamode(ap, adev);
         }
 
-        return ata_sff_qc_issue(qc);
+        return ata_bmdma_qc_issue(qc);
 }
 
 /**
@@ -209,7 +209,7 @@ static struct scsi_host_template sc1200_sht = {
 
 static struct ata_port_operations sc1200_port_ops = {
         .inherits       = &ata_bmdma_port_ops,
-        .qc_prep        = ata_sff_dumb_qc_prep,
+        .qc_prep        = ata_bmdma_dumb_qc_prep,
         .qc_issue       = sc1200_qc_issue,
         .qc_defer       = sc1200_qc_defer,
         .cable_detect   = ata_cable_40wire,
@@ -237,7 +237,7 @@ static int sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
         };
         const struct ata_port_info *ppi[] = { &info, NULL };
 
-        return ata_pci_sff_init_one(dev, ppi, &sc1200_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(dev, ppi, &sc1200_sht, NULL, 0);
 }
 
 static const struct pci_device_id sc1200[] = {
diff --git a/drivers/ata/pata_scc.c b/drivers/ata/pata_scc.c
index 4257d6b40af4..fe36966f7e34 100644
--- a/drivers/ata/pata_scc.c
+++ b/drivers/ata/pata_scc.c
@@ -168,8 +168,7 @@ static const unsigned long JCACTSELtbl[2][7] = {
 };
 
 static const struct pci_device_id scc_pci_tbl[] = {
-        {PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,
-         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+        { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0},
         { }     /* terminate list */
 };
 
@@ -265,7 +264,7 @@ unsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask)
                 printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME);
                 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
         }
-        return ata_bmdma_mode_filter(adev, mask);
+        return mask;
 }
 
 /**
@@ -416,6 +415,17 @@ static void scc_dev_select (struct ata_port *ap, unsigned int device)
 }
 
 /**
+ *      scc_set_devctl - Write device control reg
+ *      @ap: port where the device is
+ *      @ctl: value to write
+ */
+
+static void scc_set_devctl(struct ata_port *ap, u8 ctl)
+{
+        out_be32(ap->ioaddr.ctl_addr, ctl);
+}
+
+/**
  *      scc_bmdma_setup - Set up PCI IDE BMDMA transaction
  *      @qc: Info associated with this ATA transaction.
  *
@@ -430,7 +440,7 @@ static void scc_bmdma_setup (struct ata_queued_cmd *qc)
         void __iomem *mmio = ap->ioaddr.bmdma_addr;
 
         /* load PRD table addr */
-        out_be32(mmio + SCC_DMA_TABLE_OFS, ap->prd_dma);
+        out_be32(mmio + SCC_DMA_TABLE_OFS, ap->bmdma_prd_dma);
 
         /* specify data direction, triple-check start bit is clear */
         dmactl = in_be32(mmio + SCC_DMA_CMD);
@@ -501,8 +511,8 @@ static unsigned int scc_devchk (struct ata_port *ap,
  *      Note: Original code is ata_sff_wait_after_reset
  */
 
-int scc_wait_after_reset(struct ata_link *link, unsigned int devmask,
-                         unsigned long deadline)
+static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask,
+                                unsigned long deadline)
 {
         struct ata_port *ap = link->ap;
         struct ata_ioports *ioaddr = &ap->ioaddr;
@@ -817,54 +827,6 @@ static unsigned int scc_data_xfer (struct ata_device *dev, unsigned char *buf,
 }
 
 /**
- *      scc_irq_on - Enable interrupts on a port.
- *      @ap: Port on which interrupts are enabled.
- *
- *      Note: Original code is ata_sff_irq_on().
- */
-
-static u8 scc_irq_on (struct ata_port *ap)
-{
-        struct ata_ioports *ioaddr = &ap->ioaddr;
-        u8 tmp;
-
-        ap->ctl &= ~ATA_NIEN;
-        ap->last_ctl = ap->ctl;
-
-        out_be32(ioaddr->ctl_addr, ap->ctl);
-        tmp = ata_wait_idle(ap);
-
-        ap->ops->sff_irq_clear(ap);
-
-        return tmp;
-}
-
-/**
- *      scc_freeze - Freeze BMDMA controller port
- *      @ap: port to freeze
- *
- *      Note: Original code is ata_sff_freeze().
- */
-
-static void scc_freeze (struct ata_port *ap)
-{
-        struct ata_ioports *ioaddr = &ap->ioaddr;
-
-        ap->ctl |= ATA_NIEN;
-        ap->last_ctl = ap->ctl;
-
-        out_be32(ioaddr->ctl_addr, ap->ctl);
-
-        /* Under certain circumstances, some controllers raise IRQ on
-         * ATA_NIEN manipulation.  Also, many controllers fail to mask
-         * previously pending IRQ on ATA_NIEN assertion.  Clear it.
-         */
-        ap->ops->sff_check_status(ap);
-
-        ap->ops->sff_irq_clear(ap);
-}
-
-/**
  *      scc_pata_prereset - prepare for reset
  *      @ap: ATA port to be reset
  *      @deadline: deadline jiffies for the operation
@@ -903,8 +865,7 @@ static void scc_postreset(struct ata_link *link, unsigned int *classes)
         }
 
         /* set up device control */
-        if (ap->ioaddr.ctl_addr)
-                out_be32(ap->ioaddr.ctl_addr, ap->ctl);
+        out_be32(ap->ioaddr.ctl_addr, ap->ctl);
 
         DPRINTK("EXIT\n");
 }
@@ -913,7 +874,7 @@ static void scc_postreset(struct ata_link *link, unsigned int *classes)
  *      scc_irq_clear - Clear PCI IDE BMDMA interrupt.
  *      @ap: Port associated with this ATA transaction.
  *
- *      Note: Original code is ata_sff_irq_clear().
+ *      Note: Original code is ata_bmdma_irq_clear().
  */
 
 static void scc_irq_clear (struct ata_port *ap)
@@ -930,7 +891,7 @@ static void scc_irq_clear (struct ata_port *ap)
  *      scc_port_start - Set port up for dma.
  *      @ap: Port to initialize
  *
- *      Allocate space for PRD table using ata_port_start().
+ *      Allocate space for PRD table using ata_bmdma_port_start().
  *      Set PRD table address for PTERADD. (PRD Transfer End Read)
  */
 
@@ -939,11 +900,11 @@ static int scc_port_start (struct ata_port *ap)
         void __iomem *mmio = ap->ioaddr.bmdma_addr;
         int rc;
 
-        rc = ata_port_start(ap);
+        rc = ata_bmdma_port_start(ap);
         if (rc)
                 return rc;
 
-        out_be32(mmio + SCC_DMA_PTERADD, ap->prd_dma);
+        out_be32(mmio + SCC_DMA_PTERADD, ap->bmdma_prd_dma);
         return 0;
 }
 
@@ -978,6 +939,7 @@ static struct ata_port_operations scc_pata_ops = {
         .sff_check_status       = scc_check_status,
         .sff_check_altstatus    = scc_check_altstatus,
         .sff_dev_select         = scc_dev_select,
+        .sff_set_devctl         = scc_set_devctl,
 
         .bmdma_setup            = scc_bmdma_setup,
         .bmdma_start            = scc_bmdma_start,
@@ -985,14 +947,11 @@ static struct ata_port_operations scc_pata_ops = {
         .bmdma_status           = scc_bmdma_status,
         .sff_data_xfer          = scc_data_xfer,
 
-        .freeze                 = scc_freeze,
         .prereset               = scc_pata_prereset,
         .softreset              = scc_softreset,
         .postreset              = scc_postreset,
-        .post_internal_cmd      = scc_bmdma_stop,
 
         .sff_irq_clear          = scc_irq_clear,
-        .sff_irq_on             = scc_irq_on,
 
         .port_start             = scc_port_start,
         .port_stop              = scc_port_stop,
@@ -1145,7 +1104,7 @@ static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
         if (rc)
                 return rc;
 
-        return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
+        return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
                                  IRQF_SHARED, &scc_sht);
 }
 
diff --git a/drivers/ata/pata_sch.c b/drivers/ata/pata_sch.c
index 99cceb458e2a..e97b32f03a6e 100644
--- a/drivers/ata/pata_sch.c
+++ b/drivers/ata/pata_sch.c
@@ -174,22 +174,12 @@ static int __devinit sch_init_one(struct pci_dev *pdev,
 {
         static int printed_version;
         const struct ata_port_info *ppi[] = { &sch_port_info, NULL };
-        struct ata_host *host;
-        int rc;
 
         if (!printed_version++)
                 dev_printk(KERN_DEBUG, &pdev->dev,
                            "version " DRV_VERSION "\n");
 
-        /* enable device and prepare host */
-        rc = pcim_enable_device(pdev);
-        if (rc)
-                return rc;
-        rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
-        if (rc)
-                return rc;
-        pci_set_master(pdev);
-        return ata_pci_sff_activate_host(host, ata_sff_interrupt, &sch_sht);
+        return ata_pci_bmdma_init_one(pdev, ppi, &sch_sht, NULL, 0);
 }
 
 static int __init sch_init(void)
diff --git a/drivers/ata/pata_serverworks.c b/drivers/ata/pata_serverworks.c
index 9524d54035f7..86dd714e3e1d 100644
--- a/drivers/ata/pata_serverworks.c
+++ b/drivers/ata/pata_serverworks.c
@@ -198,7 +198,7 @@ static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned l
 {
         if (adev->class == ATA_DEV_ATA)
                 mask &= ~ATA_MASK_UDMA;
-        return ata_bmdma_mode_filter(adev, mask);
+        return mask;
 }
 
 
@@ -218,7 +218,7 @@ static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned lo
 
         /* Disk, UDMA */
         if (adev->class != ATA_DEV_ATA)
-                return ata_bmdma_mode_filter(adev, mask);
+                return mask;
 
         /* Actually do need to check */
         ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
@@ -227,7 +227,7 @@ static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned lo
                 if (!strcmp(p, model_num))
                         mask &= ~(0xE0 << ATA_SHIFT_UDMA);
         }
-        return ata_bmdma_mode_filter(adev, mask);
+        return mask;
 }
 
 /**
@@ -460,7 +460,7 @@ static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id
         if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
                 ata_pci_bmdma_clear_simplex(pdev);
 
-        return ata_pci_sff_init_one(pdev, ppi, &serverworks_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &serverworks_sht, NULL, 0);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/ata/pata_sil680.c b/drivers/ata/pata_sil680.c
index c6c589c23ffc..d3190d7ec304 100644
--- a/drivers/ata/pata_sil680.c
+++ b/drivers/ata/pata_sil680.c
@@ -190,15 +190,37 @@ static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
         pci_write_config_word(pdev, ua, ultra);
 }
 
+/**
+ *      sil680_sff_exec_command - issue ATA command to host controller
+ *      @ap: port to which command is being issued
+ *      @tf: ATA taskfile register set
+ *
+ *      Issues ATA command, with proper synchronization with interrupt
+ *      handler / other threads. Use our MMIO space for PCI posting to avoid
+ *      a hideously slow cycle all the way to the device.
+ *
+ *      LOCKING:
+ *      spin_lock_irqsave(host lock)
+ */
+void sil680_sff_exec_command(struct ata_port *ap,
+                                        const struct ata_taskfile *tf)
+{
+        DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
+        iowrite8(tf->command, ap->ioaddr.command_addr);
+        ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
+}
+
 static struct scsi_host_template sil680_sht = {
         ATA_BMDMA_SHT(DRV_NAME),
 };
 
+
 static struct ata_port_operations sil680_port_ops = {
-        .inherits       = &ata_bmdma32_port_ops,
-        .cable_detect   = sil680_cable_detect,
-        .set_piomode    = sil680_set_piomode,
-        .set_dmamode    = sil680_set_dmamode,
+        .inherits               = &ata_bmdma32_port_ops,
+        .sff_exec_command       = sil680_sff_exec_command,
+        .cable_detect           = sil680_cable_detect,
+        .set_piomode            = sil680_set_piomode,
+        .set_dmamode            = sil680_set_dmamode,
 };
 
 /**
@@ -352,11 +374,11 @@ static int __devinit sil680_init_one(struct pci_dev *pdev,
         ata_sff_std_ports(&host->ports[1]->ioaddr);
 
         /* Register & activate */
-        return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
+        return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
                                  IRQF_SHARED, &sil680_sht);
 
 use_ioports:
-        return ata_pci_sff_init_one(pdev, ppi, &sil680_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/ata/pata_sis.c b/drivers/ata/pata_sis.c
index b6708032f321..60cea13cccce 100644
--- a/drivers/ata/pata_sis.c
+++ b/drivers/ata/pata_sis.c
@@ -826,7 +826,7 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 
         sis_fixup(pdev, chipset);
 
-        return ata_pci_sff_init_one(pdev, ppi, &sis_sht, chipset, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/ata/pata_sl82c105.c b/drivers/ata/pata_sl82c105.c
index 733b042a7469..98548f640c8e 100644
--- a/drivers/ata/pata_sl82c105.c
+++ b/drivers/ata/pata_sl82c105.c
@@ -316,7 +316,7 @@ static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id
         val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
         pci_write_config_dword(dev, 0x40, val);
 
-        return ata_pci_sff_init_one(dev, ppi, &sl82c105_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(dev, ppi, &sl82c105_sht, NULL, 0);
 }
 
 static const struct pci_device_id sl82c105[] = {
diff --git a/drivers/ata/pata_triflex.c b/drivers/ata/pata_triflex.c
index 48f50600ed2a..0d1f89e571dd 100644
--- a/drivers/ata/pata_triflex.c
+++ b/drivers/ata/pata_triflex.c
@@ -201,7 +201,7 @@ static int triflex_init_one(struct pci_dev *dev, const struct pci_device_id *id)
         if (!printed_version++)
                 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
 
-        return ata_pci_sff_init_one(dev, ppi, &triflex_sht, NULL, 0);
+        return ata_pci_bmdma_init_one(dev, ppi, &triflex_sht, NULL, 0);
 }
 
 static const struct pci_device_id triflex[] = {
diff --git a/drivers/ata/pata_via.c b/drivers/ata/pata_via.c
index 741e7cb69d8c..ac8d7d97e408 100644
--- a/drivers/ata/pata_via.c
+++ b/drivers/ata/pata_via.c
@@ -355,7 +355,7 @@ static unsigned long via_mode_filter(struct ata_device *dev, unsigned long mask)
                         mask &= ~ ATA_MASK_UDMA;
                 }
         }
-        return ata_bmdma_mode_filter(dev, mask);
+        return mask;
 }
 
 /**
@@ -426,7 +426,7 @@ static int via_port_start(struct ata_port *ap)
         struct via_port *vp;
         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 
-        int ret = ata_sff_port_start(ap);
+        int ret = ata_bmdma_port_start(ap);
         if (ret < 0)
                 return ret;
 
@@ -629,7 +629,7 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
         }
 
         /* We have established the device type, now fire it up */
-        return ata_pci_sff_init_one(pdev, ppi, &via_sht, (void *)config, 0);
+        return ata_pci_bmdma_init_one(pdev, ppi, &via_sht, (void *)config, 0);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/ata/pata_winbond.c b/drivers/ata/pata_winbond.c
deleted file mode 100644
index 6d8619b6f670..000000000000
--- a/drivers/ata/pata_winbond.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- *    pata_winbond.c - Winbond VLB ATA controllers
- *      (C) 2006 Red Hat
- *
- *    Support for the Winbond 83759A when operating in advanced mode.
- *    Multichip mode is not currently supported.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/blkdev.h>
-#include <linux/delay.h>
-#include <scsi/scsi_host.h>
-#include <linux/libata.h>
-#include <linux/platform_device.h>
-
-#define DRV_NAME "pata_winbond"
-#define DRV_VERSION "0.0.3"
-
-#define NR_HOST 4       /* Two winbond controllers, two channels each */
-
-struct winbond_data {
-        unsigned long config;
-        struct platform_device *platform_dev;
-};
-
-static struct ata_host *winbond_host[NR_HOST];
-static struct winbond_data winbond_data[NR_HOST];
-static int nr_winbond_host;
-
-#ifdef MODULE
-static int probe_winbond = 1;
-#else
-static int probe_winbond;
-#endif
-
-static DEFINE_SPINLOCK(winbond_lock);
-
-static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&winbond_lock, flags);
-        outb(reg, port + 0x01);
-        outb(val, port + 0x02);
-        spin_unlock_irqrestore(&winbond_lock, flags);
-}
-
-static u8 winbond_readcfg(unsigned long port, u8 reg)
-{
-        u8 val;
-
-        unsigned long flags;
-        spin_lock_irqsave(&winbond_lock, flags);
-        outb(reg, port + 0x01);
-        val = inb(port + 0x02);
-        spin_unlock_irqrestore(&winbond_lock, flags);
-
-        return val;
-}
-
-static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
-{
-        struct ata_timing t;
-        struct winbond_data *winbond = ap->host->private_data;
-        int active, recovery;
-        u8 reg;
-        int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
-
-        reg = winbond_readcfg(winbond->config, 0x81);
-
-        /* Get the timing data in cycles */
-        if (reg & 0x40)         /* Fast VLB bus, assume 50MHz */
-                ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
-        else
-                ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
-
-        active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
-        recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
-        timing = (active << 4) | recovery;
-        winbond_writecfg(winbond->config, timing, reg);
-
-        /* Load the setup timing */
-
-        reg = 0x35;
-        if (adev->class != ATA_DEV_ATA)
-                reg |= 0x08;    /* FIFO off */
-        if (!ata_pio_need_iordy(adev))
-                reg |= 0x02;    /* IORDY off */
-        reg |= (clamp_val(t.setup, 0, 3) << 6);
-        winbond_writecfg(winbond->config, timing + 1, reg);
-}
-
-
-static unsigned int winbond_data_xfer(struct ata_device *dev,
-                        unsigned char *buf, unsigned int buflen, int rw)
-{
-        struct ata_port *ap = dev->link->ap;
-        int slop = buflen & 3;
-
-        if (ata_id_has_dword_io(dev->id)) {
-                if (rw == READ)
-                        ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
-                else
-                        iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
-
-                if (unlikely(slop)) {
-                        __le32 pad;
-                        if (rw == READ) {
-                                pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
-                                memcpy(buf + buflen - slop, &pad, slop);
-                        } else {
-                                memcpy(&pad, buf + buflen - slop, slop);
-                                iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
-                        }
-                        buflen += 4 - slop;
-                }
-        } else
-                buflen = ata_sff_data_xfer(dev, buf, buflen, rw);
-
-        return buflen;
-}
-
-static struct scsi_host_template winbond_sht = {
-        ATA_PIO_SHT(DRV_NAME),
-};
-
-static struct ata_port_operations winbond_port_ops = {
-        .inherits       = &ata_sff_port_ops,
-        .sff_data_xfer  = winbond_data_xfer,
-        .cable_detect   = ata_cable_40wire,
-        .set_piomode    = winbond_set_piomode,
-};
-
-/**
- *      winbond_init_one                -       attach a winbond interface
- *      @type: Type to display
- *      @io: I/O port start
- *      @irq: interrupt line
- *      @fast: True if on a > 33Mhz VLB
- *
- *      Register a VLB bus IDE interface. Such interfaces are PIO and we
- *      assume do not support IRQ sharing.
- */
-
-static __init int winbond_init_one(unsigned long port)
-{
-        struct platform_device *pdev;
-        u8 reg;
-        int i, rc;
-
-        reg = winbond_readcfg(port, 0x81);
-        reg |= 0x80;    /* jumpered mode off */
-        winbond_writecfg(port, 0x81, reg);
-        reg = winbond_readcfg(port, 0x83);
-        reg |= 0xF0;    /* local control */
-        winbond_writecfg(port, 0x83, reg);
-        reg = winbond_readcfg(port, 0x85);
-        reg |= 0xF0;    /* programmable timing */
-        winbond_writecfg(port, 0x85, reg);
-
-        reg = winbond_readcfg(port, 0x81);
-
-        if (!(reg & 0x03))              /* Disabled */
-                return -ENODEV;
-
-        for (i = 0; i < 2 ; i ++) {
-                unsigned long cmd_port = 0x1F0 - (0x80 * i);
-                unsigned long ctl_port = cmd_port + 0x206;
-                struct ata_host *host;
-                struct ata_port *ap;
-                void __iomem *cmd_addr, *ctl_addr;
-
-                if (!(reg & (1 << i)))
-                        continue;
-
-                pdev = platform_device_register_simple(DRV_NAME, nr_winbond_host, NULL, 0);
-                if (IS_ERR(pdev))
-                        return PTR_ERR(pdev);
-
-                rc = -ENOMEM;
-                host = ata_host_alloc(&pdev->dev, 1);
-                if (!host)
-                        goto err_unregister;
-                ap = host->ports[0];
-
-                rc = -ENOMEM;
-                cmd_addr = devm_ioport_map(&pdev->dev, cmd_port, 8);
-                ctl_addr = devm_ioport_map(&pdev->dev, ctl_port, 1);
-                if (!cmd_addr || !ctl_addr)
-                        goto err_unregister;
-
-                ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", cmd_port, ctl_port);
-
-                ap->ops = &winbond_port_ops;
-                ap->pio_mask = ATA_PIO4;
-                ap->flags |= ATA_FLAG_SLAVE_POSS;
-                ap->ioaddr.cmd_addr = cmd_addr;
-                ap->ioaddr.altstatus_addr = ctl_addr;
-                ap->ioaddr.ctl_addr = ctl_addr;
-                ata_sff_std_ports(&ap->ioaddr);
-
-                /* hook in a private data structure per channel */
-                host->private_data = &winbond_data[nr_winbond_host];
-                winbond_data[nr_winbond_host].config = port;
-                winbond_data[nr_winbond_host].platform_dev = pdev;
-
-                /* activate */
-                rc = ata_host_activate(host, 14 + i, ata_sff_interrupt, 0,
-                                       &winbond_sht);
-                if (rc)
-                        goto err_unregister;
-
-                winbond_host[nr_winbond_host++] = dev_get_drvdata(&pdev->dev);
-        }
-
-        return 0;
-
- err_unregister:
-        platform_device_unregister(pdev);
-        return rc;
-}
-
-/**
- *      winbond_init            -       attach winbond interfaces
- *
- *      Attach winbond IDE interfaces by scanning the ports it may occupy.
- */
-
-static __init int winbond_init(void)
-{
-        static const unsigned long config[2] = { 0x130, 0x1B0 };
-
-        int ct = 0;
-        int i;
-
-        if (probe_winbond == 0)
-                return -ENODEV;
-
-        /*
-         *      Check both base addresses
-         */
-
-        for (i = 0; i < 2; i++) {
-                if (probe_winbond & (1<<i)) {
-                        int ret = 0;
-                        unsigned long port = config[i];
-
-                        if (request_region(port, 2, "pata_winbond")) {
-                                ret = winbond_init_one(port);
-                                if (ret <= 0)
-                                        release_region(port, 2);
-                                else ct+= ret;
-                        }
-                }
-        }
-        if (ct != 0)
-                return 0;
-        return -ENODEV;
-}
-
-static __exit void winbond_exit(void)
-{
-        int i;
-
-        for (i = 0; i < nr_winbond_host; i++) {
-                ata_host_detach(winbond_host[i]);
-                release_region(winbond_data[i].config, 2);
-                platform_device_unregister(winbond_data[i].platform_dev);
-        }
-}
-
-MODULE_AUTHOR("Alan Cox");
-MODULE_DESCRIPTION("low-level driver for Winbond VL ATA");
-MODULE_LICENSE("GPL");
-MODULE_VERSION(DRV_VERSION);
-
-module_init(winbond_init);
-module_exit(winbond_exit);
-
-module_param(probe_winbond, int, 0);
-
diff --git a/drivers/ata/pdc_adma.c b/drivers/ata/pdc_adma.c
index 5904cfdb8dbe..adbe0426c8f0 100644
--- a/drivers/ata/pdc_adma.c
+++ b/drivers/ata/pdc_adma.c
@@ -324,10 +324,8 @@ static void adma_qc_prep(struct ata_queued_cmd *qc)
         VPRINTK("ENTER\n");
 
         adma_enter_reg_mode(qc->ap);
-        if (qc->tf.protocol != ATA_PROT_DMA) {
-                ata_sff_qc_prep(qc);
+        if (qc->tf.protocol != ATA_PROT_DMA)
                 return;
-        }
 
         buf[i++] = 0;   /* Response flags */
         buf[i++] = 0;   /* reserved */
@@ -442,8 +440,6 @@ static inline unsigned int adma_intr_pkt(struct ata_host *host)
                         continue;
                 handled = 1;
                 adma_enter_reg_mode(ap);
-                if (ap->flags & ATA_FLAG_DISABLED)
-                        continue;
                 pp = ap->private_data;
                 if (!pp || pp->state != adma_state_pkt)
                         continue;
@@ -484,42 +480,38 @@ static inline unsigned int adma_intr_mmio(struct ata_host *host)
         unsigned int handled = 0, port_no;
 
         for (port_no = 0; port_no < host->n_ports; ++port_no) {
-                struct ata_port *ap;
-                ap = host->ports[port_no];
-                if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
-                        struct ata_queued_cmd *qc;
-                        struct adma_port_priv *pp = ap->private_data;
-                        if (!pp || pp->state != adma_state_mmio)
+                struct ata_port *ap = host->ports[port_no];
+                struct adma_port_priv *pp = ap->private_data;
+                struct ata_queued_cmd *qc;
+
+                if (!pp || pp->state != adma_state_mmio)
+                        continue;
+                qc = ata_qc_from_tag(ap, ap->link.active_tag);
+                if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
+
+                        /* check main status, clearing INTRQ */
+                        u8 status = ata_sff_check_status(ap);
+                        if ((status & ATA_BUSY))
                                 continue;
-                        qc = ata_qc_from_tag(ap, ap->link.active_tag);
-                        if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
-
-                                /* check main status, clearing INTRQ */
-                                u8 status = ata_sff_check_status(ap);
-                                if ((status & ATA_BUSY))
-                                        continue;
-                                DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
-                                        ap->print_id, qc->tf.protocol, status);
-
-                                /* complete taskfile transaction */
-                                pp->state = adma_state_idle;
-                                qc->err_mask |= ac_err_mask(status);
-                                if (!qc->err_mask)
-                                        ata_qc_complete(qc);
-                                else {
-                                        struct ata_eh_info *ehi =
-                                                &ap->link.eh_info;
-                                        ata_ehi_clear_desc(ehi);
-                                        ata_ehi_push_desc(ehi,
-                                                "status 0x%02X", status);
-
-                                        if (qc->err_mask == AC_ERR_DEV)
-                                                ata_port_abort(ap);
-                                        else
-                                                ata_port_freeze(ap);
-                                }
-                                handled = 1;
+                        DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
+                                ap->print_id, qc->tf.protocol, status);
+
+                        /* complete taskfile transaction */
+                        pp->state = adma_state_idle;
+                        qc->err_mask |= ac_err_mask(status);
+                        if (!qc->err_mask)
+                                ata_qc_complete(qc);
+                        else {
+                                struct ata_eh_info *ehi = &ap->link.eh_info;
+                                ata_ehi_clear_desc(ehi);
+                                ata_ehi_push_desc(ehi, "status 0x%02X", status);
+
+                                if (qc->err_mask == AC_ERR_DEV)
+                                        ata_port_abort(ap);
+                                else
+                                        ata_port_freeze(ap);
                         }
+                        handled = 1;
                 }
         }
         return handled;
@@ -562,11 +554,7 @@ static int adma_port_start(struct ata_port *ap)
 {
         struct device *dev = ap->host->dev;
         struct adma_port_priv *pp;
-        int rc;
 
-        rc = ata_port_start(ap);
-        if (rc)
-                return rc;
         adma_enter_reg_mode(ap);
         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
         if (!pp)
diff --git a/drivers/ata/sata_dwc_460ex.c b/drivers/ata/sata_dwc_460ex.c
new file mode 100644
index 000000000000..6cf57c5c2b5f
--- /dev/null
+++ b/drivers/ata/sata_dwc_460ex.c
@@ -0,0 +1,1756 @@
+/*
+ * drivers/ata/sata_dwc_460ex.c
+ *
+ * Synopsys DesignWare Cores (DWC) SATA host driver
+ *
+ * Author: Mark Miesfeld <mmiesfeld@amcc.com>
+ *
+ * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
+ * Copyright 2008 DENX Software Engineering
+ *
+ * Based on versions provided by AMCC and Synopsys which are:
+ *          Copyright 2006 Applied Micro Circuits Corporation
+ *          COPYRIGHT (C) 2005  SYNOPSYS, INC.  ALL RIGHTS RESERVED
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef CONFIG_SATA_DWC_DEBUG
+#define DEBUG
+#endif
+
+#ifdef CONFIG_SATA_DWC_VDEBUG
+#define VERBOSE_DEBUG
+#define DEBUG_NCQ
+#endif
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/libata.h>
+#include <linux/slab.h>
+#include "libata.h"
+
+#include <scsi/scsi_host.h>
+#include <scsi/scsi_cmnd.h>
+
+#define DRV_NAME        "sata-dwc"
+#define DRV_VERSION     "1.0"
+
+/* SATA DMA driver Globals */
+#define DMA_NUM_CHANS           1
+#define DMA_NUM_CHAN_REGS       8
+
+/* SATA DMA Register definitions */
+#define AHB_DMA_BRST_DFLT       64      /* 16 data items burst length*/
+
+struct dmareg {
+        u32 low;                /* Low bits 0-31 */
+        u32 high;               /* High bits 32-63 */
+};
+
+/* DMA Per Channel registers */
+struct dma_chan_regs {
+        struct dmareg sar;      /* Source Address */
+        struct dmareg dar;      /* Destination address */
+        struct dmareg llp;      /* Linked List Pointer */
+        struct dmareg ctl;      /* Control */
+        struct dmareg sstat;    /* Source Status not implemented in core */
+        struct dmareg dstat;    /* Destination Status not implemented in core*/
+        struct dmareg sstatar;  /* Source Status Address not impl in core */
+        struct dmareg dstatar;  /* Destination Status Address not implemente */
+        struct dmareg cfg;      /* Config */
+        struct dmareg sgr;      /* Source Gather */
+        struct dmareg dsr;      /* Destination Scatter */
+};
+
+/* Generic Interrupt Registers */
+struct dma_interrupt_regs {
+        struct dmareg tfr;      /* Transfer Interrupt */
+        struct dmareg block;    /* Block Interrupt */
+        struct dmareg srctran;  /* Source Transfer Interrupt */
+        struct dmareg dsttran;  /* Dest Transfer Interrupt */
+        struct dmareg error;    /* Error */
+};
+
+struct ahb_dma_regs {
+        struct dma_chan_regs    chan_regs[DMA_NUM_CHAN_REGS];
+        struct dma_interrupt_regs interrupt_raw;        /* Raw Interrupt */
+        struct dma_interrupt_regs interrupt_status;     /* Interrupt Status */
+        struct dma_interrupt_regs interrupt_mask;       /* Interrupt Mask */
+        struct dma_interrupt_regs interrupt_clear;      /* Interrupt Clear */
+        struct dmareg           statusInt;      /* Interrupt combined*/
+        struct dmareg           rq_srcreg;      /* Src Trans Req */
+        struct dmareg           rq_dstreg;      /* Dst Trans Req */
+        struct dmareg           rq_sgl_srcreg;  /* Sngl Src Trans Req*/
+        struct dmareg           rq_sgl_dstreg;  /* Sngl Dst Trans Req*/
+        struct dmareg           rq_lst_srcreg;  /* Last Src Trans Req*/
+        struct dmareg           rq_lst_dstreg;  /* Last Dst Trans Req*/
+        struct dmareg           dma_cfg;                /* DMA Config */
+        struct dmareg           dma_chan_en;            /* DMA Channel Enable*/
+        struct dmareg           dma_id;                 /* DMA ID */
+        struct dmareg           dma_test;               /* DMA Test */
+        struct dmareg           res1;                   /* reserved */
+        struct dmareg           res2;                   /* reserved */
+        /*
+         * DMA Comp Params
+         * Param 6 = dma_param[0], Param 5 = dma_param[1],
+         * Param 4 = dma_param[2] ...
+         */
+        struct dmareg           dma_params[6];
+};
+
+/* Data structure for linked list item */
+struct lli {
+        u32             sar;            /* Source Address */
+        u32             dar;            /* Destination address */
+        u32             llp;            /* Linked List Pointer */
+        struct dmareg   ctl;            /* Control */
+        struct dmareg   dstat;          /* Destination Status */
+};
+
+enum {
+        SATA_DWC_DMAC_LLI_SZ =  (sizeof(struct lli)),
+        SATA_DWC_DMAC_LLI_NUM = 256,
+        SATA_DWC_DMAC_LLI_TBL_SZ = (SATA_DWC_DMAC_LLI_SZ * \
+                                        SATA_DWC_DMAC_LLI_NUM),
+        SATA_DWC_DMAC_TWIDTH_BYTES = 4,
+        SATA_DWC_DMAC_CTRL_TSIZE_MAX = (0x00000800 * \
+                                                SATA_DWC_DMAC_TWIDTH_BYTES),
+};
+
+/* DMA Register Operation Bits */
+enum {
+        DMA_EN  =               0x00000001, /* Enable AHB DMA */
+        DMA_CTL_LLP_SRCEN =     0x10000000, /* Blk chain enable Src */
+        DMA_CTL_LLP_DSTEN =     0x08000000, /* Blk chain enable Dst */
+};
+
+#define DMA_CTL_BLK_TS(size)    ((size) & 0x000000FFF)  /* Blk Transfer size */
+#define DMA_CHANNEL(ch)         (0x00000001 << (ch))    /* Select channel */
+        /* Enable channel */
+#define DMA_ENABLE_CHAN(ch)     ((0x00000001 << (ch)) |                 \
+                                 ((0x000000001 << (ch)) << 8))
+        /* Disable channel */
+#define DMA_DISABLE_CHAN(ch)    (0x00000000 | ((0x000000001 << (ch)) << 8))
+        /* Transfer Type & Flow Controller */
+#define DMA_CTL_TTFC(type)      (((type) & 0x7) << 20)
+#define DMA_CTL_SMS(num)        (((num) & 0x3) << 25) /* Src Master Select */
+#define DMA_CTL_DMS(num)        (((num) & 0x3) << 23)/* Dst Master Select */
+        /* Src Burst Transaction Length */
+#define DMA_CTL_SRC_MSIZE(size) (((size) & 0x7) << 14)
+        /* Dst Burst Transaction Length */
+#define DMA_CTL_DST_MSIZE(size) (((size) & 0x7) << 11)
+        /* Source Transfer Width */
+#define DMA_CTL_SRC_TRWID(size) (((size) & 0x7) << 4)
+        /* Destination Transfer Width */
+#define DMA_CTL_DST_TRWID(size) (((size) & 0x7) << 1)
+
+/* Assign HW handshaking interface (x) to destination / source peripheral */
+#define DMA_CFG_HW_HS_DEST(int_num) (((int_num) & 0xF) << 11)
+#define DMA_CFG_HW_HS_SRC(int_num) (((int_num) & 0xF) << 7)
+#define DMA_LLP_LMS(addr, master) (((addr) & 0xfffffffc) | (master))
+
+/*
+ * This define is used to set block chaining disabled in the control low
+ * register.  It is already in little endian format so it can be &'d dirctly.
+ * It is essentially: cpu_to_le32(~(DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN))
+ */
+enum {
+        DMA_CTL_LLP_DISABLE_LE32 = 0xffffffe7,
+        DMA_CTL_TTFC_P2M_DMAC = 0x00000002, /* Per to mem, DMAC cntr */
+        DMA_CTL_TTFC_M2P_PER =  0x00000003, /* Mem to per, peripheral cntr */
+        DMA_CTL_SINC_INC =      0x00000000, /* Source Address Increment */
+        DMA_CTL_SINC_DEC =      0x00000200,
+        DMA_CTL_SINC_NOCHANGE = 0x00000400,
+        DMA_CTL_DINC_INC =      0x00000000, /* Destination Address Increment */
+        DMA_CTL_DINC_DEC =      0x00000080,
+        DMA_CTL_DINC_NOCHANGE = 0x00000100,
+        DMA_CTL_INT_EN =        0x00000001, /* Interrupt Enable */
+
+/* Channel Configuration Register high bits */
+        DMA_CFG_FCMOD_REQ =     0x00000001, /* Flow Control - request based */
+        DMA_CFG_PROTCTL =       (0x00000003 << 2),/* Protection Control */
+
+/* Channel Configuration Register low bits */
+        DMA_CFG_RELD_DST =      0x80000000, /* Reload Dest / Src Addr */
+        DMA_CFG_RELD_SRC =      0x40000000,
+        DMA_CFG_HS_SELSRC =     0x00000800, /* Software handshake Src/ Dest */
+        DMA_CFG_HS_SELDST =     0x00000400,
+        DMA_CFG_FIFOEMPTY =     (0x00000001 << 9), /* FIFO Empty bit */
+
+/* Channel Linked List Pointer Register */
+        DMA_LLP_AHBMASTER1 =    0,      /* List Master Select */
+        DMA_LLP_AHBMASTER2 =    1,
+
+        SATA_DWC_MAX_PORTS = 1,
+
+        SATA_DWC_SCR_OFFSET = 0x24,
+        SATA_DWC_REG_OFFSET = 0x64,
+};
+
+/* DWC SATA Registers */
+struct sata_dwc_regs {
+        u32 fptagr;             /* 1st party DMA tag */
+        u32 fpbor;              /* 1st party DMA buffer offset */
+        u32 fptcr;              /* 1st party DMA Xfr count */
+        u32 dmacr;              /* DMA Control */
+        u32 dbtsr;              /* DMA Burst Transac size */
+        u32 intpr;              /* Interrupt Pending */
+        u32 intmr;              /* Interrupt Mask */
+        u32 errmr;              /* Error Mask */
+        u32 llcr;               /* Link Layer Control */
+        u32 phycr;              /* PHY Control */
+        u32 physr;              /* PHY Status */
+        u32 rxbistpd;           /* Recvd BIST pattern def register */
+        u32 rxbistpd1;          /* Recvd BIST data dword1 */
+        u32 rxbistpd2;          /* Recvd BIST pattern data dword2 */
+        u32 txbistpd;           /* Trans BIST pattern def register */
+        u32 txbistpd1;          /* Trans BIST data dword1 */
+        u32 txbistpd2;          /* Trans BIST data dword2 */
+        u32 bistcr;             /* BIST Control Register */
+        u32 bistfctr;           /* BIST FIS Count Register */
+        u32 bistsr;             /* BIST Status Register */
+        u32 bistdecr;           /* BIST Dword Error count register */
+        u32 res[15];            /* Reserved locations */
+        u32 testr;              /* Test Register */
+        u32 versionr;           /* Version Register */
+        u32 idr;                /* ID Register */
+        u32 unimpl[192];        /* Unimplemented */
+        u32 dmadr[256]; /* FIFO Locations in DMA Mode */
+};
+
+enum {
+        SCR_SCONTROL_DET_ENABLE =       0x00000001,
+        SCR_SSTATUS_DET_PRESENT =       0x00000001,
+        SCR_SERROR_DIAG_X       =       0x04000000,
+/* DWC SATA Register Operations */
+        SATA_DWC_TXFIFO_DEPTH   =       0x01FF,
+        SATA_DWC_RXFIFO_DEPTH   =       0x01FF,
+        SATA_DWC_DMACR_TMOD_TXCHEN =    0x00000004,
+        SATA_DWC_DMACR_TXCHEN   = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
+        SATA_DWC_DMACR_RXCHEN   = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
+        SATA_DWC_DMACR_TXRXCH_CLEAR =   SATA_DWC_DMACR_TMOD_TXCHEN,
+        SATA_DWC_INTPR_DMAT     =       0x00000001,
+        SATA_DWC_INTPR_NEWFP    =       0x00000002,
+        SATA_DWC_INTPR_PMABRT   =       0x00000004,
+        SATA_DWC_INTPR_ERR      =       0x00000008,
+        SATA_DWC_INTPR_NEWBIST  =       0x00000010,
+        SATA_DWC_INTPR_IPF      =       0x10000000,
+        SATA_DWC_INTMR_DMATM    =       0x00000001,
+        SATA_DWC_INTMR_NEWFPM   =       0x00000002,
+        SATA_DWC_INTMR_PMABRTM  =       0x00000004,
+        SATA_DWC_INTMR_ERRM     =       0x00000008,
+        SATA_DWC_INTMR_NEWBISTM =       0x00000010,
+        SATA_DWC_LLCR_SCRAMEN   =       0x00000001,
+        SATA_DWC_LLCR_DESCRAMEN =       0x00000002,
+        SATA_DWC_LLCR_RPDEN     =       0x00000004,
+/* This is all error bits, zero's are reserved fields. */
+        SATA_DWC_SERROR_ERR_BITS =      0x0FFF0F03
+};
+
+#define SATA_DWC_SCR0_SPD_GET(v)        (((v) >> 4) & 0x0000000F)
+#define SATA_DWC_DMACR_TX_CLEAR(v)      (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
+                                                 SATA_DWC_DMACR_TMOD_TXCHEN)
+#define SATA_DWC_DMACR_RX_CLEAR(v)      (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
+                                                 SATA_DWC_DMACR_TMOD_TXCHEN)
+#define SATA_DWC_DBTSR_MWR(size)        (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
+#define SATA_DWC_DBTSR_MRD(size)        ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
+                                                 << 16)
+struct sata_dwc_device {
+        struct device           *dev;           /* generic device struct */
+        struct ata_probe_ent    *pe;            /* ptr to probe-ent */
+        struct ata_host         *host;
+        u8                      *reg_base;
+        struct sata_dwc_regs    *sata_dwc_regs; /* DW Synopsys SATA specific */
+        int                     irq_dma;
+};
+
+#define SATA_DWC_QCMD_MAX       32
+
+struct sata_dwc_device_port {
+        struct sata_dwc_device  *hsdev;
+        int                     cmd_issued[SATA_DWC_QCMD_MAX];
+        struct lli              *llit[SATA_DWC_QCMD_MAX];  /* DMA LLI table */
+        dma_addr_t              llit_dma[SATA_DWC_QCMD_MAX];
+        u32                     dma_chan[SATA_DWC_QCMD_MAX];
+        int                     dma_pending[SATA_DWC_QCMD_MAX];
+};
+
+/*
+ * Commonly used DWC SATA driver Macros
+ */
+#define HSDEV_FROM_HOST(host)  ((struct sata_dwc_device *)\
+                                        (host)->private_data)
+#define HSDEV_FROM_AP(ap)  ((struct sata_dwc_device *)\
+                                        (ap)->host->private_data)
+#define HSDEVP_FROM_AP(ap)   ((struct sata_dwc_device_port *)\
+                                        (ap)->private_data)
+#define HSDEV_FROM_QC(qc)       ((struct sata_dwc_device *)\
+                                        (qc)->ap->host->private_data)
+#define HSDEV_FROM_HSDEVP(p)    ((struct sata_dwc_device *)\
+                                                (hsdevp)->hsdev)
+
+enum {
+        SATA_DWC_CMD_ISSUED_NOT         = 0,
+        SATA_DWC_CMD_ISSUED_PEND        = 1,
+        SATA_DWC_CMD_ISSUED_EXEC        = 2,
+        SATA_DWC_CMD_ISSUED_NODATA      = 3,
+
+        SATA_DWC_DMA_PENDING_NONE       = 0,
+        SATA_DWC_DMA_PENDING_TX         = 1,
+        SATA_DWC_DMA_PENDING_RX         = 2,
+};
+
+struct sata_dwc_host_priv {
+        void    __iomem  *scr_addr_sstatus;
+        u32     sata_dwc_sactive_issued ;
+        u32     sata_dwc_sactive_queued ;
+        u32     dma_interrupt_count;
+        struct  ahb_dma_regs    *sata_dma_regs;
+        struct  device  *dwc_dev;
+};
+struct sata_dwc_host_priv host_pvt;
+/*
+ * Prototypes
+ */
+static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
+static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
+                                u32 check_status);
+static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
+static void sata_dwc_port_stop(struct ata_port *ap);
+static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
+static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq);
+static void dma_dwc_exit(struct sata_dwc_device *hsdev);
+static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
+                              struct lli *lli, dma_addr_t dma_lli,
+                              void __iomem *addr, int dir);
+static void dma_dwc_xfer_start(int dma_ch);
+
+static void sata_dwc_tf_dump(struct ata_taskfile *tf)
+{
+        dev_vdbg(host_pvt.dwc_dev, "taskfile cmd: 0x%02x protocol: %s flags:"
+                "0x%lx device: %x\n", tf->command, ata_get_cmd_descript\
+                (tf->protocol), tf->flags, tf->device);
+        dev_vdbg(host_pvt.dwc_dev, "feature: 0x%02x nsect: 0x%x lbal: 0x%x "
+                "lbam: 0x%x lbah: 0x%x\n", tf->feature, tf->nsect, tf->lbal,
+                 tf->lbam, tf->lbah);
+        dev_vdbg(host_pvt.dwc_dev, "hob_feature: 0x%02x hob_nsect: 0x%x "
+                "hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
+                tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
+                tf->hob_lbah);
+}
+
+/*
+ * Function: get_burst_length_encode
+ * arguments: datalength: length in bytes of data
+ * returns value to be programmed in register corrresponding to data length
+ * This value is effectively the log(base 2) of the length
+ */
+static  int get_burst_length_encode(int datalength)
+{
+        int items = datalength >> 2;    /* div by 4 to get lword count */
+
+        if (items >= 64)
+                return 5;
+
+        if (items >= 32)
+                return 4;
+
+        if (items >= 16)
+                return 3;
+
+        if (items >= 8)
+                return 2;
+
+        if (items >= 4)
+                return 1;
+
+        return 0;
+}
+
+static  void clear_chan_interrupts(int c)
+{
+        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.tfr.low),
+                 DMA_CHANNEL(c));
+        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.block.low),
+                 DMA_CHANNEL(c));
+        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.srctran.low),
+                 DMA_CHANNEL(c));
+        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.dsttran.low),
+                 DMA_CHANNEL(c));
+        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.error.low),
+                 DMA_CHANNEL(c));
+}
+
+/*
+ * Function: dma_request_channel
+ * arguments: None
+ * returns channel number if available else -1
+ * This function assigns the next available DMA channel from the list to the
+ * requester
+ */
+static int dma_request_channel(void)
+{
+        int i;
+
+        for (i = 0; i < DMA_NUM_CHANS; i++) {
+                if (!(in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) &\
+                        DMA_CHANNEL(i)))
+                        return i;
+        }
+        dev_err(host_pvt.dwc_dev, "%s NO channel chan_en: 0x%08x\n", __func__,
+                in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)));
+        return -1;
+}
+
+/*
+ * Function: dma_dwc_interrupt
+ * arguments: irq, dev_id, pt_regs
+ * returns channel number if available else -1
+ * Interrupt Handler for DW AHB SATA DMA
+ */
+static irqreturn_t dma_dwc_interrupt(int irq, void *hsdev_instance)
+{
+        int chan;
+        u32 tfr_reg, err_reg;
+        unsigned long flags;
+        struct sata_dwc_device *hsdev =
+                (struct sata_dwc_device *)hsdev_instance;
+        struct ata_host *host = (struct ata_host *)hsdev->host;
+        struct ata_port *ap;
+        struct sata_dwc_device_port *hsdevp;
+        u8 tag = 0;
+        unsigned int port = 0;
+
+        spin_lock_irqsave(&host->lock, flags);
+        ap = host->ports[port];
+        hsdevp = HSDEVP_FROM_AP(ap);
+        tag = ap->link.active_tag;
+
+        tfr_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.tfr\
+                        .low));
+        err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error\
+                        .low));
+
+        dev_dbg(ap->dev, "eot=0x%08x err=0x%08x pending=%d active port=%d\n",
+                tfr_reg, err_reg, hsdevp->dma_pending[tag], port);
+
+        for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
+                /* Check for end-of-transfer interrupt. */
+                if (tfr_reg & DMA_CHANNEL(chan)) {
+                        /*
+                         * Each DMA command produces 2 interrupts.  Only
+                         * complete the command after both interrupts have been
+                         * seen. (See sata_dwc_isr())
+                         */
+                        host_pvt.dma_interrupt_count++;
+                        sata_dwc_clear_dmacr(hsdevp, tag);
+
+                        if (hsdevp->dma_pending[tag] ==
+                            SATA_DWC_DMA_PENDING_NONE) {
+                                dev_err(ap->dev, "DMA not pending eot=0x%08x "
+                                        "err=0x%08x tag=0x%02x pending=%d\n",
+                                        tfr_reg, err_reg, tag,
+                                        hsdevp->dma_pending[tag]);
+                        }
+
+                        if ((host_pvt.dma_interrupt_count % 2) == 0)
+                                sata_dwc_dma_xfer_complete(ap, 1);
+
+                        /* Clear the interrupt */
+                        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
+                                .tfr.low),
+                                 DMA_CHANNEL(chan));
+                }
+
+                /* Check for error interrupt. */
+                if (err_reg & DMA_CHANNEL(chan)) {
+                        /* TODO Need error handler ! */
+                        dev_err(ap->dev, "error interrupt err_reg=0x%08x\n",
+                                err_reg);
+
+                        /* Clear the interrupt. */
+                        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
+                                .error.low),
+                                 DMA_CHANNEL(chan));
+                }
+        }
+        spin_unlock_irqrestore(&host->lock, flags);
+        return IRQ_HANDLED;
+}
+
+/*
+ * Function: dma_request_interrupts
+ * arguments: hsdev
+ * returns status
+ * This function registers ISR for a particular DMA channel interrupt
+ */
+static int dma_request_interrupts(struct sata_dwc_device *hsdev, int irq)
+{
+        int retval = 0;
+        int chan;
+
+        for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
+                /* Unmask error interrupt */
+                out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.error.low,
+                         DMA_ENABLE_CHAN(chan));
+
+                /* Unmask end-of-transfer interrupt */
+                out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.tfr.low,
+                         DMA_ENABLE_CHAN(chan));
+        }
+
+        retval = request_irq(irq, dma_dwc_interrupt, 0, "SATA DMA", hsdev);
+        if (retval) {
+                dev_err(host_pvt.dwc_dev, "%s: could not get IRQ %d\n",
+                __func__, irq);
+                return -ENODEV;
+        }
+
+        /* Mark this interrupt as requested */
+        hsdev->irq_dma = irq;
+        return 0;
+}
+
+/*
+ * Function: map_sg_to_lli
+ * The Synopsis driver has a comment proposing that better performance
+ * is possible by only enabling interrupts on the last item in the linked list.
+ * However, it seems that could be a problem if an error happened on one of the
+ * first items.  The transfer would halt, but no error interrupt would occur.
+ * Currently this function sets interrupts enabled for each linked list item:
+ * DMA_CTL_INT_EN.
+ */
+static int map_sg_to_lli(struct scatterlist *sg, int num_elems,
+                        struct lli *lli, dma_addr_t dma_lli,
+                        void __iomem *dmadr_addr, int dir)
+{
+        int i, idx = 0;
+        int fis_len = 0;
+        dma_addr_t next_llp;
+        int bl;
+
+        dev_dbg(host_pvt.dwc_dev, "%s: sg=%p nelem=%d lli=%p dma_lli=0x%08x"
+                " dmadr=0x%08x\n", __func__, sg, num_elems, lli, (u32)dma_lli,
+                (u32)dmadr_addr);
+
+        bl = get_burst_length_encode(AHB_DMA_BRST_DFLT);
+
+        for (i = 0; i < num_elems; i++, sg++) {
+                u32 addr, offset;
+                u32 sg_len, len;
+
+                addr = (u32) sg_dma_address(sg);
+                sg_len = sg_dma_len(sg);
+
+                dev_dbg(host_pvt.dwc_dev, "%s: elem=%d sg_addr=0x%x sg_len"
+                        "=%d\n", __func__, i, addr, sg_len);
+
+                while (sg_len) {
+                        if (idx >= SATA_DWC_DMAC_LLI_NUM) {
+                                /* The LLI table is not large enough. */
+                                dev_err(host_pvt.dwc_dev, "LLI table overrun "
+                                "(idx=%d)\n", idx);
+                                break;
+                        }
+                        len = (sg_len > SATA_DWC_DMAC_CTRL_TSIZE_MAX) ?
+                                SATA_DWC_DMAC_CTRL_TSIZE_MAX : sg_len;
+
+                        offset = addr & 0xffff;
+                        if ((offset + sg_len) > 0x10000)
+                                len = 0x10000 - offset;
+
+                        /*
+                         * Make sure a LLI block is not created that will span
+                         * 8K max FIS boundary.  If the block spans such a FIS
+                         * boundary, there is a chance that a DMA burst will
+                         * cross that boundary -- this results in an error in
+                         * the host controller.
+                         */
+                        if (fis_len + len > 8192) {
+                                dev_dbg(host_pvt.dwc_dev, "SPLITTING: fis_len="
+                                        "%d(0x%x) len=%d(0x%x)\n", fis_len,
+                                         fis_len, len, len);
+                                len = 8192 - fis_len;
+                                fis_len = 0;
+                        } else {
+                                fis_len += len;
+                        }
+                        if (fis_len == 8192)
+                                fis_len = 0;
+
+                        /*
+                         * Set DMA addresses and lower half of control register
+                         * based on direction.
+                         */
+                        if (dir == DMA_FROM_DEVICE) {
+                                lli[idx].dar = cpu_to_le32(addr);
+                                lli[idx].sar = cpu_to_le32((u32)dmadr_addr);
+
+                                lli[idx].ctl.low = cpu_to_le32(
+                                        DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
+                                        DMA_CTL_SMS(0) |
+                                        DMA_CTL_DMS(1) |
+                                        DMA_CTL_SRC_MSIZE(bl) |
+                                        DMA_CTL_DST_MSIZE(bl) |
+                                        DMA_CTL_SINC_NOCHANGE |
+                                        DMA_CTL_SRC_TRWID(2) |
+                                        DMA_CTL_DST_TRWID(2) |
+                                        DMA_CTL_INT_EN |
+                                        DMA_CTL_LLP_SRCEN |
+                                        DMA_CTL_LLP_DSTEN);
+                        } else {        /* DMA_TO_DEVICE */
+                                lli[idx].sar = cpu_to_le32(addr);
+                                lli[idx].dar = cpu_to_le32((u32)dmadr_addr);
+
+                                lli[idx].ctl.low = cpu_to_le32(
+                                        DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
+                                        DMA_CTL_SMS(1) |
+                                        DMA_CTL_DMS(0) |
+                                        DMA_CTL_SRC_MSIZE(bl) |
+                                        DMA_CTL_DST_MSIZE(bl) |
+                                        DMA_CTL_DINC_NOCHANGE |
+                                        DMA_CTL_SRC_TRWID(2) |
+                                        DMA_CTL_DST_TRWID(2) |
+                                        DMA_CTL_INT_EN |
+                                        DMA_CTL_LLP_SRCEN |
+                                        DMA_CTL_LLP_DSTEN);
+                        }
+
+                        dev_dbg(host_pvt.dwc_dev, "%s setting ctl.high len: "
+                                "0x%08x val: 0x%08x\n", __func__,
+                                len, DMA_CTL_BLK_TS(len / 4));
+
+                        /* Program the LLI CTL high register */
+                        lli[idx].ctl.high = cpu_to_le32(DMA_CTL_BLK_TS\
+                                                (len / 4));
+
+                        /* Program the next pointer.  The next pointer must be
+                         * the physical address, not the virtual address.
+                         */
+                        next_llp = (dma_lli + ((idx + 1) * sizeof(struct \
+                                                        lli)));
+
+                        /* The last 2 bits encode the list master select. */
+                        next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER2);
+
+                        lli[idx].llp = cpu_to_le32(next_llp);
+                        idx++;
+                        sg_len -= len;
+                        addr += len;
+                }
+        }
+
+        /*
+         * The last next ptr has to be zero and the last control low register
+         * has to have LLP_SRC_EN and LLP_DST_EN (linked list pointer source
+         * and destination enable) set back to 0 (disabled.) This is what tells
+         * the core that this is the last item in the linked list.
+         */
+        if (idx) {
+                lli[idx-1].llp = 0x00000000;
+                lli[idx-1].ctl.low &= DMA_CTL_LLP_DISABLE_LE32;
+
+                /* Flush cache to memory */
+                dma_cache_sync(NULL, lli, (sizeof(struct lli) * idx),
+                               DMA_BIDIRECTIONAL);
+        }
+
+        return idx;
+}
+
+/*
+ * Function: dma_dwc_xfer_start
+ * arguments: Channel number
+ * Return : None
+ * Enables the DMA channel
+ */
+static void dma_dwc_xfer_start(int dma_ch)
+{
+        /* Enable the DMA channel */
+        out_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low),
+                 in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) |
+                 DMA_ENABLE_CHAN(dma_ch));
+}
+
+static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
+                              struct lli *lli, dma_addr_t dma_lli,
+                              void __iomem *addr, int dir)
+{
+        int dma_ch;
+        int num_lli;
+        /* Acquire DMA channel */
+        dma_ch = dma_request_channel();
+        if (dma_ch == -1) {
+                dev_err(host_pvt.dwc_dev, "%s: dma channel unavailable\n",
+                         __func__);
+                return -EAGAIN;
+        }
+
+        /* Convert SG list to linked list of items (LLIs) for AHB DMA */
+        num_lli = map_sg_to_lli(sg, num_elems, lli, dma_lli, addr, dir);
+
+        dev_dbg(host_pvt.dwc_dev, "%s sg: 0x%p, count: %d lli: %p dma_lli:"
+                " 0x%0xlx addr: %p lli count: %d\n", __func__, sg, num_elems,
+                 lli, (u32)dma_lli, addr, num_lli);
+
+        clear_chan_interrupts(dma_ch);
+
+        /* Program the CFG register. */
+        out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.high),
+                 DMA_CFG_PROTCTL | DMA_CFG_FCMOD_REQ);
+        out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.low), 0);
+
+        /* Program the address of the linked list */
+        out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].llp.low),
+                 DMA_LLP_LMS(dma_lli, DMA_LLP_AHBMASTER2));
+
+        /* Program the CTL register with src enable / dst enable */
+        out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].ctl.low),
+                 DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN);
+        return 0;
+}
+
+/*
+ * Function: dma_dwc_exit
+ * arguments: None
+ * returns status
+ * This function exits the SATA DMA driver
+ */
+static void dma_dwc_exit(struct sata_dwc_device *hsdev)
+{
+        dev_dbg(host_pvt.dwc_dev, "%s:\n", __func__);
+        if (host_pvt.sata_dma_regs)
+                iounmap(host_pvt.sata_dma_regs);
+
+        if (hsdev->irq_dma)
+                free_irq(hsdev->irq_dma, hsdev);
+}
+
+/*
+ * Function: dma_dwc_init
+ * arguments: hsdev
+ * returns status
+ * This function initializes the SATA DMA driver
+ */
+static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq)
+{
+        int err;
+
+        err = dma_request_interrupts(hsdev, irq);
+        if (err) {
+                dev_err(host_pvt.dwc_dev, "%s: dma_request_interrupts returns"
+                        " %d\n", __func__, err);
+                goto error_out;
+        }
+
+        /* Enabe DMA */
+        out_le32(&(host_pvt.sata_dma_regs->dma_cfg.low), DMA_EN);
+
+        dev_notice(host_pvt.dwc_dev, "DMA initialized\n");
+        dev_dbg(host_pvt.dwc_dev, "SATA DMA registers=0x%p\n", host_pvt.\
+                sata_dma_regs);
+
+        return 0;
+
+error_out:
+        dma_dwc_exit(hsdev);
+
+        return err;
+}
+
+static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
+{
+        if (scr > SCR_NOTIFICATION) {
+                dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
+                        __func__, scr);
+                return -EINVAL;
+        }
+
+        *val = in_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4));
+        dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
+                __func__, link->ap->print_id, scr, *val);
+
+        return 0;
+}
+
+static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
+{
+        dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
+                __func__, link->ap->print_id, scr, val);
+        if (scr > SCR_NOTIFICATION) {
+                dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
+                         __func__, scr);
+                return -EINVAL;
+        }
+        out_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4), val);
+
+        return 0;
+}
+
+static u32 core_scr_read(unsigned int scr)
+{
+        return in_le32((void __iomem *)(host_pvt.scr_addr_sstatus) +\
+                        (scr * 4));
+}
+
+static void core_scr_write(unsigned int scr, u32 val)
+{
+        out_le32((void __iomem *)(host_pvt.scr_addr_sstatus) + (scr * 4),
+                val);
+}
+
+static void clear_serror(void)
+{
+        u32 val;
+        val = core_scr_read(SCR_ERROR);
+        core_scr_write(SCR_ERROR, val);
+
+}
+
+static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
+{
+        out_le32(&hsdev->sata_dwc_regs->intpr,
+                 in_le32(&hsdev->sata_dwc_regs->intpr));
+}
+
+static u32 qcmd_tag_to_mask(u8 tag)
+{
+        return 0x00000001 << (tag & 0x1f);
+}
+
+/* See ahci.c */
+static void sata_dwc_error_intr(struct ata_port *ap,
+                                struct sata_dwc_device *hsdev, uint intpr)
+{
+        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+        struct ata_eh_info *ehi = &ap->link.eh_info;
+        unsigned int err_mask = 0, action = 0;
+        struct ata_queued_cmd *qc;
+        u32 serror;
+        u8 status, tag;
+        u32 err_reg;
+
+        ata_ehi_clear_desc(ehi);
+
+        serror = core_scr_read(SCR_ERROR);
+        status = ap->ops->sff_check_status(ap);
+
+        err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error.\
+                        low));
+        tag = ap->link.active_tag;
+
+        dev_err(ap->dev, "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x "
+                "dma_intp=%d pending=%d issued=%d dma_err_status=0x%08x\n",
+                __func__, serror, intpr, status, host_pvt.dma_interrupt_count,
+                hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag], err_reg);
+
+        /* Clear error register and interrupt bit */
+        clear_serror();
+        clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
+
+        /* This is the only error happening now.  TODO check for exact error */
+
+        err_mask |= AC_ERR_HOST_BUS;
+        action |= ATA_EH_RESET;
+
+        /* Pass this on to EH */
+        ehi->serror |= serror;
+        ehi->action |= action;
+
+        qc = ata_qc_from_tag(ap, tag);
+        if (qc)
+                qc->err_mask |= err_mask;
+        else
+                ehi->err_mask |= err_mask;
+
+        ata_port_abort(ap);
+}
+
+/*
+ * Function : sata_dwc_isr
+ * arguments : irq, void *dev_instance, struct pt_regs *regs
+ * Return value : irqreturn_t - status of IRQ
+ * This Interrupt handler called via port ops registered function.
+ * .irq_handler = sata_dwc_isr
+ */
+static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
+{
+        struct ata_host *host = (struct ata_host *)dev_instance;
+        struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
+        struct ata_port *ap;
+        struct ata_queued_cmd *qc;
+        unsigned long flags;
+        u8 status, tag;
+        int handled, num_processed, port = 0;
+        uint intpr, sactive, sactive2, tag_mask;
+        struct sata_dwc_device_port *hsdevp;
+        host_pvt.sata_dwc_sactive_issued = 0;
+
+        spin_lock_irqsave(&host->lock, flags);
+
+        /* Read the interrupt register */
+        intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
+
+        ap = host->ports[port];
+        hsdevp = HSDEVP_FROM_AP(ap);
+
+        dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
+                ap->link.active_tag);
+
+        /* Check for error interrupt */
+        if (intpr & SATA_DWC_INTPR_ERR) {
+                sata_dwc_error_intr(ap, hsdev, intpr);
+                handled = 1;
+                goto DONE;
+        }
+
+        /* Check for DMA SETUP FIS (FP DMA) interrupt */
+        if (intpr & SATA_DWC_INTPR_NEWFP) {
+                clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
+
+                tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
+                dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
+                if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
+                        dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
+
+                host_pvt.sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag);
+
+                qc = ata_qc_from_tag(ap, tag);
+                /*
+                 * Start FP DMA for NCQ command.  At this point the tag is the
+                 * active tag.  It is the tag that matches the command about to
+                 * be completed.
+                 */
+                qc->ap->link.active_tag = tag;
+                sata_dwc_bmdma_start_by_tag(qc, tag);
+
+                handled = 1;
+                goto DONE;
+        }
+        sactive = core_scr_read(SCR_ACTIVE);
+        tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
+
+        /* If no sactive issued and tag_mask is zero then this is not NCQ */
+        if (host_pvt.sata_dwc_sactive_issued == 0 && tag_mask == 0) {
+                if (ap->link.active_tag == ATA_TAG_POISON)
+                        tag = 0;
+                else
+                        tag = ap->link.active_tag;
+                qc = ata_qc_from_tag(ap, tag);
+
+                /* DEV interrupt w/ no active qc? */
+                if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
+                        dev_err(ap->dev, "%s interrupt with no active qc "
+                                "qc=%p\n", __func__, qc);
+                        ap->ops->sff_check_status(ap);
+                        handled = 1;
+                        goto DONE;
+                }
+                status = ap->ops->sff_check_status(ap);
+
+                qc->ap->link.active_tag = tag;
+                hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
+
+                if (status & ATA_ERR) {
+                        dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
+                        sata_dwc_qc_complete(ap, qc, 1);
+                        handled = 1;
+                        goto DONE;
+                }
+
+                dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
+                        __func__, ata_get_cmd_descript(qc->tf.protocol));
+DRVSTILLBUSY:
+                if (ata_is_dma(qc->tf.protocol)) {
+                        /*
+                         * Each DMA transaction produces 2 interrupts. The DMAC
+                         * transfer complete interrupt and the SATA controller
+                         * operation done interrupt. The command should be
+                         * completed only after both interrupts are seen.
+                         */
+                        host_pvt.dma_interrupt_count++;
+                        if (hsdevp->dma_pending[tag] == \
+                                        SATA_DWC_DMA_PENDING_NONE) {
+                                dev_err(ap->dev, "%s: DMA not pending "
+                                        "intpr=0x%08x status=0x%08x pending"
+                                        "=%d\n", __func__, intpr, status,
+                                        hsdevp->dma_pending[tag]);
+                        }
+
+                        if ((host_pvt.dma_interrupt_count % 2) == 0)
+                                sata_dwc_dma_xfer_complete(ap, 1);
+                } else if (ata_is_pio(qc->tf.protocol)) {
+                        ata_sff_hsm_move(ap, qc, status, 0);
+                        handled = 1;
+                        goto DONE;
+                } else {
+                        if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
+                                goto DRVSTILLBUSY;
+                }
+
+                handled = 1;
+                goto DONE;
+        }
+
+        /*
+         * This is a NCQ command. At this point we need to figure out for which
+         * tags we have gotten a completion interrupt.  One interrupt may serve
+         * as completion for more than one operation when commands are queued
+         * (NCQ).  We need to process each completed command.
+         */
+
+         /* process completed commands */
+        sactive = core_scr_read(SCR_ACTIVE);
+        tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
+
+        if (sactive != 0 || (host_pvt.sata_dwc_sactive_issued) > 1 || \
+                                                        tag_mask > 1) {
+                dev_dbg(ap->dev, "%s NCQ:sactive=0x%08x  sactive_issued=0x%08x"
+                        "tag_mask=0x%08x\n", __func__, sactive,
+                        host_pvt.sata_dwc_sactive_issued, tag_mask);
+        }
+
+        if ((tag_mask | (host_pvt.sata_dwc_sactive_issued)) != \
+                                        (host_pvt.sata_dwc_sactive_issued)) {
+                dev_warn(ap->dev, "Bad tag mask?  sactive=0x%08x "
+                         "(host_pvt.sata_dwc_sactive_issued)=0x%08x  tag_mask"
+                         "=0x%08x\n", sactive, host_pvt.sata_dwc_sactive_issued,
+                          tag_mask);
+        }
+
+        /* read just to clear ... not bad if currently still busy */
+        status = ap->ops->sff_check_status(ap);
+        dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
+
+        tag = 0;
+        num_processed = 0;
+        while (tag_mask) {
+                num_processed++;
+                while (!(tag_mask & 0x00000001)) {
+                        tag++;
+                        tag_mask <<= 1;
+                }
+
+                tag_mask &= (~0x00000001);
+                qc = ata_qc_from_tag(ap, tag);
+
+                /* To be picked up by completion functions */
+                qc->ap->link.active_tag = tag;
+                hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
+
+                /* Let libata/scsi layers handle error */
+                if (status & ATA_ERR) {
+                        dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
+                                status);
+                        sata_dwc_qc_complete(ap, qc, 1);
+                        handled = 1;
+                        goto DONE;
+                }
+
+                /* Process completed command */
+                dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
+                        ata_get_cmd_descript(qc->tf.protocol));
+                if (ata_is_dma(qc->tf.protocol)) {
+                        host_pvt.dma_interrupt_count++;
+                        if (hsdevp->dma_pending[tag] == \
+                                        SATA_DWC_DMA_PENDING_NONE)
+                                dev_warn(ap->dev, "%s: DMA not pending?\n",
+                                        __func__);
+                        if ((host_pvt.dma_interrupt_count % 2) == 0)
+                                sata_dwc_dma_xfer_complete(ap, 1);
+                } else {
+                        if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
+                                goto STILLBUSY;
+                }
+                continue;
+
+STILLBUSY:
+                ap->stats.idle_irq++;
+                dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
+                        ap->print_id);
+        } /* while tag_mask */
+
+        /*
+         * Check to see if any commands completed while we were processing our
+         * initial set of completed commands (read status clears interrupts,
+         * so we might miss a completed command interrupt if one came in while
+         * we were processing --we read status as part of processing a completed
+         * command).
+         */
+        sactive2 = core_scr_read(SCR_ACTIVE);
+        if (sactive2 != sactive) {
+                dev_dbg(ap->dev, "More completed - sactive=0x%x sactive2"
+                        "=0x%x\n", sactive, sactive2);
+        }
+        handled = 1;
+
+DONE:
+        spin_unlock_irqrestore(&host->lock, flags);
+        return IRQ_RETVAL(handled);
+}
+
+static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
+{
+        struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
+
+        if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
+                out_le32(&(hsdev->sata_dwc_regs->dmacr),
+                         SATA_DWC_DMACR_RX_CLEAR(
+                                 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
+        } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
+                out_le32(&(hsdev->sata_dwc_regs->dmacr),
+                         SATA_DWC_DMACR_TX_CLEAR(
+                                 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
+        } else {
+                /*
+                 * This should not happen, it indicates the driver is out of
+                 * sync.  If it does happen, clear dmacr anyway.
+                 */
+                dev_err(host_pvt.dwc_dev, "%s DMA protocol RX and"
+                        "TX DMA not pending tag=0x%02x pending=%d"
+                        " dmacr: 0x%08x\n", __func__, tag,
+                        hsdevp->dma_pending[tag],
+                        in_le32(&(hsdev->sata_dwc_regs->dmacr)));
+                out_le32(&(hsdev->sata_dwc_regs->dmacr),
+                        SATA_DWC_DMACR_TXRXCH_CLEAR);
+        }
+}
+
+static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
+{
+        struct ata_queued_cmd *qc;
+        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+        struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
+        u8 tag = 0;
+
+        tag = ap->link.active_tag;
+        qc = ata_qc_from_tag(ap, tag);
+        if (!qc) {
+                dev_err(ap->dev, "failed to get qc");
+                return;
+        }
+
+#ifdef DEBUG_NCQ
+        if (tag > 0) {
+                dev_info(ap->dev, "%s tag=%u cmd=0x%02x dma dir=%s proto=%s "
+                         "dmacr=0x%08x\n", __func__, qc->tag, qc->tf.command,
+                         ata_get_cmd_descript(qc->dma_dir),
+                         ata_get_cmd_descript(qc->tf.protocol),
+                         in_le32(&(hsdev->sata_dwc_regs->dmacr)));
+        }
+#endif
+
+        if (ata_is_dma(qc->tf.protocol)) {
+                if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
+                        dev_err(ap->dev, "%s DMA protocol RX and TX DMA not "
+                                "pending dmacr: 0x%08x\n", __func__,
+                                in_le32(&(hsdev->sata_dwc_regs->dmacr)));
+                }
+
+                hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
+                sata_dwc_qc_complete(ap, qc, check_status);
+                ap->link.active_tag = ATA_TAG_POISON;
+        } else {
+                sata_dwc_qc_complete(ap, qc, check_status);
+        }
+}
+
+static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
+                                u32 check_status)
+{
+        u8 status = 0;
+        u32 mask = 0x0;
+        u8 tag = qc->tag;
+        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+        host_pvt.sata_dwc_sactive_queued = 0;
+        dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
+
+        if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
+                dev_err(ap->dev, "TX DMA PENDING\n");
+        else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
+                dev_err(ap->dev, "RX DMA PENDING\n");
+        dev_dbg(ap->dev, "QC complete cmd=0x%02x status=0x%02x ata%u:"
+                " protocol=%d\n", qc->tf.command, status, ap->print_id,
+                 qc->tf.protocol);
+
+        /* clear active bit */
+        mask = (~(qcmd_tag_to_mask(tag)));
+        host_pvt.sata_dwc_sactive_queued = (host_pvt.sata_dwc_sactive_queued) \
+                                                & mask;
+        host_pvt.sata_dwc_sactive_issued = (host_pvt.sata_dwc_sactive_issued) \
+                                                & mask;
+        ata_qc_complete(qc);
+        return 0;
+}
+
+static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
+{
+        /* Enable selective interrupts by setting the interrupt maskregister*/
+        out_le32(&hsdev->sata_dwc_regs->intmr,
+                 SATA_DWC_INTMR_ERRM |
+                 SATA_DWC_INTMR_NEWFPM |
+                 SATA_DWC_INTMR_PMABRTM |
+                 SATA_DWC_INTMR_DMATM);
+        /*
+         * Unmask the error bits that should trigger an error interrupt by
+         * setting the error mask register.
+         */
+        out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
+
+        dev_dbg(host_pvt.dwc_dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
+                 __func__, in_le32(&hsdev->sata_dwc_regs->intmr),
+                in_le32(&hsdev->sata_dwc_regs->errmr));
+}
+
+static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base)
+{
+        port->cmd_addr = (void *)base + 0x00;
+        port->data_addr = (void *)base + 0x00;
+
+        port->error_addr = (void *)base + 0x04;
+        port->feature_addr = (void *)base + 0x04;
+
+        port->nsect_addr = (void *)base + 0x08;
+
+        port->lbal_addr = (void *)base + 0x0c;
+        port->lbam_addr = (void *)base + 0x10;
+        port->lbah_addr = (void *)base + 0x14;
+
+        port->device_addr = (void *)base + 0x18;
+        port->command_addr = (void *)base + 0x1c;
+        port->status_addr = (void *)base + 0x1c;
+
+        port->altstatus_addr = (void *)base + 0x20;
+        port->ctl_addr = (void *)base + 0x20;
+}
+
+/*
+ * Function : sata_dwc_port_start
+ * arguments : struct ata_ioports *port
+ * Return value : returns 0 if success, error code otherwise
+ * This function allocates the scatter gather LLI table for AHB DMA
+ */
+static int sata_dwc_port_start(struct ata_port *ap)
+{
+        int err = 0;
+        struct sata_dwc_device *hsdev;
+        struct sata_dwc_device_port *hsdevp = NULL;
+        struct device *pdev;
+        int i;
+
+        hsdev = HSDEV_FROM_AP(ap);
+
+        dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
+
+        hsdev->host = ap->host;
+        pdev = ap->host->dev;
+        if (!pdev) {
+                dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
+                err = -ENODEV;
+                goto CLEANUP;
+        }
+
+        /* Allocate Port Struct */
+        hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
+        if (!hsdevp) {
+                dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
+                err = -ENOMEM;
+                goto CLEANUP;
+        }
+        hsdevp->hsdev = hsdev;
+
+        for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
+                hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
+
+        ap->bmdma_prd = 0;      /* set these so libata doesn't use them */
+        ap->bmdma_prd_dma = 0;
+
+        /*
+         * DMA - Assign scatter gather LLI table. We can't use the libata
+         * version since it's PRD is IDE PCI specific.
+         */
+        for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
+                hsdevp->llit[i] = dma_alloc_coherent(pdev,
+                                                     SATA_DWC_DMAC_LLI_TBL_SZ,
+                                                     &(hsdevp->llit_dma[i]),
+                                                     GFP_ATOMIC);
+                if (!hsdevp->llit[i]) {
+                        dev_err(ap->dev, "%s: dma_alloc_coherent failed\n",
+                                 __func__);
+                        err = -ENOMEM;
+                        goto CLEANUP;
+                }
+        }
+
+        if (ap->port_no == 0)  {
+                dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
+                        __func__);
+                out_le32(&hsdev->sata_dwc_regs->dmacr,
+                         SATA_DWC_DMACR_TXRXCH_CLEAR);
+
+                dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
+                         __func__);
+                out_le32(&hsdev->sata_dwc_regs->dbtsr,
+                         (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
+                          SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
+        }
+
+        /* Clear any error bits before libata starts issuing commands */
+        clear_serror();
+        ap->private_data = hsdevp;
+
+CLEANUP:
+        if (err) {
+                sata_dwc_port_stop(ap);
+                dev_dbg(ap->dev, "%s: fail\n", __func__);
+        } else {
+                dev_dbg(ap->dev, "%s: done\n", __func__);
+        }
+
+        return err;
+}
+
+static void sata_dwc_port_stop(struct ata_port *ap)
+{
+        int i;
+        struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
+        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+
+        dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
+
+        if (hsdevp && hsdev) {
+                /* deallocate LLI table */
+                for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
+                        dma_free_coherent(ap->host->dev,
+                                          SATA_DWC_DMAC_LLI_TBL_SZ,
+                                         hsdevp->llit[i], hsdevp->llit_dma[i]);
+                }
+
+                kfree(hsdevp);
+        }
+        ap->private_data = NULL;
+}
+
+/*
+ * Function : sata_dwc_exec_command_by_tag
+ * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
+ * Return value : None
+ * This function keeps track of individual command tag ids and calls
+ * ata_exec_command in libata
+ */
+static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
+                                         struct ata_taskfile *tf,
+                                         u8 tag, u32 cmd_issued)
+{
+        unsigned long flags;
+        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+
+        dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
+                ata_get_cmd_descript(tf), tag);
+
+        spin_lock_irqsave(&ap->host->lock, flags);
+        hsdevp->cmd_issued[tag] = cmd_issued;
+        spin_unlock_irqrestore(&ap->host->lock, flags);
+        /*
+         * Clear SError before executing a new command.
+         * sata_dwc_scr_write and read can not be used here. Clearing the PM
+         * managed SError register for the disk needs to be done before the
+         * task file is loaded.
+         */
+        clear_serror();
+        ata_sff_exec_command(ap, tf);
+}
+
+static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
+{
+        sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
+                                     SATA_DWC_CMD_ISSUED_PEND);
+}
+
+static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
+{
+        u8 tag = qc->tag;
+
+        if (ata_is_ncq(qc->tf.protocol)) {
+                dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
+                        __func__, qc->ap->link.sactive, tag);
+        } else {
+                tag = 0;
+        }
+        sata_dwc_bmdma_setup_by_tag(qc, tag);
+}
+
+static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
+{
+        int start_dma;
+        u32 reg, dma_chan;
+        struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
+        struct ata_port *ap = qc->ap;
+        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+        int dir = qc->dma_dir;
+        dma_chan = hsdevp->dma_chan[tag];
+
+        if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
+                start_dma = 1;
+                if (dir == DMA_TO_DEVICE)
+                        hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
+                else
+                        hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
+        } else {
+                dev_err(ap->dev, "%s: Command not pending cmd_issued=%d "
+                        "(tag=%d) DMA NOT started\n", __func__,
+                        hsdevp->cmd_issued[tag], tag);
+                start_dma = 0;
+        }
+
+        dev_dbg(ap->dev, "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s "
+                "start_dma? %x\n", __func__, qc, tag, qc->tf.command,
+                ata_get_cmd_descript(qc->dma_dir), start_dma);
+        sata_dwc_tf_dump(&(qc->tf));
+
+        if (start_dma) {
+                reg = core_scr_read(SCR_ERROR);
+                if (reg & SATA_DWC_SERROR_ERR_BITS) {
+                        dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
+                                __func__, reg);
+                }
+
+                if (dir == DMA_TO_DEVICE)
+                        out_le32(&hsdev->sata_dwc_regs->dmacr,
+                                SATA_DWC_DMACR_TXCHEN);
+                else
+                        out_le32(&hsdev->sata_dwc_regs->dmacr,
+                                SATA_DWC_DMACR_RXCHEN);
+
+                /* Enable AHB DMA transfer on the specified channel */
+                dma_dwc_xfer_start(dma_chan);
+        }
+}
+
+static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
+{
+        u8 tag = qc->tag;
+
+        if (ata_is_ncq(qc->tf.protocol)) {
+                dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
+                        __func__, qc->ap->link.sactive, tag);
+        } else {
+                tag = 0;
+        }
+        dev_dbg(qc->ap->dev, "%s\n", __func__);
+        sata_dwc_bmdma_start_by_tag(qc, tag);
+}
+
+/*
+ * Function : sata_dwc_qc_prep_by_tag
+ * arguments : ata_queued_cmd *qc, u8 tag
+ * Return value : None
+ * qc_prep for a particular queued command based on tag
+ */
+static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag)
+{
+        struct scatterlist *sg = qc->sg;
+        struct ata_port *ap = qc->ap;
+        int dma_chan;
+        struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
+        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+        int err;
+
+        dev_dbg(ap->dev, "%s: port=%d dma dir=%s n_elem=%d\n",
+                __func__, ap->port_no, ata_get_cmd_descript(qc->dma_dir),
+                 qc->n_elem);
+
+        dma_chan = dma_dwc_xfer_setup(sg, qc->n_elem, hsdevp->llit[tag],
+                                      hsdevp->llit_dma[tag],
+                                      (void *__iomem)(&hsdev->sata_dwc_regs->\
+                                      dmadr), qc->dma_dir);
+        if (dma_chan < 0) {
+                dev_err(ap->dev, "%s: dma_dwc_xfer_setup returns err %d\n",
+                        __func__, err);
+                return;
+        }
+        hsdevp->dma_chan[tag] = dma_chan;
+}
+
+static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
+{
+        u32 sactive;
+        u8 tag = qc->tag;
+        struct ata_port *ap = qc->ap;
+
+#ifdef DEBUG_NCQ
+        if (qc->tag > 0 || ap->link.sactive > 1)
+                dev_info(ap->dev, "%s ap id=%d cmd(0x%02x)=%s qc tag=%d "
+                         "prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
+                         __func__, ap->print_id, qc->tf.command,
+                         ata_get_cmd_descript(&qc->tf),
+                         qc->tag, ata_get_cmd_descript(qc->tf.protocol),
+                         ap->link.active_tag, ap->link.sactive);
+#endif
+
+        if (!ata_is_ncq(qc->tf.protocol))
+                tag = 0;
+        sata_dwc_qc_prep_by_tag(qc, tag);
+
+        if (ata_is_ncq(qc->tf.protocol)) {
+                sactive = core_scr_read(SCR_ACTIVE);
+                sactive |= (0x00000001 << tag);
+                core_scr_write(SCR_ACTIVE, sactive);
+
+                dev_dbg(qc->ap->dev, "%s: tag=%d ap->link.sactive = 0x%08x "
+                        "sactive=0x%08x\n", __func__, tag, qc->ap->link.sactive,
+                        sactive);
+
+                ap->ops->sff_tf_load(ap, &qc->tf);
+                sata_dwc_exec_command_by_tag(ap, &qc->tf, qc->tag,
+                                             SATA_DWC_CMD_ISSUED_PEND);
+        } else {
+                ata_sff_qc_issue(qc);
+        }
+        return 0;
+}
+
+/*
+ * Function : sata_dwc_qc_prep
+ * arguments : ata_queued_cmd *qc
+ * Return value : None
+ * qc_prep for a particular queued command
+ */
+
+static void sata_dwc_qc_prep(struct ata_queued_cmd *qc)
+{
+        if ((qc->dma_dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO))
+                return;
+
+#ifdef DEBUG_NCQ
+        if (qc->tag > 0)
+                dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
+                         __func__, tag, qc->ap->link.active_tag);
+
+        return ;
+#endif
+}
+
+static void sata_dwc_error_handler(struct ata_port *ap)
+{
+        ap->link.flags |= ATA_LFLAG_NO_HRST;
+        ata_sff_error_handler(ap);
+}
+
+/*
+ * scsi mid-layer and libata interface structures
+ */
+static struct scsi_host_template sata_dwc_sht = {
+        ATA_NCQ_SHT(DRV_NAME),
+        /*
+         * test-only: Currently this driver doesn't handle NCQ
+         * correctly. We enable NCQ but set the queue depth to a
+         * max of 1. This will get fixed in in a future release.
+         */
+        .sg_tablesize           = LIBATA_MAX_PRD,
+        .can_queue              = ATA_DEF_QUEUE,        /* ATA_MAX_QUEUE */
+        .dma_boundary           = ATA_DMA_BOUNDARY,
+};
+
+static struct ata_port_operations sata_dwc_ops = {
+        .inherits               = &ata_sff_port_ops,
+
+        .error_handler          = sata_dwc_error_handler,
+
+        .qc_prep                = sata_dwc_qc_prep,
+        .qc_issue               = sata_dwc_qc_issue,
+
+        .scr_read               = sata_dwc_scr_read,
+        .scr_write              = sata_dwc_scr_write,
+
+        .port_start             = sata_dwc_port_start,
+        .port_stop              = sata_dwc_port_stop,
+
+        .bmdma_setup            = sata_dwc_bmdma_setup,
+        .bmdma_start            = sata_dwc_bmdma_start,
+};
+
+static const struct ata_port_info sata_dwc_port_info[] = {
+        {
+                .flags          = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
+                                  ATA_FLAG_MMIO | ATA_FLAG_NCQ,
+                .pio_mask       = 0x1f, /* pio 0-4 */
+                .udma_mask      = ATA_UDMA6,
+                .port_ops       = &sata_dwc_ops,
+        },
+};
+
+static int sata_dwc_probe(struct platform_device *ofdev,
+                        const struct of_device_id *match)
+{
+        struct sata_dwc_device *hsdev;
+        u32 idr, versionr;
+        char *ver = (char *)&versionr;
+        u8 *base = NULL;
+        int err = 0;
+        int irq, rc;
+        struct ata_host *host;
+        struct ata_port_info pi = sata_dwc_port_info[0];
+        const struct ata_port_info *ppi[] = { &pi, NULL };
+
+        /* Allocate DWC SATA device */
+        hsdev = kmalloc(sizeof(*hsdev), GFP_KERNEL);
+        if (hsdev == NULL) {
+                dev_err(&ofdev->dev, "kmalloc failed for hsdev\n");
+                err = -ENOMEM;
+                goto error_out;
+        }
+        memset(hsdev, 0, sizeof(*hsdev));
+
+        /* Ioremap SATA registers */
+        base = of_iomap(ofdev->dev.of_node, 0);
+        if (!base) {
+                dev_err(&ofdev->dev, "ioremap failed for SATA register"
+                        " address\n");
+                err = -ENODEV;
+                goto error_out;
+        }
+        hsdev->reg_base = base;
+        dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
+
+        /* Synopsys DWC SATA specific Registers */
+        hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
+
+        /* Allocate and fill host */
+        host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
+        if (!host) {
+                dev_err(&ofdev->dev, "ata_host_alloc_pinfo failed\n");
+                err = -ENOMEM;
+                goto error_out;
+        }
+
+        host->private_data = hsdev;
+
+        /* Setup port */
+        host->ports[0]->ioaddr.cmd_addr = base;
+        host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
+        host_pvt.scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
+        sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base);
+
+        /* Read the ID and Version Registers */
+        idr = in_le32(&hsdev->sata_dwc_regs->idr);
+        versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
+        dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
+                   idr, ver[0], ver[1], ver[2]);
+
+        /* Get SATA DMA interrupt number */
+        irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
+        if (irq == NO_IRQ) {
+                dev_err(&ofdev->dev, "no SATA DMA irq\n");
+                err = -ENODEV;
+                goto error_out;
+        }
+
+        /* Get physical SATA DMA register base address */
+        host_pvt.sata_dma_regs = of_iomap(ofdev->dev.of_node, 1);
+        if (!(host_pvt.sata_dma_regs)) {
+                dev_err(&ofdev->dev, "ioremap failed for AHBDMA register"
+                        " address\n");
+                err = -ENODEV;
+                goto error_out;
+        }
+
+        /* Save dev for later use in dev_xxx() routines */
+        host_pvt.dwc_dev = &ofdev->dev;
+
+        /* Initialize AHB DMAC */
+        dma_dwc_init(hsdev, irq);
+
+        /* Enable SATA Interrupts */
+        sata_dwc_enable_interrupts(hsdev);
+
+        /* Get SATA interrupt number */
+        irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
+        if (irq == NO_IRQ) {
+                dev_err(&ofdev->dev, "no SATA DMA irq\n");
+                err = -ENODEV;
+                goto error_out;
+        }
+
+        /*
+         * Now, register with libATA core, this will also initiate the
+         * device discovery process, invoking our port_start() handler &
+         * error_handler() to execute a dummy Softreset EH session
+         */
+        rc = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
+
+        if (rc != 0)
+                dev_err(&ofdev->dev, "failed to activate host");
+
+        dev_set_drvdata(&ofdev->dev, host);
+        return 0;
+
+error_out:
+        /* Free SATA DMA resources */
+        dma_dwc_exit(hsdev);
+
+        if (base)
+                iounmap(base);
+        return err;
+}
+
+static int sata_dwc_remove(struct platform_device *ofdev)
+{
+        struct device *dev = &ofdev->dev;
+        struct ata_host *host = dev_get_drvdata(dev);
+        struct sata_dwc_device *hsdev = host->private_data;
+
+        ata_host_detach(host);
+        dev_set_drvdata(dev, NULL);
+
+        /* Free SATA DMA resources */
+        dma_dwc_exit(hsdev);
+
+        iounmap(hsdev->reg_base);
+        kfree(hsdev);
+        kfree(host);
+        dev_dbg(&ofdev->dev, "done\n");
+        return 0;
+}
+
+static const struct of_device_id sata_dwc_match[] = {
+        { .compatible = "amcc,sata-460ex", },
+        {}
+};
+MODULE_DEVICE_TABLE(of, sata_dwc_match);
+
+static struct of_platform_driver sata_dwc_driver = {
+        .driver = {
+                .name = DRV_NAME,
+                .owner = THIS_MODULE,
+                .of_match_table = sata_dwc_match,
+        },
+        .probe = sata_dwc_probe,
+        .remove = sata_dwc_remove,
+};
+
+static int __init sata_dwc_init(void)
+{
+        return  of_register_platform_driver(&sata_dwc_driver);
+}
+
+static void __exit sata_dwc_exit(void)
+{
+        of_unregister_platform_driver(&sata_dwc_driver);
+}
+
+module_init(sata_dwc_init);
+module_exit(sata_dwc_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
+MODULE_DESCRIPTION("DesignWare Cores SATA controller low lever driver");
+MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index a69192b38b43..7325f77480dc 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -1096,7 +1096,7 @@ static void sata_fsl_host_intr(struct ata_port *ap)
 {
         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
         void __iomem *hcr_base = host_priv->hcr_base;
-        u32 hstatus, qc_active = 0;
+        u32 hstatus, done_mask = 0;
         struct ata_queued_cmd *qc;
         u32 SError;
 
@@ -1116,28 +1116,28 @@ static void sata_fsl_host_intr(struct ata_port *ap)
         }
 
         /* Read command completed register */
-        qc_active = ioread32(hcr_base + CC);
+        done_mask = ioread32(hcr_base + CC);
 
         VPRINTK("Status of all queues :\n");
-        VPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
-                qc_active,
+        VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
+                done_mask,
                 ioread32(hcr_base + CA),
                 ioread32(hcr_base + CE),
                 ioread32(hcr_base + CQ),
                 ap->qc_active);
 
-        if (qc_active & ap->qc_active) {
+        if (done_mask & ap->qc_active) {
                 int i;
                 /* clear CC bit, this will also complete the interrupt */
-                iowrite32(qc_active, hcr_base + CC);
+                iowrite32(done_mask, hcr_base + CC);
 
                 DPRINTK("Status of all queues :\n");
-                DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
-                        qc_active, ioread32(hcr_base + CA),
+                DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
+                        done_mask, ioread32(hcr_base + CA),
                         ioread32(hcr_base + CE));
 
                 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
-                        if (qc_active & (1 << i)) {
+                        if (done_mask & (1 << i)) {
                                 qc = ata_qc_from_tag(ap, i);
                                 if (qc) {
                                         ata_qc_complete(qc);
@@ -1164,7 +1164,7 @@ static void sata_fsl_host_intr(struct ata_port *ap)
                 /* Spurious Interrupt!! */
                 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
                         ioread32(hcr_base + CC));
-                iowrite32(qc_active, hcr_base + CC);
+                iowrite32(done_mask, hcr_base + CC);
                 return;
         }
 }
@@ -1296,7 +1296,7 @@ static const struct ata_port_info sata_fsl_port_info[] = {
          },
 };
 
-static int sata_fsl_probe(struct of_device *ofdev,
+static int sata_fsl_probe(struct platform_device *ofdev,
                         const struct of_device_id *match)
 {
         int retval = -ENXIO;
@@ -1313,7 +1313,7 @@ static int sata_fsl_probe(struct of_device *ofdev,
         dev_printk(KERN_INFO, &ofdev->dev,
                    "Sata FSL Platform/CSB Driver init\n");
 
-        hcr_base = of_iomap(ofdev->node, 0);
+        hcr_base = of_iomap(ofdev->dev.of_node, 0);
         if (!hcr_base)
                 goto error_exit_with_cleanup;
 
@@ -1332,7 +1332,7 @@ static int sata_fsl_probe(struct of_device *ofdev,
         host_priv->ssr_base = ssr_base;
         host_priv->csr_base = csr_base;
 
-        irq = irq_of_parse_and_map(ofdev->node, 0);
+        irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
         if (irq < 0) {
                 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n");
                 goto error_exit_with_cleanup;
@@ -1370,7 +1370,7 @@ error_exit_with_cleanup:
         return retval;
 }
 
-static int sata_fsl_remove(struct of_device *ofdev)
+static int sata_fsl_remove(struct platform_device *ofdev)
 {
         struct ata_host *host = dev_get_drvdata(&ofdev->dev);
         struct sata_fsl_host_priv *host_priv = host->private_data;
@@ -1387,13 +1387,13 @@ static int sata_fsl_remove(struct of_device *ofdev)
 }
 
 #ifdef CONFIG_PM
-static int sata_fsl_suspend(struct of_device *op, pm_message_t state)
+static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
 {
         struct ata_host *host = dev_get_drvdata(&op->dev);
         return ata_host_suspend(host, state);
 }
 
-static int sata_fsl_resume(struct of_device *op)
+static int sata_fsl_resume(struct platform_device *op)
 {
         struct ata_host *host = dev_get_drvdata(&op->dev);
         struct sata_fsl_host_priv *host_priv = host->private_data;
@@ -1427,8 +1427,11 @@ static struct of_device_id fsl_sata_match[] = {
 MODULE_DEVICE_TABLE(of, fsl_sata_match);
 
 static struct of_platform_driver fsl_sata_driver = {
-        .name           = "fsl-sata",
-        .match_table    = fsl_sata_match,
+        .driver = {
+                .name = "fsl-sata",
+                .owner = THIS_MODULE,
+                .of_match_table = fsl_sata_match,
+        },
         .probe          = sata_fsl_probe,
         .remove         = sata_fsl_remove,
 #ifdef CONFIG_PM
diff --git a/drivers/ata/sata_inic162x.c b/drivers/ata/sata_inic162x.c
index 27dc6c86a4cd..a36149ebf4a2 100644
--- a/drivers/ata/sata_inic162x.c
+++ b/drivers/ata/sata_inic162x.c
@@ -415,22 +415,11 @@ static irqreturn_t inic_interrupt(int irq, void *dev_instance)
 
         spin_lock(&host->lock);
 
-        for (i = 0; i < NR_PORTS; i++) {
-                struct ata_port *ap = host->ports[i];
-
-                if (!(host_irq_stat & (HIRQ_PORT0 << i)))
-                        continue;
-
-                if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) {
-                        inic_host_intr(ap);
+        for (i = 0; i < NR_PORTS; i++)
+                if (host_irq_stat & (HIRQ_PORT0 << i)) {
+                        inic_host_intr(host->ports[i]);
                         handled++;
-                } else {
-                        if (ata_ratelimit())
-                                dev_printk(KERN_ERR, host->dev, "interrupt "
-                                           "from disabled port %d (0x%x)\n",
-                                           i, host_irq_stat);
                 }
-        }
 
         spin_unlock(&host->lock);
 
@@ -679,8 +668,7 @@ static void init_port(struct ata_port *ap)
         memset(pp->pkt, 0, sizeof(struct inic_pkt));
         memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE);
 
-        /* setup PRD and CPB lookup table addresses */
-        writel(ap->prd_dma, port_base + PORT_PRD_ADDR);
+        /* setup CPB lookup table addresses */
         writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR);
 }
 
@@ -694,7 +682,6 @@ static int inic_port_start(struct ata_port *ap)
 {
         struct device *dev = ap->host->dev;
         struct inic_port_priv *pp;
-        int rc;
 
         /* alloc and initialize private data */
         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
@@ -703,10 +690,6 @@ static int inic_port_start(struct ata_port *ap)
         ap->private_data = pp;
 
         /* Alloc resources */
-        rc = ata_port_start(ap);
-        if (rc)
-                return rc;
-
         pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt),
                                       &pp->pkt_dma, GFP_KERNEL);
         if (!pp->pkt)
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 71cc0d42f9e1..a9fd9709c262 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -675,8 +675,6 @@ static struct ata_port_operations mv5_ops = {
         .freeze                 = mv_eh_freeze,
         .thaw                   = mv_eh_thaw,
         .hardreset              = mv_hardreset,
-        .error_handler          = ata_std_error_handler, /* avoid SFF EH */
-        .post_internal_cmd      = ATA_OP_NULL,
 
         .scr_read               = mv5_scr_read,
         .scr_write              = mv5_scr_write,
@@ -686,16 +684,27 @@ static struct ata_port_operations mv5_ops = {
 };
 
 static struct ata_port_operations mv6_ops = {
-        .inherits               = &mv5_ops,
+        .inherits               = &ata_bmdma_port_ops,
+
+        .lost_interrupt         = ATA_OP_NULL,
+
+        .qc_defer               = mv_qc_defer,
+        .qc_prep                = mv_qc_prep,
+        .qc_issue               = mv_qc_issue,
+
         .dev_config             = mv6_dev_config,
-        .scr_read               = mv_scr_read,
-        .scr_write              = mv_scr_write,
 
+        .freeze                 = mv_eh_freeze,
+        .thaw                   = mv_eh_thaw,
+        .hardreset              = mv_hardreset,
+        .softreset              = mv_softreset,
         .pmp_hardreset          = mv_pmp_hardreset,
         .pmp_softreset          = mv_softreset,
-        .softreset              = mv_softreset,
         .error_handler          = mv_pmp_error_handler,
 
+        .scr_read               = mv_scr_read,
+        .scr_write              = mv_scr_write,
+
         .sff_check_status       = mv_sff_check_status,
         .sff_irq_clear          = mv_sff_irq_clear,
         .check_atapi_dma        = mv_check_atapi_dma,
@@ -703,6 +712,9 @@ static struct ata_port_operations mv6_ops = {
         .bmdma_start            = mv_bmdma_start,
         .bmdma_stop             = mv_bmdma_stop,
         .bmdma_status           = mv_bmdma_status,
+
+        .port_start             = mv_port_start,
+        .port_stop              = mv_port_stop,
 };
 
 static struct ata_port_operations mv_iie_ops = {
@@ -1886,19 +1898,25 @@ static void mv_bmdma_start(struct ata_queued_cmd *qc)
  *      LOCKING:
  *      Inherited from caller.
  */
-static void mv_bmdma_stop(struct ata_queued_cmd *qc)
+static void mv_bmdma_stop_ap(struct ata_port *ap)
 {
-        struct ata_port *ap = qc->ap;
         void __iomem *port_mmio = mv_ap_base(ap);
         u32 cmd;
 
         /* clear start/stop bit */
         cmd = readl(port_mmio + BMDMA_CMD);
-        cmd &= ~ATA_DMA_START;
-        writelfl(cmd, port_mmio + BMDMA_CMD);
+        if (cmd & ATA_DMA_START) {
+                cmd &= ~ATA_DMA_START;
+                writelfl(cmd, port_mmio + BMDMA_CMD);
+
+                /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
+                ata_sff_dma_pause(ap);
+        }
+}
 
-        /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
-        ata_sff_dma_pause(ap);
+static void mv_bmdma_stop(struct ata_queued_cmd *qc)
+{
+        mv_bmdma_stop_ap(qc->ap);
 }
 
 /**
@@ -1922,8 +1940,21 @@ static u8 mv_bmdma_status(struct ata_port *ap)
         reg = readl(port_mmio + BMDMA_STATUS);
         if (reg & ATA_DMA_ACTIVE)
                 status = ATA_DMA_ACTIVE;
-        else
+        else if (reg & ATA_DMA_ERR)
                 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
+        else {
+                /*
+                 * Just because DMA_ACTIVE is 0 (DMA completed),
+                 * this does _not_ mean the device is "done".
+                 * So we should not yet be signalling ATA_DMA_INTR
+                 * in some cases.  Eg. DSM/TRIM, and perhaps others.
+                 */
+                mv_bmdma_stop_ap(ap);
+                if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
+                        status = 0;
+                else
+                        status = ATA_DMA_INTR;
+        }
         return status;
 }
 
@@ -1983,6 +2014,9 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
 
         switch (tf->protocol) {
         case ATA_PROT_DMA:
+                if (tf->command == ATA_CMD_DSM)
+                        return;
+                /* fall-thru */
         case ATA_PROT_NCQ:
                 break;  /* continue below */
         case ATA_PROT_PIO:
@@ -2082,6 +2116,8 @@ static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
         if ((tf->protocol != ATA_PROT_DMA) &&
             (tf->protocol != ATA_PROT_NCQ))
                 return;
+        if (tf->command == ATA_CMD_DSM)
+                return;  /* use bmdma for this */
 
         /* Fill in Gen IIE command request block */
         if (!(tf->flags & ATA_TFLAG_WRITE))
@@ -2248,7 +2284,7 @@ static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
         }
 
         if (qc->tf.flags & ATA_TFLAG_POLLING)
-                ata_pio_queue_task(ap, qc, 0);
+                ata_sff_queue_pio_task(link, 0);
         return 0;
 }
 
@@ -2277,6 +2313,12 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
 
         switch (qc->tf.protocol) {
         case ATA_PROT_DMA:
+                if (qc->tf.command == ATA_CMD_DSM) {
+                        if (!ap->ops->bmdma_setup)  /* no bmdma on GEN_I */
+                                return AC_ERR_OTHER;
+                        break;  /* use bmdma for this */
+                }
+                /* fall thru */
         case ATA_PROT_NCQ:
                 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
                 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
@@ -2344,7 +2386,7 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
                 if (IS_GEN_II(hpriv))
                         return mv_qc_issue_fis(qc);
         }
-        return ata_sff_qc_issue(qc);
+        return ata_bmdma_qc_issue(qc);
 }
 
 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
@@ -2355,13 +2397,9 @@ static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
         if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
                 return NULL;
         qc = ata_qc_from_tag(ap, ap->link.active_tag);
-        if (qc) {
-                if (qc->tf.flags & ATA_TFLAG_POLLING)
-                        qc = NULL;
-                else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
-                        qc = NULL;
-        }
-        return qc;
+        if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
+                return qc;
+        return NULL;
 }
 
 static void mv_pmp_error_handler(struct ata_port *ap)
@@ -2546,9 +2584,7 @@ static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
         char *when = "idle";
 
         ata_ehi_clear_desc(ehi);
-        if (ap->flags & ATA_FLAG_DISABLED) {
-                when = "disabled";
-        } else if (edma_was_enabled) {
+        if (edma_was_enabled) {
                 when = "EDMA enabled";
         } else {
                 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
@@ -2710,34 +2746,35 @@ static void mv_err_intr(struct ata_port *ap)
 static void mv_process_crpb_response(struct ata_port *ap,
                 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
 {
+        u8 ata_status;
+        u16 edma_status = le16_to_cpu(response->flags);
         struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
 
-        if (qc) {
-                u8 ata_status;
-                u16 edma_status = le16_to_cpu(response->flags);
-                /*
-                 * edma_status from a response queue entry:
-                 *   LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
-                 *   MSB is saved ATA status from command completion.
-                 */
-                if (!ncq_enabled) {
-                        u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
-                        if (err_cause) {
-                                /*
-                                 * Error will be seen/handled by mv_err_intr().
-                                 * So do nothing at all here.
-                                 */
-                                return;
-                        }
-                }
-                ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
-                if (!ac_err_mask(ata_status))
-                        ata_qc_complete(qc);
-                /* else: leave it for mv_err_intr() */
-        } else {
+        if (unlikely(!qc)) {
                 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
                                 __func__, tag);
+                return;
         }
+
+        /*
+         * edma_status from a response queue entry:
+         *   LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
+         *   MSB is saved ATA status from command completion.
+         */
+        if (!ncq_enabled) {
+                u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
+                if (err_cause) {
+                        /*
+                         * Error will be seen/handled by
+                         * mv_err_intr().  So do nothing at all here.
+                         */
+                        return;
+                }
+        }
+        ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
+        if (!ac_err_mask(ata_status))
+                ata_qc_complete(qc);
+        /* else: leave it for mv_err_intr() */
 }
 
 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
@@ -2782,10 +2819,6 @@ static void mv_port_intr(struct ata_port *ap, u32 port_cause)
         struct mv_port_priv *pp;
         int edma_was_enabled;
 
-        if (ap->flags & ATA_FLAG_DISABLED) {
-                mv_unexpected_intr(ap, 0);
-                return;
-        }
         /*
          * Grab a snapshot of the EDMA_EN flag setting,
          * so that we have a consistent view for this port,
@@ -2809,7 +2842,7 @@ static void mv_port_intr(struct ata_port *ap, u32 port_cause)
         } else if (!edma_was_enabled) {
                 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
                 if (qc)
-                        ata_sff_host_intr(ap, qc);
+                        ata_bmdma_port_intr(ap, qc);
                 else
                         mv_unexpected_intr(ap, edma_was_enabled);
         }
@@ -3656,9 +3689,6 @@ static void mv_port_init(struct ata_ioports *port,  void __iomem *port_mmio)
         /* special case: control/altstatus doesn't have ATA_REG_ address */
         port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
 
-        /* unused: */
-        port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
-
         /* Clear any currently outstanding port interrupt conditions */
         serr = port_mmio + mv_scr_offset(SCR_ERROR);
         writelfl(readl(serr), serr);
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c
index 2a98b09ab735..cb89ef8d99d9 100644
--- a/drivers/ata/sata_nv.c
+++ b/drivers/ata/sata_nv.c
@@ -272,7 +272,7 @@ enum ncq_saw_flag_list {
 };
 
 struct nv_swncq_port_priv {
-        struct ata_prd  *prd;    /* our SG list */
+        struct ata_bmdma_prd *prd;       /* our SG list */
         dma_addr_t      prd_dma; /* and its DMA mapping */
         void __iomem    *sactive_block;
         void __iomem    *irq_block;
@@ -920,7 +920,7 @@ static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
         }
 
         /* handle interrupt */
-        return ata_sff_host_intr(ap, qc);
+        return ata_bmdma_port_intr(ap, qc);
 }
 
 static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
@@ -933,107 +933,110 @@ static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
 
         for (i = 0; i < host->n_ports; i++) {
                 struct ata_port *ap = host->ports[i];
+                struct nv_adma_port_priv *pp = ap->private_data;
+                void __iomem *mmio = pp->ctl_block;
+                u16 status;
+                u32 gen_ctl;
+                u32 notifier, notifier_error;
+
                 notifier_clears[i] = 0;
 
-                if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
-                        struct nv_adma_port_priv *pp = ap->private_data;
-                        void __iomem *mmio = pp->ctl_block;
-                        u16 status;
-                        u32 gen_ctl;
-                        u32 notifier, notifier_error;
-
-                        /* if ADMA is disabled, use standard ata interrupt handler */
-                        if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
-                                u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
-                                        >> (NV_INT_PORT_SHIFT * i);
-                                handled += nv_host_intr(ap, irq_stat);
-                                continue;
-                        }
+                /* if ADMA is disabled, use standard ata interrupt handler */
+                if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
+                        u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
+                                >> (NV_INT_PORT_SHIFT * i);
+                        handled += nv_host_intr(ap, irq_stat);
+                        continue;
+                }
 
-                        /* if in ATA register mode, check for standard interrupts */
-                        if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
-                                u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
-                                        >> (NV_INT_PORT_SHIFT * i);
-                                if (ata_tag_valid(ap->link.active_tag))
-                                        /** NV_INT_DEV indication seems unreliable at times
-                                            at least in ADMA mode. Force it on always when a
-                                            command is active, to prevent losing interrupts. */
-                                        irq_stat |= NV_INT_DEV;
-                                handled += nv_host_intr(ap, irq_stat);
-                        }
+                /* if in ATA register mode, check for standard interrupts */
+                if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
+                        u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
+                                >> (NV_INT_PORT_SHIFT * i);
+                        if (ata_tag_valid(ap->link.active_tag))
+                                /** NV_INT_DEV indication seems unreliable
+                                    at times at least in ADMA mode. Force it
+                                    on always when a command is active, to
+                                    prevent losing interrupts. */
+                                irq_stat |= NV_INT_DEV;
+                        handled += nv_host_intr(ap, irq_stat);
+                }
+
+                notifier = readl(mmio + NV_ADMA_NOTIFIER);
+                notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
+                notifier_clears[i] = notifier | notifier_error;
+
+                gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
 
-                        notifier = readl(mmio + NV_ADMA_NOTIFIER);
-                        notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
-                        notifier_clears[i] = notifier | notifier_error;
-
-                        gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
-
-                        if (!NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
-                            !notifier_error)
-                                /* Nothing to do */
-                                continue;
-
-                        status = readw(mmio + NV_ADMA_STAT);
-
-                        /* Clear status. Ensure the controller sees the clearing before we start
-                           looking at any of the CPB statuses, so that any CPB completions after
-                           this point in the handler will raise another interrupt. */
-                        writew(status, mmio + NV_ADMA_STAT);
-                        readw(mmio + NV_ADMA_STAT); /* flush posted write */
-                        rmb();
-
-                        handled++; /* irq handled if we got here */
-
-                        /* freeze if hotplugged or controller error */
-                        if (unlikely(status & (NV_ADMA_STAT_HOTPLUG |
-                                               NV_ADMA_STAT_HOTUNPLUG |
-                                               NV_ADMA_STAT_TIMEOUT |
-                                               NV_ADMA_STAT_SERROR))) {
-                                struct ata_eh_info *ehi = &ap->link.eh_info;
-
-                                ata_ehi_clear_desc(ehi);
-                                __ata_ehi_push_desc(ehi, "ADMA status 0x%08x: ", status);
-                                if (status & NV_ADMA_STAT_TIMEOUT) {
-                                        ehi->err_mask |= AC_ERR_SYSTEM;
-                                        ata_ehi_push_desc(ehi, "timeout");
-                                } else if (status & NV_ADMA_STAT_HOTPLUG) {
-                                        ata_ehi_hotplugged(ehi);
-                                        ata_ehi_push_desc(ehi, "hotplug");
-                                } else if (status & NV_ADMA_STAT_HOTUNPLUG) {
-                                        ata_ehi_hotplugged(ehi);
-                                        ata_ehi_push_desc(ehi, "hot unplug");
-                                } else if (status & NV_ADMA_STAT_SERROR) {
-                                        /* let libata analyze SError and figure out the cause */
-                                        ata_ehi_push_desc(ehi, "SError");
-                                } else
-                                        ata_ehi_push_desc(ehi, "unknown");
-                                ata_port_freeze(ap);
-                                continue;
+                if (!NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
+                    !notifier_error)
+                        /* Nothing to do */
+                        continue;
+
+                status = readw(mmio + NV_ADMA_STAT);
+
+                /*
+                 * Clear status. Ensure the controller sees the
+                 * clearing before we start looking at any of the CPB
+                 * statuses, so that any CPB completions after this
+                 * point in the handler will raise another interrupt.
+                 */
+                writew(status, mmio + NV_ADMA_STAT);
+                readw(mmio + NV_ADMA_STAT); /* flush posted write */
+                rmb();
+
+                handled++; /* irq handled if we got here */
+
+                /* freeze if hotplugged or controller error */
+                if (unlikely(status & (NV_ADMA_STAT_HOTPLUG |
+                                       NV_ADMA_STAT_HOTUNPLUG |
+                                       NV_ADMA_STAT_TIMEOUT |
+                                       NV_ADMA_STAT_SERROR))) {
+                        struct ata_eh_info *ehi = &ap->link.eh_info;
+
+                        ata_ehi_clear_desc(ehi);
+                        __ata_ehi_push_desc(ehi, "ADMA status 0x%08x: ", status);
+                        if (status & NV_ADMA_STAT_TIMEOUT) {
+                                ehi->err_mask |= AC_ERR_SYSTEM;
+                                ata_ehi_push_desc(ehi, "timeout");
+                        } else if (status & NV_ADMA_STAT_HOTPLUG) {
+                                ata_ehi_hotplugged(ehi);
+                                ata_ehi_push_desc(ehi, "hotplug");
+                        } else if (status & NV_ADMA_STAT_HOTUNPLUG) {
+                                ata_ehi_hotplugged(ehi);
+                                ata_ehi_push_desc(ehi, "hot unplug");
+                        } else if (status & NV_ADMA_STAT_SERROR) {
+                                /* let EH analyze SError and figure out cause */
+                                ata_ehi_push_desc(ehi, "SError");
+                        } else
+                                ata_ehi_push_desc(ehi, "unknown");
+                        ata_port_freeze(ap);
+                        continue;
+                }
+
+                if (status & (NV_ADMA_STAT_DONE |
+                              NV_ADMA_STAT_CPBERR |
+                              NV_ADMA_STAT_CMD_COMPLETE)) {
+                        u32 check_commands = notifier_clears[i];
+                        int pos, rc;
+
+                        if (status & NV_ADMA_STAT_CPBERR) {
+                                /* check all active commands */
+                                if (ata_tag_valid(ap->link.active_tag))
+                                        check_commands = 1 <<
+                                                ap->link.active_tag;
+                                else
+                                        check_commands = ap->link.sactive;
                         }
 
-                        if (status & (NV_ADMA_STAT_DONE |
-                                      NV_ADMA_STAT_CPBERR |
-                                      NV_ADMA_STAT_CMD_COMPLETE)) {
-                                u32 check_commands = notifier_clears[i];
-                                int pos, error = 0;
-
-                                if (status & NV_ADMA_STAT_CPBERR) {
-                                        /* Check all active commands */
-                                        if (ata_tag_valid(ap->link.active_tag))
-                                                check_commands = 1 <<
-                                                        ap->link.active_tag;
-                                        else
-                                                check_commands = ap->
-                                                        link.sactive;
-                                }
-
-                                /** Check CPBs for completed commands */
-                                while ((pos = ffs(check_commands)) && !error) {
-                                        pos--;
-                                        error = nv_adma_check_cpb(ap, pos,
+                        /* check CPBs for completed commands */
+                        while ((pos = ffs(check_commands))) {
+                                pos--;
+                                rc = nv_adma_check_cpb(ap, pos,
                                                 notifier_error & (1 << pos));
-                                        check_commands &= ~(1 << pos);
-                                }
+                                if (unlikely(rc))
+                                        check_commands = 0;
+                                check_commands &= ~(1 << pos);
                         }
                 }
         }
@@ -1099,7 +1102,7 @@ static void nv_adma_irq_clear(struct ata_port *ap)
         u32 notifier_clears[2];
 
         if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
-                ata_sff_irq_clear(ap);
+                ata_bmdma_irq_clear(ap);
                 return;
         }
 
@@ -1130,7 +1133,7 @@ static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc)
         struct nv_adma_port_priv *pp = qc->ap->private_data;
 
         if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
-                ata_sff_post_internal_cmd(qc);
+                ata_bmdma_post_internal_cmd(qc);
 }
 
 static int nv_adma_port_start(struct ata_port *ap)
@@ -1155,7 +1158,8 @@ static int nv_adma_port_start(struct ata_port *ap)
         if (rc)
                 return rc;
 
-        rc = ata_port_start(ap);
+        /* we might fallback to bmdma, allocate bmdma resources */
+        rc = ata_bmdma_port_start(ap);
         if (rc)
                 return rc;
 
@@ -1407,7 +1411,7 @@ static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
                 BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
                         (qc->flags & ATA_QCFLAG_DMAMAP));
                 nv_adma_register_mode(qc->ap);
-                ata_sff_qc_prep(qc);
+                ata_bmdma_qc_prep(qc);
                 return;
         }
 
@@ -1466,7 +1470,7 @@ static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
                 BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
                         (qc->flags & ATA_QCFLAG_DMAMAP));
                 nv_adma_register_mode(qc->ap);
-                return ata_sff_qc_issue(qc);
+                return ata_bmdma_qc_issue(qc);
         } else
                 nv_adma_mode(qc->ap);
 
@@ -1498,22 +1502,19 @@ static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
         spin_lock_irqsave(&host->lock, flags);
 
         for (i = 0; i < host->n_ports; i++) {
-                struct ata_port *ap;
-
-                ap = host->ports[i];
-                if (ap &&
-                    !(ap->flags & ATA_FLAG_DISABLED)) {
-                        struct ata_queued_cmd *qc;
+                struct ata_port *ap = host->ports[i];
+                struct ata_queued_cmd *qc;
 
-                        qc = ata_qc_from_tag(ap, ap->link.active_tag);
-                        if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
-                                handled += ata_sff_host_intr(ap, qc);
-                        else
-                                // No request pending?  Clear interrupt status
-                                // anyway, in case there's one pending.
-                                ap->ops->sff_check_status(ap);
+                qc = ata_qc_from_tag(ap, ap->link.active_tag);
+                if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
+                        handled += ata_bmdma_port_intr(ap, qc);
+                } else {
+                        /*
+                         * No request pending?  Clear interrupt status
+                         * anyway, in case there's one pending.
+                         */
+                        ap->ops->sff_check_status(ap);
                 }
-
         }
 
         spin_unlock_irqrestore(&host->lock, flags);
@@ -1526,11 +1527,7 @@ static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
         int i, handled = 0;
 
         for (i = 0; i < host->n_ports; i++) {
-                struct ata_port *ap = host->ports[i];
-
-                if (ap && !(ap->flags & ATA_FLAG_DISABLED))
-                        handled += nv_host_intr(ap, irq_stat);
-
+                handled += nv_host_intr(host->ports[i], irq_stat);
                 irq_stat >>= NV_INT_PORT_SHIFT;
         }
 
@@ -1674,7 +1671,6 @@ static void nv_mcp55_freeze(struct ata_port *ap)
         mask = readl(mmio_base + NV_INT_ENABLE_MCP55);
         mask &= ~(NV_INT_ALL_MCP55 << shift);
         writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
-        ata_sff_freeze(ap);
 }
 
 static void nv_mcp55_thaw(struct ata_port *ap)
@@ -1688,7 +1684,6 @@ static void nv_mcp55_thaw(struct ata_port *ap)
         mask = readl(mmio_base + NV_INT_ENABLE_MCP55);
         mask |= (NV_INT_MASK_MCP55 << shift);
         writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
-        ata_sff_thaw(ap);
 }
 
 static void nv_adma_error_handler(struct ata_port *ap)
@@ -1744,7 +1739,7 @@ static void nv_adma_error_handler(struct ata_port *ap)
                 readw(mmio + NV_ADMA_CTL);      /* flush posted write */
         }
 
-        ata_sff_error_handler(ap);
+        ata_bmdma_error_handler(ap);
 }
 
 static void nv_swncq_qc_to_dq(struct ata_port *ap, struct ata_queued_cmd *qc)
@@ -1870,7 +1865,7 @@ static void nv_swncq_error_handler(struct ata_port *ap)
                 ehc->i.action |= ATA_EH_RESET;
         }
 
-        ata_sff_error_handler(ap);
+        ata_bmdma_error_handler(ap);
 }
 
 #ifdef CONFIG_PM
@@ -1991,7 +1986,8 @@ static int nv_swncq_port_start(struct ata_port *ap)
         struct nv_swncq_port_priv *pp;
         int rc;
 
-        rc = ata_port_start(ap);
+        /* we might fallback to bmdma, allocate bmdma resources */
+        rc = ata_bmdma_port_start(ap);
         if (rc)
                 return rc;
 
@@ -2016,7 +2012,7 @@ static int nv_swncq_port_start(struct ata_port *ap)
 static void nv_swncq_qc_prep(struct ata_queued_cmd *qc)
 {
         if (qc->tf.protocol != ATA_PROT_NCQ) {
-                ata_sff_qc_prep(qc);
+                ata_bmdma_qc_prep(qc);
                 return;
         }
 
@@ -2031,7 +2027,7 @@ static void nv_swncq_fill_sg(struct ata_queued_cmd *qc)
         struct ata_port *ap = qc->ap;
         struct scatterlist *sg;
         struct nv_swncq_port_priv *pp = ap->private_data;
-        struct ata_prd *prd;
+        struct ata_bmdma_prd *prd;
         unsigned int si, idx;
 
         prd = pp->prd + ATA_MAX_PRD * qc->tag;
@@ -2092,7 +2088,7 @@ static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc)
         struct nv_swncq_port_priv *pp = ap->private_data;
 
         if (qc->tf.protocol != ATA_PROT_NCQ)
-                return ata_sff_qc_issue(qc);
+                return ata_bmdma_qc_issue(qc);
 
         DPRINTK("Enter\n");
 
@@ -2135,7 +2131,6 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
         struct nv_swncq_port_priv *pp = ap->private_data;
         struct ata_eh_info *ehi = &ap->link.eh_info;
         u32 sactive;
-        int nr_done = 0;
         u32 done_mask;
         int i;
         u8 host_stat;
@@ -2176,22 +2171,21 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
                         pp->dhfis_bits &= ~(1 << i);
                         pp->dmafis_bits &= ~(1 << i);
                         pp->sdbfis_bits |= (1 << i);
-                        nr_done++;
                 }
         }
 
         if (!ap->qc_active) {
                 DPRINTK("over\n");
                 nv_swncq_pp_reinit(ap);
-                return nr_done;
+                return 0;
         }
 
         if (pp->qc_active & pp->dhfis_bits)
-                return nr_done;
+                return 0;
 
         if ((pp->ncq_flags & ncq_saw_backout) ||
             (pp->qc_active ^ pp->dhfis_bits))
-                /* if the controller cann't get a device to host register FIS,
+                /* if the controller can't get a device to host register FIS,
                  * The driver needs to reissue the new command.
                  */
                 lack_dhfis = 1;
@@ -2208,7 +2202,7 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
         if (lack_dhfis) {
                 qc = ata_qc_from_tag(ap, pp->last_issue_tag);
                 nv_swncq_issue_atacmd(ap, qc);
-                return nr_done;
+                return 0;
         }
 
         if (pp->defer_queue.defer_bits) {
@@ -2218,7 +2212,7 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
                 nv_swncq_issue_atacmd(ap, qc);
         }
 
-        return nr_done;
+        return 0;
 }
 
 static inline u32 nv_swncq_tag(struct ata_port *ap)
@@ -2230,7 +2224,7 @@ static inline u32 nv_swncq_tag(struct ata_port *ap)
         return (tag & 0x1f);
 }
 
-static int nv_swncq_dmafis(struct ata_port *ap)
+static void nv_swncq_dmafis(struct ata_port *ap)
 {
         struct ata_queued_cmd *qc;
         unsigned int rw;
@@ -2245,7 +2239,7 @@ static int nv_swncq_dmafis(struct ata_port *ap)
         qc = ata_qc_from_tag(ap, tag);
 
         if (unlikely(!qc))
-                return 0;
+                return;
 
         rw = qc->tf.flags & ATA_TFLAG_WRITE;
 
@@ -2260,8 +2254,6 @@ static int nv_swncq_dmafis(struct ata_port *ap)
                 dmactl |= ATA_DMA_WR;
 
         iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
-
-        return 1;
 }
 
 static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
@@ -2271,7 +2263,6 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
         struct ata_eh_info *ehi = &ap->link.eh_info;
         u32 serror;
         u8 ata_stat;
-        int rc = 0;
 
         ata_stat = ap->ops->sff_check_status(ap);
         nv_swncq_irq_clear(ap, fis);
@@ -2316,8 +2307,7 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
                         "dhfis 0x%X dmafis 0x%X sactive 0x%X\n",
                         ap->print_id, pp->qc_active, pp->dhfis_bits,
                         pp->dmafis_bits, readl(pp->sactive_block));
-                rc = nv_swncq_sdbfis(ap);
-                if (rc < 0)
+                if (nv_swncq_sdbfis(ap) < 0)
                         goto irq_error;
         }
 
@@ -2354,7 +2344,7 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
                  */
                 pp->dmafis_bits |= (0x1 << nv_swncq_tag(ap));
                 pp->ncq_flags |= ncq_saw_dmas;
-                rc = nv_swncq_dmafis(ap);
+                nv_swncq_dmafis(ap);
         }
 
 irq_exit:
@@ -2380,16 +2370,14 @@ static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance)
         for (i = 0; i < host->n_ports; i++) {
                 struct ata_port *ap = host->ports[i];
 
-                if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
-                        if (ap->link.sactive) {
-                                nv_swncq_host_interrupt(ap, (u16)irq_stat);
-                                handled = 1;
-                        } else {
-                                if (irq_stat)   /* reserve Hotplug */
-                                        nv_swncq_irq_clear(ap, 0xfff0);
+                if (ap->link.sactive) {
+                        nv_swncq_host_interrupt(ap, (u16)irq_stat);
+                        handled = 1;
+                } else {
+                        if (irq_stat)   /* reserve Hotplug */
+                                nv_swncq_irq_clear(ap, 0xfff0);
 
-                                handled += nv_host_intr(ap, (u8)irq_stat);
-                        }
+                        handled += nv_host_intr(ap, (u8)irq_stat);
                 }
                 irq_stat >>= NV_INT_PORT_SHIFT_MCP55;
         }
@@ -2436,7 +2424,7 @@ static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         ppi[0] = &nv_port_info[type];
         ipriv = ppi[0]->private_data;
-        rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
+        rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
         if (rc)
                 return rc;
 
@@ -2479,8 +2467,7 @@ static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         }
 
         pci_set_master(pdev);
-        return ata_host_activate(host, pdev->irq, ipriv->irq_handler,
-                                 IRQF_SHARED, ipriv->sht);
+        return ata_pci_sff_activate_host(host, ipriv->irq_handler, ipriv->sht);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c
index 5356ec00d2b4..f03ad48273ff 100644
--- a/drivers/ata/sata_promise.c
+++ b/drivers/ata/sata_promise.c
@@ -333,7 +333,8 @@ static int pdc_common_port_start(struct ata_port *ap)
         struct pdc_port_priv *pp;
         int rc;
 
-        rc = ata_port_start(ap);
+        /* we use the same prd table as bmdma, allocate it */
+        rc = ata_bmdma_port_start(ap);
         if (rc)
                 return rc;
 
@@ -499,7 +500,7 @@ static int pdc_sata_scr_write(struct ata_link *link,
 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
 {
         struct ata_port *ap = qc->ap;
-        dma_addr_t sg_table = ap->prd_dma;
+        dma_addr_t sg_table = ap->bmdma_prd_dma;
         unsigned int cdb_len = qc->dev->cdb_len;
         u8 *cdb = qc->cdb;
         struct pdc_port_priv *pp = ap->private_data;
@@ -587,6 +588,7 @@ static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
 static void pdc_fill_sg(struct ata_queued_cmd *qc)
 {
         struct ata_port *ap = qc->ap;
+        struct ata_bmdma_prd *prd = ap->bmdma_prd;
         struct scatterlist *sg;
         const u32 SG_COUNT_ASIC_BUG = 41*4;
         unsigned int si, idx;
@@ -613,8 +615,8 @@ static void pdc_fill_sg(struct ata_queued_cmd *qc)
                         if ((offset + sg_len) > 0x10000)
                                 len = 0x10000 - offset;
 
-                        ap->prd[idx].addr = cpu_to_le32(addr);
-                        ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
+                        prd[idx].addr = cpu_to_le32(addr);
+                        prd[idx].flags_len = cpu_to_le32(len & 0xffff);
                         VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
 
                         idx++;
@@ -623,27 +625,27 @@ static void pdc_fill_sg(struct ata_queued_cmd *qc)
                 }
         }
 
-        len = le32_to_cpu(ap->prd[idx - 1].flags_len);
+        len = le32_to_cpu(prd[idx - 1].flags_len);
 
         if (len > SG_COUNT_ASIC_BUG) {
                 u32 addr;
 
                 VPRINTK("Splitting last PRD.\n");
 
-                addr = le32_to_cpu(ap->prd[idx - 1].addr);
-                ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
+                addr = le32_to_cpu(prd[idx - 1].addr);
+                prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
                 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
 
                 addr = addr + len - SG_COUNT_ASIC_BUG;
                 len = SG_COUNT_ASIC_BUG;
-                ap->prd[idx].addr = cpu_to_le32(addr);
-                ap->prd[idx].flags_len = cpu_to_le32(len);
+                prd[idx].addr = cpu_to_le32(addr);
+                prd[idx].flags_len = cpu_to_le32(len);
                 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
 
                 idx++;
         }
 
-        ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
+        prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
 }
 
 static void pdc_qc_prep(struct ata_queued_cmd *qc)
@@ -658,7 +660,7 @@ static void pdc_qc_prep(struct ata_queued_cmd *qc)
                 pdc_fill_sg(qc);
                 /*FALLTHROUGH*/
         case ATA_PROT_NODATA:
-                i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
+                i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma,
                                    qc->dev->devno, pp->pkt);
                 if (qc->tf.flags & ATA_TFLAG_LBA48)
                         i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
@@ -838,7 +840,7 @@ static void pdc_error_handler(struct ata_port *ap)
         if (!(ap->pflags & ATA_PFLAG_FROZEN))
                 pdc_reset_port(ap);
 
-        ata_std_error_handler(ap);
+        ata_sff_error_handler(ap);
 }
 
 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
@@ -984,8 +986,7 @@ static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
                 /* check for a plug or unplug event */
                 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
                 tmp = hotplug_status & (0x11 << ata_no);
-                if (tmp && ap &&
-                    !(ap->flags & ATA_FLAG_DISABLED)) {
+                if (tmp) {
                         struct ata_eh_info *ehi = &ap->link.eh_info;
                         ata_ehi_clear_desc(ehi);
                         ata_ehi_hotplugged(ehi);
@@ -997,8 +998,7 @@ static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
 
                 /* check for a packet interrupt */
                 tmp = mask & (1 << (i + 1));
-                if (tmp && ap &&
-                    !(ap->flags & ATA_FLAG_DISABLED)) {
+                if (tmp) {
                         struct ata_queued_cmd *qc;
 
                         qc = ata_qc_from_tag(ap, ap->link.active_tag);
diff --git a/drivers/ata/sata_qstor.c b/drivers/ata/sata_qstor.c
index 92ba45e6689b..daeebf19a6a9 100644
--- a/drivers/ata/sata_qstor.c
+++ b/drivers/ata/sata_qstor.c
@@ -120,8 +120,6 @@ static void qs_host_stop(struct ata_host *host);
 static void qs_qc_prep(struct ata_queued_cmd *qc);
 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
-static void qs_bmdma_stop(struct ata_queued_cmd *qc);
-static u8 qs_bmdma_status(struct ata_port *ap);
 static void qs_freeze(struct ata_port *ap);
 static void qs_thaw(struct ata_port *ap);
 static int qs_prereset(struct ata_link *link, unsigned long deadline);
@@ -137,8 +135,6 @@ static struct ata_port_operations qs_ata_ops = {
         .inherits               = &ata_sff_port_ops,
 
         .check_atapi_dma        = qs_check_atapi_dma,
-        .bmdma_stop             = qs_bmdma_stop,
-        .bmdma_status           = qs_bmdma_status,
         .qc_prep                = qs_qc_prep,
         .qc_issue               = qs_qc_issue,
 
@@ -147,7 +143,6 @@ static struct ata_port_operations qs_ata_ops = {
         .prereset               = qs_prereset,
         .softreset              = ATA_OP_NULL,
         .error_handler          = qs_error_handler,
-        .post_internal_cmd      = ATA_OP_NULL,
         .lost_interrupt         = ATA_OP_NULL,
 
         .scr_read               = qs_scr_read,
@@ -191,16 +186,6 @@ static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
         return 1;       /* ATAPI DMA not supported */
 }
 
-static void qs_bmdma_stop(struct ata_queued_cmd *qc)
-{
-        /* nothing */
-}
-
-static u8 qs_bmdma_status(struct ata_port *ap)
-{
-        return 0;
-}
-
 static inline void qs_enter_reg_mode(struct ata_port *ap)
 {
         u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
@@ -255,7 +240,7 @@ static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
 static void qs_error_handler(struct ata_port *ap)
 {
         qs_enter_reg_mode(ap);
-        ata_std_error_handler(ap);
+        ata_sff_error_handler(ap);
 }
 
 static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
@@ -304,10 +289,8 @@ static void qs_qc_prep(struct ata_queued_cmd *qc)
         VPRINTK("ENTER\n");
 
         qs_enter_reg_mode(qc->ap);
-        if (qc->tf.protocol != ATA_PROT_DMA) {
-                ata_sff_qc_prep(qc);
+        if (qc->tf.protocol != ATA_PROT_DMA)
                 return;
-        }
 
         nelem = qs_fill_sg(qc);
 
@@ -404,26 +387,24 @@ static inline unsigned int qs_intr_pkt(struct ata_host *host)
                         u8 sHST = sff1 & 0x3f;  /* host status */
                         unsigned int port_no = (sff1 >> 8) & 0x03;
                         struct ata_port *ap = host->ports[port_no];
+                        struct qs_port_priv *pp = ap->private_data;
+                        struct ata_queued_cmd *qc;
 
                         DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
                                         sff1, sff0, port_no, sHST, sDST);
                         handled = 1;
-                        if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
-                                struct ata_queued_cmd *qc;
-                                struct qs_port_priv *pp = ap->private_data;
-                                if (!pp || pp->state != qs_state_pkt)
-                                        continue;
-                                qc = ata_qc_from_tag(ap, ap->link.active_tag);
-                                if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
-                                        switch (sHST) {
-                                        case 0: /* successful CPB */
-                                        case 3: /* device error */
-                                                qs_enter_reg_mode(qc->ap);
-                                                qs_do_or_die(qc, sDST);
-                                                break;
-                                        default:
-                                                break;
-                                        }
+                        if (!pp || pp->state != qs_state_pkt)
+                                continue;
+                        qc = ata_qc_from_tag(ap, ap->link.active_tag);
+                        if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
+                                switch (sHST) {
+                                case 0: /* successful CPB */
+                                case 3: /* device error */
+                                        qs_enter_reg_mode(qc->ap);
+                                        qs_do_or_die(qc, sDST);
+                                        break;
+                                default:
+                                        break;
                                 }
                         }
                 }
@@ -436,33 +417,30 @@ static inline unsigned int qs_intr_mmio(struct ata_host *host)
         unsigned int handled = 0, port_no;
 
         for (port_no = 0; port_no < host->n_ports; ++port_no) {
-                struct ata_port *ap;
-                ap = host->ports[port_no];
-                if (ap &&
-                    !(ap->flags & ATA_FLAG_DISABLED)) {
-                        struct ata_queued_cmd *qc;
-                        struct qs_port_priv *pp;
-                        qc = ata_qc_from_tag(ap, ap->link.active_tag);
-                        if (!qc || !(qc->flags & ATA_QCFLAG_ACTIVE)) {
-                                /*
-                                 * The qstor hardware generates spurious
-                                 * interrupts from time to time when switching
-                                 * in and out of packet mode.
-                                 * There's no obvious way to know if we're
-                                 * here now due to that, so just ack the irq
-                                 * and pretend we knew it was ours.. (ugh).
-                                 * This does not affect packet mode.
-                                 */
-                                ata_sff_check_status(ap);
-                                handled = 1;
-                                continue;
-                        }
-                        pp = ap->private_data;
-                        if (!pp || pp->state != qs_state_mmio)
-                                continue;
-                        if (!(qc->tf.flags & ATA_TFLAG_POLLING))
-                                handled |= ata_sff_host_intr(ap, qc);
+                struct ata_port *ap = host->ports[port_no];
+                struct qs_port_priv *pp = ap->private_data;
+                struct ata_queued_cmd *qc;
+
+                qc = ata_qc_from_tag(ap, ap->link.active_tag);
+                if (!qc) {
+                        /*
+                         * The qstor hardware generates spurious
+                         * interrupts from time to time when switching
+                         * in and out of packet mode.  There's no
+                         * obvious way to know if we're here now due
+                         * to that, so just ack the irq and pretend we
+                         * knew it was ours.. (ugh).  This does not
+                         * affect packet mode.
+                         */
+                        ata_sff_check_status(ap);
+                        handled = 1;
+                        continue;
                 }
+
+                if (!pp || pp->state != qs_state_mmio)
+                        continue;
+                if (!(qc->tf.flags & ATA_TFLAG_POLLING))
+                        handled |= ata_sff_port_intr(ap, qc);
         }
         return handled;
 }
@@ -509,11 +487,7 @@ static int qs_port_start(struct ata_port *ap)
         void __iomem *mmio_base = qs_mmio_base(ap->host);
         void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
         u64 addr;
-        int rc;
 
-        rc = ata_port_start(ap);
-        if (rc)
-                return rc;
         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
         if (!pp)
                 return -ENOMEM;
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c
index 3cb69d5fb817..3a4f84219719 100644
--- a/drivers/ata/sata_sil.c
+++ b/drivers/ata/sata_sil.c
@@ -284,7 +284,7 @@ static void sil_bmdma_setup(struct ata_queued_cmd *qc)
         void __iomem *bmdma = ap->ioaddr.bmdma_addr;
 
         /* load PRD table addr. */
-        iowrite32(ap->prd_dma, bmdma + ATA_DMA_TABLE_OFS);
+        iowrite32(ap->bmdma_prd_dma, bmdma + ATA_DMA_TABLE_OFS);
 
         /* issue r/w command */
         ap->ops->sff_exec_command(ap, &qc->tf);
@@ -311,10 +311,10 @@ static void sil_fill_sg(struct ata_queued_cmd *qc)
 {
         struct scatterlist *sg;
         struct ata_port *ap = qc->ap;
-        struct ata_prd *prd, *last_prd = NULL;
+        struct ata_bmdma_prd *prd, *last_prd = NULL;
         unsigned int si;
 
-        prd = &ap->prd[0];
+        prd = &ap->bmdma_prd[0];
         for_each_sg(qc->sg, sg, qc->n_elem, si) {
                 /* Note h/w doesn't support 64-bit, so we unconditionally
                  * truncate dma_addr_t to u32.
@@ -503,7 +503,7 @@ static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
                 goto err_hsm;
 
         /* ack bmdma irq events */
-        ata_sff_irq_clear(ap);
+        ata_bmdma_irq_clear(ap);
 
         /* kick HSM in the ass */
         ata_sff_hsm_move(ap, qc, status, 0);
@@ -532,9 +532,6 @@ static irqreturn_t sil_interrupt(int irq, void *dev_instance)
                 struct ata_port *ap = host->ports[i];
                 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
 
-                if (unlikely(ap->flags & ATA_FLAG_DISABLED))
-                        continue;
-
                 /* turn off SATA_IRQ if not supported */
                 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
                         bmdma2 &= ~SIL_DMA_SATA_IRQ;
@@ -587,7 +584,7 @@ static void sil_thaw(struct ata_port *ap)
 
         /* clear IRQ */
         ap->ops->sff_check_status(ap);
-        ata_sff_irq_clear(ap);
+        ata_bmdma_irq_clear(ap);
 
         /* turn on SATA IRQ if supported */
         if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c
index 433b6b89c795..be7726d7686d 100644
--- a/drivers/ata/sata_sil24.c
+++ b/drivers/ata/sata_sil24.c
@@ -539,12 +539,12 @@ static void sil24_config_port(struct ata_port *ap)
                 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
 
         /* zero error counters. */
-        writel(0x8000, port + PORT_DECODE_ERR_THRESH);
-        writel(0x8000, port + PORT_CRC_ERR_THRESH);
-        writel(0x8000, port + PORT_HSHK_ERR_THRESH);
-        writel(0x0000, port + PORT_DECODE_ERR_CNT);
-        writel(0x0000, port + PORT_CRC_ERR_CNT);
-        writel(0x0000, port + PORT_HSHK_ERR_CNT);
+        writew(0x8000, port + PORT_DECODE_ERR_THRESH);
+        writew(0x8000, port + PORT_CRC_ERR_THRESH);
+        writew(0x8000, port + PORT_HSHK_ERR_THRESH);
+        writew(0x0000, port + PORT_DECODE_ERR_CNT);
+        writew(0x0000, port + PORT_CRC_ERR_CNT);
+        writew(0x0000, port + PORT_HSHK_ERR_CNT);
 
         /* always use 64bit activation */
         writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
@@ -622,6 +622,11 @@ static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
         irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
         writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
 
+        /*
+         * The barrier is required to ensure that writes to cmd_block reach
+         * the memory before the write to PORT_CMD_ACTIVATE.
+         */
+        wmb();
         writel((u32)paddr, port + PORT_CMD_ACTIVATE);
         writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
 
@@ -865,7 +870,7 @@ static void sil24_qc_prep(struct ata_queued_cmd *qc)
         } else {
                 prb = &cb->atapi.prb;
                 sge = cb->atapi.sge;
-                memset(cb->atapi.cdb, 0, 32);
+                memset(cb->atapi.cdb, 0, sizeof(cb->atapi.cdb));
                 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
 
                 if (ata_is_data(qc->tf.protocol)) {
@@ -895,6 +900,11 @@ static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
         paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
         activate = port + PORT_CMD_ACTIVATE + tag * 8;
 
+        /*
+         * The barrier is required to ensure that writes to cmd_block reach
+         * the memory before the write to PORT_CMD_ACTIVATE.
+         */
+        wmb();
         writel((u32)paddr, activate);
         writel((u64)paddr >> 32, activate + 4);
 
@@ -1160,13 +1170,8 @@ static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
 
         for (i = 0; i < host->n_ports; i++)
                 if (status & (1 << i)) {
-                        struct ata_port *ap = host->ports[i];
-                        if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
-                                sil24_host_intr(ap);
-                                handled++;
-                        } else
-                                printk(KERN_ERR DRV_NAME
-                                       ": interrupt from disabled port %d\n", i);
+                        sil24_host_intr(host->ports[i]);
+                        handled++;
                 }
 
         spin_unlock(&host->lock);
diff --git a/drivers/ata/sata_sis.c b/drivers/ata/sata_sis.c
index f8a91bfd66a8..2bfe3ae03976 100644
--- a/drivers/ata/sata_sis.c
+++ b/drivers/ata/sata_sis.c
@@ -279,7 +279,7 @@ static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
                 break;
         }
 
-        rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
+        rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
         if (rc)
                 return rc;
 
@@ -308,7 +308,7 @@ static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         pci_set_master(pdev);
         pci_intx(pdev, 1);
-        return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
+        return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
                                  IRQF_SHARED, &sis_sht);
 }
 
diff --git a/drivers/ata/sata_svw.c b/drivers/ata/sata_svw.c
index 7257f2d5c52c..7d9db4aaf07e 100644
--- a/drivers/ata/sata_svw.c
+++ b/drivers/ata/sata_svw.c
@@ -224,7 +224,7 @@ static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
 
         /* load PRD table addr. */
         mb();   /* make sure PRD table writes are visible to controller */
-        writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
+        writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
 
         /* specify data direction, triple-check start bit is clear */
         dmactl = readb(mmio + ATA_DMA_CMD);
@@ -502,7 +502,7 @@ static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *en
         writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
 
         pci_set_master(pdev);
-        return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
+        return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
                                  IRQF_SHARED, &k2_sata_sht);
 }
 
diff --git a/drivers/ata/sata_sx4.c b/drivers/ata/sata_sx4.c
index 232468f2ea90..bedd5188e5b0 100644
--- a/drivers/ata/sata_sx4.c
+++ b/drivers/ata/sata_sx4.c
@@ -302,11 +302,6 @@ static int pdc_port_start(struct ata_port *ap)
 {
         struct device *dev = ap->host->dev;
         struct pdc_port_priv *pp;
-        int rc;
-
-        rc = ata_port_start(ap);
-        if (rc)
-                return rc;
 
         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
         if (!pp)
@@ -840,8 +835,7 @@ static irqreturn_t pdc20621_interrupt(int irq, void *dev_instance)
                         ap = host->ports[port_no];
                 tmp = mask & (1 << i);
                 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
-                if (tmp && ap &&
-                    !(ap->flags & ATA_FLAG_DISABLED)) {
+                if (tmp && ap) {
                         struct ata_queued_cmd *qc;
 
                         qc = ata_qc_from_tag(ap, ap->link.active_tag);
@@ -927,7 +921,7 @@ static void pdc_error_handler(struct ata_port *ap)
         if (!(ap->pflags & ATA_PFLAG_FROZEN))
                 pdc_reset_port(ap);
 
-        ata_std_error_handler(ap);
+        ata_sff_error_handler(ap);
 }
 
 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
diff --git a/drivers/ata/sata_uli.c b/drivers/ata/sata_uli.c
index 011e098590d1..b8578c32d344 100644
--- a/drivers/ata/sata_uli.c
+++ b/drivers/ata/sata_uli.c
@@ -181,9 +181,7 @@ static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         if (rc)
                 return rc;
 
-        rc = ata_pci_bmdma_init(host);
-        if (rc)
-                return rc;
+        ata_pci_bmdma_init(host);
 
         iomap = host->iomap;
 
@@ -244,7 +242,7 @@ static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         pci_set_master(pdev);
         pci_intx(pdev, 1);
-        return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
+        return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
                                  IRQF_SHARED, &uli_sht);
 }
 
diff --git a/drivers/ata/sata_via.c b/drivers/ata/sata_via.c
index 08f65492cc81..4730c42a5ee5 100644
--- a/drivers/ata/sata_via.c
+++ b/drivers/ata/sata_via.c
@@ -308,7 +308,7 @@ static void svia_noop_freeze(struct ata_port *ap)
          * certain way.  Leave it alone and just clear pending IRQ.
          */
         ap->ops->sff_check_status(ap);
-        ata_sff_irq_clear(ap);
+        ata_bmdma_irq_clear(ap);
 }
 
 /**
@@ -463,7 +463,7 @@ static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
         struct ata_host *host;
         int rc;
 
-        rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
+        rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
         if (rc)
                 return rc;
         *r_host = host;
@@ -520,7 +520,7 @@ static int vt8251_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
         struct ata_host *host;
         int i, rc;
 
-        rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
+        rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
         if (rc)
                 return rc;
         *r_host = host;
@@ -575,6 +575,33 @@ static void svia_configure(struct pci_dev *pdev)
                 tmp8 |= NATIVE_MODE_ALL;
                 pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
         }
+
+        /*
+         * vt6421 has problems talking to some drives.  The following
+         * is the fix from Joseph Chan <JosephChan@via.com.tw>.
+         *
+         * When host issues HOLD, device may send up to 20DW of data
+         * before acknowledging it with HOLDA and the host should be
+         * able to buffer them in FIFO.  Unfortunately, some WD drives
+         * send upto 40DW before acknowledging HOLD and, in the
+         * default configuration, this ends up overflowing vt6421's
+         * FIFO, making the controller abort the transaction with
+         * R_ERR.
+         *
+         * Rx52[2] is the internal 128DW FIFO Flow control watermark
+         * adjusting mechanism enable bit and the default value 0
+         * means host will issue HOLD to device when the left FIFO
+         * size goes below 32DW.  Setting it to 1 makes the watermark
+         * 64DW.
+         *
+         * https://bugzilla.kernel.org/show_bug.cgi?id=15173
+         * http://article.gmane.org/gmane.linux.ide/46352
+         */
+        if (pdev->device == 0x3249) {
+                pci_read_config_byte(pdev, 0x52, &tmp8);
+                tmp8 |= 1 << 2;
+                pci_write_config_byte(pdev, 0x52, tmp8);
+        }
 }
 
 static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
@@ -628,7 +655,7 @@ static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         svia_configure(pdev);
 
         pci_set_master(pdev);
-        return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
+        return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
                                  IRQF_SHARED, &svia_sht);
 }
 
diff --git a/drivers/ata/sata_vsc.c b/drivers/ata/sata_vsc.c
index 8b2a278b2547..b777176ff494 100644
--- a/drivers/ata/sata_vsc.c
+++ b/drivers/ata/sata_vsc.c
@@ -245,7 +245,7 @@ static void vsc_port_intr(u8 port_status, struct ata_port *ap)
 
         qc = ata_qc_from_tag(ap, ap->link.active_tag);
         if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
-                handled = ata_sff_host_intr(ap, qc);
+                handled = ata_bmdma_port_intr(ap, qc);
 
         /* We received an interrupt during a polled command,
          * or some other spurious condition.  Interrupt reporting
@@ -284,14 +284,8 @@ static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance)
         for (i = 0; i < host->n_ports; i++) {
                 u8 port_status = (status >> (8 * i)) & 0xff;
                 if (port_status) {
-                        struct ata_port *ap = host->ports[i];
-
-                        if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
-                                vsc_port_intr(port_status, ap);
-                                handled++;
-                        } else
-                                dev_printk(KERN_ERR, host->dev,
-                                        "interrupt from disabled port %d\n", i);
+                        vsc_port_intr(port_status, host->ports[i]);
+                        handled++;
                 }
         }