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-rw-r--r--drivers/ata/Kconfig10
-rw-r--r--drivers/ata/ahci.c191
-rw-r--r--drivers/ata/ata_piix.c16
-rw-r--r--drivers/ata/libata-acpi.c167
-rw-r--r--drivers/ata/libata-core.c46
-rw-r--r--drivers/ata/libata-eh.c207
-rw-r--r--drivers/ata/libata-pmp.c51
-rw-r--r--drivers/ata/libata-scsi.c25
-rw-r--r--drivers/ata/libata-sff.c145
-rw-r--r--drivers/ata/libata.h2
-rw-r--r--drivers/ata/pata_ali.c10
-rw-r--r--drivers/ata/pata_amd.c14
-rw-r--r--drivers/ata/pata_at32.c2
-rw-r--r--drivers/ata/pata_bf54x.c5
-rw-r--r--drivers/ata/pata_cypress.c8
-rw-r--r--drivers/ata/pata_icside.c2
-rw-r--r--drivers/ata/pata_legacy.c50
-rw-r--r--drivers/ata/pata_ns87410.c6
-rw-r--r--drivers/ata/pata_ns87415.c4
-rw-r--r--drivers/ata/pata_pcmcia.c2
-rw-r--r--drivers/ata/pata_qdi.c16
-rw-r--r--drivers/ata/pata_rb532_cf.c4
-rw-r--r--drivers/ata/pata_scc.c5
-rw-r--r--drivers/ata/pata_sis.c1
-rw-r--r--drivers/ata/pata_sl82c105.c2
-rw-r--r--drivers/ata/pata_via.c14
-rw-r--r--drivers/ata/pata_winbond.c6
-rw-r--r--drivers/ata/sata_fsl.c224
-rw-r--r--drivers/ata/sata_mv.c279
-rw-r--r--drivers/ata/sata_promise.c148
-rw-r--r--drivers/ata/sata_sil24.c12
-rw-r--r--drivers/ata/sata_uli.c1
32 files changed, 1089 insertions, 586 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 9bf2986a2788..ae8494944c45 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -651,9 +651,17 @@ config PATA_WINBOND_VLB
651 Support for the Winbond W83759A controller on Vesa Local Bus 651 Support for the Winbond W83759A controller on Vesa Local Bus
652 systems. 652 systems.
653 653
654config HAVE_PATA_PLATFORM
655 bool
656 help
657 This is an internal configuration node for any machine that
658 uses pata-platform driver to enable the relevant driver in the
659 configuration structure without having to submit endless patches
660 to update the PATA_PLATFORM entry.
661
654config PATA_PLATFORM 662config PATA_PLATFORM
655 tristate "Generic platform device PATA support" 663 tristate "Generic platform device PATA support"
656 depends on EMBEDDED || ARCH_RPC || PPC 664 depends on EMBEDDED || ARCH_RPC || PPC || HAVE_PATA_PLATFORM
657 help 665 help
658 This option enables support for generic directly connected ATA 666 This option enables support for generic directly connected ATA
659 devices commonly found on embedded systems. 667 devices commonly found on embedded systems.
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 97f83fb2ee2e..5e6468a7ca4b 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -89,6 +89,8 @@ enum {
89 board_ahci_sb600 = 3, 89 board_ahci_sb600 = 3,
90 board_ahci_mv = 4, 90 board_ahci_mv = 4,
91 board_ahci_sb700 = 5, 91 board_ahci_sb700 = 5,
92 board_ahci_mcp65 = 6,
93 board_ahci_nopmp = 7,
92 94
93 /* global controller registers */ 95 /* global controller registers */
94 HOST_CAP = 0x00, /* host capabilities */ 96 HOST_CAP = 0x00, /* host capabilities */
@@ -190,6 +192,7 @@ enum {
190 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ 192 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
191 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ 193 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
192 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ 194 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
195 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
193 196
194 /* ap->flags bits */ 197 /* ap->flags bits */
195 198
@@ -253,6 +256,8 @@ static void ahci_pmp_attach(struct ata_port *ap);
253static void ahci_pmp_detach(struct ata_port *ap); 256static void ahci_pmp_detach(struct ata_port *ap);
254static int ahci_softreset(struct ata_link *link, unsigned int *class, 257static int ahci_softreset(struct ata_link *link, unsigned int *class,
255 unsigned long deadline); 258 unsigned long deadline);
259static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
260 unsigned long deadline);
256static int ahci_hardreset(struct ata_link *link, unsigned int *class, 261static int ahci_hardreset(struct ata_link *link, unsigned int *class,
257 unsigned long deadline); 262 unsigned long deadline);
258static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 263static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
@@ -329,6 +334,12 @@ static struct ata_port_operations ahci_p5wdh_ops = {
329 .hardreset = ahci_p5wdh_hardreset, 334 .hardreset = ahci_p5wdh_hardreset,
330}; 335};
331 336
337static struct ata_port_operations ahci_sb600_ops = {
338 .inherits = &ahci_ops,
339 .softreset = ahci_sb600_softreset,
340 .pmp_softreset = ahci_sb600_softreset,
341};
342
332#define AHCI_HFLAGS(flags) .private_data = (void *)(flags) 343#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
333 344
334static const struct ata_port_info ahci_port_info[] = { 345static const struct ata_port_info ahci_port_info[] = {
@@ -359,11 +370,11 @@ static const struct ata_port_info ahci_port_info[] = {
359 { 370 {
360 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 371 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
361 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI | 372 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
362 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP), 373 AHCI_HFLAG_SECT255),
363 .flags = AHCI_FLAG_COMMON, 374 .flags = AHCI_FLAG_COMMON,
364 .pio_mask = 0x1f, /* pio0-4 */ 375 .pio_mask = 0x1f, /* pio0-4 */
365 .udma_mask = ATA_UDMA6, 376 .udma_mask = ATA_UDMA6,
366 .port_ops = &ahci_ops, 377 .port_ops = &ahci_sb600_ops,
367 }, 378 },
368 /* board_ahci_mv */ 379 /* board_ahci_mv */
369 { 380 {
@@ -377,8 +388,23 @@ static const struct ata_port_info ahci_port_info[] = {
377 }, 388 },
378 /* board_ahci_sb700 */ 389 /* board_ahci_sb700 */
379 { 390 {
380 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 391 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
381 AHCI_HFLAG_NO_PMP), 392 .flags = AHCI_FLAG_COMMON,
393 .pio_mask = 0x1f, /* pio0-4 */
394 .udma_mask = ATA_UDMA6,
395 .port_ops = &ahci_sb600_ops,
396 },
397 /* board_ahci_mcp65 */
398 {
399 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
400 .flags = AHCI_FLAG_COMMON,
401 .pio_mask = 0x1f, /* pio0-4 */
402 .udma_mask = ATA_UDMA6,
403 .port_ops = &ahci_ops,
404 },
405 /* board_ahci_nopmp */
406 {
407 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
382 .flags = AHCI_FLAG_COMMON, 408 .flags = AHCI_FLAG_COMMON,
383 .pio_mask = 0x1f, /* pio0-4 */ 409 .pio_mask = 0x1f, /* pio0-4 */
384 .udma_mask = ATA_UDMA6, 410 .udma_mask = ATA_UDMA6,
@@ -438,14 +464,14 @@ static const struct pci_device_id ahci_pci_tbl[] = {
438 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 464 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
439 465
440 /* NVIDIA */ 466 /* NVIDIA */
441 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ 467 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
442 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ 468 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
443 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ 469 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
444 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ 470 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
445 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ 471 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
446 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ 472 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
447 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ 473 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
448 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ 474 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
449 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ 475 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
450 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ 476 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
451 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ 477 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
@@ -502,15 +528,15 @@ static const struct pci_device_id ahci_pci_tbl[] = {
502 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */ 528 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
503 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */ 529 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
504 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */ 530 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
505 { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */ 531 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
506 { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */ 532 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
507 { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */ 533 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
508 { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */ 534 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
509 535
510 /* SiS */ 536 /* SiS */
511 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 537 { PCI_VDEVICE(SI, 0x1184), board_ahci_nopmp }, /* SiS 966 */
512 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ 538 { PCI_VDEVICE(SI, 0x1185), board_ahci_nopmp }, /* SiS 968 */
513 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 539 { PCI_VDEVICE(SI, 0x0186), board_ahci_nopmp }, /* SiS 968 */
514 540
515 /* Marvell */ 541 /* Marvell */
516 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 542 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
@@ -624,12 +650,26 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
624 cap &= ~HOST_CAP_NCQ; 650 cap &= ~HOST_CAP_NCQ;
625 } 651 }
626 652
653 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
654 dev_printk(KERN_INFO, &pdev->dev,
655 "controller can do NCQ, turning on CAP_NCQ\n");
656 cap |= HOST_CAP_NCQ;
657 }
658
627 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 659 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
628 dev_printk(KERN_INFO, &pdev->dev, 660 dev_printk(KERN_INFO, &pdev->dev,
629 "controller can't do PMP, turning off CAP_PMP\n"); 661 "controller can't do PMP, turning off CAP_PMP\n");
630 cap &= ~HOST_CAP_PMP; 662 cap &= ~HOST_CAP_PMP;
631 } 663 }
632 664
665 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
666 port_map != 1) {
667 dev_printk(KERN_INFO, &pdev->dev,
668 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
669 port_map, 1);
670 port_map = 1;
671 }
672
633 /* 673 /*
634 * Temporary Marvell 6145 hack: PATA port presence 674 * Temporary Marvell 6145 hack: PATA port presence
635 * is asserted through the standard AHCI port 675 * is asserted through the standard AHCI port
@@ -1262,19 +1302,11 @@ static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1262 return 0; 1302 return 0;
1263} 1303}
1264 1304
1265static int ahci_check_ready(struct ata_link *link) 1305static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1266{ 1306 int pmp, unsigned long deadline,
1267 void __iomem *port_mmio = ahci_port_base(link->ap); 1307 int (*check_ready)(struct ata_link *link))
1268 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1269
1270 return ata_check_ready(status);
1271}
1272
1273static int ahci_softreset(struct ata_link *link, unsigned int *class,
1274 unsigned long deadline)
1275{ 1308{
1276 struct ata_port *ap = link->ap; 1309 struct ata_port *ap = link->ap;
1277 int pmp = sata_srst_pmp(link);
1278 const char *reason = NULL; 1310 const char *reason = NULL;
1279 unsigned long now, msecs; 1311 unsigned long now, msecs;
1280 struct ata_taskfile tf; 1312 struct ata_taskfile tf;
@@ -1312,7 +1344,7 @@ static int ahci_softreset(struct ata_link *link, unsigned int *class,
1312 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1344 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1313 1345
1314 /* wait for link to become ready */ 1346 /* wait for link to become ready */
1315 rc = ata_wait_after_reset(link, deadline, ahci_check_ready); 1347 rc = ata_wait_after_reset(link, deadline, check_ready);
1316 /* link occupied, -ENODEV too is an error */ 1348 /* link occupied, -ENODEV too is an error */
1317 if (rc) { 1349 if (rc) {
1318 reason = "device not ready"; 1350 reason = "device not ready";
@@ -1328,6 +1360,72 @@ static int ahci_softreset(struct ata_link *link, unsigned int *class,
1328 return rc; 1360 return rc;
1329} 1361}
1330 1362
1363static int ahci_check_ready(struct ata_link *link)
1364{
1365 void __iomem *port_mmio = ahci_port_base(link->ap);
1366 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1367
1368 return ata_check_ready(status);
1369}
1370
1371static int ahci_softreset(struct ata_link *link, unsigned int *class,
1372 unsigned long deadline)
1373{
1374 int pmp = sata_srst_pmp(link);
1375
1376 DPRINTK("ENTER\n");
1377
1378 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1379}
1380
1381static int ahci_sb600_check_ready(struct ata_link *link)
1382{
1383 void __iomem *port_mmio = ahci_port_base(link->ap);
1384 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1385 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1386
1387 /*
1388 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1389 * which can save timeout delay.
1390 */
1391 if (irq_status & PORT_IRQ_BAD_PMP)
1392 return -EIO;
1393
1394 return ata_check_ready(status);
1395}
1396
1397static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1398 unsigned long deadline)
1399{
1400 struct ata_port *ap = link->ap;
1401 void __iomem *port_mmio = ahci_port_base(ap);
1402 int pmp = sata_srst_pmp(link);
1403 int rc;
1404 u32 irq_sts;
1405
1406 DPRINTK("ENTER\n");
1407
1408 rc = ahci_do_softreset(link, class, pmp, deadline,
1409 ahci_sb600_check_ready);
1410
1411 /*
1412 * Soft reset fails on some ATI chips with IPMS set when PMP
1413 * is enabled but SATA HDD/ODD is connected to SATA port,
1414 * do soft reset again to port 0.
1415 */
1416 if (rc == -EIO) {
1417 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1418 if (irq_sts & PORT_IRQ_BAD_PMP) {
1419 ata_link_printk(link, KERN_WARNING,
1420 "failed due to HW bug, retry pmp=0\n");
1421 rc = ahci_do_softreset(link, class, 0, deadline,
1422 ahci_check_ready);
1423 }
1424 }
1425
1426 return rc;
1427}
1428
1331static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1429static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1332 unsigned long deadline) 1430 unsigned long deadline)
1333{ 1431{
@@ -1679,7 +1777,7 @@ static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1679 struct ahci_host_priv *hpriv; 1777 struct ahci_host_priv *hpriv;
1680 unsigned int i, handled = 0; 1778 unsigned int i, handled = 0;
1681 void __iomem *mmio; 1779 void __iomem *mmio;
1682 u32 irq_stat, irq_ack = 0; 1780 u32 irq_stat, irq_masked;
1683 1781
1684 VPRINTK("ENTER\n"); 1782 VPRINTK("ENTER\n");
1685 1783
@@ -1688,16 +1786,17 @@ static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1688 1786
1689 /* sigh. 0xffffffff is a valid return from h/w */ 1787 /* sigh. 0xffffffff is a valid return from h/w */
1690 irq_stat = readl(mmio + HOST_IRQ_STAT); 1788 irq_stat = readl(mmio + HOST_IRQ_STAT);
1691 irq_stat &= hpriv->port_map;
1692 if (!irq_stat) 1789 if (!irq_stat)
1693 return IRQ_NONE; 1790 return IRQ_NONE;
1694 1791
1792 irq_masked = irq_stat & hpriv->port_map;
1793
1695 spin_lock(&host->lock); 1794 spin_lock(&host->lock);
1696 1795
1697 for (i = 0; i < host->n_ports; i++) { 1796 for (i = 0; i < host->n_ports; i++) {
1698 struct ata_port *ap; 1797 struct ata_port *ap;
1699 1798
1700 if (!(irq_stat & (1 << i))) 1799 if (!(irq_masked & (1 << i)))
1701 continue; 1800 continue;
1702 1801
1703 ap = host->ports[i]; 1802 ap = host->ports[i];
@@ -1711,14 +1810,20 @@ static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1711 "interrupt on disabled port %u\n", i); 1810 "interrupt on disabled port %u\n", i);
1712 } 1811 }
1713 1812
1714 irq_ack |= (1 << i);
1715 }
1716
1717 if (irq_ack) {
1718 writel(irq_ack, mmio + HOST_IRQ_STAT);
1719 handled = 1; 1813 handled = 1;
1720 } 1814 }
1721 1815
1816 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1817 * it should be cleared after all the port events are cleared;
1818 * otherwise, it will raise a spurious interrupt after each
1819 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1820 * information.
1821 *
1822 * Also, use the unmasked value to clear interrupt as spurious
1823 * pending event on a dummy port might cause screaming IRQ.
1824 */
1825 writel(irq_stat, mmio + HOST_IRQ_STAT);
1826
1722 spin_unlock(&host->lock); 1827 spin_unlock(&host->lock);
1723 1828
1724 VPRINTK("EXIT\n"); 1829 VPRINTK("EXIT\n");
@@ -2118,7 +2223,8 @@ static void ahci_p5wdh_workaround(struct ata_host *host)
2118static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 2223static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2119{ 2224{
2120 static int printed_version; 2225 static int printed_version;
2121 struct ata_port_info pi = ahci_port_info[ent->driver_data]; 2226 unsigned int board_id = ent->driver_data;
2227 struct ata_port_info pi = ahci_port_info[board_id];
2122 const struct ata_port_info *ppi[] = { &pi, NULL }; 2228 const struct ata_port_info *ppi[] = { &pi, NULL };
2123 struct device *dev = &pdev->dev; 2229 struct device *dev = &pdev->dev;
2124 struct ahci_host_priv *hpriv; 2230 struct ahci_host_priv *hpriv;
@@ -2167,6 +2273,11 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2167 return -ENOMEM; 2273 return -ENOMEM;
2168 hpriv->flags |= (unsigned long)pi.private_data; 2274 hpriv->flags |= (unsigned long)pi.private_data;
2169 2275
2276 /* MCP65 revision A1 and A2 can't do MSI */
2277 if (board_id == board_ahci_mcp65 &&
2278 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2279 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2280
2170 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev)) 2281 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2171 pci_intx(pdev, 1); 2282 pci_intx(pdev, 1);
2172 2283
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index a9027b8fbdd5..a90ae03f56b2 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -247,10 +247,11 @@ static const struct pci_device_id piix_pci_tbl[] = {
247 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 247 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
248 /* SATA Controller 2 IDE (ICH8) */ 248 /* SATA Controller 2 IDE (ICH8) */
249 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 249 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
250 /* Mobile SATA Controller IDE (ICH8M) */
251 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
252 /* Mobile SATA Controller IDE (ICH8M), Apple */ 250 /* Mobile SATA Controller IDE (ICH8M), Apple */
253 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, 251 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
252 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
253 /* Mobile SATA Controller IDE (ICH8M) */
254 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
254 /* SATA Controller IDE (ICH9) */ 255 /* SATA Controller IDE (ICH9) */
255 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 256 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
256 /* SATA Controller IDE (ICH9) */ 257 /* SATA Controller IDE (ICH9) */
@@ -526,7 +527,7 @@ static struct ata_port_info piix_port_info[] = {
526 527
527 [ich8m_apple_sata] = 528 [ich8m_apple_sata] =
528 { 529 {
529 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 530 .flags = PIIX_SATA_FLAGS,
530 .pio_mask = 0x1f, /* pio0-4 */ 531 .pio_mask = 0x1f, /* pio0-4 */
531 .mwdma_mask = 0x07, /* mwdma0-2 */ 532 .mwdma_mask = 0x07, /* mwdma0-2 */
532 .udma_mask = ATA_UDMA6, 533 .udma_mask = ATA_UDMA6,
@@ -573,6 +574,8 @@ static const struct ich_laptop ich_laptop[] = {
573 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 574 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
574 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 575 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
575 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 576 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
577 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
578 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
576 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ 579 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
577 /* end marker */ 580 /* end marker */
578 { 0, } 581 { 0, }
@@ -1040,6 +1043,13 @@ static int piix_broken_suspend(void)
1040 }, 1043 },
1041 }, 1044 },
1042 { 1045 {
1046 .ident = "TECRA M4",
1047 .matches = {
1048 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1049 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1050 },
1051 },
1052 {
1043 .ident = "TECRA M5", 1053 .ident = "TECRA M5",
1044 .matches = { 1054 .matches = {
1045 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1055 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
diff --git a/drivers/ata/libata-acpi.c b/drivers/ata/libata-acpi.c
index 70b77e0899a8..9330b7922f62 100644
--- a/drivers/ata/libata-acpi.c
+++ b/drivers/ata/libata-acpi.c
@@ -29,14 +29,16 @@
29enum { 29enum {
30 ATA_ACPI_FILTER_SETXFER = 1 << 0, 30 ATA_ACPI_FILTER_SETXFER = 1 << 0,
31 ATA_ACPI_FILTER_LOCK = 1 << 1, 31 ATA_ACPI_FILTER_LOCK = 1 << 1,
32 ATA_ACPI_FILTER_DIPM = 1 << 2,
32 33
33 ATA_ACPI_FILTER_DEFAULT = ATA_ACPI_FILTER_SETXFER | 34 ATA_ACPI_FILTER_DEFAULT = ATA_ACPI_FILTER_SETXFER |
34 ATA_ACPI_FILTER_LOCK, 35 ATA_ACPI_FILTER_LOCK |
36 ATA_ACPI_FILTER_DIPM,
35}; 37};
36 38
37static unsigned int ata_acpi_gtf_filter = ATA_ACPI_FILTER_DEFAULT; 39static unsigned int ata_acpi_gtf_filter = ATA_ACPI_FILTER_DEFAULT;
38module_param_named(acpi_gtf_filter, ata_acpi_gtf_filter, int, 0644); 40module_param_named(acpi_gtf_filter, ata_acpi_gtf_filter, int, 0644);
39MODULE_PARM_DESC(acpi_gtf_filter, "filter mask for ACPI _GTF commands, set to filter out (0x1=set xfermode, 0x2=lock/freeze lock)"); 41MODULE_PARM_DESC(acpi_gtf_filter, "filter mask for ACPI _GTF commands, set to filter out (0x1=set xfermode, 0x2=lock/freeze lock, 0x4=DIPM)");
40 42
41#define NO_PORT_MULT 0xffff 43#define NO_PORT_MULT 0xffff
42#define SATA_ADR(root, pmp) (((root) << 16) | (pmp)) 44#define SATA_ADR(root, pmp) (((root) << 16) | (pmp))
@@ -118,19 +120,86 @@ static void ata_acpi_associate_ide_port(struct ata_port *ap)
118 ap->pflags |= ATA_PFLAG_INIT_GTM_VALID; 120 ap->pflags |= ATA_PFLAG_INIT_GTM_VALID;
119} 121}
120 122
123static void ata_acpi_eject_device(acpi_handle handle)
124{
125 struct acpi_object_list arg_list;
126 union acpi_object arg;
127
128 arg_list.count = 1;
129 arg_list.pointer = &arg;
130 arg.type = ACPI_TYPE_INTEGER;
131 arg.integer.value = 1;
132
133 if (ACPI_FAILURE(acpi_evaluate_object(handle, "_EJ0",
134 &arg_list, NULL)))
135 printk(KERN_ERR "Failed to evaluate _EJ0!\n");
136}
137
138/* @ap and @dev are the same as ata_acpi_handle_hotplug() */
139static void ata_acpi_detach_device(struct ata_port *ap, struct ata_device *dev)
140{
141 if (dev)
142 dev->flags |= ATA_DFLAG_DETACH;
143 else {
144 struct ata_link *tlink;
145 struct ata_device *tdev;
146
147 ata_port_for_each_link(tlink, ap)
148 ata_link_for_each_dev(tdev, tlink)
149 tdev->flags |= ATA_DFLAG_DETACH;
150 }
151
152 ata_port_schedule_eh(ap);
153}
154
155/**
156 * ata_acpi_handle_hotplug - ACPI event handler backend
157 * @ap: ATA port ACPI event occurred
158 * @dev: ATA device ACPI event occurred (can be NULL)
159 * @event: ACPI event which occurred
160 * @is_dock_event: boolean indicating whether the event was a dock one
161 *
162 * All ACPI bay / device realted events end up in this function. If
163 * the event is port-wide @dev is NULL. If the event is specific to a
164 * device, @dev points to it.
165 *
166 * Hotplug (as opposed to unplug) notification is always handled as
167 * port-wide while unplug only kills the target device on device-wide
168 * event.
169 *
170 * LOCKING:
171 * ACPI notify handler context. May sleep.
172 */
121static void ata_acpi_handle_hotplug(struct ata_port *ap, struct ata_device *dev, 173static void ata_acpi_handle_hotplug(struct ata_port *ap, struct ata_device *dev,
122 u32 event) 174 u32 event, int is_dock_event)
123{ 175{
124 char event_string[12]; 176 char event_string[12];
125 char *envp[] = { event_string, NULL }; 177 char *envp[] = { event_string, NULL };
126 struct ata_eh_info *ehi; 178 struct ata_eh_info *ehi = &ap->link.eh_info;
127 struct kobject *kobj = NULL; 179 struct kobject *kobj = NULL;
128 int wait = 0; 180 int wait = 0;
129 unsigned long flags; 181 unsigned long flags;
182 acpi_handle handle, tmphandle;
183 unsigned long sta;
184 acpi_status status;
130 185
131 if (!ap) 186 if (dev) {
132 ap = dev->link->ap; 187 if (dev->sdev)
133 ehi = &ap->link.eh_info; 188 kobj = &dev->sdev->sdev_gendev.kobj;
189 handle = dev->acpi_handle;
190 } else {
191 kobj = &ap->dev->kobj;
192 handle = ap->acpi_handle;
193 }
194
195 status = acpi_get_handle(handle, "_EJ0", &tmphandle);
196 if (ACPI_FAILURE(status))
197 /* This device does not support hotplug */
198 return;
199
200 if (event == ACPI_NOTIFY_BUS_CHECK ||
201 event == ACPI_NOTIFY_DEVICE_CHECK)
202 status = acpi_evaluate_integer(handle, "_STA", NULL, &sta);
134 203
135 spin_lock_irqsave(ap->lock, flags); 204 spin_lock_irqsave(ap->lock, flags);
136 205
@@ -138,57 +207,79 @@ static void ata_acpi_handle_hotplug(struct ata_port *ap, struct ata_device *dev,
138 case ACPI_NOTIFY_BUS_CHECK: 207 case ACPI_NOTIFY_BUS_CHECK:
139 case ACPI_NOTIFY_DEVICE_CHECK: 208 case ACPI_NOTIFY_DEVICE_CHECK:
140 ata_ehi_push_desc(ehi, "ACPI event"); 209 ata_ehi_push_desc(ehi, "ACPI event");
141 ata_ehi_hotplugged(ehi);
142 ata_port_freeze(ap);
143 break;
144 210
211 if (ACPI_FAILURE(status)) {
212 ata_port_printk(ap, KERN_ERR,
213 "acpi: failed to determine bay status (0x%x)\n",
214 status);
215 break;
216 }
217
218 if (sta) {
219 ata_ehi_hotplugged(ehi);
220 ata_port_freeze(ap);
221 } else {
222 /* The device has gone - unplug it */
223 ata_acpi_detach_device(ap, dev);
224 wait = 1;
225 }
226 break;
145 case ACPI_NOTIFY_EJECT_REQUEST: 227 case ACPI_NOTIFY_EJECT_REQUEST:
146 ata_ehi_push_desc(ehi, "ACPI event"); 228 ata_ehi_push_desc(ehi, "ACPI event");
147 if (dev)
148 dev->flags |= ATA_DFLAG_DETACH;
149 else {
150 struct ata_link *tlink;
151 struct ata_device *tdev;
152
153 ata_port_for_each_link(tlink, ap)
154 ata_link_for_each_dev(tdev, tlink)
155 tdev->flags |= ATA_DFLAG_DETACH;
156 }
157 229
158 ata_port_schedule_eh(ap); 230 if (!is_dock_event)
231 break;
232
233 /* undock event - immediate unplug */
234 ata_acpi_detach_device(ap, dev);
159 wait = 1; 235 wait = 1;
160 break; 236 break;
161 } 237 }
162 238
163 if (dev) { 239 /* make sure kobj doesn't go away while ap->lock is released */
164 if (dev->sdev) 240 kobject_get(kobj);
165 kobj = &dev->sdev->sdev_gendev.kobj; 241
166 } else 242 spin_unlock_irqrestore(ap->lock, flags);
167 kobj = &ap->dev->kobj;
168 243
169 if (kobj) { 244 if (wait) {
245 ata_port_wait_eh(ap);
246 ata_acpi_eject_device(handle);
247 }
248
249 if (kobj && !is_dock_event) {
170 sprintf(event_string, "BAY_EVENT=%d", event); 250 sprintf(event_string, "BAY_EVENT=%d", event);
171 kobject_uevent_env(kobj, KOBJ_CHANGE, envp); 251 kobject_uevent_env(kobj, KOBJ_CHANGE, envp);
172 } 252 }
173 253
174 spin_unlock_irqrestore(ap->lock, flags); 254 kobject_put(kobj);
255}
175 256
176 if (wait) 257static void ata_acpi_dev_notify_dock(acpi_handle handle, u32 event, void *data)
177 ata_port_wait_eh(ap); 258{
259 struct ata_device *dev = data;
260
261 ata_acpi_handle_hotplug(dev->link->ap, dev, event, 1);
262}
263
264static void ata_acpi_ap_notify_dock(acpi_handle handle, u32 event, void *data)
265{
266 struct ata_port *ap = data;
267
268 ata_acpi_handle_hotplug(ap, NULL, event, 1);
178} 269}
179 270
180static void ata_acpi_dev_notify(acpi_handle handle, u32 event, void *data) 271static void ata_acpi_dev_notify(acpi_handle handle, u32 event, void *data)
181{ 272{
182 struct ata_device *dev = data; 273 struct ata_device *dev = data;
183 274
184 ata_acpi_handle_hotplug(NULL, dev, event); 275 ata_acpi_handle_hotplug(dev->link->ap, dev, event, 0);
185} 276}
186 277
187static void ata_acpi_ap_notify(acpi_handle handle, u32 event, void *data) 278static void ata_acpi_ap_notify(acpi_handle handle, u32 event, void *data)
188{ 279{
189 struct ata_port *ap = data; 280 struct ata_port *ap = data;
190 281
191 ata_acpi_handle_hotplug(ap, NULL, event); 282 ata_acpi_handle_hotplug(ap, NULL, event, 0);
192} 283}
193 284
194/** 285/**
@@ -229,7 +320,7 @@ void ata_acpi_associate(struct ata_host *host)
229 ata_acpi_ap_notify, ap); 320 ata_acpi_ap_notify, ap);
230 /* we might be on a docking station */ 321 /* we might be on a docking station */
231 register_hotplug_dock_device(ap->acpi_handle, 322 register_hotplug_dock_device(ap->acpi_handle,
232 ata_acpi_ap_notify, ap); 323 ata_acpi_ap_notify_dock, ap);
233 } 324 }
234 325
235 for (j = 0; j < ata_link_max_devices(&ap->link); j++) { 326 for (j = 0; j < ata_link_max_devices(&ap->link); j++) {
@@ -241,7 +332,7 @@ void ata_acpi_associate(struct ata_host *host)
241 ata_acpi_dev_notify, dev); 332 ata_acpi_dev_notify, dev);
242 /* we might be on a docking station */ 333 /* we might be on a docking station */
243 register_hotplug_dock_device(dev->acpi_handle, 334 register_hotplug_dock_device(dev->acpi_handle,
244 ata_acpi_dev_notify, dev); 335 ata_acpi_dev_notify_dock, dev);
245 } 336 }
246 } 337 }
247 } 338 }
@@ -604,6 +695,14 @@ static int ata_acpi_filter_tf(const struct ata_taskfile *tf,
604 return 1; 695 return 1;
605 } 696 }
606 697
698 if (ata_acpi_gtf_filter & ATA_ACPI_FILTER_DIPM) {
699 /* inhibit enabling DIPM */
700 if (tf->command == ATA_CMD_SET_FEATURES &&
701 tf->feature == SETFEATURES_SATA_ENABLE &&
702 tf->nsect == SATA_DIPM)
703 return 1;
704 }
705
607 return 0; 706 return 0;
608} 707}
609 708
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 927b692d723c..303fc0d2b978 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -2126,6 +2126,13 @@ int ata_dev_configure(struct ata_device *dev)
2126 dev->horkage |= ata_dev_blacklisted(dev); 2126 dev->horkage |= ata_dev_blacklisted(dev);
2127 ata_force_horkage(dev); 2127 ata_force_horkage(dev);
2128 2128
2129 if (dev->horkage & ATA_HORKAGE_DISABLE) {
2130 ata_dev_printk(dev, KERN_INFO,
2131 "unsupported device, disabling\n");
2132 ata_dev_disable(dev);
2133 return 0;
2134 }
2135
2129 /* let ACPI work its magic */ 2136 /* let ACPI work its magic */
2130 rc = ata_acpi_on_devcfg(dev); 2137 rc = ata_acpi_on_devcfg(dev);
2131 if (rc) 2138 if (rc)
@@ -3490,22 +3497,11 @@ int sata_link_resume(struct ata_link *link, const unsigned long *params,
3490 if ((rc = sata_link_debounce(link, params, deadline))) 3497 if ((rc = sata_link_debounce(link, params, deadline)))
3491 return rc; 3498 return rc;
3492 3499
3493 /* Clear SError. PMP and some host PHYs require this to 3500 /* clear SError, some PHYs require this even for SRST to work */
3494 * operate and clearing should be done before checking PHY
3495 * online status to avoid race condition (hotplugging between
3496 * link resume and status check).
3497 */
3498 if (!(rc = sata_scr_read(link, SCR_ERROR, &serror))) 3501 if (!(rc = sata_scr_read(link, SCR_ERROR, &serror)))
3499 rc = sata_scr_write(link, SCR_ERROR, serror); 3502 rc = sata_scr_write(link, SCR_ERROR, serror);
3500 if (rc == 0 || rc == -EINVAL) {
3501 unsigned long flags;
3502 3503
3503 spin_lock_irqsave(link->ap->lock, flags); 3504 return rc != -EINVAL ? rc : 0;
3504 link->eh_info.serror = 0;
3505 spin_unlock_irqrestore(link->ap->lock, flags);
3506 rc = 0;
3507 }
3508 return rc;
3509} 3505}
3510 3506
3511/** 3507/**
@@ -3653,9 +3649,13 @@ int sata_link_hardreset(struct ata_link *link, const unsigned long *timing,
3653 if (check_ready) 3649 if (check_ready)
3654 rc = ata_wait_ready(link, deadline, check_ready); 3650 rc = ata_wait_ready(link, deadline, check_ready);
3655 out: 3651 out:
3656 if (rc && rc != -EAGAIN) 3652 if (rc && rc != -EAGAIN) {
3653 /* online is set iff link is online && reset succeeded */
3654 if (online)
3655 *online = false;
3657 ata_link_printk(link, KERN_ERR, 3656 ata_link_printk(link, KERN_ERR,
3658 "COMRESET failed (errno=%d)\n", rc); 3657 "COMRESET failed (errno=%d)\n", rc);
3658 }
3659 DPRINTK("EXIT, rc=%d\n", rc); 3659 DPRINTK("EXIT, rc=%d\n", rc);
3660 return rc; 3660 return rc;
3661} 3661}
@@ -3700,8 +3700,14 @@ int sata_std_hardreset(struct ata_link *link, unsigned int *class,
3700 */ 3700 */
3701void ata_std_postreset(struct ata_link *link, unsigned int *classes) 3701void ata_std_postreset(struct ata_link *link, unsigned int *classes)
3702{ 3702{
3703 u32 serror;
3704
3703 DPRINTK("ENTER\n"); 3705 DPRINTK("ENTER\n");
3704 3706
3707 /* reset complete, clear SError */
3708 if (!sata_scr_read(link, SCR_ERROR, &serror))
3709 sata_scr_write(link, SCR_ERROR, serror);
3710
3705 /* print link status */ 3711 /* print link status */
3706 sata_print_link_status(link); 3712 sata_print_link_status(link);
3707 3713
@@ -3894,8 +3900,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
3894 { "SAMSUNG CD-ROM SN-124", "N001", ATA_HORKAGE_NODMA }, 3900 { "SAMSUNG CD-ROM SN-124", "N001", ATA_HORKAGE_NODMA },
3895 { "Seagate STT20000A", NULL, ATA_HORKAGE_NODMA }, 3901 { "Seagate STT20000A", NULL, ATA_HORKAGE_NODMA },
3896 /* Odd clown on sil3726/4726 PMPs */ 3902 /* Odd clown on sil3726/4726 PMPs */
3897 { "Config Disk", NULL, ATA_HORKAGE_NODMA | 3903 { "Config Disk", NULL, ATA_HORKAGE_DISABLE },
3898 ATA_HORKAGE_SKIP_PM },
3899 3904
3900 /* Weird ATAPI devices */ 3905 /* Weird ATAPI devices */
3901 { "TORiSAN DVD-ROM DRD-N216", NULL, ATA_HORKAGE_MAX_SEC_128 }, 3906 { "TORiSAN DVD-ROM DRD-N216", NULL, ATA_HORKAGE_MAX_SEC_128 },
@@ -4292,7 +4297,7 @@ void ata_sg_clean(struct ata_queued_cmd *qc)
4292} 4297}
4293 4298
4294/** 4299/**
4295 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported 4300 * atapi_check_dma - Check whether ATAPI DMA can be supported
4296 * @qc: Metadata associated with taskfile to check 4301 * @qc: Metadata associated with taskfile to check
4297 * 4302 *
4298 * Allow low-level driver to filter ATA PACKET commands, returning 4303 * Allow low-level driver to filter ATA PACKET commands, returning
@@ -4305,7 +4310,7 @@ void ata_sg_clean(struct ata_queued_cmd *qc)
4305 * RETURNS: 0 when ATAPI DMA can be used 4310 * RETURNS: 0 when ATAPI DMA can be used
4306 * nonzero otherwise 4311 * nonzero otherwise
4307 */ 4312 */
4308int ata_check_atapi_dma(struct ata_queued_cmd *qc) 4313int atapi_check_dma(struct ata_queued_cmd *qc)
4309{ 4314{
4310 struct ata_port *ap = qc->ap; 4315 struct ata_port *ap = qc->ap;
4311 4316
@@ -5398,7 +5403,7 @@ static void ata_host_stop(struct device *gendev, void *res)
5398 */ 5403 */
5399static void ata_finalize_port_ops(struct ata_port_operations *ops) 5404static void ata_finalize_port_ops(struct ata_port_operations *ops)
5400{ 5405{
5401 static spinlock_t lock = SPIN_LOCK_UNLOCKED; 5406 static DEFINE_SPINLOCK(lock);
5402 const struct ata_port_operations *cur; 5407 const struct ata_port_operations *cur;
5403 void **begin = (void **)ops; 5408 void **begin = (void **)ops;
5404 void **end = (void **)&ops->inherits; 5409 void **end = (void **)&ops->inherits;
@@ -5616,7 +5621,7 @@ int ata_host_register(struct ata_host *host, struct scsi_host_template *sht)
5616 spin_lock_irqsave(ap->lock, flags); 5621 spin_lock_irqsave(ap->lock, flags);
5617 5622
5618 ehi->probe_mask |= ATA_ALL_DEVICES; 5623 ehi->probe_mask |= ATA_ALL_DEVICES;
5619 ehi->action |= ATA_EH_RESET; 5624 ehi->action |= ATA_EH_RESET | ATA_EH_LPM;
5620 ehi->flags |= ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET; 5625 ehi->flags |= ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET;
5621 5626
5622 ap->pflags &= ~ATA_PFLAG_INITIALIZING; 5627 ap->pflags &= ~ATA_PFLAG_INITIALIZING;
@@ -5649,7 +5654,6 @@ int ata_host_register(struct ata_host *host, struct scsi_host_template *sht)
5649 struct ata_port *ap = host->ports[i]; 5654 struct ata_port *ap = host->ports[i];
5650 5655
5651 ata_scsi_scan_host(ap, 1); 5656 ata_scsi_scan_host(ap, 1);
5652 ata_lpm_schedule(ap, ap->pm_policy);
5653 } 5657 }
5654 5658
5655 return 0; 5659 return 0;
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index 62e033146bed..7894d83ea1eb 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -1308,12 +1308,7 @@ static void ata_eh_analyze_serror(struct ata_link *link)
1308 unsigned int err_mask = 0, action = 0; 1308 unsigned int err_mask = 0, action = 0;
1309 u32 hotplug_mask; 1309 u32 hotplug_mask;
1310 1310
1311 if (serror & SERR_PERSISTENT) { 1311 if (serror & (SERR_PERSISTENT | SERR_DATA)) {
1312 err_mask |= AC_ERR_ATA_BUS;
1313 action |= ATA_EH_RESET;
1314 }
1315 if (serror &
1316 (SERR_DATA_RECOVERED | SERR_COMM_RECOVERED | SERR_DATA)) {
1317 err_mask |= AC_ERR_ATA_BUS; 1312 err_mask |= AC_ERR_ATA_BUS;
1318 action |= ATA_EH_RESET; 1313 action |= ATA_EH_RESET;
1319 } 1314 }
@@ -2047,19 +2042,11 @@ static int ata_do_reset(struct ata_link *link, ata_reset_fn_t reset,
2047 unsigned int *classes, unsigned long deadline) 2042 unsigned int *classes, unsigned long deadline)
2048{ 2043{
2049 struct ata_device *dev; 2044 struct ata_device *dev;
2050 int rc;
2051 2045
2052 ata_link_for_each_dev(dev, link) 2046 ata_link_for_each_dev(dev, link)
2053 classes[dev->devno] = ATA_DEV_UNKNOWN; 2047 classes[dev->devno] = ATA_DEV_UNKNOWN;
2054 2048
2055 rc = reset(link, classes, deadline); 2049 return reset(link, classes, deadline);
2056
2057 /* convert all ATA_DEV_UNKNOWN to ATA_DEV_NONE */
2058 ata_link_for_each_dev(dev, link)
2059 if (classes[dev->devno] == ATA_DEV_UNKNOWN)
2060 classes[dev->devno] = ATA_DEV_NONE;
2061
2062 return rc;
2063} 2050}
2064 2051
2065static int ata_eh_followup_srst_needed(struct ata_link *link, 2052static int ata_eh_followup_srst_needed(struct ata_link *link,
@@ -2096,9 +2083,11 @@ int ata_eh_reset(struct ata_link *link, int classify,
2096 ata_reset_fn_t reset; 2083 ata_reset_fn_t reset;
2097 unsigned long flags; 2084 unsigned long flags;
2098 u32 sstatus; 2085 u32 sstatus;
2099 int rc; 2086 int nr_known, rc;
2100 2087
2101 /* about to reset */ 2088 /*
2089 * Prepare to reset
2090 */
2102 spin_lock_irqsave(ap->lock, flags); 2091 spin_lock_irqsave(ap->lock, flags);
2103 ap->pflags |= ATA_PFLAG_RESETTING; 2092 ap->pflags |= ATA_PFLAG_RESETTING;
2104 spin_unlock_irqrestore(ap->lock, flags); 2093 spin_unlock_irqrestore(ap->lock, flags);
@@ -2124,16 +2113,8 @@ int ata_eh_reset(struct ata_link *link, int classify,
2124 ap->ops->set_piomode(ap, dev); 2113 ap->ops->set_piomode(ap, dev);
2125 } 2114 }
2126 2115
2127 if (!softreset && !hardreset) {
2128 if (verbose)
2129 ata_link_printk(link, KERN_INFO, "no reset method "
2130 "available, skipping reset\n");
2131 if (!(lflags & ATA_LFLAG_ASSUME_CLASS))
2132 lflags |= ATA_LFLAG_ASSUME_ATA;
2133 goto done;
2134 }
2135
2136 /* prefer hardreset */ 2116 /* prefer hardreset */
2117 reset = NULL;
2137 ehc->i.action &= ~ATA_EH_RESET; 2118 ehc->i.action &= ~ATA_EH_RESET;
2138 if (hardreset) { 2119 if (hardreset) {
2139 reset = hardreset; 2120 reset = hardreset;
@@ -2141,11 +2122,6 @@ int ata_eh_reset(struct ata_link *link, int classify,
2141 } else if (softreset) { 2122 } else if (softreset) {
2142 reset = softreset; 2123 reset = softreset;
2143 ehc->i.action = ATA_EH_SOFTRESET; 2124 ehc->i.action = ATA_EH_SOFTRESET;
2144 } else {
2145 ata_link_printk(link, KERN_ERR, "BUG: no reset method, "
2146 "please report to linux-ide@vger.kernel.org\n");
2147 dump_stack();
2148 return -EINVAL;
2149 } 2125 }
2150 2126
2151 if (prereset) { 2127 if (prereset) {
@@ -2165,55 +2141,71 @@ int ata_eh_reset(struct ata_link *link, int classify,
2165 "prereset failed (errno=%d)\n", rc); 2141 "prereset failed (errno=%d)\n", rc);
2166 goto out; 2142 goto out;
2167 } 2143 }
2168 }
2169 2144
2170 /* prereset() might have cleared ATA_EH_RESET */ 2145 /* prereset() might have cleared ATA_EH_RESET. If so,
2171 if (!(ehc->i.action & ATA_EH_RESET)) { 2146 * bang classes and return.
2172 /* prereset told us not to reset, bang classes and return */ 2147 */
2173 ata_link_for_each_dev(dev, link) 2148 if (reset && !(ehc->i.action & ATA_EH_RESET)) {
2174 classes[dev->devno] = ATA_DEV_NONE; 2149 ata_link_for_each_dev(dev, link)
2175 rc = 0; 2150 classes[dev->devno] = ATA_DEV_NONE;
2176 goto out; 2151 rc = 0;
2152 goto out;
2153 }
2177 } 2154 }
2178 2155
2179 retry: 2156 retry:
2157 /*
2158 * Perform reset
2159 */
2160 if (ata_is_host_link(link))
2161 ata_eh_freeze_port(ap);
2162
2180 deadline = jiffies + ata_eh_reset_timeouts[try++]; 2163 deadline = jiffies + ata_eh_reset_timeouts[try++];
2181 2164
2182 /* shut up during boot probing */ 2165 if (reset) {
2183 if (verbose) 2166 if (verbose)
2184 ata_link_printk(link, KERN_INFO, "%s resetting link\n", 2167 ata_link_printk(link, KERN_INFO, "%s resetting link\n",
2185 reset == softreset ? "soft" : "hard"); 2168 reset == softreset ? "soft" : "hard");
2186 2169
2187 /* mark that this EH session started with reset */ 2170 /* mark that this EH session started with reset */
2188 if (reset == hardreset) 2171 if (reset == hardreset)
2189 ehc->i.flags |= ATA_EHI_DID_HARDRESET; 2172 ehc->i.flags |= ATA_EHI_DID_HARDRESET;
2190 else 2173 else
2191 ehc->i.flags |= ATA_EHI_DID_SOFTRESET; 2174 ehc->i.flags |= ATA_EHI_DID_SOFTRESET;
2192 2175
2193 rc = ata_do_reset(link, reset, classes, deadline); 2176 rc = ata_do_reset(link, reset, classes, deadline);
2194 2177
2195 if (reset == hardreset && 2178 if (reset == hardreset &&
2196 ata_eh_followup_srst_needed(link, rc, classify, classes)) { 2179 ata_eh_followup_srst_needed(link, rc, classify, classes)) {
2197 /* okay, let's do follow-up softreset */ 2180 /* okay, let's do follow-up softreset */
2198 reset = softreset; 2181 reset = softreset;
2199 2182
2200 if (!reset) { 2183 if (!reset) {
2201 ata_link_printk(link, KERN_ERR, 2184 ata_link_printk(link, KERN_ERR,
2202 "follow-up softreset required " 2185 "follow-up softreset required "
2203 "but no softreset avaliable\n"); 2186 "but no softreset avaliable\n");
2204 rc = -EINVAL; 2187 rc = -EINVAL;
2205 goto fail; 2188 goto fail;
2189 }
2190
2191 ata_eh_about_to_do(link, NULL, ATA_EH_RESET);
2192 rc = ata_do_reset(link, reset, classes, deadline);
2206 } 2193 }
2207 2194
2208 ata_eh_about_to_do(link, NULL, ATA_EH_RESET); 2195 /* -EAGAIN can happen if we skipped followup SRST */
2209 rc = ata_do_reset(link, reset, classes, deadline); 2196 if (rc && rc != -EAGAIN)
2197 goto fail;
2198 } else {
2199 if (verbose)
2200 ata_link_printk(link, KERN_INFO, "no reset method "
2201 "available, skipping reset\n");
2202 if (!(lflags & ATA_LFLAG_ASSUME_CLASS))
2203 lflags |= ATA_LFLAG_ASSUME_ATA;
2210 } 2204 }
2211 2205
2212 /* -EAGAIN can happen if we skipped followup SRST */ 2206 /*
2213 if (rc && rc != -EAGAIN) 2207 * Post-reset processing
2214 goto fail; 2208 */
2215
2216 done:
2217 ata_link_for_each_dev(dev, link) { 2209 ata_link_for_each_dev(dev, link) {
2218 /* After the reset, the device state is PIO 0 and the 2210 /* After the reset, the device state is PIO 0 and the
2219 * controller state is undefined. Reset also wakes up 2211 * controller state is undefined. Reset also wakes up
@@ -2236,9 +2228,53 @@ int ata_eh_reset(struct ata_link *link, int classify,
2236 if (sata_scr_read(link, SCR_STATUS, &sstatus) == 0) 2228 if (sata_scr_read(link, SCR_STATUS, &sstatus) == 0)
2237 link->sata_spd = (sstatus >> 4) & 0xf; 2229 link->sata_spd = (sstatus >> 4) & 0xf;
2238 2230
2231 /* thaw the port */
2232 if (ata_is_host_link(link))
2233 ata_eh_thaw_port(ap);
2234
2235 /* postreset() should clear hardware SError. Although SError
2236 * is cleared during link resume, clearing SError here is
2237 * necessary as some PHYs raise hotplug events after SRST.
2238 * This introduces race condition where hotplug occurs between
2239 * reset and here. This race is mediated by cross checking
2240 * link onlineness and classification result later.
2241 */
2239 if (postreset) 2242 if (postreset)
2240 postreset(link, classes); 2243 postreset(link, classes);
2241 2244
2245 /* clear cached SError */
2246 spin_lock_irqsave(link->ap->lock, flags);
2247 link->eh_info.serror = 0;
2248 spin_unlock_irqrestore(link->ap->lock, flags);
2249
2250 /* Make sure onlineness and classification result correspond.
2251 * Hotplug could have happened during reset and some
2252 * controllers fail to wait while a drive is spinning up after
2253 * being hotplugged causing misdetection. By cross checking
2254 * link onlineness and classification result, those conditions
2255 * can be reliably detected and retried.
2256 */
2257 nr_known = 0;
2258 ata_link_for_each_dev(dev, link) {
2259 /* convert all ATA_DEV_UNKNOWN to ATA_DEV_NONE */
2260 if (classes[dev->devno] == ATA_DEV_UNKNOWN)
2261 classes[dev->devno] = ATA_DEV_NONE;
2262 else
2263 nr_known++;
2264 }
2265
2266 if (classify && !nr_known && ata_link_online(link)) {
2267 if (try < max_tries) {
2268 ata_link_printk(link, KERN_WARNING, "link online but "
2269 "device misclassified, retrying\n");
2270 rc = -EAGAIN;
2271 goto fail;
2272 }
2273 ata_link_printk(link, KERN_WARNING,
2274 "link online but device misclassified, "
2275 "device detection might fail\n");
2276 }
2277
2242 /* reset successful, schedule revalidation */ 2278 /* reset successful, schedule revalidation */
2243 ata_eh_done(link, NULL, ATA_EH_RESET); 2279 ata_eh_done(link, NULL, ATA_EH_RESET);
2244 ehc->i.action |= ATA_EH_REVALIDATE; 2280 ehc->i.action |= ATA_EH_REVALIDATE;
@@ -2587,7 +2623,7 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
2587 struct ata_link *link; 2623 struct ata_link *link;
2588 struct ata_device *dev; 2624 struct ata_device *dev;
2589 int nr_failed_devs, nr_disabled_devs; 2625 int nr_failed_devs, nr_disabled_devs;
2590 int reset, rc; 2626 int rc;
2591 unsigned long flags; 2627 unsigned long flags;
2592 2628
2593 DPRINTK("ENTER\n"); 2629 DPRINTK("ENTER\n");
@@ -2630,7 +2666,6 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
2630 rc = 0; 2666 rc = 0;
2631 nr_failed_devs = 0; 2667 nr_failed_devs = 0;
2632 nr_disabled_devs = 0; 2668 nr_disabled_devs = 0;
2633 reset = 0;
2634 2669
2635 /* if UNLOADING, finish immediately */ 2670 /* if UNLOADING, finish immediately */
2636 if (ap->pflags & ATA_PFLAG_UNLOADING) 2671 if (ap->pflags & ATA_PFLAG_UNLOADING)
@@ -2644,40 +2679,24 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
2644 if (ata_eh_skip_recovery(link)) 2679 if (ata_eh_skip_recovery(link))
2645 ehc->i.action = 0; 2680 ehc->i.action = 0;
2646 2681
2647 /* do we need to reset? */
2648 if (ehc->i.action & ATA_EH_RESET)
2649 reset = 1;
2650
2651 ata_link_for_each_dev(dev, link) 2682 ata_link_for_each_dev(dev, link)
2652 ehc->classes[dev->devno] = ATA_DEV_UNKNOWN; 2683 ehc->classes[dev->devno] = ATA_DEV_UNKNOWN;
2653 } 2684 }
2654 2685
2655 /* reset */ 2686 /* reset */
2656 if (reset) { 2687 ata_port_for_each_link(link, ap) {
2657 /* if PMP is attached, this function only deals with 2688 struct ata_eh_context *ehc = &link->eh_context;
2658 * downstream links, port should stay thawed.
2659 */
2660 if (!sata_pmp_attached(ap))
2661 ata_eh_freeze_port(ap);
2662
2663 ata_port_for_each_link(link, ap) {
2664 struct ata_eh_context *ehc = &link->eh_context;
2665 2689
2666 if (!(ehc->i.action & ATA_EH_RESET)) 2690 if (!(ehc->i.action & ATA_EH_RESET))
2667 continue; 2691 continue;
2668 2692
2669 rc = ata_eh_reset(link, ata_link_nr_vacant(link), 2693 rc = ata_eh_reset(link, ata_link_nr_vacant(link),
2670 prereset, softreset, hardreset, 2694 prereset, softreset, hardreset, postreset);
2671 postreset); 2695 if (rc) {
2672 if (rc) { 2696 ata_link_printk(link, KERN_ERR,
2673 ata_link_printk(link, KERN_ERR, 2697 "reset failed, giving up\n");
2674 "reset failed, giving up\n"); 2698 goto out;
2675 goto out;
2676 }
2677 } 2699 }
2678
2679 if (!sata_pmp_attached(ap))
2680 ata_eh_thaw_port(ap);
2681 } 2700 }
2682 2701
2683 /* the rest */ 2702 /* the rest */
diff --git a/drivers/ata/libata-pmp.c b/drivers/ata/libata-pmp.c
index ff1822a7da38..7daf4c0f6216 100644
--- a/drivers/ata/libata-pmp.c
+++ b/drivers/ata/libata-pmp.c
@@ -48,7 +48,7 @@ static unsigned int sata_pmp_read(struct ata_link *link, int reg, u32 *r_val)
48 tf.device = link->pmp; 48 tf.device = link->pmp;
49 49
50 err_mask = ata_exec_internal(pmp_dev, &tf, NULL, DMA_NONE, NULL, 0, 50 err_mask = ata_exec_internal(pmp_dev, &tf, NULL, DMA_NONE, NULL, 0,
51 SATA_PMP_SCR_TIMEOUT); 51 SATA_PMP_RW_TIMEOUT);
52 if (err_mask) 52 if (err_mask)
53 return err_mask; 53 return err_mask;
54 54
@@ -88,7 +88,7 @@ static unsigned int sata_pmp_write(struct ata_link *link, int reg, u32 val)
88 tf.lbah = (val >> 24) & 0xff; 88 tf.lbah = (val >> 24) & 0xff;
89 89
90 return ata_exec_internal(pmp_dev, &tf, NULL, DMA_NONE, NULL, 0, 90 return ata_exec_internal(pmp_dev, &tf, NULL, DMA_NONE, NULL, 0,
91 SATA_PMP_SCR_TIMEOUT); 91 SATA_PMP_RW_TIMEOUT);
92} 92}
93 93
94/** 94/**
@@ -257,19 +257,6 @@ static int sata_pmp_configure(struct ata_device *dev, int print_info)
257 goto fail; 257 goto fail;
258 } 258 }
259 259
260 /* turn off notification till fan-out ports are reset and configured */
261 if (gscr[SATA_PMP_GSCR_FEAT_EN] & SATA_PMP_FEAT_NOTIFY) {
262 gscr[SATA_PMP_GSCR_FEAT_EN] &= ~SATA_PMP_FEAT_NOTIFY;
263
264 err_mask = sata_pmp_write(dev->link, SATA_PMP_GSCR_FEAT_EN,
265 gscr[SATA_PMP_GSCR_FEAT_EN]);
266 if (err_mask) {
267 rc = -EIO;
268 reason = "failed to write GSCR_FEAT_EN";
269 goto fail;
270 }
271 }
272
273 if (print_info) { 260 if (print_info) {
274 ata_dev_printk(dev, KERN_INFO, "Port Multiplier %s, " 261 ata_dev_printk(dev, KERN_INFO, "Port Multiplier %s, "
275 "0x%04x:0x%04x r%d, %d ports, feat 0x%x/0x%x\n", 262 "0x%04x:0x%04x r%d, %d ports, feat 0x%x/0x%x\n",
@@ -335,9 +322,12 @@ static void sata_pmp_quirks(struct ata_port *ap)
335 if (vendor == 0x1095 && devid == 0x3726) { 322 if (vendor == 0x1095 && devid == 0x3726) {
336 /* sil3726 quirks */ 323 /* sil3726 quirks */
337 ata_port_for_each_link(link, ap) { 324 ata_port_for_each_link(link, ap) {
338 /* class code report is unreliable */ 325 /* Class code report is unreliable and SRST
326 * times out under certain configurations.
327 */
339 if (link->pmp < 5) 328 if (link->pmp < 5)
340 link->flags |= ATA_LFLAG_ASSUME_ATA; 329 link->flags |= ATA_LFLAG_NO_SRST |
330 ATA_LFLAG_ASSUME_ATA;
341 331
342 /* port 5 is for SEMB device and it doesn't like SRST */ 332 /* port 5 is for SEMB device and it doesn't like SRST */
343 if (link->pmp == 5) 333 if (link->pmp == 5)
@@ -700,8 +690,6 @@ static int sata_pmp_eh_recover_pmp(struct ata_port *ap,
700 if (ehc->i.action & ATA_EH_RESET) { 690 if (ehc->i.action & ATA_EH_RESET) {
701 struct ata_link *tlink; 691 struct ata_link *tlink;
702 692
703 ata_eh_freeze_port(ap);
704
705 /* reset */ 693 /* reset */
706 rc = ata_eh_reset(link, 0, prereset, softreset, hardreset, 694 rc = ata_eh_reset(link, 0, prereset, softreset, hardreset,
707 postreset); 695 postreset);
@@ -711,8 +699,6 @@ static int sata_pmp_eh_recover_pmp(struct ata_port *ap,
711 goto fail; 699 goto fail;
712 } 700 }
713 701
714 ata_eh_thaw_port(ap);
715
716 /* PMP is reset, SErrors cannot be trusted, scan all */ 702 /* PMP is reset, SErrors cannot be trusted, scan all */
717 ata_port_for_each_link(tlink, ap) { 703 ata_port_for_each_link(tlink, ap) {
718 struct ata_eh_context *ehc = &tlink->eh_context; 704 struct ata_eh_context *ehc = &tlink->eh_context;
@@ -864,6 +850,7 @@ static int sata_pmp_eh_recover(struct ata_port *ap)
864 struct ata_link *pmp_link = &ap->link; 850 struct ata_link *pmp_link = &ap->link;
865 struct ata_device *pmp_dev = pmp_link->device; 851 struct ata_device *pmp_dev = pmp_link->device;
866 struct ata_eh_context *pmp_ehc = &pmp_link->eh_context; 852 struct ata_eh_context *pmp_ehc = &pmp_link->eh_context;
853 u32 *gscr = pmp_dev->gscr;
867 struct ata_link *link; 854 struct ata_link *link;
868 struct ata_device *dev; 855 struct ata_device *dev;
869 unsigned int err_mask; 856 unsigned int err_mask;
@@ -901,6 +888,22 @@ static int sata_pmp_eh_recover(struct ata_port *ap)
901 if (rc) 888 if (rc)
902 goto pmp_fail; 889 goto pmp_fail;
903 890
891 /* PHY event notification can disturb reset and other recovery
892 * operations. Turn it off.
893 */
894 if (gscr[SATA_PMP_GSCR_FEAT_EN] & SATA_PMP_FEAT_NOTIFY) {
895 gscr[SATA_PMP_GSCR_FEAT_EN] &= ~SATA_PMP_FEAT_NOTIFY;
896
897 err_mask = sata_pmp_write(pmp_link, SATA_PMP_GSCR_FEAT_EN,
898 gscr[SATA_PMP_GSCR_FEAT_EN]);
899 if (err_mask) {
900 ata_link_printk(pmp_link, KERN_WARNING,
901 "failed to disable NOTIFY (err_mask=0x%x)\n",
902 err_mask);
903 goto pmp_fail;
904 }
905 }
906
904 /* handle disabled links */ 907 /* handle disabled links */
905 rc = sata_pmp_eh_handle_disabled_links(ap); 908 rc = sata_pmp_eh_handle_disabled_links(ap);
906 if (rc) 909 if (rc)
@@ -923,10 +926,10 @@ static int sata_pmp_eh_recover(struct ata_port *ap)
923 926
924 /* enable notification */ 927 /* enable notification */
925 if (pmp_dev->flags & ATA_DFLAG_AN) { 928 if (pmp_dev->flags & ATA_DFLAG_AN) {
926 pmp_dev->gscr[SATA_PMP_GSCR_FEAT_EN] |= SATA_PMP_FEAT_NOTIFY; 929 gscr[SATA_PMP_GSCR_FEAT_EN] |= SATA_PMP_FEAT_NOTIFY;
927 930
928 err_mask = sata_pmp_write(pmp_dev->link, SATA_PMP_GSCR_FEAT_EN, 931 err_mask = sata_pmp_write(pmp_link, SATA_PMP_GSCR_FEAT_EN,
929 pmp_dev->gscr[SATA_PMP_GSCR_FEAT_EN]); 932 gscr[SATA_PMP_GSCR_FEAT_EN]);
930 if (err_mask) { 933 if (err_mask) {
931 ata_dev_printk(pmp_dev, KERN_ERR, "failed to write " 934 ata_dev_printk(pmp_dev, KERN_ERR, "failed to write "
932 "PMP_FEAT_EN (Emask=0x%x)\n", err_mask); 935 "PMP_FEAT_EN (Emask=0x%x)\n", err_mask);
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index 3ce43920e459..57a43649a461 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -1082,12 +1082,6 @@ static unsigned int ata_scsi_start_stop_xlat(struct ata_queued_cmd *qc)
1082 if (((cdb[4] >> 4) & 0xf) != 0) 1082 if (((cdb[4] >> 4) & 0xf) != 0)
1083 goto invalid_fld; /* power conditions not supported */ 1083 goto invalid_fld; /* power conditions not supported */
1084 1084
1085 if (qc->dev->horkage & ATA_HORKAGE_SKIP_PM) {
1086 /* the device lacks PM support, finish without doing anything */
1087 scmd->result = SAM_STAT_GOOD;
1088 return 1;
1089 }
1090
1091 if (cdb[4] & 0x1) { 1085 if (cdb[4] & 0x1) {
1092 tf->nsect = 1; /* 1 sector, lba=0 */ 1086 tf->nsect = 1; /* 1 sector, lba=0 */
1093 1087
@@ -1643,6 +1637,7 @@ defer:
1643 1637
1644/** 1638/**
1645 * ata_scsi_rbuf_get - Map response buffer. 1639 * ata_scsi_rbuf_get - Map response buffer.
1640 * @cmd: SCSI command containing buffer to be mapped.
1646 * @flags: unsigned long variable to store irq enable status 1641 * @flags: unsigned long variable to store irq enable status
1647 * @copy_in: copy in from user buffer 1642 * @copy_in: copy in from user buffer
1648 * 1643 *
@@ -1960,7 +1955,7 @@ static unsigned int ata_msense_ctl_mode(u8 *buf)
1960 1955
1961/** 1956/**
1962 * ata_msense_rw_recovery - Simulate MODE SENSE r/w error recovery page 1957 * ata_msense_rw_recovery - Simulate MODE SENSE r/w error recovery page
1963 * @bufp: output buffer 1958 * @buf: output buffer
1964 * 1959 *
1965 * Generate a generic MODE SENSE r/w error recovery page. 1960 * Generate a generic MODE SENSE r/w error recovery page.
1966 * 1961 *
@@ -2348,8 +2343,8 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
2348{ 2343{
2349 struct scsi_cmnd *scmd = qc->scsicmd; 2344 struct scsi_cmnd *scmd = qc->scsicmd;
2350 struct ata_device *dev = qc->dev; 2345 struct ata_device *dev = qc->dev;
2351 int using_pio = (dev->flags & ATA_DFLAG_PIO);
2352 int nodata = (scmd->sc_data_direction == DMA_NONE); 2346 int nodata = (scmd->sc_data_direction == DMA_NONE);
2347 int using_pio = !nodata && (dev->flags & ATA_DFLAG_PIO);
2353 unsigned int nbytes; 2348 unsigned int nbytes;
2354 2349
2355 memset(qc->cdb, 0, dev->cdb_len); 2350 memset(qc->cdb, 0, dev->cdb_len);
@@ -2367,7 +2362,7 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
2367 ata_qc_set_pc_nbytes(qc); 2362 ata_qc_set_pc_nbytes(qc);
2368 2363
2369 /* check whether ATAPI DMA is safe */ 2364 /* check whether ATAPI DMA is safe */
2370 if (!using_pio && ata_check_atapi_dma(qc)) 2365 if (!nodata && !using_pio && atapi_check_dma(qc))
2371 using_pio = 1; 2366 using_pio = 1;
2372 2367
2373 /* Some controller variants snoop this value for Packet 2368 /* Some controller variants snoop this value for Packet
@@ -2407,13 +2402,11 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
2407 qc->tf.lbam = (nbytes & 0xFF); 2402 qc->tf.lbam = (nbytes & 0xFF);
2408 qc->tf.lbah = (nbytes >> 8); 2403 qc->tf.lbah = (nbytes >> 8);
2409 2404
2410 if (using_pio || nodata) { 2405 if (nodata)
2411 /* no data, or PIO data xfer */ 2406 qc->tf.protocol = ATAPI_PROT_NODATA;
2412 if (nodata) 2407 else if (using_pio)
2413 qc->tf.protocol = ATAPI_PROT_NODATA; 2408 qc->tf.protocol = ATAPI_PROT_PIO;
2414 else 2409 else {
2415 qc->tf.protocol = ATAPI_PROT_PIO;
2416 } else {
2417 /* DMA data xfer */ 2410 /* DMA data xfer */
2418 qc->tf.protocol = ATAPI_PROT_DMA; 2411 qc->tf.protocol = ATAPI_PROT_DMA;
2419 qc->tf.feature |= ATAPI_PKT_DMA; 2412 qc->tf.feature |= ATAPI_PKT_DMA;
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c
index 3c2d2289f85e..c0908c225483 100644
--- a/drivers/ata/libata-sff.c
+++ b/drivers/ata/libata-sff.c
@@ -247,7 +247,7 @@ u8 ata_sff_check_status(struct ata_port *ap)
247 * LOCKING: 247 * LOCKING:
248 * Inherited from caller. 248 * Inherited from caller.
249 */ 249 */
250u8 ata_sff_altstatus(struct ata_port *ap) 250static u8 ata_sff_altstatus(struct ata_port *ap)
251{ 251{
252 if (ap->ops->sff_check_altstatus) 252 if (ap->ops->sff_check_altstatus)
253 return ap->ops->sff_check_altstatus(ap); 253 return ap->ops->sff_check_altstatus(ap);
@@ -256,6 +256,93 @@ u8 ata_sff_altstatus(struct ata_port *ap)
256} 256}
257 257
258/** 258/**
259 * ata_sff_irq_status - Check if the device is busy
260 * @ap: port where the device is
261 *
262 * Determine if the port is currently busy. Uses altstatus
263 * if available in order to avoid clearing shared IRQ status
264 * when finding an IRQ source. Non ctl capable devices don't
265 * share interrupt lines fortunately for us.
266 *
267 * LOCKING:
268 * Inherited from caller.
269 */
270static u8 ata_sff_irq_status(struct ata_port *ap)
271{
272 u8 status;
273
274 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
275 status = ata_sff_altstatus(ap);
276 /* Not us: We are busy */
277 if (status & ATA_BUSY)
278 return status;
279 }
280 /* Clear INTRQ latch */
281 status = ap->ops->sff_check_status(ap);
282 return status;
283}
284
285/**
286 * ata_sff_sync - Flush writes
287 * @ap: Port to wait for.
288 *
289 * CAUTION:
290 * If we have an mmio device with no ctl and no altstatus
291 * method this will fail. No such devices are known to exist.
292 *
293 * LOCKING:
294 * Inherited from caller.
295 */
296
297static void ata_sff_sync(struct ata_port *ap)
298{
299 if (ap->ops->sff_check_altstatus)
300 ap->ops->sff_check_altstatus(ap);
301 else if (ap->ioaddr.altstatus_addr)
302 ioread8(ap->ioaddr.altstatus_addr);
303}
304
305/**
306 * ata_sff_pause - Flush writes and wait 400nS
307 * @ap: Port to pause for.
308 *
309 * CAUTION:
310 * If we have an mmio device with no ctl and no altstatus
311 * method this will fail. No such devices are known to exist.
312 *
313 * LOCKING:
314 * Inherited from caller.
315 */
316
317void ata_sff_pause(struct ata_port *ap)
318{
319 ata_sff_sync(ap);
320 ndelay(400);
321}
322
323/**
324 * ata_sff_dma_pause - Pause before commencing DMA
325 * @ap: Port to pause for.
326 *
327 * Perform I/O fencing and ensure sufficient cycle delays occur
328 * for the HDMA1:0 transition
329 */
330
331void ata_sff_dma_pause(struct ata_port *ap)
332{
333 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
334 /* An altstatus read will cause the needed delay without
335 messing up the IRQ status */
336 ata_sff_altstatus(ap);
337 return;
338 }
339 /* There are no DMA controllers without ctl. BUG here to ensure
340 we never violate the HDMA1:0 transition timing and risk
341 corruption. */
342 BUG();
343}
344
345/**
259 * ata_sff_busy_sleep - sleep until BSY clears, or timeout 346 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
260 * @ap: port containing status register to be polled 347 * @ap: port containing status register to be polled
261 * @tmout_pat: impatience timeout 348 * @tmout_pat: impatience timeout
@@ -742,7 +829,7 @@ static void ata_pio_sectors(struct ata_queued_cmd *qc)
742 } else 829 } else
743 ata_pio_sector(qc); 830 ata_pio_sector(qc);
744 831
745 ata_sff_altstatus(qc->ap); /* flush */ 832 ata_sff_sync(qc->ap); /* flush */
746} 833}
747 834
748/** 835/**
@@ -763,8 +850,9 @@ static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
763 WARN_ON(qc->dev->cdb_len < 12); 850 WARN_ON(qc->dev->cdb_len < 12);
764 851
765 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1); 852 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
766 ata_sff_altstatus(ap); /* flush */ 853 ata_sff_sync(ap);
767 854 /* FIXME: If the CDB is for DMA do we need to do the transition delay
855 or is bmdma_start guaranteed to do it ? */
768 switch (qc->tf.protocol) { 856 switch (qc->tf.protocol) {
769 case ATAPI_PROT_PIO: 857 case ATAPI_PROT_PIO:
770 ap->hsm_task_state = HSM_ST; 858 ap->hsm_task_state = HSM_ST;
@@ -905,7 +993,7 @@ static void atapi_pio_bytes(struct ata_queued_cmd *qc)
905 993
906 if (unlikely(__atapi_pio_bytes(qc, bytes))) 994 if (unlikely(__atapi_pio_bytes(qc, bytes)))
907 goto err_out; 995 goto err_out;
908 ata_sff_altstatus(ap); /* flush */ 996 ata_sff_sync(ap); /* flush */
909 997
910 return; 998 return;
911 999
@@ -1006,6 +1094,7 @@ static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
1006int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, 1094int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1007 u8 status, int in_wq) 1095 u8 status, int in_wq)
1008{ 1096{
1097 struct ata_eh_info *ehi = &ap->link.eh_info;
1009 unsigned long flags = 0; 1098 unsigned long flags = 0;
1010 int poll_next; 1099 int poll_next;
1011 1100
@@ -1037,9 +1126,12 @@ fsm_start:
1037 if (likely(status & (ATA_ERR | ATA_DF))) 1126 if (likely(status & (ATA_ERR | ATA_DF)))
1038 /* device stops HSM for abort/error */ 1127 /* device stops HSM for abort/error */
1039 qc->err_mask |= AC_ERR_DEV; 1128 qc->err_mask |= AC_ERR_DEV;
1040 else 1129 else {
1041 /* HSM violation. Let EH handle this */ 1130 /* HSM violation. Let EH handle this */
1131 ata_ehi_push_desc(ehi,
1132 "ST_FIRST: !(DRQ|ERR|DF)");
1042 qc->err_mask |= AC_ERR_HSM; 1133 qc->err_mask |= AC_ERR_HSM;
1134 }
1043 1135
1044 ap->hsm_task_state = HSM_ST_ERR; 1136 ap->hsm_task_state = HSM_ST_ERR;
1045 goto fsm_start; 1137 goto fsm_start;
@@ -1058,9 +1150,9 @@ fsm_start:
1058 * the CDB. 1150 * the CDB.
1059 */ 1151 */
1060 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { 1152 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1061 ata_port_printk(ap, KERN_WARNING, 1153 ata_ehi_push_desc(ehi, "ST_FIRST: "
1062 "DRQ=1 with device error, " 1154 "DRQ=1 with device error, "
1063 "dev_stat 0x%X\n", status); 1155 "dev_stat 0x%X", status);
1064 qc->err_mask |= AC_ERR_HSM; 1156 qc->err_mask |= AC_ERR_HSM;
1065 ap->hsm_task_state = HSM_ST_ERR; 1157 ap->hsm_task_state = HSM_ST_ERR;
1066 goto fsm_start; 1158 goto fsm_start;
@@ -1117,9 +1209,9 @@ fsm_start:
1117 * let the EH abort the command or reset the device. 1209 * let the EH abort the command or reset the device.
1118 */ 1210 */
1119 if (unlikely(status & (ATA_ERR | ATA_DF))) { 1211 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1120 ata_port_printk(ap, KERN_WARNING, "DRQ=1 with " 1212 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1121 "device error, dev_stat 0x%X\n", 1213 "DRQ=1 with device error, "
1122 status); 1214 "dev_stat 0x%X", status);
1123 qc->err_mask |= AC_ERR_HSM; 1215 qc->err_mask |= AC_ERR_HSM;
1124 ap->hsm_task_state = HSM_ST_ERR; 1216 ap->hsm_task_state = HSM_ST_ERR;
1125 goto fsm_start; 1217 goto fsm_start;
@@ -1138,13 +1230,17 @@ fsm_start:
1138 if (likely(status & (ATA_ERR | ATA_DF))) 1230 if (likely(status & (ATA_ERR | ATA_DF)))
1139 /* device stops HSM for abort/error */ 1231 /* device stops HSM for abort/error */
1140 qc->err_mask |= AC_ERR_DEV; 1232 qc->err_mask |= AC_ERR_DEV;
1141 else 1233 else {
1142 /* HSM violation. Let EH handle this. 1234 /* HSM violation. Let EH handle this.
1143 * Phantom devices also trigger this 1235 * Phantom devices also trigger this
1144 * condition. Mark hint. 1236 * condition. Mark hint.
1145 */ 1237 */
1238 ata_ehi_push_desc(ehi, "ST-ATA: "
1239 "DRQ=1 with device error, "
1240 "dev_stat 0x%X", status);
1146 qc->err_mask |= AC_ERR_HSM | 1241 qc->err_mask |= AC_ERR_HSM |
1147 AC_ERR_NODEV_HINT; 1242 AC_ERR_NODEV_HINT;
1243 }
1148 1244
1149 ap->hsm_task_state = HSM_ST_ERR; 1245 ap->hsm_task_state = HSM_ST_ERR;
1150 goto fsm_start; 1246 goto fsm_start;
@@ -1169,8 +1265,12 @@ fsm_start:
1169 status = ata_wait_idle(ap); 1265 status = ata_wait_idle(ap);
1170 } 1266 }
1171 1267
1172 if (status & (ATA_BUSY | ATA_DRQ)) 1268 if (status & (ATA_BUSY | ATA_DRQ)) {
1269 ata_ehi_push_desc(ehi, "ST-ATA: "
1270 "BUSY|DRQ persists on ERR|DF, "
1271 "dev_stat 0x%X", status);
1173 qc->err_mask |= AC_ERR_HSM; 1272 qc->err_mask |= AC_ERR_HSM;
1273 }
1174 1274
1175 /* ata_pio_sectors() might change the 1275 /* ata_pio_sectors() might change the
1176 * state to HSM_ST_LAST. so, the state 1276 * state to HSM_ST_LAST. so, the state
@@ -1489,14 +1589,10 @@ inline unsigned int ata_sff_host_intr(struct ata_port *ap,
1489 goto idle_irq; 1589 goto idle_irq;
1490 } 1590 }
1491 1591
1492 /* check altstatus */
1493 status = ata_sff_altstatus(ap);
1494 if (status & ATA_BUSY)
1495 goto idle_irq;
1496 1592
1497 /* check main status, clearing INTRQ */ 1593 /* check main status, clearing INTRQ if needed */
1498 status = ap->ops->sff_check_status(ap); 1594 status = ata_sff_irq_status(ap);
1499 if (unlikely(status & ATA_BUSY)) 1595 if (status & ATA_BUSY)
1500 goto idle_irq; 1596 goto idle_irq;
1501 1597
1502 /* ack bmdma irq events */ 1598 /* ack bmdma irq events */
@@ -2030,7 +2126,7 @@ void ata_sff_error_handler(struct ata_port *ap)
2030 ap->ops->bmdma_stop(qc); 2126 ap->ops->bmdma_stop(qc);
2031 } 2127 }
2032 2128
2033 ata_sff_altstatus(ap); 2129 ata_sff_sync(ap); /* FIXME: We don't need this */
2034 ap->ops->sff_check_status(ap); 2130 ap->ops->sff_check_status(ap);
2035 ap->ops->sff_irq_clear(ap); 2131 ap->ops->sff_irq_clear(ap);
2036 2132
@@ -2203,7 +2299,7 @@ void ata_bmdma_stop(struct ata_queued_cmd *qc)
2203 mmio + ATA_DMA_CMD); 2299 mmio + ATA_DMA_CMD);
2204 2300
2205 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 2301 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
2206 ata_sff_altstatus(ap); /* dummy read */ 2302 ata_sff_dma_pause(ap);
2207} 2303}
2208 2304
2209/** 2305/**
@@ -2722,7 +2818,8 @@ EXPORT_SYMBOL_GPL(ata_sff_qc_prep);
2722EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep); 2818EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep);
2723EXPORT_SYMBOL_GPL(ata_sff_dev_select); 2819EXPORT_SYMBOL_GPL(ata_sff_dev_select);
2724EXPORT_SYMBOL_GPL(ata_sff_check_status); 2820EXPORT_SYMBOL_GPL(ata_sff_check_status);
2725EXPORT_SYMBOL_GPL(ata_sff_altstatus); 2821EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
2822EXPORT_SYMBOL_GPL(ata_sff_pause);
2726EXPORT_SYMBOL_GPL(ata_sff_busy_sleep); 2823EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
2727EXPORT_SYMBOL_GPL(ata_sff_wait_ready); 2824EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
2728EXPORT_SYMBOL_GPL(ata_sff_tf_load); 2825EXPORT_SYMBOL_GPL(ata_sff_tf_load);
diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h
index 4514283937ea..1cf803adbc95 100644
--- a/drivers/ata/libata.h
+++ b/drivers/ata/libata.h
@@ -106,7 +106,7 @@ extern void ata_sg_clean(struct ata_queued_cmd *qc);
106extern void ata_qc_free(struct ata_queued_cmd *qc); 106extern void ata_qc_free(struct ata_queued_cmd *qc);
107extern void ata_qc_issue(struct ata_queued_cmd *qc); 107extern void ata_qc_issue(struct ata_queued_cmd *qc);
108extern void __ata_qc_complete(struct ata_queued_cmd *qc); 108extern void __ata_qc_complete(struct ata_queued_cmd *qc);
109extern int ata_check_atapi_dma(struct ata_queued_cmd *qc); 109extern int atapi_check_dma(struct ata_queued_cmd *qc);
110extern void swap_buf_le16(u16 *buf, unsigned int buf_words); 110extern void swap_buf_le16(u16 *buf, unsigned int buf_words);
111extern void ata_dev_init(struct ata_device *dev); 111extern void ata_dev_init(struct ata_device *dev);
112extern void ata_link_init(struct ata_port *ap, struct ata_link *link, int pmp); 112extern void ata_link_init(struct ata_port *ap, struct ata_link *link, int pmp);
diff --git a/drivers/ata/pata_ali.c b/drivers/ata/pata_ali.c
index fcabe46f262b..0f3e659db99a 100644
--- a/drivers/ata/pata_ali.c
+++ b/drivers/ata/pata_ali.c
@@ -177,11 +177,11 @@ static void ali_program_modes(struct ata_port *ap, struct ata_device *adev, stru
177 u8 udma; 177 u8 udma;
178 178
179 if (t != NULL) { 179 if (t != NULL) {
180 t->setup = FIT(t->setup, 1, 8) & 7; 180 t->setup = clamp_val(t->setup, 1, 8) & 7;
181 t->act8b = FIT(t->act8b, 1, 8) & 7; 181 t->act8b = clamp_val(t->act8b, 1, 8) & 7;
182 t->rec8b = FIT(t->rec8b, 1, 16) & 15; 182 t->rec8b = clamp_val(t->rec8b, 1, 16) & 15;
183 t->active = FIT(t->active, 1, 8) & 7; 183 t->active = clamp_val(t->active, 1, 8) & 7;
184 t->recover = FIT(t->recover, 1, 16) & 15; 184 t->recover = clamp_val(t->recover, 1, 16) & 15;
185 185
186 pci_write_config_byte(pdev, cas, t->setup); 186 pci_write_config_byte(pdev, cas, t->setup);
187 pci_write_config_byte(pdev, cbt, (t->act8b << 4) | t->rec8b); 187 pci_write_config_byte(pdev, cbt, (t->act8b << 4) | t->rec8b);
diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c
index 26665c396485..57dd00f463d3 100644
--- a/drivers/ata/pata_amd.c
+++ b/drivers/ata/pata_amd.c
@@ -84,32 +84,32 @@ static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offse
84 84
85 /* Configure the address set up timing */ 85 /* Configure the address set up timing */
86 pci_read_config_byte(pdev, offset + 0x0C, &t); 86 pci_read_config_byte(pdev, offset + 0x0C, &t);
87 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1)); 87 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
88 pci_write_config_byte(pdev, offset + 0x0C , t); 88 pci_write_config_byte(pdev, offset + 0x0C , t);
89 89
90 /* Configure the 8bit I/O timing */ 90 /* Configure the 8bit I/O timing */
91 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)), 91 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
92 ((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1)); 92 ((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1));
93 93
94 /* Drive timing */ 94 /* Drive timing */
95 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn), 95 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
96 ((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1)); 96 ((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1));
97 97
98 switch (clock) { 98 switch (clock) {
99 case 1: 99 case 1:
100 t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03; 100 t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03;
101 break; 101 break;
102 102
103 case 2: 103 case 2:
104 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03; 104 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03;
105 break; 105 break;
106 106
107 case 3: 107 case 3:
108 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03; 108 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03;
109 break; 109 break;
110 110
111 case 4: 111 case 4:
112 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03; 112 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03;
113 break; 113 break;
114 114
115 default: 115 default:
diff --git a/drivers/ata/pata_at32.c b/drivers/ata/pata_at32.c
index 5e104385d6a3..82fb6e273169 100644
--- a/drivers/ata/pata_at32.c
+++ b/drivers/ata/pata_at32.c
@@ -291,8 +291,6 @@ static int __init pata_at32_probe(struct platform_device *pdev)
291 if (!info) 291 if (!info)
292 return -ENOMEM; 292 return -ENOMEM;
293 293
294 memset(info, 0, sizeof(struct at32_ide_info));
295
296 info->irq = irq; 294 info->irq = irq;
297 info->cs = board->cs; 295 info->cs = board->cs;
298 296
diff --git a/drivers/ata/pata_bf54x.c b/drivers/ata/pata_bf54x.c
index 9ab89732cf94..55516103626a 100644
--- a/drivers/ata/pata_bf54x.c
+++ b/drivers/ata/pata_bf54x.c
@@ -911,7 +911,10 @@ static void bfin_bmdma_start(struct ata_queued_cmd *qc)
911 /* Reset all transfer count */ 911 /* Reset all transfer count */
912 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST); 912 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST);
913 913
914 /* Set transfer length to buffer len */ 914 /* Set ATAPI state machine contorl in terminate sequence */
915 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM);
916
917 /* Set transfer length to buffer len */
915 for_each_sg(qc->sg, sg, qc->n_elem, si) { 918 for_each_sg(qc->sg, sg, qc->n_elem, si) {
916 ATAPI_SET_XFER_LEN(base, (sg_dma_len(sg) >> 1)); 919 ATAPI_SET_XFER_LEN(base, (sg_dma_len(sg) >> 1));
917 } 920 }
diff --git a/drivers/ata/pata_cypress.c b/drivers/ata/pata_cypress.c
index a9c3218e22fd..2ff62608ae37 100644
--- a/drivers/ata/pata_cypress.c
+++ b/drivers/ata/pata_cypress.c
@@ -62,14 +62,14 @@ static void cy82c693_set_piomode(struct ata_port *ap, struct ata_device *adev)
62 return; 62 return;
63 } 63 }
64 64
65 time_16 = FIT(t.recover, 0, 15) | (FIT(t.active, 0, 15) << 4); 65 time_16 = clamp_val(t.recover, 0, 15) | (clamp_val(t.active, 0, 15) << 4);
66 time_8 = FIT(t.act8b, 0, 15) | (FIT(t.rec8b, 0, 15) << 4); 66 time_8 = clamp_val(t.act8b, 0, 15) | (clamp_val(t.rec8b, 0, 15) << 4);
67 67
68 if (adev->devno == 0) { 68 if (adev->devno == 0) {
69 pci_read_config_dword(pdev, CY82_IDE_ADDRSETUP, &addr); 69 pci_read_config_dword(pdev, CY82_IDE_ADDRSETUP, &addr);
70 70
71 addr &= ~0x0F; /* Mask bits */ 71 addr &= ~0x0F; /* Mask bits */
72 addr |= FIT(t.setup, 0, 15); 72 addr |= clamp_val(t.setup, 0, 15);
73 73
74 pci_write_config_dword(pdev, CY82_IDE_ADDRSETUP, addr); 74 pci_write_config_dword(pdev, CY82_IDE_ADDRSETUP, addr);
75 pci_write_config_byte(pdev, CY82_IDE_MASTER_IOR, time_16); 75 pci_write_config_byte(pdev, CY82_IDE_MASTER_IOR, time_16);
@@ -79,7 +79,7 @@ static void cy82c693_set_piomode(struct ata_port *ap, struct ata_device *adev)
79 pci_read_config_dword(pdev, CY82_IDE_ADDRSETUP, &addr); 79 pci_read_config_dword(pdev, CY82_IDE_ADDRSETUP, &addr);
80 80
81 addr &= ~0xF0; /* Mask bits */ 81 addr &= ~0xF0; /* Mask bits */
82 addr |= (FIT(t.setup, 0, 15) << 4); 82 addr |= (clamp_val(t.setup, 0, 15) << 4);
83 83
84 pci_write_config_dword(pdev, CY82_IDE_ADDRSETUP, addr); 84 pci_write_config_dword(pdev, CY82_IDE_ADDRSETUP, addr);
85 pci_write_config_byte(pdev, CY82_IDE_SLAVE_IOR, time_16); 85 pci_write_config_byte(pdev, CY82_IDE_SLAVE_IOR, time_16);
diff --git a/drivers/ata/pata_icside.c b/drivers/ata/pata_icside.c
index 17138436423d..cf9e9848f8b5 100644
--- a/drivers/ata/pata_icside.c
+++ b/drivers/ata/pata_icside.c
@@ -270,7 +270,7 @@ static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
270 disable_dma(state->dma); 270 disable_dma(state->dma);
271 271
272 /* see ata_bmdma_stop */ 272 /* see ata_bmdma_stop */
273 ata_sff_altstatus(ap); 273 ata_sff_dma_pause(ap);
274} 274}
275 275
276static u8 pata_icside_bmdma_status(struct ata_port *ap) 276static u8 pata_icside_bmdma_status(struct ata_port *ap)
diff --git a/drivers/ata/pata_legacy.c b/drivers/ata/pata_legacy.c
index 7af4b29cc422..fe7cc8ed4ea4 100644
--- a/drivers/ata/pata_legacy.c
+++ b/drivers/ata/pata_legacy.c
@@ -343,8 +343,8 @@ static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
343 /* Get the timing data in cycles. For now play safe at 50Mhz */ 343 /* Get the timing data in cycles. For now play safe at 50Mhz */
344 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 344 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
345 345
346 active = FIT(t.active, 2, 15); 346 active = clamp_val(t.active, 2, 15);
347 recover = FIT(t.recover, 4, 15); 347 recover = clamp_val(t.recover, 4, 15);
348 348
349 inb(0x3E6); 349 inb(0x3E6);
350 inb(0x3E6); 350 inb(0x3E6);
@@ -377,8 +377,8 @@ static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
377 /* Get the timing data in cycles. For now play safe at 50Mhz */ 377 /* Get the timing data in cycles. For now play safe at 50Mhz */
378 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 378 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
379 379
380 active = FIT(t.active, 2, 15); 380 active = clamp_val(t.active, 2, 15);
381 recover = FIT(t.recover, 2, 16); 381 recover = clamp_val(t.recover, 2, 16);
382 recover &= 0x15; 382 recover &= 0x15;
383 383
384 inb(0x3E6); 384 inb(0x3E6);
@@ -462,9 +462,9 @@ static void opti82c611a_set_piomode(struct ata_port *ap,
462 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 462 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
463 } 463 }
464 464
465 active = FIT(t.active, 2, 17) - 2; 465 active = clamp_val(t.active, 2, 17) - 2;
466 recover = FIT(t.recover, 1, 16) - 1; 466 recover = clamp_val(t.recover, 1, 16) - 1;
467 setup = FIT(t.setup, 1, 4) - 1; 467 setup = clamp_val(t.setup, 1, 4) - 1;
468 468
469 /* Select the right timing bank for write timing */ 469 /* Select the right timing bank for write timing */
470 rc = ioread8(ap->ioaddr.lbal_addr); 470 rc = ioread8(ap->ioaddr.lbal_addr);
@@ -541,9 +541,9 @@ static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
541 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 541 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
542 } 542 }
543 543
544 active = FIT(t.active, 2, 17) - 2; 544 active = clamp_val(t.active, 2, 17) - 2;
545 recover = FIT(t.recover, 1, 16) - 1; 545 recover = clamp_val(t.recover, 1, 16) - 1;
546 setup = FIT(t.setup, 1, 4) - 1; 546 setup = clamp_val(t.setup, 1, 4) - 1;
547 547
548 /* Select the right timing bank for write timing */ 548 /* Select the right timing bank for write timing */
549 rc = ioread8(ap->ioaddr.lbal_addr); 549 rc = ioread8(ap->ioaddr.lbal_addr);
@@ -624,11 +624,11 @@ static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev)
624 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 624 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
625 625
626 if (ld_qdi->fast) { 626 if (ld_qdi->fast) {
627 active = 8 - FIT(t.active, 1, 8); 627 active = 8 - clamp_val(t.active, 1, 8);
628 recovery = 18 - FIT(t.recover, 3, 18); 628 recovery = 18 - clamp_val(t.recover, 3, 18);
629 } else { 629 } else {
630 active = 9 - FIT(t.active, 2, 9); 630 active = 9 - clamp_val(t.active, 2, 9);
631 recovery = 15 - FIT(t.recover, 0, 15); 631 recovery = 15 - clamp_val(t.recover, 0, 15);
632 } 632 }
633 timing = (recovery << 4) | active | 0x08; 633 timing = (recovery << 4) | active | 0x08;
634 634
@@ -658,11 +658,11 @@ static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev)
658 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 658 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
659 659
660 if (ld_qdi->fast) { 660 if (ld_qdi->fast) {
661 active = 8 - FIT(t.active, 1, 8); 661 active = 8 - clamp_val(t.active, 1, 8);
662 recovery = 18 - FIT(t.recover, 3, 18); 662 recovery = 18 - clamp_val(t.recover, 3, 18);
663 } else { 663 } else {
664 active = 9 - FIT(t.active, 2, 9); 664 active = 9 - clamp_val(t.active, 2, 9);
665 recovery = 15 - FIT(t.recover, 0, 15); 665 recovery = 15 - clamp_val(t.recover, 0, 15);
666 } 666 }
667 timing = (recovery << 4) | active | 0x08; 667 timing = (recovery << 4) | active | 0x08;
668 668
@@ -695,11 +695,11 @@ static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev)
695 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 695 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
696 696
697 if (ld_qdi->fast) { 697 if (ld_qdi->fast) {
698 active = 8 - FIT(t.active, 1, 8); 698 active = 8 - clamp_val(t.active, 1, 8);
699 recovery = 18 - FIT(t.recover, 3, 18); 699 recovery = 18 - clamp_val(t.recover, 3, 18);
700 } else { 700 } else {
701 active = 9 - FIT(t.active, 2, 9); 701 active = 9 - clamp_val(t.active, 2, 9);
702 recovery = 15 - FIT(t.recover, 0, 15); 702 recovery = 15 - clamp_val(t.recover, 0, 15);
703 } 703 }
704 timing = (recovery << 4) | active | 0x08; 704 timing = (recovery << 4) | active | 0x08;
705 ld_qdi->clock[adev->devno] = timing; 705 ld_qdi->clock[adev->devno] = timing;
@@ -830,8 +830,8 @@ static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
830 else 830 else
831 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 831 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
832 832
833 active = (FIT(t.active, 3, 17) - 1) & 0x0F; 833 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
834 recovery = (FIT(t.recover, 1, 15) + 1) & 0x0F; 834 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
835 timing = (active << 4) | recovery; 835 timing = (active << 4) | recovery;
836 winbond_writecfg(ld_winbond->timing, timing, reg); 836 winbond_writecfg(ld_winbond->timing, timing, reg);
837 837
@@ -842,7 +842,7 @@ static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
842 reg |= 0x08; /* FIFO off */ 842 reg |= 0x08; /* FIFO off */
843 if (!ata_pio_need_iordy(adev)) 843 if (!ata_pio_need_iordy(adev))
844 reg |= 0x02; /* IORDY off */ 844 reg |= 0x02; /* IORDY off */
845 reg |= (FIT(t.setup, 0, 3) << 6); 845 reg |= (clamp_val(t.setup, 0, 3) << 6);
846 winbond_writecfg(ld_winbond->timing, timing + 1, reg); 846 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
847} 847}
848 848
diff --git a/drivers/ata/pata_ns87410.c b/drivers/ata/pata_ns87410.c
index 76d2455bc453..be756b7ef07e 100644
--- a/drivers/ata/pata_ns87410.c
+++ b/drivers/ata/pata_ns87410.c
@@ -91,9 +91,9 @@ static void ns87410_set_piomode(struct ata_port *ap, struct ata_device *adev)
91 return; 91 return;
92 } 92 }
93 93
94 at.active = FIT(at.active, 2, 16) - 2; 94 at.active = clamp_val(at.active, 2, 16) - 2;
95 at.setup = FIT(at.setup, 1, 4) - 1; 95 at.setup = clamp_val(at.setup, 1, 4) - 1;
96 at.recover = FIT(at.recover, 1, 12) - 1; 96 at.recover = clamp_val(at.recover, 1, 12) - 1;
97 97
98 idetcr = (at.setup << 6) | (recoverbits[at.recover] << 3) | activebits[at.active]; 98 idetcr = (at.setup << 6) | (recoverbits[at.recover] << 3) | activebits[at.active];
99 99
diff --git a/drivers/ata/pata_ns87415.c b/drivers/ata/pata_ns87415.c
index ae92b0049bd5..e0aa7eaaee0a 100644
--- a/drivers/ata/pata_ns87415.c
+++ b/drivers/ata/pata_ns87415.c
@@ -66,8 +66,8 @@ static void ns87415_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mo
66 66
67 ata_timing_compute(adev, adev->pio_mode, &t, T, 0); 67 ata_timing_compute(adev, adev->pio_mode, &t, T, 0);
68 68
69 clocking = 17 - FIT(t.active, 2, 17); 69 clocking = 17 - clamp_val(t.active, 2, 17);
70 clocking |= (16 - FIT(t.recover, 1, 16)) << 4; 70 clocking |= (16 - clamp_val(t.recover, 1, 16)) << 4;
71 /* Use the same timing for read and write bytes */ 71 /* Use the same timing for read and write bytes */
72 clocking |= (clocking << 8); 72 clocking |= (clocking << 8);
73 pci_write_config_word(dev, timing, clocking); 73 pci_write_config_word(dev, timing, clocking);
diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c
index 3d39f9dfec5a..41b4361bbf6e 100644
--- a/drivers/ata/pata_pcmcia.c
+++ b/drivers/ata/pata_pcmcia.c
@@ -414,6 +414,7 @@ static struct pcmcia_device_id pcmcia_devices[] = {
414 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149), 414 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149),
415 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674), 415 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674),
416 PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2 ", 0xe37be2b5, 0x8671043b), 416 PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2 ", 0xe37be2b5, 0x8671043b),
417 PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF300", 0x7ed2ad87, 0x7e9e78ee),
417 PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c), 418 PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c),
418 PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79), 419 PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79),
419 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591), 420 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591),
@@ -424,6 +425,7 @@ static struct pcmcia_device_id pcmcia_devices[] = {
424 PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6), 425 PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6),
425 PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003), 426 PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003),
426 PCMCIA_DEVICE_PROD_ID1("TRANSCEND 512M ", 0xd0909443), 427 PCMCIA_DEVICE_PROD_ID1("TRANSCEND 512M ", 0xd0909443),
428 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF45", 0x709b1bf1, 0xf68b6f32),
427 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1), 429 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1),
428 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2), 430 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2),
429 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8), 431 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8),
diff --git a/drivers/ata/pata_qdi.c b/drivers/ata/pata_qdi.c
index bf45cf017753..97e5b090d7c2 100644
--- a/drivers/ata/pata_qdi.c
+++ b/drivers/ata/pata_qdi.c
@@ -60,11 +60,11 @@ static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev)
60 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 60 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
61 61
62 if (qdi->fast) { 62 if (qdi->fast) {
63 active = 8 - FIT(t.active, 1, 8); 63 active = 8 - clamp_val(t.active, 1, 8);
64 recovery = 18 - FIT(t.recover, 3, 18); 64 recovery = 18 - clamp_val(t.recover, 3, 18);
65 } else { 65 } else {
66 active = 9 - FIT(t.active, 2, 9); 66 active = 9 - clamp_val(t.active, 2, 9);
67 recovery = 15 - FIT(t.recover, 0, 15); 67 recovery = 15 - clamp_val(t.recover, 0, 15);
68 } 68 }
69 timing = (recovery << 4) | active | 0x08; 69 timing = (recovery << 4) | active | 0x08;
70 70
@@ -84,11 +84,11 @@ static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev)
84 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 84 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
85 85
86 if (qdi->fast) { 86 if (qdi->fast) {
87 active = 8 - FIT(t.active, 1, 8); 87 active = 8 - clamp_val(t.active, 1, 8);
88 recovery = 18 - FIT(t.recover, 3, 18); 88 recovery = 18 - clamp_val(t.recover, 3, 18);
89 } else { 89 } else {
90 active = 9 - FIT(t.active, 2, 9); 90 active = 9 - clamp_val(t.active, 2, 9);
91 recovery = 15 - FIT(t.recover, 0, 15); 91 recovery = 15 - clamp_val(t.recover, 0, 15);
92 } 92 }
93 timing = (recovery << 4) | active | 0x08; 93 timing = (recovery << 4) | active | 0x08;
94 94
diff --git a/drivers/ata/pata_rb532_cf.c b/drivers/ata/pata_rb532_cf.c
index a108d259f19d..f8b3ffc8ae9e 100644
--- a/drivers/ata/pata_rb532_cf.c
+++ b/drivers/ata/pata_rb532_cf.c
@@ -57,7 +57,9 @@ static inline void rb532_pata_finish_io(struct ata_port *ap)
57 struct ata_host *ah = ap->host; 57 struct ata_host *ah = ap->host;
58 struct rb532_cf_info *info = ah->private_data; 58 struct rb532_cf_info *info = ah->private_data;
59 59
60 ata_sff_altstatus(ap); 60 /* FIXME: Keep previous delay. If this is merely a fence then
61 ata_sff_sync might be sufficient. */
62 ata_sff_dma_pause(ap);
61 ndelay(RB500_CF_IO_DELAY); 63 ndelay(RB500_CF_IO_DELAY);
62 64
63 set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH); 65 set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
diff --git a/drivers/ata/pata_scc.c b/drivers/ata/pata_scc.c
index e965b251ca24..bbf5aa345e68 100644
--- a/drivers/ata/pata_scc.c
+++ b/drivers/ata/pata_scc.c
@@ -726,7 +726,7 @@ static void scc_bmdma_stop (struct ata_queued_cmd *qc)
726 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); 726 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
727 727
728 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 728 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
729 ata_sff_altstatus(ap); /* dummy read */ 729 ata_sff_dma_pause(ap); /* dummy read */
730} 730}
731 731
732/** 732/**
@@ -747,7 +747,8 @@ static u8 scc_bmdma_status (struct ata_port *ap)
747 return host_stat; 747 return host_stat;
748 748
749 /* errata A252,A308 workaround: Step4 */ 749 /* errata A252,A308 workaround: Step4 */
750 if ((ata_sff_altstatus(ap) & ATA_ERR) && (int_status & INTSTS_INTRQ)) 750 if ((scc_check_altstatus(ap) & ATA_ERR)
751 && (int_status & INTSTS_INTRQ))
751 return (host_stat | ATA_DMA_INTR); 752 return (host_stat | ATA_DMA_INTR);
752 753
753 /* errata A308 workaround Step5 */ 754 /* errata A308 workaround Step5 */
diff --git a/drivers/ata/pata_sis.c b/drivers/ata/pata_sis.c
index e82c66e8d31b..26345d7b531c 100644
--- a/drivers/ata/pata_sis.c
+++ b/drivers/ata/pata_sis.c
@@ -56,6 +56,7 @@ static const struct sis_laptop sis_laptop[] = {
56 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ 56 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
57 { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ 57 { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */
58 { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ 58 { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
59 { 0x5513, 0x1039, 0x5513 }, /* Targa Visionary 1000 */
59 /* end marker */ 60 /* end marker */
60 { 0, } 61 { 0, }
61}; 62};
diff --git a/drivers/ata/pata_sl82c105.c b/drivers/ata/pata_sl82c105.c
index 70d94fb28a5f..69877bd81815 100644
--- a/drivers/ata/pata_sl82c105.c
+++ b/drivers/ata/pata_sl82c105.c
@@ -216,7 +216,7 @@ static int sl82c105_qc_defer(struct ata_queued_cmd *qc)
216 struct ata_port *alt = host->ports[1 ^ qc->ap->port_no]; 216 struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
217 int rc; 217 int rc;
218 218
219 /* First apply the usual rules */ 219 /* First apply the usual rules */
220 rc = ata_std_qc_defer(qc); 220 rc = ata_std_qc_defer(qc);
221 if (rc != 0) 221 if (rc != 0)
222 return rc; 222 return rc;
diff --git a/drivers/ata/pata_via.c b/drivers/ata/pata_via.c
index 2fea6cbe7755..708ed144ede9 100644
--- a/drivers/ata/pata_via.c
+++ b/drivers/ata/pata_via.c
@@ -259,15 +259,15 @@ static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mo
259 259
260 pci_read_config_byte(pdev, 0x4C, &setup); 260 pci_read_config_byte(pdev, 0x4C, &setup);
261 setup &= ~(3 << shift); 261 setup &= ~(3 << shift);
262 setup |= FIT(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */ 262 setup |= clamp_val(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */
263 pci_write_config_byte(pdev, 0x4C, setup); 263 pci_write_config_byte(pdev, 0x4C, setup);
264 } 264 }
265 265
266 /* Load the PIO mode bits */ 266 /* Load the PIO mode bits */
267 pci_write_config_byte(pdev, 0x4F - ap->port_no, 267 pci_write_config_byte(pdev, 0x4F - ap->port_no,
268 ((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1)); 268 ((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1));
269 pci_write_config_byte(pdev, 0x48 + offset, 269 pci_write_config_byte(pdev, 0x48 + offset,
270 ((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1)); 270 ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1));
271 271
272 /* Load the UDMA bits according to type */ 272 /* Load the UDMA bits according to type */
273 switch(udma_type) { 273 switch(udma_type) {
@@ -275,16 +275,16 @@ static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mo
275 /* BUG() ? */ 275 /* BUG() ? */
276 /* fall through */ 276 /* fall through */
277 case 33: 277 case 33:
278 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03; 278 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03;
279 break; 279 break;
280 case 66: 280 case 66:
281 ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f; 281 ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f;
282 break; 282 break;
283 case 100: 283 case 100:
284 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07; 284 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
285 break; 285 break;
286 case 133: 286 case 133:
287 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07; 287 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
288 break; 288 break;
289 } 289 }
290 290
diff --git a/drivers/ata/pata_winbond.c b/drivers/ata/pata_winbond.c
index 6e52a3573fbf..474528f8fe3d 100644
--- a/drivers/ata/pata_winbond.c
+++ b/drivers/ata/pata_winbond.c
@@ -75,8 +75,8 @@ static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
75 else 75 else
76 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 76 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
77 77
78 active = (FIT(t.active, 3, 17) - 1) & 0x0F; 78 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
79 recovery = (FIT(t.recover, 1, 15) + 1) & 0x0F; 79 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
80 timing = (active << 4) | recovery; 80 timing = (active << 4) | recovery;
81 winbond_writecfg(winbond->config, timing, reg); 81 winbond_writecfg(winbond->config, timing, reg);
82 82
@@ -87,7 +87,7 @@ static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
87 reg |= 0x08; /* FIFO off */ 87 reg |= 0x08; /* FIFO off */
88 if (!ata_pio_need_iordy(adev)) 88 if (!ata_pio_need_iordy(adev))
89 reg |= 0x02; /* IORDY off */ 89 reg |= 0x02; /* IORDY off */
90 reg |= (FIT(t.setup, 0, 3) << 6); 90 reg |= (clamp_val(t.setup, 0, 3) << 6);
91 winbond_writecfg(winbond->config, timing + 1, reg); 91 winbond_writecfg(winbond->config, timing + 1, reg);
92} 92}
93 93
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index 853559e32315..3924e7209a44 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -34,7 +34,7 @@ enum {
34 34
35 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 35 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
36 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 36 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
37 ATA_FLAG_NCQ), 37 ATA_FLAG_PMP | ATA_FLAG_NCQ),
38 38
39 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, 39 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
40 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ 40 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
@@ -395,7 +395,7 @@ static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
395 cd = (struct command_desc *)pp->cmdentry + tag; 395 cd = (struct command_desc *)pp->cmdentry + tag;
396 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; 396 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
397 397
398 ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) &cd->cfis); 398 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
399 399
400 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", 400 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
401 cd->cfis[0], cd->cfis[1], cd->cfis[2]); 401 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
@@ -438,6 +438,8 @@ static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
438 ioread32(CA + hcr_base), 438 ioread32(CA + hcr_base),
439 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); 439 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
440 440
441 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
442
441 /* Simply queue command to the controller/device */ 443 /* Simply queue command to the controller/device */
442 iowrite32(1 << tag, CQ + hcr_base); 444 iowrite32(1 << tag, CQ + hcr_base);
443 445
@@ -558,11 +560,36 @@ static void sata_fsl_thaw(struct ata_port *ap)
558 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 560 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
559} 561}
560 562
563static void sata_fsl_pmp_attach(struct ata_port *ap)
564{
565 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
566 void __iomem *hcr_base = host_priv->hcr_base;
567 u32 temp;
568
569 temp = ioread32(hcr_base + HCONTROL);
570 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
571}
572
573static void sata_fsl_pmp_detach(struct ata_port *ap)
574{
575 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
576 void __iomem *hcr_base = host_priv->hcr_base;
577 u32 temp;
578
579 temp = ioread32(hcr_base + HCONTROL);
580 temp &= ~HCONTROL_PMP_ATTACHED;
581 iowrite32(temp, hcr_base + HCONTROL);
582
583 /* enable interrupts on the controller/port */
584 temp = ioread32(hcr_base + HCONTROL);
585 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
586
587}
588
561static int sata_fsl_port_start(struct ata_port *ap) 589static int sata_fsl_port_start(struct ata_port *ap)
562{ 590{
563 struct device *dev = ap->host->dev; 591 struct device *dev = ap->host->dev;
564 struct sata_fsl_port_priv *pp; 592 struct sata_fsl_port_priv *pp;
565 int retval;
566 void *mem; 593 void *mem;
567 dma_addr_t mem_dma; 594 dma_addr_t mem_dma;
568 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 595 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
@@ -688,12 +715,13 @@ static int sata_fsl_prereset(struct ata_link *link, unsigned long deadline)
688} 715}
689 716
690static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, 717static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
691 unsigned long deadline) 718 unsigned long deadline)
692{ 719{
693 struct ata_port *ap = link->ap; 720 struct ata_port *ap = link->ap;
694 struct sata_fsl_port_priv *pp = ap->private_data; 721 struct sata_fsl_port_priv *pp = ap->private_data;
695 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 722 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
696 void __iomem *hcr_base = host_priv->hcr_base; 723 void __iomem *hcr_base = host_priv->hcr_base;
724 int pmp = sata_srst_pmp(link);
697 u32 temp; 725 u32 temp;
698 struct ata_taskfile tf; 726 struct ata_taskfile tf;
699 u8 *cfis; 727 u8 *cfis;
@@ -703,6 +731,9 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
703 731
704 DPRINTK("in xx_softreset\n"); 732 DPRINTK("in xx_softreset\n");
705 733
734 if (pmp != SATA_PMP_CTRL_PORT)
735 goto issue_srst;
736
706try_offline_again: 737try_offline_again:
707 /* 738 /*
708 * Force host controller to go off-line, aborting current operations 739 * Force host controller to go off-line, aborting current operations
@@ -746,6 +777,7 @@ try_offline_again:
746 777
747 temp = ioread32(hcr_base + HCONTROL); 778 temp = ioread32(hcr_base + HCONTROL);
748 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); 779 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
780 temp |= HCONTROL_PMP_ATTACHED;
749 iowrite32(temp, hcr_base + HCONTROL); 781 iowrite32(temp, hcr_base + HCONTROL);
750 782
751 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500); 783 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500);
@@ -771,7 +803,8 @@ try_offline_again:
771 ata_port_printk(ap, KERN_WARNING, 803 ata_port_printk(ap, KERN_WARNING,
772 "No Device OR PHYRDY change,Hstatus = 0x%x\n", 804 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
773 ioread32(hcr_base + HSTATUS)); 805 ioread32(hcr_base + HSTATUS));
774 goto err; 806 *class = ATA_DEV_NONE;
807 goto out;
775 } 808 }
776 809
777 /* 810 /*
@@ -783,7 +816,8 @@ try_offline_again:
783 816
784 if ((temp & 0xFF) != 0x18) { 817 if ((temp & 0xFF) != 0x18) {
785 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n"); 818 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
786 goto err; 819 *class = ATA_DEV_NONE;
820 goto out;
787 } else { 821 } else {
788 ata_port_printk(ap, KERN_INFO, 822 ata_port_printk(ap, KERN_INFO,
789 "Signature Update detected @ %d msecs\n", 823 "Signature Update detected @ %d msecs\n",
@@ -798,6 +832,7 @@ try_offline_again:
798 * reached here, we can send a command to the target device 832 * reached here, we can send a command to the target device
799 */ 833 */
800 834
835issue_srst:
801 DPRINTK("Sending SRST/device reset\n"); 836 DPRINTK("Sending SRST/device reset\n");
802 837
803 ata_tf_init(link->device, &tf); 838 ata_tf_init(link->device, &tf);
@@ -808,7 +843,7 @@ try_offline_again:
808 SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 843 SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
809 844
810 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ 845 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
811 ata_tf_to_fis(&tf, 0, 0, cfis); 846 ata_tf_to_fis(&tf, pmp, 0, cfis);
812 847
813 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", 848 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
814 cfis[0], cfis[1], cfis[2], cfis[3]); 849 cfis[0], cfis[1], cfis[2], cfis[3]);
@@ -854,8 +889,10 @@ try_offline_again:
854 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 889 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
855 890
856 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 891 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
857 ata_tf_to_fis(&tf, 0, 0, cfis); 892 ata_tf_to_fis(&tf, pmp, 0, cfis);
858 893
894 if (pmp != SATA_PMP_CTRL_PORT)
895 iowrite32(pmp, CQPMP + hcr_base);
859 iowrite32(1, CQ + hcr_base); 896 iowrite32(1, CQ + hcr_base);
860 msleep(150); /* ?? */ 897 msleep(150); /* ?? */
861 898
@@ -886,12 +923,21 @@ try_offline_again:
886 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); 923 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
887 } 924 }
888 925
926out:
889 return 0; 927 return 0;
890 928
891err: 929err:
892 return -EIO; 930 return -EIO;
893} 931}
894 932
933static void sata_fsl_error_handler(struct ata_port *ap)
934{
935
936 DPRINTK("in xx_error_handler\n");
937 sata_pmp_error_handler(ap);
938
939}
940
895static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) 941static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
896{ 942{
897 if (qc->flags & ATA_QCFLAG_FAILED) 943 if (qc->flags & ATA_QCFLAG_FAILED)
@@ -905,18 +951,21 @@ static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
905 951
906static void sata_fsl_error_intr(struct ata_port *ap) 952static void sata_fsl_error_intr(struct ata_port *ap)
907{ 953{
908 struct ata_link *link = &ap->link;
909 struct ata_eh_info *ehi = &link->eh_info;
910 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 954 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
911 void __iomem *hcr_base = host_priv->hcr_base; 955 void __iomem *hcr_base = host_priv->hcr_base;
912 u32 hstatus, dereg, cereg = 0, SError = 0; 956 u32 hstatus, dereg=0, cereg = 0, SError = 0;
913 unsigned int err_mask = 0, action = 0; 957 unsigned int err_mask = 0, action = 0;
914 struct ata_queued_cmd *qc; 958 int freeze = 0, abort=0;
915 int freeze = 0; 959 struct ata_link *link = NULL;
960 struct ata_queued_cmd *qc = NULL;
961 struct ata_eh_info *ehi;
916 962
917 hstatus = ioread32(hcr_base + HSTATUS); 963 hstatus = ioread32(hcr_base + HSTATUS);
918 cereg = ioread32(hcr_base + CE); 964 cereg = ioread32(hcr_base + CE);
919 965
966 /* first, analyze and record host port events */
967 link = &ap->link;
968 ehi = &link->eh_info;
920 ata_ehi_clear_desc(ehi); 969 ata_ehi_clear_desc(ehi);
921 970
922 /* 971 /*
@@ -926,42 +975,28 @@ static void sata_fsl_error_intr(struct ata_port *ap)
926 sata_fsl_scr_read(ap, SCR_ERROR, &SError); 975 sata_fsl_scr_read(ap, SCR_ERROR, &SError);
927 if (unlikely(SError & 0xFFFF0000)) { 976 if (unlikely(SError & 0xFFFF0000)) {
928 sata_fsl_scr_write(ap, SCR_ERROR, SError); 977 sata_fsl_scr_write(ap, SCR_ERROR, SError);
929 err_mask |= AC_ERR_ATA_BUS;
930 } 978 }
931 979
932 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", 980 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
933 hstatus, cereg, ioread32(hcr_base + DE), SError); 981 hstatus, cereg, ioread32(hcr_base + DE), SError);
934 982
935 /* handle single device errors */ 983 /* handle fatal errors */
936 if (cereg) { 984 if (hstatus & FATAL_ERROR_DECODE) {
937 /* 985 ehi->err_mask |= AC_ERR_ATA_BUS;
938 * clear the command error, also clears queue to the device 986 ehi->action |= ATA_EH_SOFTRESET;
939 * in error, and we can (re)issue commands to this device.
940 * When a device is in error all commands queued into the
941 * host controller and at the device are considered aborted
942 * and the queue for that device is stopped. Now, after
943 * clearing the device error, we can issue commands to the
944 * device to interrogate it to find the source of the error.
945 */
946 dereg = ioread32(hcr_base + DE);
947 iowrite32(dereg, hcr_base + DE);
948 iowrite32(cereg, hcr_base + CE);
949 987
950 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
951 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
952 /* 988 /*
953 * We should consider this as non fatal error, and TF must 989 * Ignore serror in case of fatal errors as we always want
954 * be updated as done below. 990 * to do a soft-reset of the FSL SATA controller. Analyzing
991 * serror may cause libata to schedule a hard-reset action,
992 * and hard-reset currently does not do controller
993 * offline/online, causing command timeouts and leads to an
994 * un-recoverable state, hence make libATA ignore
995 * autopsy in case of fatal errors.
955 */ 996 */
956 997
957 err_mask |= AC_ERR_DEV; 998 ehi->flags |= ATA_EHI_NO_AUTOPSY;
958 }
959 999
960 /* handle fatal errors */
961 if (hstatus & FATAL_ERROR_DECODE) {
962 err_mask |= AC_ERR_ATA_BUS;
963 action |= ATA_EH_RESET;
964 /* how will fatal error interrupts be completed ?? */
965 freeze = 1; 1000 freeze = 1;
966 } 1001 }
967 1002
@@ -971,30 +1006,83 @@ static void sata_fsl_error_intr(struct ata_port *ap)
971 1006
972 /* Setup a soft-reset EH action */ 1007 /* Setup a soft-reset EH action */
973 ata_ehi_hotplugged(ehi); 1008 ata_ehi_hotplugged(ehi);
1009 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
974 freeze = 1; 1010 freeze = 1;
975 } 1011 }
976 1012
977 /* record error info */ 1013 /* handle single device errors */
978 qc = ata_qc_from_tag(ap, link->active_tag); 1014 if (cereg) {
1015 /*
1016 * clear the command error, also clears queue to the device
1017 * in error, and we can (re)issue commands to this device.
1018 * When a device is in error all commands queued into the
1019 * host controller and at the device are considered aborted
1020 * and the queue for that device is stopped. Now, after
1021 * clearing the device error, we can issue commands to the
1022 * device to interrogate it to find the source of the error.
1023 */
1024 abort = 1;
1025
1026 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1027 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
979 1028
980 if (qc) 1029 /* find out the offending link and qc */
1030 if (ap->nr_pmp_links) {
1031 dereg = ioread32(hcr_base + DE);
1032 iowrite32(dereg, hcr_base + DE);
1033 iowrite32(cereg, hcr_base + CE);
1034
1035 if (dereg < ap->nr_pmp_links) {
1036 link = &ap->pmp_link[dereg];
1037 ehi = &link->eh_info;
1038 qc = ata_qc_from_tag(ap, link->active_tag);
1039 /*
1040 * We should consider this as non fatal error,
1041 * and TF must be updated as done below.
1042 */
1043
1044 err_mask |= AC_ERR_DEV;
1045
1046 } else {
1047 err_mask |= AC_ERR_HSM;
1048 action |= ATA_EH_HARDRESET;
1049 freeze = 1;
1050 }
1051 } else {
1052 dereg = ioread32(hcr_base + DE);
1053 iowrite32(dereg, hcr_base + DE);
1054 iowrite32(cereg, hcr_base + CE);
1055
1056 qc = ata_qc_from_tag(ap, link->active_tag);
1057 /*
1058 * We should consider this as non fatal error,
1059 * and TF must be updated as done below.
1060 */
1061 err_mask |= AC_ERR_DEV;
1062 }
1063 }
1064
1065 /* record error info */
1066 if (qc) {
981 qc->err_mask |= err_mask; 1067 qc->err_mask |= err_mask;
982 else 1068 } else
983 ehi->err_mask |= err_mask; 1069 ehi->err_mask |= err_mask;
984 1070
985 ehi->action |= action; 1071 ehi->action |= action;
986 ehi->serror |= SError;
987 1072
988 /* freeze or abort */ 1073 /* freeze or abort */
989 if (freeze) 1074 if (freeze)
990 ata_port_freeze(ap); 1075 ata_port_freeze(ap);
991 else 1076 else if (abort) {
992 ata_port_abort(ap); 1077 if (qc)
1078 ata_link_abort(qc->dev->link);
1079 else
1080 ata_port_abort(ap);
1081 }
993} 1082}
994 1083
995static void sata_fsl_host_intr(struct ata_port *ap) 1084static void sata_fsl_host_intr(struct ata_port *ap)
996{ 1085{
997 struct ata_link *link = &ap->link;
998 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1086 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
999 void __iomem *hcr_base = host_priv->hcr_base; 1087 void __iomem *hcr_base = host_priv->hcr_base;
1000 u32 hstatus, qc_active = 0; 1088 u32 hstatus, qc_active = 0;
@@ -1017,10 +1105,19 @@ static void sata_fsl_host_intr(struct ata_port *ap)
1017 return; 1105 return;
1018 } 1106 }
1019 1107
1020 if (link->sactive) { /* only true for NCQ commands */ 1108 /* Read command completed register */
1109 qc_active = ioread32(hcr_base + CC);
1110
1111 VPRINTK("Status of all queues :\n");
1112 VPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1113 qc_active,
1114 ioread32(hcr_base + CA),
1115 ioread32(hcr_base + CE),
1116 ioread32(hcr_base + CQ),
1117 ap->qc_active);
1118
1119 if (qc_active & ap->qc_active) {
1021 int i; 1120 int i;
1022 /* Read command completed register */
1023 qc_active = ioread32(hcr_base + CC);
1024 /* clear CC bit, this will also complete the interrupt */ 1121 /* clear CC bit, this will also complete the interrupt */
1025 iowrite32(qc_active, hcr_base + CC); 1122 iowrite32(qc_active, hcr_base + CC);
1026 1123
@@ -1032,8 +1129,9 @@ static void sata_fsl_host_intr(struct ata_port *ap)
1032 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1129 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1033 if (qc_active & (1 << i)) { 1130 if (qc_active & (1 << i)) {
1034 qc = ata_qc_from_tag(ap, i); 1131 qc = ata_qc_from_tag(ap, i);
1035 if (qc) 1132 if (qc) {
1036 ata_qc_complete(qc); 1133 ata_qc_complete(qc);
1134 }
1037 DPRINTK 1135 DPRINTK
1038 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", 1136 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1039 i, ioread32(hcr_base + CC), 1137 i, ioread32(hcr_base + CC),
@@ -1042,19 +1140,21 @@ static void sata_fsl_host_intr(struct ata_port *ap)
1042 } 1140 }
1043 return; 1141 return;
1044 1142
1045 } else if (ap->qc_active) { 1143 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) {
1046 iowrite32(1, hcr_base + CC); 1144 iowrite32(1, hcr_base + CC);
1047 qc = ata_qc_from_tag(ap, link->active_tag); 1145 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1048 1146
1049 DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n", 1147 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1050 link->active_tag, ioread32(hcr_base + CC)); 1148 ioread32(hcr_base + CC));
1051 1149
1052 if (qc) 1150 if (qc) {
1053 ata_qc_complete(qc); 1151 ata_qc_complete(qc);
1152 }
1054 } else { 1153 } else {
1055 /* Spurious Interrupt!! */ 1154 /* Spurious Interrupt!! */
1056 DPRINTK("spurious interrupt!!, CC = 0x%x\n", 1155 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1057 ioread32(hcr_base + CC)); 1156 ioread32(hcr_base + CC));
1157 iowrite32(qc_active, hcr_base + CC);
1058 return; 1158 return;
1059 } 1159 }
1060} 1160}
@@ -1130,9 +1230,6 @@ static int sata_fsl_init_controller(struct ata_host *host)
1130 iowrite32(0x00000FFFF, hcr_base + CE); 1230 iowrite32(0x00000FFFF, hcr_base + CE);
1131 iowrite32(0x00000FFFF, hcr_base + DE); 1231 iowrite32(0x00000FFFF, hcr_base + DE);
1132 1232
1133 /* initially assuming no Port multiplier, set CQPMP to 0 */
1134 iowrite32(0x0, hcr_base + CQPMP);
1135
1136 /* 1233 /*
1137 * host controller will be brought on-line, during xx_port_start() 1234 * host controller will be brought on-line, during xx_port_start()
1138 * callback, that should also initiate the OOB, COMINIT sequence 1235 * callback, that should also initiate the OOB, COMINIT sequence
@@ -1154,8 +1251,8 @@ static struct scsi_host_template sata_fsl_sht = {
1154 .dma_boundary = ATA_DMA_BOUNDARY, 1251 .dma_boundary = ATA_DMA_BOUNDARY,
1155}; 1252};
1156 1253
1157static const struct ata_port_operations sata_fsl_ops = { 1254static struct ata_port_operations sata_fsl_ops = {
1158 .inherits = &sata_port_ops, 1255 .inherits = &sata_pmp_port_ops,
1159 1256
1160 .qc_prep = sata_fsl_qc_prep, 1257 .qc_prep = sata_fsl_qc_prep,
1161 .qc_issue = sata_fsl_qc_issue, 1258 .qc_issue = sata_fsl_qc_issue,
@@ -1168,10 +1265,15 @@ static const struct ata_port_operations sata_fsl_ops = {
1168 .thaw = sata_fsl_thaw, 1265 .thaw = sata_fsl_thaw,
1169 .prereset = sata_fsl_prereset, 1266 .prereset = sata_fsl_prereset,
1170 .softreset = sata_fsl_softreset, 1267 .softreset = sata_fsl_softreset,
1268 .pmp_softreset = sata_fsl_softreset,
1269 .error_handler = sata_fsl_error_handler,
1171 .post_internal_cmd = sata_fsl_post_internal_cmd, 1270 .post_internal_cmd = sata_fsl_post_internal_cmd,
1172 1271
1173 .port_start = sata_fsl_port_start, 1272 .port_start = sata_fsl_port_start,
1174 .port_stop = sata_fsl_port_stop, 1273 .port_stop = sata_fsl_port_stop,
1274
1275 .pmp_attach = sata_fsl_pmp_attach,
1276 .pmp_detach = sata_fsl_pmp_detach,
1175}; 1277};
1176 1278
1177static const struct ata_port_info sata_fsl_port_info[] = { 1279static const struct ata_port_info sata_fsl_port_info[] = {
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index bb73b2222627..ad169ffbc4cb 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -72,7 +72,7 @@
72#include <linux/libata.h> 72#include <linux/libata.h>
73 73
74#define DRV_NAME "sata_mv" 74#define DRV_NAME "sata_mv"
75#define DRV_VERSION "1.20" 75#define DRV_VERSION "1.24"
76 76
77enum { 77enum {
78 /* BAR's are enumerated in terms of pci_resource_start() terms */ 78 /* BAR's are enumerated in terms of pci_resource_start() terms */
@@ -122,14 +122,17 @@ enum {
122 /* Host Flags */ 122 /* Host Flags */
123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
125 /* SoC integrated controllers, no PCI interface */
126 MV_FLAG_SOC = (1 << 28),
127 125
128 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 126 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
129 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 127 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
130 ATA_FLAG_PIO_POLLING, 128 ATA_FLAG_PIO_POLLING,
129
131 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, 130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
132 131
132 MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
133 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
134 ATA_FLAG_NCQ | ATA_FLAG_AN,
135
133 CRQB_FLAG_READ = (1 << 0), 136 CRQB_FLAG_READ = (1 << 0),
134 CRQB_TAG_SHIFT = 1, 137 CRQB_TAG_SHIFT = 1,
135 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 138 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
@@ -197,13 +200,6 @@ enum {
197 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 200 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
198 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 201 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
199 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 202 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
200 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
201 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
202 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
203 HC_MAIN_RSVD),
204 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
205 HC_MAIN_RSVD_5),
206 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
207 203
208 /* SATAHC registers */ 204 /* SATAHC registers */
209 HC_CFG_OFS = 0, 205 HC_CFG_OFS = 0,
@@ -221,12 +217,18 @@ enum {
221 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 217 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
222 SATA_ACTIVE_OFS = 0x350, 218 SATA_ACTIVE_OFS = 0x350,
223 SATA_FIS_IRQ_CAUSE_OFS = 0x364, 219 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
220 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
224 221
225 LTMODE_OFS = 0x30c, 222 LTMODE_OFS = 0x30c,
226 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 223 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
227 224
228 PHY_MODE3 = 0x310, 225 PHY_MODE3 = 0x310,
229 PHY_MODE4 = 0x314, 226 PHY_MODE4 = 0x314,
227 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
228 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
229 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
230 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
231
230 PHY_MODE2 = 0x330, 232 PHY_MODE2 = 0x330,
231 SATA_IFCTL_OFS = 0x344, 233 SATA_IFCTL_OFS = 0x344,
232 SATA_TESTCTL_OFS = 0x348, 234 SATA_TESTCTL_OFS = 0x348,
@@ -357,12 +359,12 @@ enum {
357 MV_HP_ERRATA_50XXB2 = (1 << 2), 359 MV_HP_ERRATA_50XXB2 = (1 << 2),
358 MV_HP_ERRATA_60X1B2 = (1 << 3), 360 MV_HP_ERRATA_60X1B2 = (1 << 3),
359 MV_HP_ERRATA_60X1C0 = (1 << 4), 361 MV_HP_ERRATA_60X1C0 = (1 << 4),
360 MV_HP_ERRATA_XX42A0 = (1 << 5),
361 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 362 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
362 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 363 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
363 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 364 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
364 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 365 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
365 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 366 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
367 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
366 368
367 /* Port private flags (pp_flags) */ 369 /* Port private flags (pp_flags) */
368 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 370 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
@@ -375,7 +377,7 @@ enum {
375#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 377#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
376#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 378#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
377#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 379#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
378#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) 380#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
379 381
380#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 382#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
381#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 383#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
@@ -459,6 +461,7 @@ struct mv_port_signal {
459 461
460struct mv_host_priv { 462struct mv_host_priv {
461 u32 hp_flags; 463 u32 hp_flags;
464 u32 main_irq_mask;
462 struct mv_port_signal signal[8]; 465 struct mv_port_signal signal[8];
463 const struct mv_hw_ops *ops; 466 const struct mv_hw_ops *ops;
464 int n_ports; 467 int n_ports;
@@ -640,25 +643,19 @@ static const struct ata_port_info mv_port_info[] = {
640 .port_ops = &mv6_ops, 643 .port_ops = &mv6_ops,
641 }, 644 },
642 { /* chip_6042 */ 645 { /* chip_6042 */
643 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 646 .flags = MV_GENIIE_FLAGS,
644 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
645 ATA_FLAG_NCQ,
646 .pio_mask = 0x1f, /* pio0-4 */ 647 .pio_mask = 0x1f, /* pio0-4 */
647 .udma_mask = ATA_UDMA6, 648 .udma_mask = ATA_UDMA6,
648 .port_ops = &mv_iie_ops, 649 .port_ops = &mv_iie_ops,
649 }, 650 },
650 { /* chip_7042 */ 651 { /* chip_7042 */
651 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 652 .flags = MV_GENIIE_FLAGS,
652 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
653 ATA_FLAG_NCQ,
654 .pio_mask = 0x1f, /* pio0-4 */ 653 .pio_mask = 0x1f, /* pio0-4 */
655 .udma_mask = ATA_UDMA6, 654 .udma_mask = ATA_UDMA6,
656 .port_ops = &mv_iie_ops, 655 .port_ops = &mv_iie_ops,
657 }, 656 },
658 { /* chip_soc */ 657 { /* chip_soc */
659 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 658 .flags = MV_GENIIE_FLAGS,
660 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
661 ATA_FLAG_NCQ | MV_FLAG_SOC,
662 .pio_mask = 0x1f, /* pio0-4 */ 659 .pio_mask = 0x1f, /* pio0-4 */
663 .udma_mask = ATA_UDMA6, 660 .udma_mask = ATA_UDMA6,
664 .port_ops = &mv_iie_ops, 661 .port_ops = &mv_iie_ops,
@@ -818,12 +815,7 @@ static void mv_set_edma_ptrs(void __iomem *port_mmio,
818 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 815 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
819 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 816 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
820 port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 817 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
821 818 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
822 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
823 writelfl((pp->crqb_dma & 0xffffffff) | index,
824 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
825 else
826 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
827 819
828 /* 820 /*
829 * initialize response queue 821 * initialize response queue
@@ -833,17 +825,38 @@ static void mv_set_edma_ptrs(void __iomem *port_mmio,
833 825
834 WARN_ON(pp->crpb_dma & 0xff); 826 WARN_ON(pp->crpb_dma & 0xff);
835 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 827 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
836 828 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
837 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
838 writelfl((pp->crpb_dma & 0xffffffff) | index,
839 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
840 else
841 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
842
843 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 829 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
844 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 830 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
845} 831}
846 832
833static void mv_set_main_irq_mask(struct ata_host *host,
834 u32 disable_bits, u32 enable_bits)
835{
836 struct mv_host_priv *hpriv = host->private_data;
837 u32 old_mask, new_mask;
838
839 old_mask = hpriv->main_irq_mask;
840 new_mask = (old_mask & ~disable_bits) | enable_bits;
841 if (new_mask != old_mask) {
842 hpriv->main_irq_mask = new_mask;
843 writelfl(new_mask, hpriv->main_irq_mask_addr);
844 }
845}
846
847static void mv_enable_port_irqs(struct ata_port *ap,
848 unsigned int port_bits)
849{
850 unsigned int shift, hardport, port = ap->port_no;
851 u32 disable_bits, enable_bits;
852
853 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
854
855 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
856 enable_bits = port_bits << shift;
857 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
858}
859
847/** 860/**
848 * mv_start_dma - Enable eDMA engine 861 * mv_start_dma - Enable eDMA engine
849 * @base: port base address 862 * @base: port base address
@@ -886,9 +899,11 @@ static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
886 mv_edma_cfg(ap, want_ncq); 899 mv_edma_cfg(ap, want_ncq);
887 900
888 /* clear FIS IRQ Cause */ 901 /* clear FIS IRQ Cause */
889 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 902 if (IS_GEN_IIE(hpriv))
903 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
890 904
891 mv_set_edma_ptrs(port_mmio, hpriv, pp); 905 mv_set_edma_ptrs(port_mmio, hpriv, pp);
906 mv_enable_port_irqs(ap, DONE_IRQ|ERR_IRQ);
892 907
893 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 908 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
894 pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 909 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
@@ -1231,7 +1246,7 @@ static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
1231 1246
1232 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1247 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1233 cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1248 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1234 if (HAS_PCI(ap->host)) 1249 if (!IS_SOC(hpriv))
1235 cfg |= (1 << 18); /* enab early completion */ 1250 cfg |= (1 << 18); /* enab early completion */
1236 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1251 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1237 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1252 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
@@ -1307,6 +1322,9 @@ static int mv_port_start(struct ata_port *ap)
1307 goto out_port_free_dma_mem; 1322 goto out_port_free_dma_mem;
1308 memset(pp->crpb, 0, MV_CRPB_Q_SZ); 1323 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1309 1324
1325 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1326 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1327 ap->flags |= ATA_FLAG_AN;
1310 /* 1328 /*
1311 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1329 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1312 * For later hardware, we need one unique sg_tbl per NCQ tag. 1330 * For later hardware, we need one unique sg_tbl per NCQ tag.
@@ -1341,6 +1359,7 @@ out_port_free_dma_mem:
1341static void mv_port_stop(struct ata_port *ap) 1359static void mv_port_stop(struct ata_port *ap)
1342{ 1360{
1343 mv_stop_edma(ap); 1361 mv_stop_edma(ap);
1362 mv_enable_port_irqs(ap, 0);
1344 mv_port_free_dma_mem(ap); 1363 mv_port_free_dma_mem(ap);
1345} 1364}
1346 1365
@@ -1576,12 +1595,31 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1576 1595
1577 if ((qc->tf.protocol != ATA_PROT_DMA) && 1596 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1578 (qc->tf.protocol != ATA_PROT_NCQ)) { 1597 (qc->tf.protocol != ATA_PROT_NCQ)) {
1598 static int limit_warnings = 10;
1599 /*
1600 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
1601 *
1602 * Someday, we might implement special polling workarounds
1603 * for these, but it all seems rather unnecessary since we
1604 * normally use only DMA for commands which transfer more
1605 * than a single block of data.
1606 *
1607 * Much of the time, this could just work regardless.
1608 * So for now, just log the incident, and allow the attempt.
1609 */
1610 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
1611 --limit_warnings;
1612 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
1613 ": attempting PIO w/multiple DRQ: "
1614 "this may fail due to h/w errata\n");
1615 }
1579 /* 1616 /*
1580 * We're about to send a non-EDMA capable command to the 1617 * We're about to send a non-EDMA capable command to the
1581 * port. Turn off EDMA so there won't be problems accessing 1618 * port. Turn off EDMA so there won't be problems accessing
1582 * shadow block, etc registers. 1619 * shadow block, etc registers.
1583 */ 1620 */
1584 mv_stop_edma(ap); 1621 mv_stop_edma(ap);
1622 mv_enable_port_irqs(ap, ERR_IRQ);
1585 mv_pmp_select(ap, qc->dev->link->pmp); 1623 mv_pmp_select(ap, qc->dev->link->pmp);
1586 return ata_sff_qc_issue(qc); 1624 return ata_sff_qc_issue(qc);
1587 } 1625 }
@@ -1670,6 +1708,18 @@ static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1670 } 1708 }
1671} 1709}
1672 1710
1711static int mv_req_q_empty(struct ata_port *ap)
1712{
1713 void __iomem *port_mmio = mv_ap_base(ap);
1714 u32 in_ptr, out_ptr;
1715
1716 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
1717 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1718 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1719 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1720 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
1721}
1722
1673static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 1723static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1674{ 1724{
1675 struct mv_port_priv *pp = ap->private_data; 1725 struct mv_port_priv *pp = ap->private_data;
@@ -1703,7 +1753,7 @@ static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1703 ap->qc_active, failed_links, 1753 ap->qc_active, failed_links,
1704 ap->nr_active_links); 1754 ap->nr_active_links);
1705 1755
1706 if (ap->nr_active_links <= failed_links) { 1756 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
1707 mv_process_crpb_entries(ap, pp); 1757 mv_process_crpb_entries(ap, pp);
1708 mv_stop_edma(ap); 1758 mv_stop_edma(ap);
1709 mv_eh_freeze(ap); 1759 mv_eh_freeze(ap);
@@ -1812,6 +1862,7 @@ static void mv_err_intr(struct ata_port *ap)
1812{ 1862{
1813 void __iomem *port_mmio = mv_ap_base(ap); 1863 void __iomem *port_mmio = mv_ap_base(ap);
1814 u32 edma_err_cause, eh_freeze_mask, serr = 0; 1864 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1865 u32 fis_cause = 0;
1815 struct mv_port_priv *pp = ap->private_data; 1866 struct mv_port_priv *pp = ap->private_data;
1816 struct mv_host_priv *hpriv = ap->host->private_data; 1867 struct mv_host_priv *hpriv = ap->host->private_data;
1817 unsigned int action = 0, err_mask = 0; 1868 unsigned int action = 0, err_mask = 0;
@@ -1821,16 +1872,19 @@ static void mv_err_intr(struct ata_port *ap)
1821 1872
1822 /* 1873 /*
1823 * Read and clear the SError and err_cause bits. 1874 * Read and clear the SError and err_cause bits.
1875 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1876 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
1824 */ 1877 */
1825 sata_scr_read(&ap->link, SCR_ERROR, &serr); 1878 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1826 sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 1879 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1827 1880
1828 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1881 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1882 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1883 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1884 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1885 }
1829 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1886 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1830 1887
1831 ata_port_printk(ap, KERN_INFO, "%s: err_cause=%08x pp_flags=0x%x\n",
1832 __func__, edma_err_cause, pp->pp_flags);
1833
1834 if (edma_err_cause & EDMA_ERR_DEV) { 1888 if (edma_err_cause & EDMA_ERR_DEV) {
1835 /* 1889 /*
1836 * Device errors during FIS-based switching operation 1890 * Device errors during FIS-based switching operation
@@ -1844,6 +1898,18 @@ static void mv_err_intr(struct ata_port *ap)
1844 ata_ehi_clear_desc(ehi); 1898 ata_ehi_clear_desc(ehi);
1845 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 1899 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1846 edma_err_cause, pp->pp_flags); 1900 edma_err_cause, pp->pp_flags);
1901
1902 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1903 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
1904 if (fis_cause & SATA_FIS_IRQ_AN) {
1905 u32 ec = edma_err_cause &
1906 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
1907 sata_async_notification(ap);
1908 if (!ec)
1909 return; /* Just an AN; no need for the nukes */
1910 ata_ehi_push_desc(ehi, "SDB notify");
1911 }
1912 }
1847 /* 1913 /*
1848 * All generations share these EDMA error cause bits: 1914 * All generations share these EDMA error cause bits:
1849 */ 1915 */
@@ -2162,20 +2228,20 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2162 struct ata_host *host = dev_instance; 2228 struct ata_host *host = dev_instance;
2163 struct mv_host_priv *hpriv = host->private_data; 2229 struct mv_host_priv *hpriv = host->private_data;
2164 unsigned int handled = 0; 2230 unsigned int handled = 0;
2165 u32 main_irq_cause, main_irq_mask; 2231 u32 main_irq_cause, pending_irqs;
2166 2232
2167 spin_lock(&host->lock); 2233 spin_lock(&host->lock);
2168 main_irq_cause = readl(hpriv->main_irq_cause_addr); 2234 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2169 main_irq_mask = readl(hpriv->main_irq_mask_addr); 2235 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2170 /* 2236 /*
2171 * Deal with cases where we either have nothing pending, or have read 2237 * Deal with cases where we either have nothing pending, or have read
2172 * a bogus register value which can indicate HW removal or PCI fault. 2238 * a bogus register value which can indicate HW removal or PCI fault.
2173 */ 2239 */
2174 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) { 2240 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2175 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host))) 2241 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2176 handled = mv_pci_error(host, hpriv->base); 2242 handled = mv_pci_error(host, hpriv->base);
2177 else 2243 else
2178 handled = mv_host_intr(host, main_irq_cause); 2244 handled = mv_host_intr(host, pending_irqs);
2179 } 2245 }
2180 spin_unlock(&host->lock); 2246 spin_unlock(&host->lock);
2181 return IRQ_RETVAL(handled); 2247 return IRQ_RETVAL(handled);
@@ -2373,7 +2439,6 @@ static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
2373 ZERO(MV_PCI_DISC_TIMER); 2439 ZERO(MV_PCI_DISC_TIMER);
2374 ZERO(MV_PCI_MSI_TRIGGER); 2440 ZERO(MV_PCI_MSI_TRIGGER);
2375 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS); 2441 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
2376 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
2377 ZERO(MV_PCI_SERR_MASK); 2442 ZERO(MV_PCI_SERR_MASK);
2378 ZERO(hpriv->irq_cause_ofs); 2443 ZERO(hpriv->irq_cause_ofs);
2379 ZERO(hpriv->irq_mask_ofs); 2444 ZERO(hpriv->irq_mask_ofs);
@@ -2495,7 +2560,7 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2495 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2560 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2496 int fix_phy_mode4 = 2561 int fix_phy_mode4 =
2497 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2562 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2498 u32 m2, tmp; 2563 u32 m2, m3;
2499 2564
2500 if (fix_phy_mode2) { 2565 if (fix_phy_mode2) {
2501 m2 = readl(port_mmio + PHY_MODE2); 2566 m2 = readl(port_mmio + PHY_MODE2);
@@ -2512,28 +2577,36 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2512 udelay(200); 2577 udelay(200);
2513 } 2578 }
2514 2579
2515 /* who knows what this magic does */ 2580 /*
2516 tmp = readl(port_mmio + PHY_MODE3); 2581 * Gen-II/IIe PHY_MODE3 errata RM#2:
2517 tmp &= ~0x7F800000; 2582 * Achieves better receiver noise performance than the h/w default:
2518 tmp |= 0x2A800000; 2583 */
2519 writel(tmp, port_mmio + PHY_MODE3); 2584 m3 = readl(port_mmio + PHY_MODE3);
2520 2585 m3 = (m3 & 0x1f) | (0x5555601 << 5);
2521 if (fix_phy_mode4) {
2522 u32 m4;
2523
2524 m4 = readl(port_mmio + PHY_MODE4);
2525
2526 if (hp_flags & MV_HP_ERRATA_60X1B2)
2527 tmp = readl(port_mmio + PHY_MODE3);
2528 2586
2529 /* workaround for errata FEr SATA#10 (part 1) */ 2587 /* Guideline 88F5182 (GL# SATA-S11) */
2530 m4 = (m4 & ~(1 << 1)) | (1 << 0); 2588 if (IS_SOC(hpriv))
2589 m3 &= ~0x1c;
2531 2590
2591 if (fix_phy_mode4) {
2592 u32 m4 = readl(port_mmio + PHY_MODE4);
2593 /*
2594 * Enforce reserved-bit restrictions on GenIIe devices only.
2595 * For earlier chipsets, force only the internal config field
2596 * (workaround for errata FEr SATA#10 part 1).
2597 */
2598 if (IS_GEN_IIE(hpriv))
2599 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
2600 else
2601 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
2532 writel(m4, port_mmio + PHY_MODE4); 2602 writel(m4, port_mmio + PHY_MODE4);
2533
2534 if (hp_flags & MV_HP_ERRATA_60X1B2)
2535 writel(tmp, port_mmio + PHY_MODE3);
2536 } 2603 }
2604 /*
2605 * Workaround for 60x1-B2 errata SATA#13:
2606 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
2607 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
2608 */
2609 writel(m3, port_mmio + PHY_MODE3);
2537 2610
2538 /* Revert values of pre-emphasis and signal amps to the saved ones */ 2611 /* Revert values of pre-emphasis and signal amps to the saved ones */
2539 m2 = readl(port_mmio + PHY_MODE2); 2612 m2 = readl(port_mmio + PHY_MODE2);
@@ -2728,6 +2801,7 @@ static int mv_hardreset(struct ata_link *link, unsigned int *class,
2728 2801
2729 rc = sata_link_hardreset(link, timing, deadline + extra, 2802 rc = sata_link_hardreset(link, timing, deadline + extra,
2730 &online, NULL); 2803 &online, NULL);
2804 rc = online ? -EAGAIN : rc;
2731 if (rc) 2805 if (rc)
2732 return rc; 2806 return rc;
2733 sata_scr_read(link, SCR_STATUS, &sstatus); 2807 sata_scr_read(link, SCR_STATUS, &sstatus);
@@ -2744,32 +2818,18 @@ static int mv_hardreset(struct ata_link *link, unsigned int *class,
2744 2818
2745static void mv_eh_freeze(struct ata_port *ap) 2819static void mv_eh_freeze(struct ata_port *ap)
2746{ 2820{
2747 struct mv_host_priv *hpriv = ap->host->private_data;
2748 unsigned int shift, hardport, port = ap->port_no;
2749 u32 main_irq_mask;
2750
2751 /* FIXME: handle coalescing completion events properly */
2752
2753 mv_stop_edma(ap); 2821 mv_stop_edma(ap);
2754 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2822 mv_enable_port_irqs(ap, 0);
2755
2756 /* disable assertion of portN err, done events */
2757 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2758 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2759 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2760} 2823}
2761 2824
2762static void mv_eh_thaw(struct ata_port *ap) 2825static void mv_eh_thaw(struct ata_port *ap)
2763{ 2826{
2764 struct mv_host_priv *hpriv = ap->host->private_data; 2827 struct mv_host_priv *hpriv = ap->host->private_data;
2765 unsigned int shift, hardport, port = ap->port_no; 2828 unsigned int port = ap->port_no;
2829 unsigned int hardport = mv_hardport_from_port(port);
2766 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 2830 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
2767 void __iomem *port_mmio = mv_ap_base(ap); 2831 void __iomem *port_mmio = mv_ap_base(ap);
2768 u32 main_irq_mask, hc_irq_cause; 2832 u32 hc_irq_cause;
2769
2770 /* FIXME: handle coalescing completion events properly */
2771
2772 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2773 2833
2774 /* clear EDMA errors on this port */ 2834 /* clear EDMA errors on this port */
2775 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2835 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
@@ -2779,10 +2839,7 @@ static void mv_eh_thaw(struct ata_port *ap)
2779 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport); 2839 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2780 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2840 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
2781 2841
2782 /* enable assertion of portN err, done events */ 2842 mv_enable_port_irqs(ap, ERR_IRQ);
2783 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2784 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2785 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2786} 2843}
2787 2844
2788/** 2845/**
@@ -2840,7 +2897,7 @@ static unsigned int mv_in_pcix_mode(struct ata_host *host)
2840 void __iomem *mmio = hpriv->base; 2897 void __iomem *mmio = hpriv->base;
2841 u32 reg; 2898 u32 reg;
2842 2899
2843 if (!HAS_PCI(host) || !IS_PCIE(hpriv)) 2900 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
2844 return 0; /* not PCI-X capable */ 2901 return 0; /* not PCI-X capable */
2845 reg = readl(mmio + MV_PCI_MODE_OFS); 2902 reg = readl(mmio + MV_PCI_MODE_OFS);
2846 if ((reg & MV_PCI_MODE_MASK) == 0) 2903 if ((reg & MV_PCI_MODE_MASK) == 0)
@@ -2967,10 +3024,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2967 hp_flags |= MV_HP_CUT_THROUGH; 3024 hp_flags |= MV_HP_CUT_THROUGH;
2968 3025
2969 switch (pdev->revision) { 3026 switch (pdev->revision) {
2970 case 0x0: 3027 case 0x2: /* Rev.B0: the first/only public release */
2971 hp_flags |= MV_HP_ERRATA_XX42A0;
2972 break;
2973 case 0x1:
2974 hp_flags |= MV_HP_ERRATA_60X1C0; 3028 hp_flags |= MV_HP_ERRATA_60X1C0;
2975 break; 3029 break;
2976 default: 3030 default:
@@ -2982,7 +3036,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2982 break; 3036 break;
2983 case chip_soc: 3037 case chip_soc:
2984 hpriv->ops = &mv_soc_ops; 3038 hpriv->ops = &mv_soc_ops;
2985 hp_flags |= MV_HP_ERRATA_60X1C0; 3039 hp_flags |= MV_HP_FLAG_SOC | MV_HP_ERRATA_60X1C0;
2986 break; 3040 break;
2987 3041
2988 default: 3042 default:
@@ -3026,16 +3080,16 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3026 if (rc) 3080 if (rc)
3027 goto done; 3081 goto done;
3028 3082
3029 if (HAS_PCI(host)) { 3083 if (IS_SOC(hpriv)) {
3030 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3031 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3032 } else {
3033 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS; 3084 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3034 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS; 3085 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3086 } else {
3087 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3088 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3035 } 3089 }
3036 3090
3037 /* global interrupt mask: 0 == mask everything */ 3091 /* global interrupt mask: 0 == mask everything */
3038 writel(0, hpriv->main_irq_mask_addr); 3092 mv_set_main_irq_mask(host, ~0, 0);
3039 3093
3040 n_hc = mv_get_hc_count(host->ports[0]->flags); 3094 n_hc = mv_get_hc_count(host->ports[0]->flags);
3041 3095
@@ -3057,7 +3111,7 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3057 mv_port_init(&ap->ioaddr, port_mmio); 3111 mv_port_init(&ap->ioaddr, port_mmio);
3058 3112
3059#ifdef CONFIG_PCI 3113#ifdef CONFIG_PCI
3060 if (HAS_PCI(host)) { 3114 if (!IS_SOC(hpriv)) {
3061 unsigned int offset = port_mmio - mmio; 3115 unsigned int offset = port_mmio - mmio;
3062 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 3116 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3063 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 3117 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
@@ -3077,31 +3131,18 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3077 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 3131 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3078 } 3132 }
3079 3133
3080 if (HAS_PCI(host)) { 3134 if (!IS_SOC(hpriv)) {
3081 /* Clear any currently outstanding host interrupt conditions */ 3135 /* Clear any currently outstanding host interrupt conditions */
3082 writelfl(0, mmio + hpriv->irq_cause_ofs); 3136 writelfl(0, mmio + hpriv->irq_cause_ofs);
3083 3137
3084 /* and unmask interrupt generation for host regs */ 3138 /* and unmask interrupt generation for host regs */
3085 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 3139 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3086 if (IS_GEN_I(hpriv)) 3140
3087 writelfl(~HC_MAIN_MASKED_IRQS_5, 3141 /*
3088 hpriv->main_irq_mask_addr); 3142 * enable only global host interrupts for now.
3089 else 3143 * The per-port interrupts get done later as ports are set up.
3090 writelfl(~HC_MAIN_MASKED_IRQS, 3144 */
3091 hpriv->main_irq_mask_addr); 3145 mv_set_main_irq_mask(host, 0, PCI_ERR);
3092
3093 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
3094 "PCI int cause/mask=0x%08x/0x%08x\n",
3095 readl(hpriv->main_irq_cause_addr),
3096 readl(hpriv->main_irq_mask_addr),
3097 readl(mmio + hpriv->irq_cause_ofs),
3098 readl(mmio + hpriv->irq_mask_ofs));
3099 } else {
3100 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
3101 hpriv->main_irq_mask_addr);
3102 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
3103 readl(hpriv->main_irq_cause_addr),
3104 readl(hpriv->main_irq_mask_addr));
3105 } 3146 }
3106done: 3147done:
3107 return rc; 3148 return rc;
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c
index 5a10dc5048ad..030665ba76b7 100644
--- a/drivers/ata/sata_promise.c
+++ b/drivers/ata/sata_promise.c
@@ -53,7 +53,15 @@ enum {
53 PDC_MMIO_BAR = 3, 53 PDC_MMIO_BAR = 3,
54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */ 54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
55 55
56 /* register offsets */ 56 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
58 PDC_FLASH_CTL = 0x44, /* Flash control register */
59 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
60 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
61 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
62 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
63
64 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
57 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ 65 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
58 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ 66 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
59 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ 67 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
@@ -63,14 +71,11 @@ enum {
63 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ 71 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
64 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ 72 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
65 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ 73 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
66 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
67 PDC_FLASH_CTL = 0x44, /* Flash control register */
68 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ 74 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
69 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ 75 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
70 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ 76
71 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ 77 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
72 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ 78 PDC_PHYMODE4 = 0x14,
73 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
74 79
75 /* PDC_GLOBAL_CTL bit definitions */ 80 /* PDC_GLOBAL_CTL bit definitions */
76 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ 81 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
@@ -134,7 +139,7 @@ struct pdc_port_priv {
134 139
135static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); 140static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
136static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); 141static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
137static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 142static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
138static int pdc_common_port_start(struct ata_port *ap); 143static int pdc_common_port_start(struct ata_port *ap);
139static int pdc_sata_port_start(struct ata_port *ap); 144static int pdc_sata_port_start(struct ata_port *ap);
140static void pdc_qc_prep(struct ata_queued_cmd *qc); 145static void pdc_qc_prep(struct ata_queued_cmd *qc);
@@ -332,12 +337,12 @@ static int pdc_sata_port_start(struct ata_port *ap)
332 337
333 /* fix up PHYMODE4 align timing */ 338 /* fix up PHYMODE4 align timing */
334 if (ap->flags & PDC_FLAG_GEN_II) { 339 if (ap->flags & PDC_FLAG_GEN_II) {
335 void __iomem *mmio = ap->ioaddr.scr_addr; 340 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
336 unsigned int tmp; 341 unsigned int tmp;
337 342
338 tmp = readl(mmio + 0x014); 343 tmp = readl(sata_mmio + PDC_PHYMODE4);
339 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ 344 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
340 writel(tmp, mmio + 0x014); 345 writel(tmp, sata_mmio + PDC_PHYMODE4);
341 } 346 }
342 347
343 return 0; 348 return 0;
@@ -345,32 +350,32 @@ static int pdc_sata_port_start(struct ata_port *ap)
345 350
346static void pdc_reset_port(struct ata_port *ap) 351static void pdc_reset_port(struct ata_port *ap)
347{ 352{
348 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; 353 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
349 unsigned int i; 354 unsigned int i;
350 u32 tmp; 355 u32 tmp;
351 356
352 for (i = 11; i > 0; i--) { 357 for (i = 11; i > 0; i--) {
353 tmp = readl(mmio); 358 tmp = readl(ata_ctlstat_mmio);
354 if (tmp & PDC_RESET) 359 if (tmp & PDC_RESET)
355 break; 360 break;
356 361
357 udelay(100); 362 udelay(100);
358 363
359 tmp |= PDC_RESET; 364 tmp |= PDC_RESET;
360 writel(tmp, mmio); 365 writel(tmp, ata_ctlstat_mmio);
361 } 366 }
362 367
363 tmp &= ~PDC_RESET; 368 tmp &= ~PDC_RESET;
364 writel(tmp, mmio); 369 writel(tmp, ata_ctlstat_mmio);
365 readl(mmio); /* flush */ 370 readl(ata_ctlstat_mmio); /* flush */
366} 371}
367 372
368static int pdc_pata_cable_detect(struct ata_port *ap) 373static int pdc_pata_cable_detect(struct ata_port *ap)
369{ 374{
370 u8 tmp; 375 u8 tmp;
371 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; 376 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
372 377
373 tmp = readb(mmio); 378 tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
374 if (tmp & 0x01) 379 if (tmp & 0x01)
375 return ATA_CBL_PATA40; 380 return ATA_CBL_PATA40;
376 return ATA_CBL_PATA80; 381 return ATA_CBL_PATA80;
@@ -557,31 +562,25 @@ static void pdc_qc_prep(struct ata_queued_cmd *qc)
557 switch (qc->tf.protocol) { 562 switch (qc->tf.protocol) {
558 case ATA_PROT_DMA: 563 case ATA_PROT_DMA:
559 pdc_fill_sg(qc); 564 pdc_fill_sg(qc);
560 /* fall through */ 565 /*FALLTHROUGH*/
561
562 case ATA_PROT_NODATA: 566 case ATA_PROT_NODATA:
563 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, 567 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
564 qc->dev->devno, pp->pkt); 568 qc->dev->devno, pp->pkt);
565
566 if (qc->tf.flags & ATA_TFLAG_LBA48) 569 if (qc->tf.flags & ATA_TFLAG_LBA48)
567 i = pdc_prep_lba48(&qc->tf, pp->pkt, i); 570 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
568 else 571 else
569 i = pdc_prep_lba28(&qc->tf, pp->pkt, i); 572 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
570
571 pdc_pkt_footer(&qc->tf, pp->pkt, i); 573 pdc_pkt_footer(&qc->tf, pp->pkt, i);
572 break; 574 break;
573
574 case ATAPI_PROT_PIO: 575 case ATAPI_PROT_PIO:
575 pdc_fill_sg(qc); 576 pdc_fill_sg(qc);
576 break; 577 break;
577
578 case ATAPI_PROT_DMA: 578 case ATAPI_PROT_DMA:
579 pdc_fill_sg(qc); 579 pdc_fill_sg(qc);
580 /*FALLTHROUGH*/ 580 /*FALLTHROUGH*/
581 case ATAPI_PROT_NODATA: 581 case ATAPI_PROT_NODATA:
582 pdc_atapi_pkt(qc); 582 pdc_atapi_pkt(qc);
583 break; 583 break;
584
585 default: 584 default:
586 break; 585 break;
587 } 586 }
@@ -611,7 +610,7 @@ static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
611 unsigned int nr_ports = pdc_sata_nr_ports(ap); 610 unsigned int nr_ports = pdc_sata_nr_ports(ap);
612 unsigned int i; 611 unsigned int i;
613 612
614 for(i = 0; i < nr_ports && host->ports[i] != ap; ++i) 613 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
615 ; 614 ;
616 BUG_ON(i >= nr_ports); 615 BUG_ON(i >= nr_ports);
617 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags)); 616 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
@@ -624,14 +623,14 @@ static unsigned int pdc_sata_hotplug_offset(const struct ata_port *ap)
624 623
625static void pdc_freeze(struct ata_port *ap) 624static void pdc_freeze(struct ata_port *ap)
626{ 625{
627 void __iomem *mmio = ap->ioaddr.cmd_addr; 626 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
628 u32 tmp; 627 u32 tmp;
629 628
630 tmp = readl(mmio + PDC_CTLSTAT); 629 tmp = readl(ata_mmio + PDC_CTLSTAT);
631 tmp |= PDC_IRQ_DISABLE; 630 tmp |= PDC_IRQ_DISABLE;
632 tmp &= ~PDC_DMA_ENABLE; 631 tmp &= ~PDC_DMA_ENABLE;
633 writel(tmp, mmio + PDC_CTLSTAT); 632 writel(tmp, ata_mmio + PDC_CTLSTAT);
634 readl(mmio + PDC_CTLSTAT); /* flush */ 633 readl(ata_mmio + PDC_CTLSTAT); /* flush */
635} 634}
636 635
637static void pdc_sata_freeze(struct ata_port *ap) 636static void pdc_sata_freeze(struct ata_port *ap)
@@ -659,17 +658,17 @@ static void pdc_sata_freeze(struct ata_port *ap)
659 658
660static void pdc_thaw(struct ata_port *ap) 659static void pdc_thaw(struct ata_port *ap)
661{ 660{
662 void __iomem *mmio = ap->ioaddr.cmd_addr; 661 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
663 u32 tmp; 662 u32 tmp;
664 663
665 /* clear IRQ */ 664 /* clear IRQ */
666 readl(mmio + PDC_INT_SEQMASK); 665 readl(ata_mmio + PDC_COMMAND);
667 666
668 /* turn IRQ back on */ 667 /* turn IRQ back on */
669 tmp = readl(mmio + PDC_CTLSTAT); 668 tmp = readl(ata_mmio + PDC_CTLSTAT);
670 tmp &= ~PDC_IRQ_DISABLE; 669 tmp &= ~PDC_IRQ_DISABLE;
671 writel(tmp, mmio + PDC_CTLSTAT); 670 writel(tmp, ata_mmio + PDC_CTLSTAT);
672 readl(mmio + PDC_CTLSTAT); /* flush */ 671 readl(ata_mmio + PDC_CTLSTAT); /* flush */
673} 672}
674 673
675static void pdc_sata_thaw(struct ata_port *ap) 674static void pdc_sata_thaw(struct ata_port *ap)
@@ -743,11 +742,11 @@ static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
743 ata_port_abort(ap); 742 ata_port_abort(ap);
744} 743}
745 744
746static inline unsigned int pdc_host_intr(struct ata_port *ap, 745static unsigned int pdc_host_intr(struct ata_port *ap,
747 struct ata_queued_cmd *qc) 746 struct ata_queued_cmd *qc)
748{ 747{
749 unsigned int handled = 0; 748 unsigned int handled = 0;
750 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 749 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
751 u32 port_status, err_mask; 750 u32 port_status, err_mask;
752 751
753 err_mask = PDC_ERR_MASK; 752 err_mask = PDC_ERR_MASK;
@@ -755,7 +754,7 @@ static inline unsigned int pdc_host_intr(struct ata_port *ap,
755 err_mask &= ~PDC1_ERR_MASK; 754 err_mask &= ~PDC1_ERR_MASK;
756 else 755 else
757 err_mask &= ~PDC2_ERR_MASK; 756 err_mask &= ~PDC2_ERR_MASK;
758 port_status = readl(port_mmio + PDC_GLOBAL_CTL); 757 port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
759 if (unlikely(port_status & err_mask)) { 758 if (unlikely(port_status & err_mask)) {
760 pdc_error_intr(ap, qc, port_status, err_mask); 759 pdc_error_intr(ap, qc, port_status, err_mask);
761 return 1; 760 return 1;
@@ -770,7 +769,6 @@ static inline unsigned int pdc_host_intr(struct ata_port *ap,
770 ata_qc_complete(qc); 769 ata_qc_complete(qc);
771 handled = 1; 770 handled = 1;
772 break; 771 break;
773
774 default: 772 default:
775 ap->stats.idle_irq++; 773 ap->stats.idle_irq++;
776 break; 774 break;
@@ -781,10 +779,9 @@ static inline unsigned int pdc_host_intr(struct ata_port *ap,
781 779
782static void pdc_irq_clear(struct ata_port *ap) 780static void pdc_irq_clear(struct ata_port *ap)
783{ 781{
784 struct ata_host *host = ap->host; 782 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
785 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
786 783
787 readl(mmio + PDC_INT_SEQMASK); 784 readl(ata_mmio + PDC_COMMAND);
788} 785}
789 786
790static irqreturn_t pdc_interrupt(int irq, void *dev_instance) 787static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
@@ -794,7 +791,7 @@ static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
794 u32 mask = 0; 791 u32 mask = 0;
795 unsigned int i, tmp; 792 unsigned int i, tmp;
796 unsigned int handled = 0; 793 unsigned int handled = 0;
797 void __iomem *mmio_base; 794 void __iomem *host_mmio;
798 unsigned int hotplug_offset, ata_no; 795 unsigned int hotplug_offset, ata_no;
799 u32 hotplug_status; 796 u32 hotplug_status;
800 int is_sataii_tx4; 797 int is_sataii_tx4;
@@ -806,7 +803,7 @@ static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
806 return IRQ_NONE; 803 return IRQ_NONE;
807 } 804 }
808 805
809 mmio_base = host->iomap[PDC_MMIO_BAR]; 806 host_mmio = host->iomap[PDC_MMIO_BAR];
810 807
811 spin_lock(&host->lock); 808 spin_lock(&host->lock);
812 809
@@ -815,26 +812,26 @@ static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
815 hotplug_offset = PDC2_SATA_PLUG_CSR; 812 hotplug_offset = PDC2_SATA_PLUG_CSR;
816 else 813 else
817 hotplug_offset = PDC_SATA_PLUG_CSR; 814 hotplug_offset = PDC_SATA_PLUG_CSR;
818 hotplug_status = readl(mmio_base + hotplug_offset); 815 hotplug_status = readl(host_mmio + hotplug_offset);
819 if (hotplug_status & 0xff) 816 if (hotplug_status & 0xff)
820 writel(hotplug_status | 0xff, mmio_base + hotplug_offset); 817 writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
821 hotplug_status &= 0xff; /* clear uninteresting bits */ 818 hotplug_status &= 0xff; /* clear uninteresting bits */
822 819
823 /* reading should also clear interrupts */ 820 /* reading should also clear interrupts */
824 mask = readl(mmio_base + PDC_INT_SEQMASK); 821 mask = readl(host_mmio + PDC_INT_SEQMASK);
825 822
826 if (mask == 0xffffffff && hotplug_status == 0) { 823 if (mask == 0xffffffff && hotplug_status == 0) {
827 VPRINTK("QUICK EXIT 2\n"); 824 VPRINTK("QUICK EXIT 2\n");
828 goto done_irq; 825 goto done_irq;
829 } 826 }
830 827
831 mask &= 0xffff; /* only 16 tags possible */ 828 mask &= 0xffff; /* only 16 SEQIDs possible */
832 if (mask == 0 && hotplug_status == 0) { 829 if (mask == 0 && hotplug_status == 0) {
833 VPRINTK("QUICK EXIT 3\n"); 830 VPRINTK("QUICK EXIT 3\n");
834 goto done_irq; 831 goto done_irq;
835 } 832 }
836 833
837 writel(mask, mmio_base + PDC_INT_SEQMASK); 834 writel(mask, host_mmio + PDC_INT_SEQMASK);
838 835
839 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); 836 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
840 837
@@ -875,23 +872,24 @@ done_irq:
875 return IRQ_RETVAL(handled); 872 return IRQ_RETVAL(handled);
876} 873}
877 874
878static inline void pdc_packet_start(struct ata_queued_cmd *qc) 875static void pdc_packet_start(struct ata_queued_cmd *qc)
879{ 876{
880 struct ata_port *ap = qc->ap; 877 struct ata_port *ap = qc->ap;
881 struct pdc_port_priv *pp = ap->private_data; 878 struct pdc_port_priv *pp = ap->private_data;
882 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; 879 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
880 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
883 unsigned int port_no = ap->port_no; 881 unsigned int port_no = ap->port_no;
884 u8 seq = (u8) (port_no + 1); 882 u8 seq = (u8) (port_no + 1);
885 883
886 VPRINTK("ENTER, ap %p\n", ap); 884 VPRINTK("ENTER, ap %p\n", ap);
887 885
888 writel(0x00000001, mmio + (seq * 4)); 886 writel(0x00000001, host_mmio + (seq * 4));
889 readl(mmio + (seq * 4)); /* flush */ 887 readl(host_mmio + (seq * 4)); /* flush */
890 888
891 pp->pkt[2] = seq; 889 pp->pkt[2] = seq;
892 wmb(); /* flush PRD, pkt writes */ 890 wmb(); /* flush PRD, pkt writes */
893 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); 891 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
894 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ 892 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
895} 893}
896 894
897static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc) 895static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
@@ -909,11 +907,9 @@ static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
909 case ATA_PROT_DMA: 907 case ATA_PROT_DMA:
910 pdc_packet_start(qc); 908 pdc_packet_start(qc);
911 return 0; 909 return 0;
912
913 default: 910 default:
914 break; 911 break;
915 } 912 }
916
917 return ata_sff_qc_issue(qc); 913 return ata_sff_qc_issue(qc);
918} 914}
919 915
@@ -987,7 +983,7 @@ static void pdc_ata_setup_port(struct ata_port *ap,
987 983
988static void pdc_host_init(struct ata_host *host) 984static void pdc_host_init(struct ata_host *host)
989{ 985{
990 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; 986 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
991 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; 987 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
992 int hotplug_offset; 988 int hotplug_offset;
993 u32 tmp; 989 u32 tmp;
@@ -1004,38 +1000,38 @@ static void pdc_host_init(struct ata_host *host)
1004 */ 1000 */
1005 1001
1006 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ 1002 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1007 tmp = readl(mmio + PDC_FLASH_CTL); 1003 tmp = readl(host_mmio + PDC_FLASH_CTL);
1008 tmp |= 0x02000; /* bit 13 (enable bmr burst) */ 1004 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1009 if (!is_gen2) 1005 if (!is_gen2)
1010 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ 1006 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1011 writel(tmp, mmio + PDC_FLASH_CTL); 1007 writel(tmp, host_mmio + PDC_FLASH_CTL);
1012 1008
1013 /* clear plug/unplug flags for all ports */ 1009 /* clear plug/unplug flags for all ports */
1014 tmp = readl(mmio + hotplug_offset); 1010 tmp = readl(host_mmio + hotplug_offset);
1015 writel(tmp | 0xff, mmio + hotplug_offset); 1011 writel(tmp | 0xff, host_mmio + hotplug_offset);
1016 1012
1017 /* unmask plug/unplug ints */ 1013 /* unmask plug/unplug ints */
1018 tmp = readl(mmio + hotplug_offset); 1014 tmp = readl(host_mmio + hotplug_offset);
1019 writel(tmp & ~0xff0000, mmio + hotplug_offset); 1015 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1020 1016
1021 /* don't initialise TBG or SLEW on 2nd generation chips */ 1017 /* don't initialise TBG or SLEW on 2nd generation chips */
1022 if (is_gen2) 1018 if (is_gen2)
1023 return; 1019 return;
1024 1020
1025 /* reduce TBG clock to 133 Mhz. */ 1021 /* reduce TBG clock to 133 Mhz. */
1026 tmp = readl(mmio + PDC_TBG_MODE); 1022 tmp = readl(host_mmio + PDC_TBG_MODE);
1027 tmp &= ~0x30000; /* clear bit 17, 16*/ 1023 tmp &= ~0x30000; /* clear bit 17, 16*/
1028 tmp |= 0x10000; /* set bit 17:16 = 0:1 */ 1024 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1029 writel(tmp, mmio + PDC_TBG_MODE); 1025 writel(tmp, host_mmio + PDC_TBG_MODE);
1030 1026
1031 readl(mmio + PDC_TBG_MODE); /* flush */ 1027 readl(host_mmio + PDC_TBG_MODE); /* flush */
1032 msleep(10); 1028 msleep(10);
1033 1029
1034 /* adjust slew rate control register. */ 1030 /* adjust slew rate control register. */
1035 tmp = readl(mmio + PDC_SLEW_CTL); 1031 tmp = readl(host_mmio + PDC_SLEW_CTL);
1036 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ 1032 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1037 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ 1033 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1038 writel(tmp, mmio + PDC_SLEW_CTL); 1034 writel(tmp, host_mmio + PDC_SLEW_CTL);
1039} 1035}
1040 1036
1041static int pdc_ata_init_one(struct pci_dev *pdev, 1037static int pdc_ata_init_one(struct pci_dev *pdev,
@@ -1045,7 +1041,7 @@ static int pdc_ata_init_one(struct pci_dev *pdev,
1045 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; 1041 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1046 const struct ata_port_info *ppi[PDC_MAX_PORTS]; 1042 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1047 struct ata_host *host; 1043 struct ata_host *host;
1048 void __iomem *base; 1044 void __iomem *host_mmio;
1049 int n_ports, i, rc; 1045 int n_ports, i, rc;
1050 int is_sataii_tx4; 1046 int is_sataii_tx4;
1051 1047
@@ -1062,7 +1058,7 @@ static int pdc_ata_init_one(struct pci_dev *pdev,
1062 pcim_pin_device(pdev); 1058 pcim_pin_device(pdev);
1063 if (rc) 1059 if (rc)
1064 return rc; 1060 return rc;
1065 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; 1061 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1066 1062
1067 /* determine port configuration and setup host */ 1063 /* determine port configuration and setup host */
1068 n_ports = 2; 1064 n_ports = 2;
@@ -1072,7 +1068,7 @@ static int pdc_ata_init_one(struct pci_dev *pdev,
1072 ppi[i] = pi; 1068 ppi[i] = pi;
1073 1069
1074 if (pi->flags & PDC_FLAG_SATA_PATA) { 1070 if (pi->flags & PDC_FLAG_SATA_PATA) {
1075 u8 tmp = readb(base + PDC_FLASH_CTL+1); 1071 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
1076 if (!(tmp & 0x80)) 1072 if (!(tmp & 0x80))
1077 ppi[n_ports++] = pi + 1; 1073 ppi[n_ports++] = pi + 1;
1078 } 1074 }
@@ -1088,13 +1084,13 @@ static int pdc_ata_init_one(struct pci_dev *pdev,
1088 for (i = 0; i < host->n_ports; i++) { 1084 for (i = 0; i < host->n_ports; i++) {
1089 struct ata_port *ap = host->ports[i]; 1085 struct ata_port *ap = host->ports[i];
1090 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 1086 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1091 unsigned int port_offset = 0x200 + ata_no * 0x80; 1087 unsigned int ata_offset = 0x200 + ata_no * 0x80;
1092 unsigned int scr_offset = 0x400 + ata_no * 0x100; 1088 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1093 1089
1094 pdc_ata_setup_port(ap, base + port_offset, base + scr_offset); 1090 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
1095 1091
1096 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); 1092 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1097 ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port"); 1093 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
1098 } 1094 }
1099 1095
1100 /* initialize adapter */ 1096 /* initialize adapter */
diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c
index 27a110110077..84ffcc26a74b 100644
--- a/drivers/ata/sata_sil24.c
+++ b/drivers/ata/sata_sil24.c
@@ -370,6 +370,7 @@ static const struct pci_device_id sil24_pci_tbl[] = {
370 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 }, 370 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
371 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 }, 371 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
372 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 }, 372 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
373 { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 },
373 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 }, 374 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
374 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 }, 375 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
375 376
@@ -899,14 +900,25 @@ static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
899 900
900static void sil24_pmp_attach(struct ata_port *ap) 901static void sil24_pmp_attach(struct ata_port *ap)
901{ 902{
903 u32 *gscr = ap->link.device->gscr;
904
902 sil24_config_pmp(ap, 1); 905 sil24_config_pmp(ap, 1);
903 sil24_init_port(ap); 906 sil24_init_port(ap);
907
908 if (sata_pmp_gscr_vendor(gscr) == 0x11ab &&
909 sata_pmp_gscr_devid(gscr) == 0x4140) {
910 ata_port_printk(ap, KERN_INFO,
911 "disabling NCQ support due to sil24-mv4140 quirk\n");
912 ap->flags &= ~ATA_FLAG_NCQ;
913 }
904} 914}
905 915
906static void sil24_pmp_detach(struct ata_port *ap) 916static void sil24_pmp_detach(struct ata_port *ap)
907{ 917{
908 sil24_init_port(ap); 918 sil24_init_port(ap);
909 sil24_config_pmp(ap, 0); 919 sil24_config_pmp(ap, 0);
920
921 ap->flags |= ATA_FLAG_NCQ;
910} 922}
911 923
912static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class, 924static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
diff --git a/drivers/ata/sata_uli.c b/drivers/ata/sata_uli.c
index f277cea904ce..db529b849948 100644
--- a/drivers/ata/sata_uli.c
+++ b/drivers/ata/sata_uli.c
@@ -83,6 +83,7 @@ static struct ata_port_operations uli_ops = {
83 .inherits = &ata_bmdma_port_ops, 83 .inherits = &ata_bmdma_port_ops,
84 .scr_read = uli_scr_read, 84 .scr_read = uli_scr_read,
85 .scr_write = uli_scr_write, 85 .scr_write = uli_scr_write,
86 .hardreset = ATA_OP_NULL,
86}; 87};
87 88
88static const struct ata_port_info uli_port_info = { 89static const struct ata_port_info uli_port_info = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 16:22:48 -0500