1 files changed, 347 insertions, 0 deletions
diff --git a/drivers/ata/sata_sis.c b/drivers/ata/sata_sis.c
new file mode 100644
index 000000000000..ac24f66897f6
--- /dev/null
+++ b/drivers/ata/sata_sis.c
@@ -0,0 +1,347 @@
+/*
+ *  sata_sis.c - Silicon Integrated Systems SATA
+ *
+ *  Maintained by:  Uwe Koziolek
+ *                  Please ALWAYS copy linux-ide@vger.kernel.org
+ *                  on emails.
+ *
+ *  Copyright 2004 Uwe Koziolek
+ *
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *  libata documentation is available via 'make {ps|pdf}docs',
+ *  as Documentation/DocBook/libata.*
+ *
+ *  Hardware documentation available under NDA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <scsi/scsi_host.h>
+#include <linux/libata.h>
+#define DRV_NAME        "sata_sis"
+#define DRV_VERSION     "0.6"
+enum {
+        sis_180                 = 0,
+        SIS_SCR_PCI_BAR         = 5,
+        /* PCI configuration registers */
+        SIS_GENCTL              = 0x54, /* IDE General Control register */
+        SIS_SCR_BASE            = 0xc0, /* sata0 phy SCR registers */
+        SIS180_SATA1_OFS        = 0x10, /* offset from sata0->sata1 phy regs */
+        SIS182_SATA1_OFS        = 0x20, /* offset from sata0->sata1 phy regs */
+        SIS_PMR                 = 0x90, /* port mapping register */
+        SIS_PMR_COMBINED        = 0x30,
+        /* random bits */
+        SIS_FLAG_CFGSCR         = (1 << 30), /* host flag: SCRs via PCI cfg */
+        GENCTL_IOMAPPED_SCR     = (1 << 26), /* if set, SCRs are in IO space */
+};
+static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
+static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
+static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
+static const struct pci_device_id sis_pci_tbl[] = {
+        { PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
+        { PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
+        { PCI_VENDOR_ID_SI, 0x182, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
+        { }     /* terminate list */
+};
+static struct pci_driver sis_pci_driver = {
+        .name                   = DRV_NAME,
+        .id_table               = sis_pci_tbl,
+        .probe                  = sis_init_one,
+        .remove                 = ata_pci_remove_one,
+};
+static struct scsi_host_template sis_sht = {
+        .module                 = THIS_MODULE,
+        .name                   = DRV_NAME,
+        .ioctl                  = ata_scsi_ioctl,
+        .queuecommand           = ata_scsi_queuecmd,
+        .can_queue              = ATA_DEF_QUEUE,
+        .this_id                = ATA_SHT_THIS_ID,
+        .sg_tablesize           = ATA_MAX_PRD,
+        .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
+        .emulated               = ATA_SHT_EMULATED,
+        .use_clustering         = ATA_SHT_USE_CLUSTERING,
+        .proc_name              = DRV_NAME,
+        .dma_boundary           = ATA_DMA_BOUNDARY,
+        .slave_configure        = ata_scsi_slave_config,
+        .slave_destroy          = ata_scsi_slave_destroy,
+        .bios_param             = ata_std_bios_param,
+};
+static const struct ata_port_operations sis_ops = {
+        .port_disable           = ata_port_disable,
+        .tf_load                = ata_tf_load,
+        .tf_read                = ata_tf_read,
+        .check_status           = ata_check_status,
+        .exec_command           = ata_exec_command,
+        .dev_select             = ata_std_dev_select,
+        .bmdma_setup            = ata_bmdma_setup,
+        .bmdma_start            = ata_bmdma_start,
+        .bmdma_stop             = ata_bmdma_stop,
+        .bmdma_status           = ata_bmdma_status,
+        .qc_prep                = ata_qc_prep,
+        .qc_issue               = ata_qc_issue_prot,
+        .data_xfer              = ata_pio_data_xfer,
+        .freeze                 = ata_bmdma_freeze,
+        .thaw                   = ata_bmdma_thaw,
+        .error_handler          = ata_bmdma_error_handler,
+        .post_internal_cmd      = ata_bmdma_post_internal_cmd,
+        .irq_handler            = ata_interrupt,
+        .irq_clear              = ata_bmdma_irq_clear,
+        .scr_read               = sis_scr_read,
+        .scr_write              = sis_scr_write,
+        .port_start             = ata_port_start,
+        .port_stop              = ata_port_stop,
+        .host_stop              = ata_host_stop,
+};
+static struct ata_port_info sis_port_info = {
+        .sht            = &sis_sht,
+        .host_flags     = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
+        .pio_mask       = 0x1f,
+        .mwdma_mask     = 0x7,
+        .udma_mask      = 0x7f,
+        .port_ops       = &sis_ops,
+};
+MODULE_AUTHOR("Uwe Koziolek");
+MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
+MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
+MODULE_VERSION(DRV_VERSION);
+static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, int device)
+{
+        unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
+        if (port_no)  {
+                if (device == 0x182)
+                        addr += SIS182_SATA1_OFS;
+                else
+                        addr += SIS180_SATA1_OFS;
+        }
+        return addr;
+}
+static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
+{
+        struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
+        unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev->device);
+        u32 val, val2 = 0;
+        u8 pmr;
+        if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
+                return 0xffffffff;
+        pci_read_config_byte(pdev, SIS_PMR, &pmr);
+        pci_read_config_dword(pdev, cfg_addr, &val);
+        if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
+                pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
+        return val|val2;
+}
+static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
+{
+        struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
+        unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev->device);
+        u8 pmr;
+        if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
+                return;
+        pci_read_config_byte(pdev, SIS_PMR, &pmr);
+        pci_write_config_dword(pdev, cfg_addr, val);
+        if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
+                pci_write_config_dword(pdev, cfg_addr+0x10, val);
+}
+static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
+{
+        struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
+        u32 val, val2 = 0;
+        u8 pmr;
+        if (sc_reg > SCR_CONTROL)
+                return 0xffffffffU;
+        if (ap->flags & SIS_FLAG_CFGSCR)
+                return sis_scr_cfg_read(ap, sc_reg);
+        pci_read_config_byte(pdev, SIS_PMR, &pmr);
+        val = inl(ap->ioaddr.scr_addr + (sc_reg * 4));
+        if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
+                val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
+        return val | val2;
+}
+static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
+{
+        struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
+        u8 pmr;
+        if (sc_reg > SCR_CONTROL)
+                return;
+        pci_read_config_byte(pdev, SIS_PMR, &pmr);
+        if (ap->flags & SIS_FLAG_CFGSCR)
+                sis_scr_cfg_write(ap, sc_reg, val);
+        else {
+                outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
+                if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
+                        outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
+        }
+}
+static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+        static int printed_version;
+        struct ata_probe_ent *probe_ent = NULL;
+        int rc;
+        u32 genctl;
+        struct ata_port_info *ppi;
+        int pci_dev_busy = 0;
+        u8 pmr;
+        u8 port2_start;
+        if (!printed_version++)
+                dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
+        rc = pci_enable_device(pdev);
+        if (rc)
+                return rc;
+        rc = pci_request_regions(pdev, DRV_NAME);
+        if (rc) {
+                pci_dev_busy = 1;
+                goto err_out;
+        }
+        rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
+        if (rc)
+                goto err_out_regions;
+        rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
+        if (rc)
+                goto err_out_regions;
+        ppi = &sis_port_info;
+        probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
+        if (!probe_ent) {
+                rc = -ENOMEM;
+                goto err_out_regions;
+        }
+        /* check and see if the SCRs are in IO space or PCI cfg space */
+        pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
+        if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
+                probe_ent->host_flags |= SIS_FLAG_CFGSCR;
+        /* if hardware thinks SCRs are in IO space, but there are
+         * no IO resources assigned, change to PCI cfg space.
+         */
+        if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) &&
+            ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
+             (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
+                genctl &= ~GENCTL_IOMAPPED_SCR;
+                pci_write_config_dword(pdev, SIS_GENCTL, genctl);
+                probe_ent->host_flags |= SIS_FLAG_CFGSCR;
+        }
+        pci_read_config_byte(pdev, SIS_PMR, &pmr);
+        if (ent->device != 0x182) {
+                if ((pmr & SIS_PMR_COMBINED) == 0) {
+                        dev_printk(KERN_INFO, &pdev->dev,
+                                   "Detected SiS 180/181 chipset in SATA mode\n");
+                        port2_start = 64;
+                }
+                else {
+                        dev_printk(KERN_INFO, &pdev->dev,
+                                   "Detected SiS 180/181 chipset in combined mode\n");
+                        port2_start=0;
+                }
+        }
+        else {
+                dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182 chipset\n");
+                port2_start = 0x20;
+        }
+        if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) {
+                probe_ent->port[0].scr_addr =
+                        pci_resource_start(pdev, SIS_SCR_PCI_BAR);
+                probe_ent->port[1].scr_addr =
+                        pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start;
+        }
+        pci_set_master(pdev);
+        pci_intx(pdev, 1);
+        /* FIXME: check ata_device_add return value */
+        ata_device_add(probe_ent);
+        kfree(probe_ent);
+        return 0;
+err_out_regions:
+        pci_release_regions(pdev);
+err_out:
+        if (!pci_dev_busy)
+                pci_disable_device(pdev);
+        return rc;
+}
+static int __init sis_init(void)
+{
+        return pci_register_driver(&sis_pci_driver);
+}
+static void __exit sis_exit(void)
+{
+        pci_unregister_driver(&sis_pci_driver);
+}
+module_init(sis_init);
+module_exit(sis_exit);

diff --git a/drivers/ata/sata_sis.c b/drivers/ata/sata_sis.c new file mode 100644 index 000000000000..ac24f66897f6 --- /dev/null +++ b/drivers/ata/sata_sis.c
@@ -0,0 +1,347 @@
	1	/*
	2	* sata_sis.c - Silicon Integrated Systems SATA
	3	*
	4	* Maintained by: Uwe Koziolek
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	* Copyright 2004 Uwe Koziolek
	9	*
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2, or (at your option)
	14	* any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; see the file COPYING. If not, write to
	23	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	24	*
	25	*
	26	* libata documentation is available via 'make {ps\|pdf}docs',
	27	* as Documentation/DocBook/libata.*
	28	*
	29	* Hardware documentation available under NDA.
	30	*
	31	*/
	32
	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
	35	#include <linux/pci.h>
	36	#include <linux/init.h>
	37	#include <linux/blkdev.h>
	38	#include <linux/delay.h>
	39	#include <linux/interrupt.h>
	40	#include <linux/device.h>
	41	#include <scsi/scsi_host.h>
	42	#include <linux/libata.h>
	43
	44	#define DRV_NAME "sata_sis"
	45	#define DRV_VERSION "0.6"
	46
	47	enum {
	48	sis_180 = 0,
	49	SIS_SCR_PCI_BAR = 5,
	50
	51	/* PCI configuration registers */
	52	SIS_GENCTL = 0x54, /* IDE General Control register */
	53	SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
	54	SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
	55	SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
	56	SIS_PMR = 0x90, /* port mapping register */
	57	SIS_PMR_COMBINED = 0x30,
	58
	59	/* random bits */
	60	SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
	61
	62	GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
	63	};
	64
	65	static int sis_init_one (struct pci_dev pdev, const struct pci_device_id ent);
	66	static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
	67	static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
	68
	69	static const struct pci_device_id sis_pci_tbl[] = {
	70	{ PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
	71	{ PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
	72	{ PCI_VENDOR_ID_SI, 0x182, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
	73	{ } /* terminate list */
	74	};
	75
	76
	77	static struct pci_driver sis_pci_driver = {
	78	.name = DRV_NAME,
	79	.id_table = sis_pci_tbl,
	80	.probe = sis_init_one,
	81	.remove = ata_pci_remove_one,
	82	};
	83
	84	static struct scsi_host_template sis_sht = {
	85	.module = THIS_MODULE,
	86	.name = DRV_NAME,
	87	.ioctl = ata_scsi_ioctl,
	88	.queuecommand = ata_scsi_queuecmd,
	89	.can_queue = ATA_DEF_QUEUE,
	90	.this_id = ATA_SHT_THIS_ID,
	91	.sg_tablesize = ATA_MAX_PRD,
	92	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	93	.emulated = ATA_SHT_EMULATED,
	94	.use_clustering = ATA_SHT_USE_CLUSTERING,
	95	.proc_name = DRV_NAME,
	96	.dma_boundary = ATA_DMA_BOUNDARY,
	97	.slave_configure = ata_scsi_slave_config,
	98	.slave_destroy = ata_scsi_slave_destroy,
	99	.bios_param = ata_std_bios_param,
	100	};
	101
	102	static const struct ata_port_operations sis_ops = {
	103	.port_disable = ata_port_disable,
	104	.tf_load = ata_tf_load,
	105	.tf_read = ata_tf_read,
	106	.check_status = ata_check_status,
	107	.exec_command = ata_exec_command,
	108	.dev_select = ata_std_dev_select,
	109	.bmdma_setup = ata_bmdma_setup,
	110	.bmdma_start = ata_bmdma_start,
	111	.bmdma_stop = ata_bmdma_stop,
	112	.bmdma_status = ata_bmdma_status,
	113	.qc_prep = ata_qc_prep,
	114	.qc_issue = ata_qc_issue_prot,
	115	.data_xfer = ata_pio_data_xfer,
	116	.freeze = ata_bmdma_freeze,
	117	.thaw = ata_bmdma_thaw,
	118	.error_handler = ata_bmdma_error_handler,
	119	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	120	.irq_handler = ata_interrupt,
	121	.irq_clear = ata_bmdma_irq_clear,
	122	.scr_read = sis_scr_read,
	123	.scr_write = sis_scr_write,
	124	.port_start = ata_port_start,
	125	.port_stop = ata_port_stop,
	126	.host_stop = ata_host_stop,
	127	};
	128
	129	static struct ata_port_info sis_port_info = {
	130	.sht = &sis_sht,
	131	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY,
	132	.pio_mask = 0x1f,
	133	.mwdma_mask = 0x7,
	134	.udma_mask = 0x7f,
	135	.port_ops = &sis_ops,
	136	};
	137
	138
	139	MODULE_AUTHOR("Uwe Koziolek");
	140	MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
	141	MODULE_LICENSE("GPL");
	142	MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
	143	MODULE_VERSION(DRV_VERSION);
	144
	145	static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, int device)
	146	{
	147	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
	148
	149	if (port_no) {
	150	if (device == 0x182)
	151	addr += SIS182_SATA1_OFS;
	152	else
	153	addr += SIS180_SATA1_OFS;
	154	}
	155
	156	return addr;
	157	}
	158
	159	static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
	160	{
	161	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
	162	unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev->device);
	163	u32 val, val2 = 0;
	164	u8 pmr;
	165
	166	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
	167	return 0xffffffff;
	168
	169	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	170
	171	pci_read_config_dword(pdev, cfg_addr, &val);
	172
	173	if ((pdev->device == 0x182) \|\| (pmr & SIS_PMR_COMBINED))
	174	pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
	175
	176	return val\|val2;
	177	}
	178
	179	static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
	180	{
	181	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
	182	unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev->device);
	183	u8 pmr;
	184
	185	if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
	186	return;
	187
	188	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	189
	190	pci_write_config_dword(pdev, cfg_addr, val);
	191
	192	if ((pdev->device == 0x182) \|\| (pmr & SIS_PMR_COMBINED))
	193	pci_write_config_dword(pdev, cfg_addr+0x10, val);
	194	}
	195
	196	static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
	197	{
	198	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
	199	u32 val, val2 = 0;
	200	u8 pmr;
	201
	202	if (sc_reg > SCR_CONTROL)
	203	return 0xffffffffU;
	204
	205	if (ap->flags & SIS_FLAG_CFGSCR)
	206	return sis_scr_cfg_read(ap, sc_reg);
	207
	208	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	209
	210	val = inl(ap->ioaddr.scr_addr + (sc_reg * 4));
	211
	212	if ((pdev->device == 0x182) \|\| (pmr & SIS_PMR_COMBINED))
	213	val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
	214
	215	return val \| val2;
	216	}
	217
	218	static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
	219	{
	220	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
	221	u8 pmr;
	222
	223	if (sc_reg > SCR_CONTROL)
	224	return;
	225
	226	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	227
	228	if (ap->flags & SIS_FLAG_CFGSCR)
	229	sis_scr_cfg_write(ap, sc_reg, val);
	230	else {
	231	outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
	232	if ((pdev->device == 0x182) \|\| (pmr & SIS_PMR_COMBINED))
	233	outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
	234	}
	235	}
	236
	237	static int sis_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	238	{
	239	static int printed_version;
	240	struct ata_probe_ent *probe_ent = NULL;
	241	int rc;
	242	u32 genctl;
	243	struct ata_port_info *ppi;
	244	int pci_dev_busy = 0;
	245	u8 pmr;
	246	u8 port2_start;
	247
	248	if (!printed_version++)
	249	dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
	250
	251	rc = pci_enable_device(pdev);
	252	if (rc)
	253	return rc;
	254
	255	rc = pci_request_regions(pdev, DRV_NAME);
	256	if (rc) {
	257	pci_dev_busy = 1;
	258	goto err_out;
	259	}
	260
	261	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	262	if (rc)
	263	goto err_out_regions;
	264	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	265	if (rc)
	266	goto err_out_regions;
	267
	268	ppi = &sis_port_info;
	269	probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY \| ATA_PORT_SECONDARY);
	270	if (!probe_ent) {
	271	rc = -ENOMEM;
	272	goto err_out_regions;
	273	}
	274
	275	/* check and see if the SCRs are in IO space or PCI cfg space */
	276	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	277	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
	278	probe_ent->host_flags \|= SIS_FLAG_CFGSCR;
	279
	280	/* if hardware thinks SCRs are in IO space, but there are
	281	* no IO resources assigned, change to PCI cfg space.
	282	*/
	283	if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) &&
	284	((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) \|\|
	285	(pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
	286	genctl &= ~GENCTL_IOMAPPED_SCR;
	287	pci_write_config_dword(pdev, SIS_GENCTL, genctl);
	288	probe_ent->host_flags \|= SIS_FLAG_CFGSCR;
	289	}
	290
	291	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	292	if (ent->device != 0x182) {
	293	if ((pmr & SIS_PMR_COMBINED) == 0) {
	294	dev_printk(KERN_INFO, &pdev->dev,
	295	"Detected SiS 180/181 chipset in SATA mode\n");
	296	port2_start = 64;
	297	}
	298	else {
	299	dev_printk(KERN_INFO, &pdev->dev,
	300	"Detected SiS 180/181 chipset in combined mode\n");
	301	port2_start=0;
	302	}
	303	}
	304	else {
	305	dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182 chipset\n");
	306	port2_start = 0x20;
	307	}
	308
	309	if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) {
	310	probe_ent->port[0].scr_addr =
	311	pci_resource_start(pdev, SIS_SCR_PCI_BAR);
	312	probe_ent->port[1].scr_addr =
	313	pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start;
	314	}
	315
	316	pci_set_master(pdev);
	317	pci_intx(pdev, 1);
	318
	319	/* FIXME: check ata_device_add return value */
	320	ata_device_add(probe_ent);
	321	kfree(probe_ent);
	322
	323	return 0;
	324
	325	err_out_regions:
	326	pci_release_regions(pdev);
	327
	328	err_out:
	329	if (!pci_dev_busy)
	330	pci_disable_device(pdev);
	331	return rc;
	332
	333	}
	334
	335	static int __init sis_init(void)
	336	{
	337	return pci_register_driver(&sis_pci_driver);
	338	}
	339
	340	static void __exit sis_exit(void)
	341	{
	342	pci_unregister_driver(&sis_pci_driver);
	343	}
	344
	345	module_init(sis_init);
	346	module_exit(sis_exit);
	347