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path: root/drivers/ata/sata_sil24.c
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Diffstat (limited to 'drivers/ata/sata_sil24.c')
-rw-r--r--drivers/ata/sata_sil24.c18
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c
index 169e200a6a71..5aa288d2fb86 100644
--- a/drivers/ata/sata_sil24.c
+++ b/drivers/ata/sata_sil24.c
@@ -100,10 +100,14 @@ enum {
100 */ 100 */
101 PORT_REGS_SIZE = 0x2000, 101 PORT_REGS_SIZE = 0x2000,
102 102
103 PORT_LRAM = 0x0000, /* 31 LRAM slots and PM regs */ 103 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
104 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ 104 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
105 105
106 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */ 106 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
107 PORT_PMP_STATUS = 0x0000, /* port device status offset */
108 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
109 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
110
107 /* 32 bit regs */ 111 /* 32 bit regs */
108 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ 112 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
109 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ 113 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
@@ -126,6 +130,7 @@ enum {
126 PORT_PHY_CFG = 0x1050, 130 PORT_PHY_CFG = 0x1050,
127 PORT_SLOT_STAT = 0x1800, 131 PORT_SLOT_STAT = 0x1800,
128 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ 132 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
133 PORT_CONTEXT = 0x1e04,
129 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ 134 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
130 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ 135 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
131 PORT_SCONTROL = 0x1f00, 136 PORT_SCONTROL = 0x1f00,
@@ -139,9 +144,9 @@ enum {
139 PORT_CS_INIT = (1 << 2), /* port initialize */ 144 PORT_CS_INIT = (1 << 2), /* port initialize */
140 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ 145 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
141 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ 146 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
142 PORT_CS_RESUME = (1 << 6), /* port resume */ 147 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
143 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ 148 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
144 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */ 149 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
145 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ 150 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
146 151
147 /* PORT_IRQ_STAT/ENABLE_SET/CLR */ 152 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
@@ -562,7 +567,7 @@ static int sil24_softreset(struct ata_port *ap, unsigned int *class)
562 567
563 /* do SRST */ 568 /* do SRST */
564 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST); 569 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
565 prb->fis[1] = 0; /* no PM yet */ 570 prb->fis[1] = 0; /* no PMP yet */
566 571
567 writel((u32)paddr, port + PORT_CMD_ACTIVATE); 572 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
568 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); 573 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
@@ -1050,7 +1055,8 @@ static void sil24_init_controller(struct pci_dev *pdev, int n_ports,
1050 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); 1055 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1051 1056
1052 /* Clear port multiplier enable and resume bits */ 1057 /* Clear port multiplier enable and resume bits */
1053 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR); 1058 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME,
1059 port + PORT_CTRL_CLR);
1054 } 1060 }
1055 1061
1056 /* Turn on interrupts */ 1062 /* Turn on interrupts */