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-rw-r--r--drivers/ata/sata_sil24.c1228
1 files changed, 1228 insertions, 0 deletions
diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c
new file mode 100644
index 000000000000..2d7cf3264587
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+++ b/drivers/ata/sata_sil24.c
@@ -0,0 +1,1228 @@
1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
27#include <linux/device.h>
28#include <scsi/scsi_host.h>
29#include <scsi/scsi_cmnd.h>
30#include <linux/libata.h>
31#include <asm/io.h>
32
33#define DRV_NAME "sata_sil24"
34#define DRV_VERSION "0.3"
35
36/*
37 * Port request block (PRB) 32 bytes
38 */
39struct sil24_prb {
40 __le16 ctrl;
41 __le16 prot;
42 __le32 rx_cnt;
43 u8 fis[6 * 4];
44};
45
46/*
47 * Scatter gather entry (SGE) 16 bytes
48 */
49struct sil24_sge {
50 __le64 addr;
51 __le32 cnt;
52 __le32 flags;
53};
54
55/*
56 * Port multiplier
57 */
58struct sil24_port_multiplier {
59 __le32 diag;
60 __le32 sactive;
61};
62
63enum {
64 /*
65 * Global controller registers (128 bytes @ BAR0)
66 */
67 /* 32 bit regs */
68 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
69 HOST_CTRL = 0x40,
70 HOST_IRQ_STAT = 0x44,
71 HOST_PHY_CFG = 0x48,
72 HOST_BIST_CTRL = 0x50,
73 HOST_BIST_PTRN = 0x54,
74 HOST_BIST_STAT = 0x58,
75 HOST_MEM_BIST_STAT = 0x5c,
76 HOST_FLASH_CMD = 0x70,
77 /* 8 bit regs */
78 HOST_FLASH_DATA = 0x74,
79 HOST_TRANSITION_DETECT = 0x75,
80 HOST_GPIO_CTRL = 0x76,
81 HOST_I2C_ADDR = 0x78, /* 32 bit */
82 HOST_I2C_DATA = 0x7c,
83 HOST_I2C_XFER_CNT = 0x7e,
84 HOST_I2C_CTRL = 0x7f,
85
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN = (1 << 31),
88
89 /* HOST_CTRL bits */
90 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
91 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
92 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
93 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
94 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
95 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
96
97 /*
98 * Port registers
99 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
100 */
101 PORT_REGS_SIZE = 0x2000,
102
103 PORT_LRAM = 0x0000, /* 31 LRAM slots and PM regs */
104 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
105
106 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
107 /* 32 bit regs */
108 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
109 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
110 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
111 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
112 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
113 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
114 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
115 PORT_CMD_ERR = 0x1024, /* command error number */
116 PORT_FIS_CFG = 0x1028,
117 PORT_FIFO_THRES = 0x102c,
118 /* 16 bit regs */
119 PORT_DECODE_ERR_CNT = 0x1040,
120 PORT_DECODE_ERR_THRESH = 0x1042,
121 PORT_CRC_ERR_CNT = 0x1044,
122 PORT_CRC_ERR_THRESH = 0x1046,
123 PORT_HSHK_ERR_CNT = 0x1048,
124 PORT_HSHK_ERR_THRESH = 0x104a,
125 /* 32 bit regs */
126 PORT_PHY_CFG = 0x1050,
127 PORT_SLOT_STAT = 0x1800,
128 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
129 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
130 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
131 PORT_SCONTROL = 0x1f00,
132 PORT_SSTATUS = 0x1f04,
133 PORT_SERROR = 0x1f08,
134 PORT_SACTIVE = 0x1f0c,
135
136 /* PORT_CTRL_STAT bits */
137 PORT_CS_PORT_RST = (1 << 0), /* port reset */
138 PORT_CS_DEV_RST = (1 << 1), /* device reset */
139 PORT_CS_INIT = (1 << 2), /* port initialize */
140 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
141 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
142 PORT_CS_RESUME = (1 << 6), /* port resume */
143 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
144 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
145 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
146
147 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
148 /* bits[11:0] are masked */
149 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
150 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
151 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
152 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
153 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
154 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
155 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
156 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
157 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
158 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
159 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
160 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
161
162 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
163 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
164 PORT_IRQ_UNK_FIS,
165
166 /* bits[27:16] are unmasked (raw) */
167 PORT_IRQ_RAW_SHIFT = 16,
168 PORT_IRQ_MASKED_MASK = 0x7ff,
169 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
170
171 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
172 PORT_IRQ_STEER_SHIFT = 30,
173 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
174
175 /* PORT_CMD_ERR constants */
176 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
177 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
178 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
179 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
180 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
181 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
182 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
183 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
184 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
185 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
186 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
187 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
188 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
189 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
190 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
191 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
192 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
193 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
194 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
195 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
196 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
197 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
198
199 /* bits of PRB control field */
200 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
201 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
202 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
203 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
204 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
205
206 /* PRB protocol field */
207 PRB_PROT_PACKET = (1 << 0),
208 PRB_PROT_TCQ = (1 << 1),
209 PRB_PROT_NCQ = (1 << 2),
210 PRB_PROT_READ = (1 << 3),
211 PRB_PROT_WRITE = (1 << 4),
212 PRB_PROT_TRANSPARENT = (1 << 5),
213
214 /*
215 * Other constants
216 */
217 SGE_TRM = (1 << 31), /* Last SGE in chain */
218 SGE_LNK = (1 << 30), /* linked list
219 Points to SGT, not SGE */
220 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
221 data address ignored */
222
223 SIL24_MAX_CMDS = 31,
224
225 /* board id */
226 BID_SIL3124 = 0,
227 BID_SIL3132 = 1,
228 BID_SIL3131 = 2,
229
230 /* host flags */
231 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
232 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
233 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY,
234 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
235
236 IRQ_STAT_4PORTS = 0xf,
237};
238
239struct sil24_ata_block {
240 struct sil24_prb prb;
241 struct sil24_sge sge[LIBATA_MAX_PRD];
242};
243
244struct sil24_atapi_block {
245 struct sil24_prb prb;
246 u8 cdb[16];
247 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
248};
249
250union sil24_cmd_block {
251 struct sil24_ata_block ata;
252 struct sil24_atapi_block atapi;
253};
254
255static struct sil24_cerr_info {
256 unsigned int err_mask, action;
257 const char *desc;
258} sil24_cerr_db[] = {
259 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
260 "device error" },
261 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
262 "device error via D2H FIS" },
263 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
264 "device error via SDB FIS" },
265 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
266 "error in data FIS" },
267 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
268 "failed to transmit command FIS" },
269 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
270 "protocol mismatch" },
271 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
272 "data directon mismatch" },
273 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
274 "ran out of SGEs while writing" },
275 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
276 "ran out of SGEs while reading" },
277 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
278 "invalid data directon for ATAPI CDB" },
279 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
280 "SGT no on qword boundary" },
281 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
282 "PCI target abort while fetching SGT" },
283 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
284 "PCI master abort while fetching SGT" },
285 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
286 "PCI parity error while fetching SGT" },
287 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
288 "PRB not on qword boundary" },
289 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
290 "PCI target abort while fetching PRB" },
291 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
292 "PCI master abort while fetching PRB" },
293 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
294 "PCI parity error while fetching PRB" },
295 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
296 "undefined error while transferring data" },
297 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
298 "PCI target abort while transferring data" },
299 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
300 "PCI master abort while transferring data" },
301 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
302 "PCI parity error while transferring data" },
303 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
304 "FIS received while sending service FIS" },
305};
306
307/*
308 * ap->private_data
309 *
310 * The preview driver always returned 0 for status. We emulate it
311 * here from the previous interrupt.
312 */
313struct sil24_port_priv {
314 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
315 dma_addr_t cmd_block_dma; /* DMA base addr for them */
316 struct ata_taskfile tf; /* Cached taskfile registers */
317};
318
319/* ap->host_set->private_data */
320struct sil24_host_priv {
321 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
322 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
323};
324
325static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
326static u8 sil24_check_status(struct ata_port *ap);
327static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
328static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
329static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
330static void sil24_qc_prep(struct ata_queued_cmd *qc);
331static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
332static void sil24_irq_clear(struct ata_port *ap);
333static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
334static void sil24_freeze(struct ata_port *ap);
335static void sil24_thaw(struct ata_port *ap);
336static void sil24_error_handler(struct ata_port *ap);
337static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
338static int sil24_port_start(struct ata_port *ap);
339static void sil24_port_stop(struct ata_port *ap);
340static void sil24_host_stop(struct ata_host_set *host_set);
341static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
342#ifdef CONFIG_PM
343static int sil24_pci_device_resume(struct pci_dev *pdev);
344#endif
345
346static const struct pci_device_id sil24_pci_tbl[] = {
347 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
348 { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
349 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
350 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
351 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
352 { } /* terminate list */
353};
354
355static struct pci_driver sil24_pci_driver = {
356 .name = DRV_NAME,
357 .id_table = sil24_pci_tbl,
358 .probe = sil24_init_one,
359 .remove = ata_pci_remove_one, /* safe? */
360#ifdef CONFIG_PM
361 .suspend = ata_pci_device_suspend,
362 .resume = sil24_pci_device_resume,
363#endif
364};
365
366static struct scsi_host_template sil24_sht = {
367 .module = THIS_MODULE,
368 .name = DRV_NAME,
369 .ioctl = ata_scsi_ioctl,
370 .queuecommand = ata_scsi_queuecmd,
371 .change_queue_depth = ata_scsi_change_queue_depth,
372 .can_queue = SIL24_MAX_CMDS,
373 .this_id = ATA_SHT_THIS_ID,
374 .sg_tablesize = LIBATA_MAX_PRD,
375 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
376 .emulated = ATA_SHT_EMULATED,
377 .use_clustering = ATA_SHT_USE_CLUSTERING,
378 .proc_name = DRV_NAME,
379 .dma_boundary = ATA_DMA_BOUNDARY,
380 .slave_configure = ata_scsi_slave_config,
381 .slave_destroy = ata_scsi_slave_destroy,
382 .bios_param = ata_std_bios_param,
383 .suspend = ata_scsi_device_suspend,
384 .resume = ata_scsi_device_resume,
385};
386
387static const struct ata_port_operations sil24_ops = {
388 .port_disable = ata_port_disable,
389
390 .dev_config = sil24_dev_config,
391
392 .check_status = sil24_check_status,
393 .check_altstatus = sil24_check_status,
394 .dev_select = ata_noop_dev_select,
395
396 .tf_read = sil24_tf_read,
397
398 .qc_prep = sil24_qc_prep,
399 .qc_issue = sil24_qc_issue,
400
401 .irq_handler = sil24_interrupt,
402 .irq_clear = sil24_irq_clear,
403
404 .scr_read = sil24_scr_read,
405 .scr_write = sil24_scr_write,
406
407 .freeze = sil24_freeze,
408 .thaw = sil24_thaw,
409 .error_handler = sil24_error_handler,
410 .post_internal_cmd = sil24_post_internal_cmd,
411
412 .port_start = sil24_port_start,
413 .port_stop = sil24_port_stop,
414 .host_stop = sil24_host_stop,
415};
416
417/*
418 * Use bits 30-31 of host_flags to encode available port numbers.
419 * Current maxium is 4.
420 */
421#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
422#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
423
424static struct ata_port_info sil24_port_info[] = {
425 /* sil_3124 */
426 {
427 .sht = &sil24_sht,
428 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
429 SIL24_FLAG_PCIX_IRQ_WOC,
430 .pio_mask = 0x1f, /* pio0-4 */
431 .mwdma_mask = 0x07, /* mwdma0-2 */
432 .udma_mask = 0x3f, /* udma0-5 */
433 .port_ops = &sil24_ops,
434 },
435 /* sil_3132 */
436 {
437 .sht = &sil24_sht,
438 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
439 .pio_mask = 0x1f, /* pio0-4 */
440 .mwdma_mask = 0x07, /* mwdma0-2 */
441 .udma_mask = 0x3f, /* udma0-5 */
442 .port_ops = &sil24_ops,
443 },
444 /* sil_3131/sil_3531 */
445 {
446 .sht = &sil24_sht,
447 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
448 .pio_mask = 0x1f, /* pio0-4 */
449 .mwdma_mask = 0x07, /* mwdma0-2 */
450 .udma_mask = 0x3f, /* udma0-5 */
451 .port_ops = &sil24_ops,
452 },
453};
454
455static int sil24_tag(int tag)
456{
457 if (unlikely(ata_tag_internal(tag)))
458 return 0;
459 return tag;
460}
461
462static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
463{
464 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
465
466 if (dev->cdb_len == 16)
467 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
468 else
469 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
470}
471
472static inline void sil24_update_tf(struct ata_port *ap)
473{
474 struct sil24_port_priv *pp = ap->private_data;
475 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
476 struct sil24_prb __iomem *prb = port;
477 u8 fis[6 * 4];
478
479 memcpy_fromio(fis, prb->fis, 6 * 4);
480 ata_tf_from_fis(fis, &pp->tf);
481}
482
483static u8 sil24_check_status(struct ata_port *ap)
484{
485 struct sil24_port_priv *pp = ap->private_data;
486 return pp->tf.command;
487}
488
489static int sil24_scr_map[] = {
490 [SCR_CONTROL] = 0,
491 [SCR_STATUS] = 1,
492 [SCR_ERROR] = 2,
493 [SCR_ACTIVE] = 3,
494};
495
496static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
497{
498 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
499 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
500 void __iomem *addr;
501 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
502 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
503 }
504 return 0xffffffffU;
505}
506
507static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
508{
509 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
510 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
511 void __iomem *addr;
512 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
513 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
514 }
515}
516
517static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
518{
519 struct sil24_port_priv *pp = ap->private_data;
520 *tf = pp->tf;
521}
522
523static int sil24_init_port(struct ata_port *ap)
524{
525 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
526 u32 tmp;
527
528 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
529 ata_wait_register(port + PORT_CTRL_STAT,
530 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
531 tmp = ata_wait_register(port + PORT_CTRL_STAT,
532 PORT_CS_RDY, 0, 10, 100);
533
534 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
535 return -EIO;
536 return 0;
537}
538
539static int sil24_softreset(struct ata_port *ap, unsigned int *class)
540{
541 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
542 struct sil24_port_priv *pp = ap->private_data;
543 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
544 dma_addr_t paddr = pp->cmd_block_dma;
545 u32 mask, irq_stat;
546 const char *reason;
547
548 DPRINTK("ENTER\n");
549
550 if (ata_port_offline(ap)) {
551 DPRINTK("PHY reports no device\n");
552 *class = ATA_DEV_NONE;
553 goto out;
554 }
555
556 /* put the port into known state */
557 if (sil24_init_port(ap)) {
558 reason ="port not ready";
559 goto err;
560 }
561
562 /* do SRST */
563 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
564 prb->fis[1] = 0; /* no PM yet */
565
566 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
567 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
568
569 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
570 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
571 100, ATA_TMOUT_BOOT / HZ * 1000);
572
573 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
574 irq_stat >>= PORT_IRQ_RAW_SHIFT;
575
576 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
577 if (irq_stat & PORT_IRQ_ERROR)
578 reason = "SRST command error";
579 else
580 reason = "timeout";
581 goto err;
582 }
583
584 sil24_update_tf(ap);
585 *class = ata_dev_classify(&pp->tf);
586
587 if (*class == ATA_DEV_UNKNOWN)
588 *class = ATA_DEV_NONE;
589
590 out:
591 DPRINTK("EXIT, class=%u\n", *class);
592 return 0;
593
594 err:
595 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
596 return -EIO;
597}
598
599static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
600{
601 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
602 const char *reason;
603 int tout_msec, rc;
604 u32 tmp;
605
606 /* sil24 does the right thing(tm) without any protection */
607 sata_set_spd(ap);
608
609 tout_msec = 100;
610 if (ata_port_online(ap))
611 tout_msec = 5000;
612
613 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
614 tmp = ata_wait_register(port + PORT_CTRL_STAT,
615 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
616
617 /* SStatus oscillates between zero and valid status after
618 * DEV_RST, debounce it.
619 */
620 rc = sata_phy_debounce(ap, sata_deb_timing_long);
621 if (rc) {
622 reason = "PHY debouncing failed";
623 goto err;
624 }
625
626 if (tmp & PORT_CS_DEV_RST) {
627 if (ata_port_offline(ap))
628 return 0;
629 reason = "link not ready";
630 goto err;
631 }
632
633 /* Sil24 doesn't store signature FIS after hardreset, so we
634 * can't wait for BSY to clear. Some devices take a long time
635 * to get ready and those devices will choke if we don't wait
636 * for BSY clearance here. Tell libata to perform follow-up
637 * softreset.
638 */
639 return -EAGAIN;
640
641 err:
642 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
643 return -EIO;
644}
645
646static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
647 struct sil24_sge *sge)
648{
649 struct scatterlist *sg;
650 unsigned int idx = 0;
651
652 ata_for_each_sg(sg, qc) {
653 sge->addr = cpu_to_le64(sg_dma_address(sg));
654 sge->cnt = cpu_to_le32(sg_dma_len(sg));
655 if (ata_sg_is_last(sg, qc))
656 sge->flags = cpu_to_le32(SGE_TRM);
657 else
658 sge->flags = 0;
659
660 sge++;
661 idx++;
662 }
663}
664
665static void sil24_qc_prep(struct ata_queued_cmd *qc)
666{
667 struct ata_port *ap = qc->ap;
668 struct sil24_port_priv *pp = ap->private_data;
669 union sil24_cmd_block *cb;
670 struct sil24_prb *prb;
671 struct sil24_sge *sge;
672 u16 ctrl = 0;
673
674 cb = &pp->cmd_block[sil24_tag(qc->tag)];
675
676 switch (qc->tf.protocol) {
677 case ATA_PROT_PIO:
678 case ATA_PROT_DMA:
679 case ATA_PROT_NCQ:
680 case ATA_PROT_NODATA:
681 prb = &cb->ata.prb;
682 sge = cb->ata.sge;
683 break;
684
685 case ATA_PROT_ATAPI:
686 case ATA_PROT_ATAPI_DMA:
687 case ATA_PROT_ATAPI_NODATA:
688 prb = &cb->atapi.prb;
689 sge = cb->atapi.sge;
690 memset(cb->atapi.cdb, 0, 32);
691 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
692
693 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
694 if (qc->tf.flags & ATA_TFLAG_WRITE)
695 ctrl = PRB_CTRL_PACKET_WRITE;
696 else
697 ctrl = PRB_CTRL_PACKET_READ;
698 }
699 break;
700
701 default:
702 prb = NULL; /* shut up, gcc */
703 sge = NULL;
704 BUG();
705 }
706
707 prb->ctrl = cpu_to_le16(ctrl);
708 ata_tf_to_fis(&qc->tf, prb->fis, 0);
709
710 if (qc->flags & ATA_QCFLAG_DMAMAP)
711 sil24_fill_sg(qc, sge);
712}
713
714static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
715{
716 struct ata_port *ap = qc->ap;
717 struct sil24_port_priv *pp = ap->private_data;
718 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
719 unsigned int tag = sil24_tag(qc->tag);
720 dma_addr_t paddr;
721 void __iomem *activate;
722
723 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
724 activate = port + PORT_CMD_ACTIVATE + tag * 8;
725
726 writel((u32)paddr, activate);
727 writel((u64)paddr >> 32, activate + 4);
728
729 return 0;
730}
731
732static void sil24_irq_clear(struct ata_port *ap)
733{
734 /* unused */
735}
736
737static void sil24_freeze(struct ata_port *ap)
738{
739 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
740
741 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
742 * PORT_IRQ_ENABLE instead.
743 */
744 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
745}
746
747static void sil24_thaw(struct ata_port *ap)
748{
749 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
750 u32 tmp;
751
752 /* clear IRQ */
753 tmp = readl(port + PORT_IRQ_STAT);
754 writel(tmp, port + PORT_IRQ_STAT);
755
756 /* turn IRQ back on */
757 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
758}
759
760static void sil24_error_intr(struct ata_port *ap)
761{
762 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
763 struct ata_eh_info *ehi = &ap->eh_info;
764 int freeze = 0;
765 u32 irq_stat;
766
767 /* on error, we need to clear IRQ explicitly */
768 irq_stat = readl(port + PORT_IRQ_STAT);
769 writel(irq_stat, port + PORT_IRQ_STAT);
770
771 /* first, analyze and record host port events */
772 ata_ehi_clear_desc(ehi);
773
774 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
775
776 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
777 ata_ehi_hotplugged(ehi);
778 ata_ehi_push_desc(ehi, ", %s",
779 irq_stat & PORT_IRQ_PHYRDY_CHG ?
780 "PHY RDY changed" : "device exchanged");
781 freeze = 1;
782 }
783
784 if (irq_stat & PORT_IRQ_UNK_FIS) {
785 ehi->err_mask |= AC_ERR_HSM;
786 ehi->action |= ATA_EH_SOFTRESET;
787 ata_ehi_push_desc(ehi , ", unknown FIS");
788 freeze = 1;
789 }
790
791 /* deal with command error */
792 if (irq_stat & PORT_IRQ_ERROR) {
793 struct sil24_cerr_info *ci = NULL;
794 unsigned int err_mask = 0, action = 0;
795 struct ata_queued_cmd *qc;
796 u32 cerr;
797
798 /* analyze CMD_ERR */
799 cerr = readl(port + PORT_CMD_ERR);
800 if (cerr < ARRAY_SIZE(sil24_cerr_db))
801 ci = &sil24_cerr_db[cerr];
802
803 if (ci && ci->desc) {
804 err_mask |= ci->err_mask;
805 action |= ci->action;
806 ata_ehi_push_desc(ehi, ", %s", ci->desc);
807 } else {
808 err_mask |= AC_ERR_OTHER;
809 action |= ATA_EH_SOFTRESET;
810 ata_ehi_push_desc(ehi, ", unknown command error %d",
811 cerr);
812 }
813
814 /* record error info */
815 qc = ata_qc_from_tag(ap, ap->active_tag);
816 if (qc) {
817 sil24_update_tf(ap);
818 qc->err_mask |= err_mask;
819 } else
820 ehi->err_mask |= err_mask;
821
822 ehi->action |= action;
823 }
824
825 /* freeze or abort */
826 if (freeze)
827 ata_port_freeze(ap);
828 else
829 ata_port_abort(ap);
830}
831
832static void sil24_finish_qc(struct ata_queued_cmd *qc)
833{
834 if (qc->flags & ATA_QCFLAG_RESULT_TF)
835 sil24_update_tf(qc->ap);
836}
837
838static inline void sil24_host_intr(struct ata_port *ap)
839{
840 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
841 u32 slot_stat, qc_active;
842 int rc;
843
844 slot_stat = readl(port + PORT_SLOT_STAT);
845
846 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
847 sil24_error_intr(ap);
848 return;
849 }
850
851 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
852 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
853
854 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
855 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
856 if (rc > 0)
857 return;
858 if (rc < 0) {
859 struct ata_eh_info *ehi = &ap->eh_info;
860 ehi->err_mask |= AC_ERR_HSM;
861 ehi->action |= ATA_EH_SOFTRESET;
862 ata_port_freeze(ap);
863 return;
864 }
865
866 if (ata_ratelimit())
867 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
868 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
869 slot_stat, ap->active_tag, ap->sactive);
870}
871
872static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
873{
874 struct ata_host_set *host_set = dev_instance;
875 struct sil24_host_priv *hpriv = host_set->private_data;
876 unsigned handled = 0;
877 u32 status;
878 int i;
879
880 status = readl(hpriv->host_base + HOST_IRQ_STAT);
881
882 if (status == 0xffffffff) {
883 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
884 "PCI fault or device removal?\n");
885 goto out;
886 }
887
888 if (!(status & IRQ_STAT_4PORTS))
889 goto out;
890
891 spin_lock(&host_set->lock);
892
893 for (i = 0; i < host_set->n_ports; i++)
894 if (status & (1 << i)) {
895 struct ata_port *ap = host_set->ports[i];
896 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
897 sil24_host_intr(host_set->ports[i]);
898 handled++;
899 } else
900 printk(KERN_ERR DRV_NAME
901 ": interrupt from disabled port %d\n", i);
902 }
903
904 spin_unlock(&host_set->lock);
905 out:
906 return IRQ_RETVAL(handled);
907}
908
909static void sil24_error_handler(struct ata_port *ap)
910{
911 struct ata_eh_context *ehc = &ap->eh_context;
912
913 if (sil24_init_port(ap)) {
914 ata_eh_freeze_port(ap);
915 ehc->i.action |= ATA_EH_HARDRESET;
916 }
917
918 /* perform recovery */
919 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
920 ata_std_postreset);
921}
922
923static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
924{
925 struct ata_port *ap = qc->ap;
926
927 if (qc->flags & ATA_QCFLAG_FAILED)
928 qc->err_mask |= AC_ERR_OTHER;
929
930 /* make DMA engine forget about the failed command */
931 if (qc->err_mask)
932 sil24_init_port(ap);
933}
934
935static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
936{
937 const size_t cb_size = sizeof(*pp->cmd_block) * SIL24_MAX_CMDS;
938
939 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
940}
941
942static int sil24_port_start(struct ata_port *ap)
943{
944 struct device *dev = ap->host_set->dev;
945 struct sil24_port_priv *pp;
946 union sil24_cmd_block *cb;
947 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
948 dma_addr_t cb_dma;
949 int rc = -ENOMEM;
950
951 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
952 if (!pp)
953 goto err_out;
954
955 pp->tf.command = ATA_DRDY;
956
957 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
958 if (!cb)
959 goto err_out_pp;
960 memset(cb, 0, cb_size);
961
962 rc = ata_pad_alloc(ap, dev);
963 if (rc)
964 goto err_out_pad;
965
966 pp->cmd_block = cb;
967 pp->cmd_block_dma = cb_dma;
968
969 ap->private_data = pp;
970
971 return 0;
972
973err_out_pad:
974 sil24_cblk_free(pp, dev);
975err_out_pp:
976 kfree(pp);
977err_out:
978 return rc;
979}
980
981static void sil24_port_stop(struct ata_port *ap)
982{
983 struct device *dev = ap->host_set->dev;
984 struct sil24_port_priv *pp = ap->private_data;
985
986 sil24_cblk_free(pp, dev);
987 ata_pad_free(ap, dev);
988 kfree(pp);
989}
990
991static void sil24_host_stop(struct ata_host_set *host_set)
992{
993 struct sil24_host_priv *hpriv = host_set->private_data;
994 struct pci_dev *pdev = to_pci_dev(host_set->dev);
995
996 pci_iounmap(pdev, hpriv->host_base);
997 pci_iounmap(pdev, hpriv->port_base);
998 kfree(hpriv);
999}
1000
1001static void sil24_init_controller(struct pci_dev *pdev, int n_ports,
1002 unsigned long host_flags,
1003 void __iomem *host_base,
1004 void __iomem *port_base)
1005{
1006 u32 tmp;
1007 int i;
1008
1009 /* GPIO off */
1010 writel(0, host_base + HOST_FLASH_CMD);
1011
1012 /* clear global reset & mask interrupts during initialization */
1013 writel(0, host_base + HOST_CTRL);
1014
1015 /* init ports */
1016 for (i = 0; i < n_ports; i++) {
1017 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1018
1019 /* Initial PHY setting */
1020 writel(0x20c, port + PORT_PHY_CFG);
1021
1022 /* Clear port RST */
1023 tmp = readl(port + PORT_CTRL_STAT);
1024 if (tmp & PORT_CS_PORT_RST) {
1025 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1026 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1027 PORT_CS_PORT_RST,
1028 PORT_CS_PORT_RST, 10, 100);
1029 if (tmp & PORT_CS_PORT_RST)
1030 dev_printk(KERN_ERR, &pdev->dev,
1031 "failed to clear port RST\n");
1032 }
1033
1034 /* Configure IRQ WoC */
1035 if (host_flags & SIL24_FLAG_PCIX_IRQ_WOC)
1036 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1037 else
1038 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1039
1040 /* Zero error counters. */
1041 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1042 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1043 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1044 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1045 writel(0x0000, port + PORT_CRC_ERR_CNT);
1046 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1047
1048 /* Always use 64bit activation */
1049 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1050
1051 /* Clear port multiplier enable and resume bits */
1052 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
1053 }
1054
1055 /* Turn on interrupts */
1056 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1057}
1058
1059static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1060{
1061 static int printed_version = 0;
1062 unsigned int board_id = (unsigned int)ent->driver_data;
1063 struct ata_port_info *pinfo = &sil24_port_info[board_id];
1064 struct ata_probe_ent *probe_ent = NULL;
1065 struct sil24_host_priv *hpriv = NULL;
1066 void __iomem *host_base = NULL;
1067 void __iomem *port_base = NULL;
1068 int i, rc;
1069 u32 tmp;
1070
1071 if (!printed_version++)
1072 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1073
1074 rc = pci_enable_device(pdev);
1075 if (rc)
1076 return rc;
1077
1078 rc = pci_request_regions(pdev, DRV_NAME);
1079 if (rc)
1080 goto out_disable;
1081
1082 rc = -ENOMEM;
1083 /* map mmio registers */
1084 host_base = pci_iomap(pdev, 0, 0);
1085 if (!host_base)
1086 goto out_free;
1087 port_base = pci_iomap(pdev, 2, 0);
1088 if (!port_base)
1089 goto out_free;
1090
1091 /* allocate & init probe_ent and hpriv */
1092 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
1093 if (!probe_ent)
1094 goto out_free;
1095
1096 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1097 if (!hpriv)
1098 goto out_free;
1099
1100 probe_ent->dev = pci_dev_to_dev(pdev);
1101 INIT_LIST_HEAD(&probe_ent->node);
1102
1103 probe_ent->sht = pinfo->sht;
1104 probe_ent->host_flags = pinfo->host_flags;
1105 probe_ent->pio_mask = pinfo->pio_mask;
1106 probe_ent->mwdma_mask = pinfo->mwdma_mask;
1107 probe_ent->udma_mask = pinfo->udma_mask;
1108 probe_ent->port_ops = pinfo->port_ops;
1109 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
1110
1111 probe_ent->irq = pdev->irq;
1112 probe_ent->irq_flags = IRQF_SHARED;
1113 probe_ent->private_data = hpriv;
1114
1115 hpriv->host_base = host_base;
1116 hpriv->port_base = port_base;
1117
1118 /*
1119 * Configure the device
1120 */
1121 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1122 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1123 if (rc) {
1124 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1125 if (rc) {
1126 dev_printk(KERN_ERR, &pdev->dev,
1127 "64-bit DMA enable failed\n");
1128 goto out_free;
1129 }
1130 }
1131 } else {
1132 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1133 if (rc) {
1134 dev_printk(KERN_ERR, &pdev->dev,
1135 "32-bit DMA enable failed\n");
1136 goto out_free;
1137 }
1138 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1139 if (rc) {
1140 dev_printk(KERN_ERR, &pdev->dev,
1141 "32-bit consistent DMA enable failed\n");
1142 goto out_free;
1143 }
1144 }
1145
1146 /* Apply workaround for completion IRQ loss on PCI-X errata */
1147 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1148 tmp = readl(host_base + HOST_CTRL);
1149 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1150 dev_printk(KERN_INFO, &pdev->dev,
1151 "Applying completion IRQ loss on PCI-X "
1152 "errata fix\n");
1153 else
1154 probe_ent->host_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1155 }
1156
1157 for (i = 0; i < probe_ent->n_ports; i++) {
1158 unsigned long portu =
1159 (unsigned long)port_base + i * PORT_REGS_SIZE;
1160
1161 probe_ent->port[i].cmd_addr = portu;
1162 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
1163
1164 ata_std_ports(&probe_ent->port[i]);
1165 }
1166
1167 sil24_init_controller(pdev, probe_ent->n_ports, probe_ent->host_flags,
1168 host_base, port_base);
1169
1170 pci_set_master(pdev);
1171
1172 /* FIXME: check ata_device_add return value */
1173 ata_device_add(probe_ent);
1174
1175 kfree(probe_ent);
1176 return 0;
1177
1178 out_free:
1179 if (host_base)
1180 pci_iounmap(pdev, host_base);
1181 if (port_base)
1182 pci_iounmap(pdev, port_base);
1183 kfree(probe_ent);
1184 kfree(hpriv);
1185 pci_release_regions(pdev);
1186 out_disable:
1187 pci_disable_device(pdev);
1188 return rc;
1189}
1190
1191#ifdef CONFIG_PM
1192static int sil24_pci_device_resume(struct pci_dev *pdev)
1193{
1194 struct ata_host_set *host_set = dev_get_drvdata(&pdev->dev);
1195 struct sil24_host_priv *hpriv = host_set->private_data;
1196
1197 ata_pci_device_do_resume(pdev);
1198
1199 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1200 writel(HOST_CTRL_GLOBAL_RST, hpriv->host_base + HOST_CTRL);
1201
1202 sil24_init_controller(pdev, host_set->n_ports,
1203 host_set->ports[0]->flags,
1204 hpriv->host_base, hpriv->port_base);
1205
1206 ata_host_set_resume(host_set);
1207
1208 return 0;
1209}
1210#endif
1211
1212static int __init sil24_init(void)
1213{
1214 return pci_register_driver(&sil24_pci_driver);
1215}
1216
1217static void __exit sil24_exit(void)
1218{
1219 pci_unregister_driver(&sil24_pci_driver);
1220}
1221
1222MODULE_AUTHOR("Tejun Heo");
1223MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1224MODULE_LICENSE("GPL");
1225MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1226
1227module_init(sil24_init);
1228module_exit(sil24_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-17 22:15:39 -0400