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path: root/drivers/ata/sata_promise.c
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Diffstat (limited to 'drivers/ata/sata_promise.c')
-rw-r--r--drivers/ata/sata_promise.c398
1 files changed, 212 insertions, 186 deletions
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c
index 2339813ce9f6..f56549b90aa6 100644
--- a/drivers/ata/sata_promise.c
+++ b/drivers/ata/sata_promise.c
@@ -45,10 +45,11 @@
45#include "sata_promise.h" 45#include "sata_promise.h"
46 46
47#define DRV_NAME "sata_promise" 47#define DRV_NAME "sata_promise"
48#define DRV_VERSION "2.00" 48#define DRV_VERSION "2.05"
49 49
50 50
51enum { 51enum {
52 PDC_MAX_PORTS = 4,
52 PDC_MMIO_BAR = 3, 53 PDC_MMIO_BAR = 3,
53 54
54 /* register offsets */ 55 /* register offsets */
@@ -70,14 +71,31 @@ enum {
70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ 71 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ 72 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
72 73
73 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | 74 /* PDC_GLOBAL_CTL bit definitions */
74 (1<<8) | (1<<9) | (1<<10), 75 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
76 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
77 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
78 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
79 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
80 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
81 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
82 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
83 PDC_DRIVE_ERR = (1 << 21), /* drive error */
84 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
85 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
86 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
87 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR,
88 PDC_ERR_MASK = (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC_OVERRUN_ERR
89 | PDC_UNDERRUN_ERR | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR
90 | PDC1_ERR_MASK | PDC2_ERR_MASK),
75 91
76 board_2037x = 0, /* FastTrak S150 TX2plus */ 92 board_2037x = 0, /* FastTrak S150 TX2plus */
77 board_20319 = 1, /* FastTrak S150 TX4 */ 93 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
78 board_20619 = 2, /* FastTrak TX4000 */ 94 board_20319 = 2, /* FastTrak S150 TX4 */
79 board_2057x = 3, /* SATAII150 Tx2plus */ 95 board_20619 = 3, /* FastTrak TX4000 */
80 board_40518 = 4, /* SATAII150 Tx4 */ 96 board_2057x = 4, /* SATAII150 Tx2plus */
97 board_2057x_pata = 5, /* SATAII150 Tx2plus */
98 board_40518 = 6, /* SATAII150 Tx4 */
81 99
82 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ 100 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
83 101
@@ -100,8 +118,10 @@ enum {
100 ATA_FLAG_MMIO | 118 ATA_FLAG_MMIO |
101 ATA_FLAG_PIO_POLLING, 119 ATA_FLAG_PIO_POLLING,
102 120
103 /* hp->flags bits */ 121 /* ap->flags bits */
104 PDC_FLAG_GEN_II = (1 << 0), 122 PDC_FLAG_GEN_II = (1 << 24),
123 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
124 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
105}; 125};
106 126
107 127
@@ -110,28 +130,25 @@ struct pdc_port_priv {
110 dma_addr_t pkt_dma; 130 dma_addr_t pkt_dma;
111}; 131};
112 132
113struct pdc_host_priv {
114 unsigned long flags;
115 unsigned long port_flags[ATA_MAX_PORTS];
116};
117
118static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); 133static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
119static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); 134static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
120static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 135static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
121static irqreturn_t pdc_interrupt (int irq, void *dev_instance); 136static int pdc_common_port_start(struct ata_port *ap);
122static int pdc_port_start(struct ata_port *ap); 137static int pdc_sata_port_start(struct ata_port *ap);
123static void pdc_qc_prep(struct ata_queued_cmd *qc); 138static void pdc_qc_prep(struct ata_queued_cmd *qc);
124static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 139static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
125static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 140static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
126static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); 141static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
127static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc); 142static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
128static void pdc_irq_clear(struct ata_port *ap); 143static void pdc_irq_clear(struct ata_port *ap);
129static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); 144static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
130static void pdc_freeze(struct ata_port *ap); 145static void pdc_freeze(struct ata_port *ap);
131static void pdc_thaw(struct ata_port *ap); 146static void pdc_thaw(struct ata_port *ap);
132static void pdc_error_handler(struct ata_port *ap); 147static void pdc_pata_error_handler(struct ata_port *ap);
148static void pdc_sata_error_handler(struct ata_port *ap);
133static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); 149static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
134 150static int pdc_pata_cable_detect(struct ata_port *ap);
151static int pdc_sata_cable_detect(struct ata_port *ap);
135 152
136static struct scsi_host_template pdc_ata_sht = { 153static struct scsi_host_template pdc_ata_sht = {
137 .module = THIS_MODULE, 154 .module = THIS_MODULE,
@@ -164,17 +181,17 @@ static const struct ata_port_operations pdc_sata_ops = {
164 .qc_issue = pdc_qc_issue_prot, 181 .qc_issue = pdc_qc_issue_prot,
165 .freeze = pdc_freeze, 182 .freeze = pdc_freeze,
166 .thaw = pdc_thaw, 183 .thaw = pdc_thaw,
167 .error_handler = pdc_error_handler, 184 .error_handler = pdc_sata_error_handler,
168 .post_internal_cmd = pdc_post_internal_cmd, 185 .post_internal_cmd = pdc_post_internal_cmd,
186 .cable_detect = pdc_sata_cable_detect,
169 .data_xfer = ata_data_xfer, 187 .data_xfer = ata_data_xfer,
170 .irq_handler = pdc_interrupt,
171 .irq_clear = pdc_irq_clear, 188 .irq_clear = pdc_irq_clear,
172 .irq_on = ata_irq_on, 189 .irq_on = ata_irq_on,
173 .irq_ack = ata_irq_ack, 190 .irq_ack = ata_irq_ack,
174 191
175 .scr_read = pdc_sata_scr_read, 192 .scr_read = pdc_sata_scr_read,
176 .scr_write = pdc_sata_scr_write, 193 .scr_write = pdc_sata_scr_write,
177 .port_start = pdc_port_start, 194 .port_start = pdc_sata_port_start,
178}; 195};
179 196
180/* First-generation chips need a more restrictive ->check_atapi_dma op */ 197/* First-generation chips need a more restrictive ->check_atapi_dma op */
@@ -185,23 +202,23 @@ static const struct ata_port_operations pdc_old_sata_ops = {
185 .check_status = ata_check_status, 202 .check_status = ata_check_status,
186 .exec_command = pdc_exec_command_mmio, 203 .exec_command = pdc_exec_command_mmio,
187 .dev_select = ata_std_dev_select, 204 .dev_select = ata_std_dev_select,
188 .check_atapi_dma = pdc_old_check_atapi_dma, 205 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
189 206
190 .qc_prep = pdc_qc_prep, 207 .qc_prep = pdc_qc_prep,
191 .qc_issue = pdc_qc_issue_prot, 208 .qc_issue = pdc_qc_issue_prot,
192 .freeze = pdc_freeze, 209 .freeze = pdc_freeze,
193 .thaw = pdc_thaw, 210 .thaw = pdc_thaw,
194 .error_handler = pdc_error_handler, 211 .error_handler = pdc_sata_error_handler,
195 .post_internal_cmd = pdc_post_internal_cmd, 212 .post_internal_cmd = pdc_post_internal_cmd,
213 .cable_detect = pdc_sata_cable_detect,
196 .data_xfer = ata_data_xfer, 214 .data_xfer = ata_data_xfer,
197 .irq_handler = pdc_interrupt,
198 .irq_clear = pdc_irq_clear, 215 .irq_clear = pdc_irq_clear,
199 .irq_on = ata_irq_on, 216 .irq_on = ata_irq_on,
200 .irq_ack = ata_irq_ack, 217 .irq_ack = ata_irq_ack,
201 218
202 .scr_read = pdc_sata_scr_read, 219 .scr_read = pdc_sata_scr_read,
203 .scr_write = pdc_sata_scr_write, 220 .scr_write = pdc_sata_scr_write,
204 .port_start = pdc_port_start, 221 .port_start = pdc_sata_port_start,
205}; 222};
206 223
207static const struct ata_port_operations pdc_pata_ops = { 224static const struct ata_port_operations pdc_pata_ops = {
@@ -217,32 +234,41 @@ static const struct ata_port_operations pdc_pata_ops = {
217 .qc_issue = pdc_qc_issue_prot, 234 .qc_issue = pdc_qc_issue_prot,
218 .freeze = pdc_freeze, 235 .freeze = pdc_freeze,
219 .thaw = pdc_thaw, 236 .thaw = pdc_thaw,
220 .error_handler = pdc_error_handler, 237 .error_handler = pdc_pata_error_handler,
221 .post_internal_cmd = pdc_post_internal_cmd, 238 .post_internal_cmd = pdc_post_internal_cmd,
239 .cable_detect = pdc_pata_cable_detect,
222 .data_xfer = ata_data_xfer, 240 .data_xfer = ata_data_xfer,
223 .irq_handler = pdc_interrupt,
224 .irq_clear = pdc_irq_clear, 241 .irq_clear = pdc_irq_clear,
225 .irq_on = ata_irq_on, 242 .irq_on = ata_irq_on,
226 .irq_ack = ata_irq_ack, 243 .irq_ack = ata_irq_ack,
227 244
228 .port_start = pdc_port_start, 245 .port_start = pdc_common_port_start,
229}; 246};
230 247
231static const struct ata_port_info pdc_port_info[] = { 248static const struct ata_port_info pdc_port_info[] = {
232 /* board_2037x */ 249 /* board_2037x */
233 { 250 {
234 .sht = &pdc_ata_sht, 251 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
235 .flags = PDC_COMMON_FLAGS, 252 PDC_FLAG_SATA_PATA,
236 .pio_mask = 0x1f, /* pio0-4 */ 253 .pio_mask = 0x1f, /* pio0-4 */
237 .mwdma_mask = 0x07, /* mwdma0-2 */ 254 .mwdma_mask = 0x07, /* mwdma0-2 */
238 .udma_mask = 0x7f, /* udma0-6 ; FIXME */ 255 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
239 .port_ops = &pdc_old_sata_ops, 256 .port_ops = &pdc_old_sata_ops,
240 }, 257 },
241 258
259 /* board_2037x_pata */
260 {
261 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
262 .pio_mask = 0x1f, /* pio0-4 */
263 .mwdma_mask = 0x07, /* mwdma0-2 */
264 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
265 .port_ops = &pdc_pata_ops,
266 },
267
242 /* board_20319 */ 268 /* board_20319 */
243 { 269 {
244 .sht = &pdc_ata_sht, 270 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
245 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, 271 PDC_FLAG_4_PORTS,
246 .pio_mask = 0x1f, /* pio0-4 */ 272 .pio_mask = 0x1f, /* pio0-4 */
247 .mwdma_mask = 0x07, /* mwdma0-2 */ 273 .mwdma_mask = 0x07, /* mwdma0-2 */
248 .udma_mask = 0x7f, /* udma0-6 ; FIXME */ 274 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
@@ -251,8 +277,8 @@ static const struct ata_port_info pdc_port_info[] = {
251 277
252 /* board_20619 */ 278 /* board_20619 */
253 { 279 {
254 .sht = &pdc_ata_sht, 280 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
255 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, 281 PDC_FLAG_4_PORTS,
256 .pio_mask = 0x1f, /* pio0-4 */ 282 .pio_mask = 0x1f, /* pio0-4 */
257 .mwdma_mask = 0x07, /* mwdma0-2 */ 283 .mwdma_mask = 0x07, /* mwdma0-2 */
258 .udma_mask = 0x7f, /* udma0-6 ; FIXME */ 284 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
@@ -261,18 +287,28 @@ static const struct ata_port_info pdc_port_info[] = {
261 287
262 /* board_2057x */ 288 /* board_2057x */
263 { 289 {
264 .sht = &pdc_ata_sht, 290 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
265 .flags = PDC_COMMON_FLAGS, 291 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
266 .pio_mask = 0x1f, /* pio0-4 */ 292 .pio_mask = 0x1f, /* pio0-4 */
267 .mwdma_mask = 0x07, /* mwdma0-2 */ 293 .mwdma_mask = 0x07, /* mwdma0-2 */
268 .udma_mask = 0x7f, /* udma0-6 ; FIXME */ 294 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
269 .port_ops = &pdc_sata_ops, 295 .port_ops = &pdc_sata_ops,
270 }, 296 },
271 297
298 /* board_2057x_pata */
299 {
300 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
301 PDC_FLAG_GEN_II,
302 .pio_mask = 0x1f, /* pio0-4 */
303 .mwdma_mask = 0x07, /* mwdma0-2 */
304 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
305 .port_ops = &pdc_pata_ops,
306 },
307
272 /* board_40518 */ 308 /* board_40518 */
273 { 309 {
274 .sht = &pdc_ata_sht, 310 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
275 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, 311 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
276 .pio_mask = 0x1f, /* pio0-4 */ 312 .pio_mask = 0x1f, /* pio0-4 */
277 .mwdma_mask = 0x07, /* mwdma0-2 */ 313 .mwdma_mask = 0x07, /* mwdma0-2 */
278 .udma_mask = 0x7f, /* udma0-6 ; FIXME */ 314 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
@@ -313,18 +349,12 @@ static struct pci_driver pdc_ata_pci_driver = {
313}; 349};
314 350
315 351
316static int pdc_port_start(struct ata_port *ap) 352static int pdc_common_port_start(struct ata_port *ap)
317{ 353{
318 struct device *dev = ap->host->dev; 354 struct device *dev = ap->host->dev;
319 struct pdc_host_priv *hp = ap->host->private_data;
320 struct pdc_port_priv *pp; 355 struct pdc_port_priv *pp;
321 int rc; 356 int rc;
322 357
323 /* fix up port flags and cable type for SATA+PATA chips */
324 ap->flags |= hp->port_flags[ap->port_no];
325 if (ap->flags & ATA_FLAG_SATA)
326 ap->cbl = ATA_CBL_SATA;
327
328 rc = ata_port_start(ap); 358 rc = ata_port_start(ap);
329 if (rc) 359 if (rc)
330 return rc; 360 return rc;
@@ -339,8 +369,19 @@ static int pdc_port_start(struct ata_port *ap)
339 369
340 ap->private_data = pp; 370 ap->private_data = pp;
341 371
372 return 0;
373}
374
375static int pdc_sata_port_start(struct ata_port *ap)
376{
377 int rc;
378
379 rc = pdc_common_port_start(ap);
380 if (rc)
381 return rc;
382
342 /* fix up PHYMODE4 align timing */ 383 /* fix up PHYMODE4 align timing */
343 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) { 384 if (ap->flags & PDC_FLAG_GEN_II) {
344 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr; 385 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
345 unsigned int tmp; 386 unsigned int tmp;
346 387
@@ -374,23 +415,25 @@ static void pdc_reset_port(struct ata_port *ap)
374 readl(mmio); /* flush */ 415 readl(mmio); /* flush */
375} 416}
376 417
377static void pdc_pata_cbl_detect(struct ata_port *ap) 418static int pdc_pata_cable_detect(struct ata_port *ap)
378{ 419{
379 u8 tmp; 420 u8 tmp;
380 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; 421 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
381 422
382 tmp = readb(mmio); 423 tmp = readb(mmio);
424 if (tmp & 0x01)
425 return ATA_CBL_PATA40;
426 return ATA_CBL_PATA80;
427}
383 428
384 if (tmp & 0x01) { 429static int pdc_sata_cable_detect(struct ata_port *ap)
385 ap->cbl = ATA_CBL_PATA40; 430{
386 ap->udma_mask &= ATA_UDMA_MASK_40C; 431 return ATA_CBL_SATA;
387 } else
388 ap->cbl = ATA_CBL_PATA80;
389} 432}
390 433
391static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) 434static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
392{ 435{
393 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) 436 if (sc_reg > SCR_CONTROL)
394 return 0xffffffffU; 437 return 0xffffffffU;
395 return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); 438 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
396} 439}
@@ -399,7 +442,7 @@ static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
399static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, 442static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
400 u32 val) 443 u32 val)
401{ 444{
402 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) 445 if (sc_reg > SCR_CONTROL)
403 return; 446 return;
404 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); 447 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
405} 448}
@@ -555,52 +598,79 @@ static void pdc_thaw(struct ata_port *ap)
555 readl(mmio + PDC_CTLSTAT); /* flush */ 598 readl(mmio + PDC_CTLSTAT); /* flush */
556} 599}
557 600
558static int pdc_pre_reset(struct ata_port *ap) 601static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
559{
560 if (!sata_scr_valid(ap))
561 pdc_pata_cbl_detect(ap);
562 return ata_std_prereset(ap);
563}
564
565static void pdc_error_handler(struct ata_port *ap)
566{ 602{
567 ata_reset_fn_t hardreset;
568
569 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 603 if (!(ap->pflags & ATA_PFLAG_FROZEN))
570 pdc_reset_port(ap); 604 pdc_reset_port(ap);
571 605
572 hardreset = NULL;
573 if (sata_scr_valid(ap))
574 hardreset = sata_std_hardreset;
575
576 /* perform recovery */ 606 /* perform recovery */
577 ata_do_eh(ap, pdc_pre_reset, ata_std_softreset, hardreset, 607 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
578 ata_std_postreset); 608 ata_std_postreset);
579} 609}
580 610
611static void pdc_pata_error_handler(struct ata_port *ap)
612{
613 pdc_common_error_handler(ap, NULL);
614}
615
616static void pdc_sata_error_handler(struct ata_port *ap)
617{
618 pdc_common_error_handler(ap, sata_std_hardreset);
619}
620
581static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) 621static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
582{ 622{
583 struct ata_port *ap = qc->ap; 623 struct ata_port *ap = qc->ap;
584 624
585 if (qc->flags & ATA_QCFLAG_FAILED)
586 qc->err_mask |= AC_ERR_OTHER;
587
588 /* make DMA engine forget about the failed command */ 625 /* make DMA engine forget about the failed command */
589 if (qc->err_mask) 626 if (qc->flags & ATA_QCFLAG_FAILED)
590 pdc_reset_port(ap); 627 pdc_reset_port(ap);
591} 628}
592 629
630static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
631 u32 port_status, u32 err_mask)
632{
633 struct ata_eh_info *ehi = &ap->eh_info;
634 unsigned int ac_err_mask = 0;
635
636 ata_ehi_clear_desc(ehi);
637 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
638 port_status &= err_mask;
639
640 if (port_status & PDC_DRIVE_ERR)
641 ac_err_mask |= AC_ERR_DEV;
642 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
643 ac_err_mask |= AC_ERR_HSM;
644 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
645 ac_err_mask |= AC_ERR_ATA_BUS;
646 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
647 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
648 ac_err_mask |= AC_ERR_HOST_BUS;
649
650 if (sata_scr_valid(ap))
651 ehi->serror |= pdc_sata_scr_read(ap, SCR_ERROR);
652
653 qc->err_mask |= ac_err_mask;
654
655 pdc_reset_port(ap);
656}
657
593static inline unsigned int pdc_host_intr( struct ata_port *ap, 658static inline unsigned int pdc_host_intr( struct ata_port *ap,
594 struct ata_queued_cmd *qc) 659 struct ata_queued_cmd *qc)
595{ 660{
596 unsigned int handled = 0; 661 unsigned int handled = 0;
597 u32 tmp; 662 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
598 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; 663 u32 port_status, err_mask;
599 664
600 tmp = readl(mmio); 665 err_mask = PDC_ERR_MASK;
601 if (tmp & PDC_ERR_MASK) { 666 if (ap->flags & PDC_FLAG_GEN_II)
602 qc->err_mask |= AC_ERR_DEV; 667 err_mask &= ~PDC1_ERR_MASK;
603 pdc_reset_port(ap); 668 else
669 err_mask &= ~PDC2_ERR_MASK;
670 port_status = readl(port_mmio + PDC_GLOBAL_CTL);
671 if (unlikely(port_status & err_mask)) {
672 pdc_error_intr(ap, qc, port_status, err_mask);
673 return 1;
604 } 674 }
605 675
606 switch (qc->tf.protocol) { 676 switch (qc->tf.protocol) {
@@ -767,44 +837,40 @@ static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
767 return pio; 837 return pio;
768} 838}
769 839
770static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc) 840static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
771{ 841{
772 struct ata_port *ap = qc->ap;
773
774 /* First generation chips cannot use ATAPI DMA on SATA ports */ 842 /* First generation chips cannot use ATAPI DMA on SATA ports */
775 if (sata_scr_valid(ap)) 843 return 1;
776 return 1;
777 return pdc_check_atapi_dma(qc);
778} 844}
779 845
780static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base, 846static void pdc_ata_setup_port(struct ata_port *ap,
781 void __iomem *scr_addr) 847 void __iomem *base, void __iomem *scr_addr)
782{ 848{
783 port->cmd_addr = base; 849 ap->ioaddr.cmd_addr = base;
784 port->data_addr = base; 850 ap->ioaddr.data_addr = base;
785 port->feature_addr = 851 ap->ioaddr.feature_addr =
786 port->error_addr = base + 0x4; 852 ap->ioaddr.error_addr = base + 0x4;
787 port->nsect_addr = base + 0x8; 853 ap->ioaddr.nsect_addr = base + 0x8;
788 port->lbal_addr = base + 0xc; 854 ap->ioaddr.lbal_addr = base + 0xc;
789 port->lbam_addr = base + 0x10; 855 ap->ioaddr.lbam_addr = base + 0x10;
790 port->lbah_addr = base + 0x14; 856 ap->ioaddr.lbah_addr = base + 0x14;
791 port->device_addr = base + 0x18; 857 ap->ioaddr.device_addr = base + 0x18;
792 port->command_addr = 858 ap->ioaddr.command_addr =
793 port->status_addr = base + 0x1c; 859 ap->ioaddr.status_addr = base + 0x1c;
794 port->altstatus_addr = 860 ap->ioaddr.altstatus_addr =
795 port->ctl_addr = base + 0x38; 861 ap->ioaddr.ctl_addr = base + 0x38;
796 port->scr_addr = scr_addr; 862 ap->ioaddr.scr_addr = scr_addr;
797} 863}
798 864
799 865
800static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) 866static void pdc_host_init(struct ata_host *host)
801{ 867{
802 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 868 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
803 struct pdc_host_priv *hp = pe->private_data; 869 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
804 int hotplug_offset; 870 int hotplug_offset;
805 u32 tmp; 871 u32 tmp;
806 872
807 if (hp->flags & PDC_FLAG_GEN_II) 873 if (is_gen2)
808 hotplug_offset = PDC2_SATA_PLUG_CSR; 874 hotplug_offset = PDC2_SATA_PLUG_CSR;
809 else 875 else
810 hotplug_offset = PDC_SATA_PLUG_CSR; 876 hotplug_offset = PDC_SATA_PLUG_CSR;
@@ -818,7 +884,7 @@ static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
818 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ 884 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
819 tmp = readl(mmio + PDC_FLASH_CTL); 885 tmp = readl(mmio + PDC_FLASH_CTL);
820 tmp |= 0x02000; /* bit 13 (enable bmr burst) */ 886 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
821 if (!(hp->flags & PDC_FLAG_GEN_II)) 887 if (!is_gen2)
822 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ 888 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
823 writel(tmp, mmio + PDC_FLASH_CTL); 889 writel(tmp, mmio + PDC_FLASH_CTL);
824 890
@@ -831,7 +897,7 @@ static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
831 writel(tmp | 0xff0000, mmio + hotplug_offset); 897 writel(tmp | 0xff0000, mmio + hotplug_offset);
832 898
833 /* don't initialise TBG or SLEW on 2nd generation chips */ 899 /* don't initialise TBG or SLEW on 2nd generation chips */
834 if (hp->flags & PDC_FLAG_GEN_II) 900 if (is_gen2)
835 return; 901 return;
836 902
837 /* reduce TBG clock to 133 Mhz. */ 903 /* reduce TBG clock to 133 Mhz. */
@@ -853,16 +919,16 @@ static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
853static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 919static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
854{ 920{
855 static int printed_version; 921 static int printed_version;
856 struct ata_probe_ent *probe_ent; 922 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
857 struct pdc_host_priv *hp; 923 const struct ata_port_info *ppi[PDC_MAX_PORTS];
924 struct ata_host *host;
858 void __iomem *base; 925 void __iomem *base;
859 unsigned int board_idx = (unsigned int) ent->driver_data; 926 int n_ports, i, rc;
860 int rc;
861 u8 tmp;
862 927
863 if (!printed_version++) 928 if (!printed_version++)
864 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 929 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
865 930
931 /* enable and acquire resources */
866 rc = pcim_enable_device(pdev); 932 rc = pcim_enable_device(pdev);
867 if (rc) 933 if (rc)
868 return rc; 934 return rc;
@@ -872,89 +938,49 @@ static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *e
872 pcim_pin_device(pdev); 938 pcim_pin_device(pdev);
873 if (rc) 939 if (rc)
874 return rc; 940 return rc;
941 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
875 942
876 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 943 /* determine port configuration and setup host */
877 if (rc) 944 n_ports = 2;
878 return rc; 945 if (pi->flags & PDC_FLAG_4_PORTS)
879 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 946 n_ports = 4;
880 if (rc) 947 for (i = 0; i < n_ports; i++)
881 return rc; 948 ppi[i] = pi;
882
883 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
884 if (probe_ent == NULL)
885 return -ENOMEM;
886 949
887 probe_ent->dev = pci_dev_to_dev(pdev); 950 if (pi->flags & PDC_FLAG_SATA_PATA) {
888 INIT_LIST_HEAD(&probe_ent->node); 951 u8 tmp = readb(base + PDC_FLASH_CTL+1);
952 if (!(tmp & 0x80)) {
953 ppi[n_ports++] = pi + 1;
954 dev_printk(KERN_INFO, &pdev->dev, "PATA port found\n");
955 }
956 }
889 957
890 hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL); 958 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
891 if (hp == NULL) 959 if (!host) {
960 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
892 return -ENOMEM; 961 return -ENOMEM;
893
894 probe_ent->private_data = hp;
895
896 probe_ent->sht = pdc_port_info[board_idx].sht;
897 probe_ent->port_flags = pdc_port_info[board_idx].flags;
898 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
899 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
900 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
901 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
902
903 probe_ent->irq = pdev->irq;
904 probe_ent->irq_flags = IRQF_SHARED;
905 probe_ent->iomap = pcim_iomap_table(pdev);
906
907 base = probe_ent->iomap[PDC_MMIO_BAR];
908
909 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200, base + 0x400);
910 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280, base + 0x500);
911
912 /* notice 4-port boards */
913 switch (board_idx) {
914 case board_40518:
915 hp->flags |= PDC_FLAG_GEN_II;
916 /* Fall through */
917 case board_20319:
918 probe_ent->n_ports = 4;
919 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, base + 0x600);
920 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, base + 0x700);
921 break;
922 case board_2057x:
923 hp->flags |= PDC_FLAG_GEN_II;
924 /* Fall through */
925 case board_2037x:
926 /* TX2plus boards also have a PATA port */
927 tmp = readb(base + PDC_FLASH_CTL+1);
928 if (!(tmp & 0x80)) {
929 probe_ent->n_ports = 3;
930 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
931 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
932 printk(KERN_INFO DRV_NAME " PATA port found\n");
933 } else
934 probe_ent->n_ports = 2;
935 hp->port_flags[0] = ATA_FLAG_SATA;
936 hp->port_flags[1] = ATA_FLAG_SATA;
937 break;
938 case board_20619:
939 probe_ent->n_ports = 4;
940 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
941 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, NULL);
942 break;
943 default:
944 BUG();
945 break;
946 } 962 }
963 host->iomap = pcim_iomap_table(pdev);
947 964
948 pci_set_master(pdev); 965 for (i = 0; i < host->n_ports; i++)
966 pdc_ata_setup_port(host->ports[i],
967 base + 0x200 + i * 0x80,
968 base + 0x400 + i * 0x100);
949 969
950 /* initialize adapter */ 970 /* initialize adapter */
951 pdc_host_init(board_idx, probe_ent); 971 pdc_host_init(host);
952 972
953 if (!ata_device_add(probe_ent)) 973 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
954 return -ENODEV; 974 if (rc)
975 return rc;
976 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
977 if (rc)
978 return rc;
955 979
956 devm_kfree(&pdev->dev, probe_ent); 980 /* start host, request IRQ and attach */
957 return 0; 981 pci_set_master(pdev);
982 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
983 &pdc_ata_sht);
958} 984}
959 985
960 986