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path: root/drivers/ata/sata_promise.c
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Diffstat (limited to 'drivers/ata/sata_promise.c')
-rw-r--r--drivers/ata/sata_promise.c46
1 files changed, 33 insertions, 13 deletions
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c
index 72eda5160fad..a2778cf016bc 100644
--- a/drivers/ata/sata_promise.c
+++ b/drivers/ata/sata_promise.c
@@ -46,20 +46,19 @@
46#include "sata_promise.h" 46#include "sata_promise.h"
47 47
48#define DRV_NAME "sata_promise" 48#define DRV_NAME "sata_promise"
49#define DRV_VERSION "1.04" 49#define DRV_VERSION "1.05"
50 50
51 51
52enum { 52enum {
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ 53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ 54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE = 0x41, /* TBG mode */
56 PDC_FLASH_CTL = 0x44, /* Flash control register */ 55 PDC_FLASH_CTL = 0x44, /* Flash control register */
57 PDC_PCI_CTL = 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ 56 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ 57 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ 58 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ 59 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
62 PDC_SLEW_CTL = 0x470, /* slew rate control reg */ 60 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
61 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
63 62
64 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | 63 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
65 (1<<8) | (1<<9) | (1<<10), 64 (1<<8) | (1<<9) | (1<<10),
@@ -78,6 +77,9 @@ enum {
78 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST | 77 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
79 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 78 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
80 ATA_FLAG_PIO_POLLING, 79 ATA_FLAG_PIO_POLLING,
80
81 /* hp->flags bits */
82 PDC_FLAG_GEN_II = (1 << 0),
81}; 83};
82 84
83 85
@@ -87,6 +89,7 @@ struct pdc_port_priv {
87}; 89};
88 90
89struct pdc_host_priv { 91struct pdc_host_priv {
92 unsigned long flags;
90 int hotplug_offset; 93 int hotplug_offset;
91}; 94};
92 95
@@ -235,20 +238,20 @@ static const struct ata_port_info pdc_port_info[] = {
235 238
236static const struct pci_device_id pdc_ata_pci_tbl[] = { 239static const struct pci_device_id pdc_ata_pci_tbl[] = {
237 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, 240 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
238 { PCI_VDEVICE(PROMISE, 0x3570), board_2037x },
239 { PCI_VDEVICE(PROMISE, 0x3571), board_2037x },
240 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, 241 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
241 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, 242 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
242 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, 243 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
244 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
245 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
243 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, 246 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
247 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
244 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, 248 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
245 { PCI_VDEVICE(PROMISE, 0x3d73), board_2037x },
246 249
247 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, 250 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
248 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, 251 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
249 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 }, 252 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
250 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 }, 253 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
251 { PCI_VDEVICE(PROMISE, 0x3d17), board_20319 }, 254 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
252 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, 255 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
253 256
254 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, 257 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
@@ -277,6 +280,7 @@ static struct pci_driver pdc_ata_pci_driver = {
277static int pdc_port_start(struct ata_port *ap) 280static int pdc_port_start(struct ata_port *ap)
278{ 281{
279 struct device *dev = ap->host->dev; 282 struct device *dev = ap->host->dev;
283 struct pdc_host_priv *hp = ap->host->private_data;
280 struct pdc_port_priv *pp; 284 struct pdc_port_priv *pp;
281 int rc; 285 int rc;
282 286
@@ -298,6 +302,16 @@ static int pdc_port_start(struct ata_port *ap)
298 302
299 ap->private_data = pp; 303 ap->private_data = pp;
300 304
305 /* fix up PHYMODE4 align timing */
306 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
307 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
308 unsigned int tmp;
309
310 tmp = readl(mmio + 0x014);
311 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
312 writel(tmp, mmio + 0x014);
313 }
314
301 return 0; 315 return 0;
302 316
303err_out_kfree: 317err_out_kfree:
@@ -640,9 +654,11 @@ static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
640 * "TODO: figure out why we do this" 654 * "TODO: figure out why we do this"
641 */ 655 */
642 656
643 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */ 657 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
644 tmp = readl(mmio + PDC_FLASH_CTL); 658 tmp = readl(mmio + PDC_FLASH_CTL);
645 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */ 659 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
660 if (!(hp->flags & PDC_FLAG_GEN_II))
661 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
646 writel(tmp, mmio + PDC_FLASH_CTL); 662 writel(tmp, mmio + PDC_FLASH_CTL);
647 663
648 /* clear plug/unplug flags for all ports */ 664 /* clear plug/unplug flags for all ports */
@@ -653,6 +669,10 @@ static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
653 tmp = readl(mmio + hotplug_offset); 669 tmp = readl(mmio + hotplug_offset);
654 writel(tmp | 0xff0000, mmio + hotplug_offset); 670 writel(tmp | 0xff0000, mmio + hotplug_offset);
655 671
672 /* don't initialise TBG or SLEW on 2nd generation chips */
673 if (hp->flags & PDC_FLAG_GEN_II)
674 return;
675
656 /* reduce TBG clock to 133 Mhz. */ 676 /* reduce TBG clock to 133 Mhz. */
657 tmp = readl(mmio + PDC_TBG_MODE); 677 tmp = readl(mmio + PDC_TBG_MODE);
658 tmp &= ~0x30000; /* clear bit 17, 16*/ 678 tmp &= ~0x30000; /* clear bit 17, 16*/
@@ -746,6 +766,7 @@ static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *e
746 /* notice 4-port boards */ 766 /* notice 4-port boards */
747 switch (board_idx) { 767 switch (board_idx) {
748 case board_40518: 768 case board_40518:
769 hp->flags |= PDC_FLAG_GEN_II;
749 /* Override hotplug offset for SATAII150 */ 770 /* Override hotplug offset for SATAII150 */
750 hp->hotplug_offset = PDC2_SATA_PLUG_CSR; 771 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
751 /* Fall through */ 772 /* Fall through */
@@ -759,15 +780,14 @@ static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *e
759 probe_ent->port[3].scr_addr = base + 0x700; 780 probe_ent->port[3].scr_addr = base + 0x700;
760 break; 781 break;
761 case board_2057x: 782 case board_2057x:
783 case board_20771:
784 hp->flags |= PDC_FLAG_GEN_II;
762 /* Override hotplug offset for SATAII150 */ 785 /* Override hotplug offset for SATAII150 */
763 hp->hotplug_offset = PDC2_SATA_PLUG_CSR; 786 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
764 /* Fall through */ 787 /* Fall through */
765 case board_2037x: 788 case board_2037x:
766 probe_ent->n_ports = 2; 789 probe_ent->n_ports = 2;
767 break; 790 break;
768 case board_20771:
769 probe_ent->n_ports = 2;
770 break;
771 case board_20619: 791 case board_20619:
772 probe_ent->n_ports = 4; 792 probe_ent->n_ports = 4;
773 793