diff options
Diffstat (limited to 'drivers/ata/sata_nv.c')
-rw-r--r-- | drivers/ata/sata_nv.c | 84 |
1 files changed, 10 insertions, 74 deletions
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c index b564ff84a390..4d9357caa1ac 100644 --- a/drivers/ata/sata_nv.c +++ b/drivers/ata/sata_nv.c | |||
@@ -255,10 +255,7 @@ static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg); | |||
255 | static int nv_adma_port_resume(struct ata_port *ap); | 255 | static int nv_adma_port_resume(struct ata_port *ap); |
256 | static void nv_adma_error_handler(struct ata_port *ap); | 256 | static void nv_adma_error_handler(struct ata_port *ap); |
257 | static void nv_adma_host_stop(struct ata_host *host); | 257 | static void nv_adma_host_stop(struct ata_host *host); |
258 | static void nv_adma_bmdma_setup(struct ata_queued_cmd *qc); | 258 | static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc); |
259 | static void nv_adma_bmdma_start(struct ata_queued_cmd *qc); | ||
260 | static void nv_adma_bmdma_stop(struct ata_queued_cmd *qc); | ||
261 | static u8 nv_adma_bmdma_status(struct ata_port *ap); | ||
262 | 259 | ||
263 | enum nv_host_type | 260 | enum nv_host_type |
264 | { | 261 | { |
@@ -433,16 +430,16 @@ static const struct ata_port_operations nv_adma_ops = { | |||
433 | .exec_command = ata_exec_command, | 430 | .exec_command = ata_exec_command, |
434 | .check_status = ata_check_status, | 431 | .check_status = ata_check_status, |
435 | .dev_select = ata_std_dev_select, | 432 | .dev_select = ata_std_dev_select, |
436 | .bmdma_setup = nv_adma_bmdma_setup, | 433 | .bmdma_setup = ata_bmdma_setup, |
437 | .bmdma_start = nv_adma_bmdma_start, | 434 | .bmdma_start = ata_bmdma_start, |
438 | .bmdma_stop = nv_adma_bmdma_stop, | 435 | .bmdma_stop = ata_bmdma_stop, |
439 | .bmdma_status = nv_adma_bmdma_status, | 436 | .bmdma_status = ata_bmdma_status, |
440 | .qc_prep = nv_adma_qc_prep, | 437 | .qc_prep = nv_adma_qc_prep, |
441 | .qc_issue = nv_adma_qc_issue, | 438 | .qc_issue = nv_adma_qc_issue, |
442 | .freeze = nv_ck804_freeze, | 439 | .freeze = nv_ck804_freeze, |
443 | .thaw = nv_ck804_thaw, | 440 | .thaw = nv_ck804_thaw, |
444 | .error_handler = nv_adma_error_handler, | 441 | .error_handler = nv_adma_error_handler, |
445 | .post_internal_cmd = nv_adma_bmdma_stop, | 442 | .post_internal_cmd = nv_adma_post_internal_cmd, |
446 | .data_xfer = ata_data_xfer, | 443 | .data_xfer = ata_data_xfer, |
447 | .irq_handler = nv_adma_interrupt, | 444 | .irq_handler = nv_adma_interrupt, |
448 | .irq_clear = nv_adma_irq_clear, | 445 | .irq_clear = nv_adma_irq_clear, |
@@ -899,73 +896,12 @@ static void nv_adma_irq_clear(struct ata_port *ap) | |||
899 | iowrite8(ioread8(dma_stat_addr), dma_stat_addr); | 896 | iowrite8(ioread8(dma_stat_addr), dma_stat_addr); |
900 | } | 897 | } |
901 | 898 | ||
902 | static void nv_adma_bmdma_setup(struct ata_queued_cmd *qc) | 899 | static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc) |
903 | { | ||
904 | struct ata_port *ap = qc->ap; | ||
905 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | ||
906 | struct nv_adma_port_priv *pp = ap->private_data; | ||
907 | u8 dmactl; | ||
908 | |||
909 | if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) { | ||
910 | WARN_ON(1); | ||
911 | return; | ||
912 | } | ||
913 | |||
914 | /* load PRD table addr. */ | ||
915 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | ||
916 | |||
917 | /* specify data direction, triple-check start bit is clear */ | ||
918 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
919 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | ||
920 | if (!rw) | ||
921 | dmactl |= ATA_DMA_WR; | ||
922 | |||
923 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
924 | |||
925 | /* issue r/w command */ | ||
926 | ata_exec_command(ap, &qc->tf); | ||
927 | } | ||
928 | |||
929 | static void nv_adma_bmdma_start(struct ata_queued_cmd *qc) | ||
930 | { | ||
931 | struct ata_port *ap = qc->ap; | ||
932 | struct nv_adma_port_priv *pp = ap->private_data; | ||
933 | u8 dmactl; | ||
934 | |||
935 | if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) { | ||
936 | WARN_ON(1); | ||
937 | return; | ||
938 | } | ||
939 | |||
940 | /* start host DMA transaction */ | ||
941 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
942 | iowrite8(dmactl | ATA_DMA_START, | ||
943 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
944 | } | ||
945 | |||
946 | static void nv_adma_bmdma_stop(struct ata_queued_cmd *qc) | ||
947 | { | ||
948 | struct ata_port *ap = qc->ap; | ||
949 | struct nv_adma_port_priv *pp = ap->private_data; | ||
950 | |||
951 | if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) | ||
952 | return; | ||
953 | |||
954 | /* clear start/stop bit */ | ||
955 | iowrite8(ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START, | ||
956 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
957 | |||
958 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | ||
959 | ata_altstatus(ap); /* dummy read */ | ||
960 | } | ||
961 | |||
962 | static u8 nv_adma_bmdma_status(struct ata_port *ap) | ||
963 | { | 900 | { |
964 | struct nv_adma_port_priv *pp = ap->private_data; | 901 | struct nv_adma_port_priv *pp = qc->ap->private_data; |
965 | |||
966 | WARN_ON(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)); | ||
967 | 902 | ||
968 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | 903 | if(pp->flags & NV_ADMA_PORT_REGISTER_MODE) |
904 | ata_bmdma_post_internal_cmd(qc); | ||
969 | } | 905 | } |
970 | 906 | ||
971 | static int nv_adma_port_start(struct ata_port *ap) | 907 | static int nv_adma_port_start(struct ata_port *ap) |