diff options
Diffstat (limited to 'drivers/ata/sata_mv.c')
-rw-r--r-- | drivers/ata/sata_mv.c | 2468 |
1 files changed, 2468 insertions, 0 deletions
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c new file mode 100644 index 000000000000..a2915a56accd --- /dev/null +++ b/drivers/ata/sata_mv.c | |||
@@ -0,0 +1,2468 @@ | |||
1 | /* | ||
2 | * sata_mv.c - Marvell SATA support | ||
3 | * | ||
4 | * Copyright 2005: EMC Corporation, all rights reserved. | ||
5 | * Copyright 2005 Red Hat, Inc. All rights reserved. | ||
6 | * | ||
7 | * Please ALWAYS copy linux-ide@vger.kernel.org on emails. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; version 2 of the License. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
21 | * | ||
22 | */ | ||
23 | |||
24 | #include <linux/kernel.h> | ||
25 | #include <linux/module.h> | ||
26 | #include <linux/pci.h> | ||
27 | #include <linux/init.h> | ||
28 | #include <linux/blkdev.h> | ||
29 | #include <linux/delay.h> | ||
30 | #include <linux/interrupt.h> | ||
31 | #include <linux/sched.h> | ||
32 | #include <linux/dma-mapping.h> | ||
33 | #include <linux/device.h> | ||
34 | #include <scsi/scsi_host.h> | ||
35 | #include <scsi/scsi_cmnd.h> | ||
36 | #include <linux/libata.h> | ||
37 | #include <asm/io.h> | ||
38 | |||
39 | #define DRV_NAME "sata_mv" | ||
40 | #define DRV_VERSION "0.7" | ||
41 | |||
42 | enum { | ||
43 | /* BAR's are enumerated in terms of pci_resource_start() terms */ | ||
44 | MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ | ||
45 | MV_IO_BAR = 2, /* offset 0x18: IO space */ | ||
46 | MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ | ||
47 | |||
48 | MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ | ||
49 | MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ | ||
50 | |||
51 | MV_PCI_REG_BASE = 0, | ||
52 | MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ | ||
53 | MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), | ||
54 | MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), | ||
55 | MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), | ||
56 | MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), | ||
57 | MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), | ||
58 | |||
59 | MV_SATAHC0_REG_BASE = 0x20000, | ||
60 | MV_FLASH_CTL = 0x1046c, | ||
61 | MV_GPIO_PORT_CTL = 0x104f0, | ||
62 | MV_RESET_CFG = 0x180d8, | ||
63 | |||
64 | MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, | ||
65 | MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, | ||
66 | MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ | ||
67 | MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, | ||
68 | |||
69 | MV_USE_Q_DEPTH = ATA_DEF_QUEUE, | ||
70 | |||
71 | MV_MAX_Q_DEPTH = 32, | ||
72 | MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, | ||
73 | |||
74 | /* CRQB needs alignment on a 1KB boundary. Size == 1KB | ||
75 | * CRPB needs alignment on a 256B boundary. Size == 256B | ||
76 | * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB | ||
77 | * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B | ||
78 | */ | ||
79 | MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), | ||
80 | MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), | ||
81 | MV_MAX_SG_CT = 176, | ||
82 | MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), | ||
83 | MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ), | ||
84 | |||
85 | MV_PORTS_PER_HC = 4, | ||
86 | /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ | ||
87 | MV_PORT_HC_SHIFT = 2, | ||
88 | /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */ | ||
89 | MV_PORT_MASK = 3, | ||
90 | |||
91 | /* Host Flags */ | ||
92 | MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ | ||
93 | MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ | ||
94 | MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | ||
95 | ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | | ||
96 | ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING), | ||
97 | MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, | ||
98 | |||
99 | CRQB_FLAG_READ = (1 << 0), | ||
100 | CRQB_TAG_SHIFT = 1, | ||
101 | CRQB_CMD_ADDR_SHIFT = 8, | ||
102 | CRQB_CMD_CS = (0x2 << 11), | ||
103 | CRQB_CMD_LAST = (1 << 15), | ||
104 | |||
105 | CRPB_FLAG_STATUS_SHIFT = 8, | ||
106 | |||
107 | EPRD_FLAG_END_OF_TBL = (1 << 31), | ||
108 | |||
109 | /* PCI interface registers */ | ||
110 | |||
111 | PCI_COMMAND_OFS = 0xc00, | ||
112 | |||
113 | PCI_MAIN_CMD_STS_OFS = 0xd30, | ||
114 | STOP_PCI_MASTER = (1 << 2), | ||
115 | PCI_MASTER_EMPTY = (1 << 3), | ||
116 | GLOB_SFT_RST = (1 << 4), | ||
117 | |||
118 | MV_PCI_MODE = 0xd00, | ||
119 | MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, | ||
120 | MV_PCI_DISC_TIMER = 0xd04, | ||
121 | MV_PCI_MSI_TRIGGER = 0xc38, | ||
122 | MV_PCI_SERR_MASK = 0xc28, | ||
123 | MV_PCI_XBAR_TMOUT = 0x1d04, | ||
124 | MV_PCI_ERR_LOW_ADDRESS = 0x1d40, | ||
125 | MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, | ||
126 | MV_PCI_ERR_ATTRIBUTE = 0x1d48, | ||
127 | MV_PCI_ERR_COMMAND = 0x1d50, | ||
128 | |||
129 | PCI_IRQ_CAUSE_OFS = 0x1d58, | ||
130 | PCI_IRQ_MASK_OFS = 0x1d5c, | ||
131 | PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ | ||
132 | |||
133 | HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, | ||
134 | HC_MAIN_IRQ_MASK_OFS = 0x1d64, | ||
135 | PORT0_ERR = (1 << 0), /* shift by port # */ | ||
136 | PORT0_DONE = (1 << 1), /* shift by port # */ | ||
137 | HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ | ||
138 | HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ | ||
139 | PCI_ERR = (1 << 18), | ||
140 | TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ | ||
141 | TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ | ||
142 | PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ | ||
143 | GPIO_INT = (1 << 22), | ||
144 | SELF_INT = (1 << 23), | ||
145 | TWSI_INT = (1 << 24), | ||
146 | HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ | ||
147 | HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | | ||
148 | PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | | ||
149 | HC_MAIN_RSVD), | ||
150 | |||
151 | /* SATAHC registers */ | ||
152 | HC_CFG_OFS = 0, | ||
153 | |||
154 | HC_IRQ_CAUSE_OFS = 0x14, | ||
155 | CRPB_DMA_DONE = (1 << 0), /* shift by port # */ | ||
156 | HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */ | ||
157 | DEV_IRQ = (1 << 8), /* shift by port # */ | ||
158 | |||
159 | /* Shadow block registers */ | ||
160 | SHD_BLK_OFS = 0x100, | ||
161 | SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ | ||
162 | |||
163 | /* SATA registers */ | ||
164 | SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ | ||
165 | SATA_ACTIVE_OFS = 0x350, | ||
166 | PHY_MODE3 = 0x310, | ||
167 | PHY_MODE4 = 0x314, | ||
168 | PHY_MODE2 = 0x330, | ||
169 | MV5_PHY_MODE = 0x74, | ||
170 | MV5_LT_MODE = 0x30, | ||
171 | MV5_PHY_CTL = 0x0C, | ||
172 | SATA_INTERFACE_CTL = 0x050, | ||
173 | |||
174 | MV_M2_PREAMP_MASK = 0x7e0, | ||
175 | |||
176 | /* Port registers */ | ||
177 | EDMA_CFG_OFS = 0, | ||
178 | EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */ | ||
179 | EDMA_CFG_NCQ = (1 << 5), | ||
180 | EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ | ||
181 | EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ | ||
182 | EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ | ||
183 | |||
184 | EDMA_ERR_IRQ_CAUSE_OFS = 0x8, | ||
185 | EDMA_ERR_IRQ_MASK_OFS = 0xc, | ||
186 | EDMA_ERR_D_PAR = (1 << 0), | ||
187 | EDMA_ERR_PRD_PAR = (1 << 1), | ||
188 | EDMA_ERR_DEV = (1 << 2), | ||
189 | EDMA_ERR_DEV_DCON = (1 << 3), | ||
190 | EDMA_ERR_DEV_CON = (1 << 4), | ||
191 | EDMA_ERR_SERR = (1 << 5), | ||
192 | EDMA_ERR_SELF_DIS = (1 << 7), | ||
193 | EDMA_ERR_BIST_ASYNC = (1 << 8), | ||
194 | EDMA_ERR_CRBQ_PAR = (1 << 9), | ||
195 | EDMA_ERR_CRPB_PAR = (1 << 10), | ||
196 | EDMA_ERR_INTRL_PAR = (1 << 11), | ||
197 | EDMA_ERR_IORDY = (1 << 12), | ||
198 | EDMA_ERR_LNK_CTRL_RX = (0xf << 13), | ||
199 | EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), | ||
200 | EDMA_ERR_LNK_DATA_RX = (0xf << 17), | ||
201 | EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), | ||
202 | EDMA_ERR_LNK_DATA_TX = (0x1f << 26), | ||
203 | EDMA_ERR_TRANS_PROTO = (1 << 31), | ||
204 | EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | | ||
205 | EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR | | ||
206 | EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR | | ||
207 | EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 | | ||
208 | EDMA_ERR_LNK_DATA_RX | | ||
209 | EDMA_ERR_LNK_DATA_TX | | ||
210 | EDMA_ERR_TRANS_PROTO), | ||
211 | |||
212 | EDMA_REQ_Q_BASE_HI_OFS = 0x10, | ||
213 | EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ | ||
214 | |||
215 | EDMA_REQ_Q_OUT_PTR_OFS = 0x18, | ||
216 | EDMA_REQ_Q_PTR_SHIFT = 5, | ||
217 | |||
218 | EDMA_RSP_Q_BASE_HI_OFS = 0x1c, | ||
219 | EDMA_RSP_Q_IN_PTR_OFS = 0x20, | ||
220 | EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ | ||
221 | EDMA_RSP_Q_PTR_SHIFT = 3, | ||
222 | |||
223 | EDMA_CMD_OFS = 0x28, | ||
224 | EDMA_EN = (1 << 0), | ||
225 | EDMA_DS = (1 << 1), | ||
226 | ATA_RST = (1 << 2), | ||
227 | |||
228 | EDMA_IORDY_TMOUT = 0x34, | ||
229 | EDMA_ARB_CFG = 0x38, | ||
230 | |||
231 | /* Host private flags (hp_flags) */ | ||
232 | MV_HP_FLAG_MSI = (1 << 0), | ||
233 | MV_HP_ERRATA_50XXB0 = (1 << 1), | ||
234 | MV_HP_ERRATA_50XXB2 = (1 << 2), | ||
235 | MV_HP_ERRATA_60X1B2 = (1 << 3), | ||
236 | MV_HP_ERRATA_60X1C0 = (1 << 4), | ||
237 | MV_HP_ERRATA_XX42A0 = (1 << 5), | ||
238 | MV_HP_50XX = (1 << 6), | ||
239 | MV_HP_GEN_IIE = (1 << 7), | ||
240 | |||
241 | /* Port private flags (pp_flags) */ | ||
242 | MV_PP_FLAG_EDMA_EN = (1 << 0), | ||
243 | MV_PP_FLAG_EDMA_DS_ACT = (1 << 1), | ||
244 | }; | ||
245 | |||
246 | #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX) | ||
247 | #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0) | ||
248 | #define IS_GEN_I(hpriv) IS_50XX(hpriv) | ||
249 | #define IS_GEN_II(hpriv) IS_60XX(hpriv) | ||
250 | #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) | ||
251 | |||
252 | enum { | ||
253 | /* Our DMA boundary is determined by an ePRD being unable to handle | ||
254 | * anything larger than 64KB | ||
255 | */ | ||
256 | MV_DMA_BOUNDARY = 0xffffU, | ||
257 | |||
258 | EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, | ||
259 | |||
260 | EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, | ||
261 | }; | ||
262 | |||
263 | enum chip_type { | ||
264 | chip_504x, | ||
265 | chip_508x, | ||
266 | chip_5080, | ||
267 | chip_604x, | ||
268 | chip_608x, | ||
269 | chip_6042, | ||
270 | chip_7042, | ||
271 | }; | ||
272 | |||
273 | /* Command ReQuest Block: 32B */ | ||
274 | struct mv_crqb { | ||
275 | __le32 sg_addr; | ||
276 | __le32 sg_addr_hi; | ||
277 | __le16 ctrl_flags; | ||
278 | __le16 ata_cmd[11]; | ||
279 | }; | ||
280 | |||
281 | struct mv_crqb_iie { | ||
282 | __le32 addr; | ||
283 | __le32 addr_hi; | ||
284 | __le32 flags; | ||
285 | __le32 len; | ||
286 | __le32 ata_cmd[4]; | ||
287 | }; | ||
288 | |||
289 | /* Command ResPonse Block: 8B */ | ||
290 | struct mv_crpb { | ||
291 | __le16 id; | ||
292 | __le16 flags; | ||
293 | __le32 tmstmp; | ||
294 | }; | ||
295 | |||
296 | /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ | ||
297 | struct mv_sg { | ||
298 | __le32 addr; | ||
299 | __le32 flags_size; | ||
300 | __le32 addr_hi; | ||
301 | __le32 reserved; | ||
302 | }; | ||
303 | |||
304 | struct mv_port_priv { | ||
305 | struct mv_crqb *crqb; | ||
306 | dma_addr_t crqb_dma; | ||
307 | struct mv_crpb *crpb; | ||
308 | dma_addr_t crpb_dma; | ||
309 | struct mv_sg *sg_tbl; | ||
310 | dma_addr_t sg_tbl_dma; | ||
311 | u32 pp_flags; | ||
312 | }; | ||
313 | |||
314 | struct mv_port_signal { | ||
315 | u32 amps; | ||
316 | u32 pre; | ||
317 | }; | ||
318 | |||
319 | struct mv_host_priv; | ||
320 | struct mv_hw_ops { | ||
321 | void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
322 | unsigned int port); | ||
323 | void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); | ||
324 | void (*read_preamp)(struct mv_host_priv *hpriv, int idx, | ||
325 | void __iomem *mmio); | ||
326 | int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
327 | unsigned int n_hc); | ||
328 | void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); | ||
329 | void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio); | ||
330 | }; | ||
331 | |||
332 | struct mv_host_priv { | ||
333 | u32 hp_flags; | ||
334 | struct mv_port_signal signal[8]; | ||
335 | const struct mv_hw_ops *ops; | ||
336 | }; | ||
337 | |||
338 | static void mv_irq_clear(struct ata_port *ap); | ||
339 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in); | ||
340 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); | ||
341 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in); | ||
342 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); | ||
343 | static void mv_phy_reset(struct ata_port *ap); | ||
344 | static void __mv_phy_reset(struct ata_port *ap, int can_sleep); | ||
345 | static void mv_host_stop(struct ata_host_set *host_set); | ||
346 | static int mv_port_start(struct ata_port *ap); | ||
347 | static void mv_port_stop(struct ata_port *ap); | ||
348 | static void mv_qc_prep(struct ata_queued_cmd *qc); | ||
349 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc); | ||
350 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); | ||
351 | static irqreturn_t mv_interrupt(int irq, void *dev_instance, | ||
352 | struct pt_regs *regs); | ||
353 | static void mv_eng_timeout(struct ata_port *ap); | ||
354 | static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); | ||
355 | |||
356 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
357 | unsigned int port); | ||
358 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); | ||
359 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, | ||
360 | void __iomem *mmio); | ||
361 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
362 | unsigned int n_hc); | ||
363 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); | ||
364 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio); | ||
365 | |||
366 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
367 | unsigned int port); | ||
368 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); | ||
369 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, | ||
370 | void __iomem *mmio); | ||
371 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
372 | unsigned int n_hc); | ||
373 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); | ||
374 | static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio); | ||
375 | static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
376 | unsigned int port_no); | ||
377 | static void mv_stop_and_reset(struct ata_port *ap); | ||
378 | |||
379 | static struct scsi_host_template mv_sht = { | ||
380 | .module = THIS_MODULE, | ||
381 | .name = DRV_NAME, | ||
382 | .ioctl = ata_scsi_ioctl, | ||
383 | .queuecommand = ata_scsi_queuecmd, | ||
384 | .can_queue = MV_USE_Q_DEPTH, | ||
385 | .this_id = ATA_SHT_THIS_ID, | ||
386 | .sg_tablesize = MV_MAX_SG_CT / 2, | ||
387 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | ||
388 | .emulated = ATA_SHT_EMULATED, | ||
389 | .use_clustering = ATA_SHT_USE_CLUSTERING, | ||
390 | .proc_name = DRV_NAME, | ||
391 | .dma_boundary = MV_DMA_BOUNDARY, | ||
392 | .slave_configure = ata_scsi_slave_config, | ||
393 | .slave_destroy = ata_scsi_slave_destroy, | ||
394 | .bios_param = ata_std_bios_param, | ||
395 | }; | ||
396 | |||
397 | static const struct ata_port_operations mv5_ops = { | ||
398 | .port_disable = ata_port_disable, | ||
399 | |||
400 | .tf_load = ata_tf_load, | ||
401 | .tf_read = ata_tf_read, | ||
402 | .check_status = ata_check_status, | ||
403 | .exec_command = ata_exec_command, | ||
404 | .dev_select = ata_std_dev_select, | ||
405 | |||
406 | .phy_reset = mv_phy_reset, | ||
407 | |||
408 | .qc_prep = mv_qc_prep, | ||
409 | .qc_issue = mv_qc_issue, | ||
410 | .data_xfer = ata_mmio_data_xfer, | ||
411 | |||
412 | .eng_timeout = mv_eng_timeout, | ||
413 | |||
414 | .irq_handler = mv_interrupt, | ||
415 | .irq_clear = mv_irq_clear, | ||
416 | |||
417 | .scr_read = mv5_scr_read, | ||
418 | .scr_write = mv5_scr_write, | ||
419 | |||
420 | .port_start = mv_port_start, | ||
421 | .port_stop = mv_port_stop, | ||
422 | .host_stop = mv_host_stop, | ||
423 | }; | ||
424 | |||
425 | static const struct ata_port_operations mv6_ops = { | ||
426 | .port_disable = ata_port_disable, | ||
427 | |||
428 | .tf_load = ata_tf_load, | ||
429 | .tf_read = ata_tf_read, | ||
430 | .check_status = ata_check_status, | ||
431 | .exec_command = ata_exec_command, | ||
432 | .dev_select = ata_std_dev_select, | ||
433 | |||
434 | .phy_reset = mv_phy_reset, | ||
435 | |||
436 | .qc_prep = mv_qc_prep, | ||
437 | .qc_issue = mv_qc_issue, | ||
438 | .data_xfer = ata_mmio_data_xfer, | ||
439 | |||
440 | .eng_timeout = mv_eng_timeout, | ||
441 | |||
442 | .irq_handler = mv_interrupt, | ||
443 | .irq_clear = mv_irq_clear, | ||
444 | |||
445 | .scr_read = mv_scr_read, | ||
446 | .scr_write = mv_scr_write, | ||
447 | |||
448 | .port_start = mv_port_start, | ||
449 | .port_stop = mv_port_stop, | ||
450 | .host_stop = mv_host_stop, | ||
451 | }; | ||
452 | |||
453 | static const struct ata_port_operations mv_iie_ops = { | ||
454 | .port_disable = ata_port_disable, | ||
455 | |||
456 | .tf_load = ata_tf_load, | ||
457 | .tf_read = ata_tf_read, | ||
458 | .check_status = ata_check_status, | ||
459 | .exec_command = ata_exec_command, | ||
460 | .dev_select = ata_std_dev_select, | ||
461 | |||
462 | .phy_reset = mv_phy_reset, | ||
463 | |||
464 | .qc_prep = mv_qc_prep_iie, | ||
465 | .qc_issue = mv_qc_issue, | ||
466 | |||
467 | .eng_timeout = mv_eng_timeout, | ||
468 | |||
469 | .irq_handler = mv_interrupt, | ||
470 | .irq_clear = mv_irq_clear, | ||
471 | |||
472 | .scr_read = mv_scr_read, | ||
473 | .scr_write = mv_scr_write, | ||
474 | |||
475 | .port_start = mv_port_start, | ||
476 | .port_stop = mv_port_stop, | ||
477 | .host_stop = mv_host_stop, | ||
478 | }; | ||
479 | |||
480 | static const struct ata_port_info mv_port_info[] = { | ||
481 | { /* chip_504x */ | ||
482 | .sht = &mv_sht, | ||
483 | .host_flags = MV_COMMON_FLAGS, | ||
484 | .pio_mask = 0x1f, /* pio0-4 */ | ||
485 | .udma_mask = 0x7f, /* udma0-6 */ | ||
486 | .port_ops = &mv5_ops, | ||
487 | }, | ||
488 | { /* chip_508x */ | ||
489 | .sht = &mv_sht, | ||
490 | .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), | ||
491 | .pio_mask = 0x1f, /* pio0-4 */ | ||
492 | .udma_mask = 0x7f, /* udma0-6 */ | ||
493 | .port_ops = &mv5_ops, | ||
494 | }, | ||
495 | { /* chip_5080 */ | ||
496 | .sht = &mv_sht, | ||
497 | .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), | ||
498 | .pio_mask = 0x1f, /* pio0-4 */ | ||
499 | .udma_mask = 0x7f, /* udma0-6 */ | ||
500 | .port_ops = &mv5_ops, | ||
501 | }, | ||
502 | { /* chip_604x */ | ||
503 | .sht = &mv_sht, | ||
504 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), | ||
505 | .pio_mask = 0x1f, /* pio0-4 */ | ||
506 | .udma_mask = 0x7f, /* udma0-6 */ | ||
507 | .port_ops = &mv6_ops, | ||
508 | }, | ||
509 | { /* chip_608x */ | ||
510 | .sht = &mv_sht, | ||
511 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS | | ||
512 | MV_FLAG_DUAL_HC), | ||
513 | .pio_mask = 0x1f, /* pio0-4 */ | ||
514 | .udma_mask = 0x7f, /* udma0-6 */ | ||
515 | .port_ops = &mv6_ops, | ||
516 | }, | ||
517 | { /* chip_6042 */ | ||
518 | .sht = &mv_sht, | ||
519 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), | ||
520 | .pio_mask = 0x1f, /* pio0-4 */ | ||
521 | .udma_mask = 0x7f, /* udma0-6 */ | ||
522 | .port_ops = &mv_iie_ops, | ||
523 | }, | ||
524 | { /* chip_7042 */ | ||
525 | .sht = &mv_sht, | ||
526 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS | | ||
527 | MV_FLAG_DUAL_HC), | ||
528 | .pio_mask = 0x1f, /* pio0-4 */ | ||
529 | .udma_mask = 0x7f, /* udma0-6 */ | ||
530 | .port_ops = &mv_iie_ops, | ||
531 | }, | ||
532 | }; | ||
533 | |||
534 | static const struct pci_device_id mv_pci_tbl[] = { | ||
535 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x}, | ||
536 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x}, | ||
537 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080}, | ||
538 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x}, | ||
539 | |||
540 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x}, | ||
541 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x}, | ||
542 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6042), 0, 0, chip_6042}, | ||
543 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x}, | ||
544 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x}, | ||
545 | |||
546 | {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x}, | ||
547 | {} /* terminate list */ | ||
548 | }; | ||
549 | |||
550 | static struct pci_driver mv_pci_driver = { | ||
551 | .name = DRV_NAME, | ||
552 | .id_table = mv_pci_tbl, | ||
553 | .probe = mv_init_one, | ||
554 | .remove = ata_pci_remove_one, | ||
555 | }; | ||
556 | |||
557 | static const struct mv_hw_ops mv5xxx_ops = { | ||
558 | .phy_errata = mv5_phy_errata, | ||
559 | .enable_leds = mv5_enable_leds, | ||
560 | .read_preamp = mv5_read_preamp, | ||
561 | .reset_hc = mv5_reset_hc, | ||
562 | .reset_flash = mv5_reset_flash, | ||
563 | .reset_bus = mv5_reset_bus, | ||
564 | }; | ||
565 | |||
566 | static const struct mv_hw_ops mv6xxx_ops = { | ||
567 | .phy_errata = mv6_phy_errata, | ||
568 | .enable_leds = mv6_enable_leds, | ||
569 | .read_preamp = mv6_read_preamp, | ||
570 | .reset_hc = mv6_reset_hc, | ||
571 | .reset_flash = mv6_reset_flash, | ||
572 | .reset_bus = mv_reset_pci_bus, | ||
573 | }; | ||
574 | |||
575 | /* | ||
576 | * module options | ||
577 | */ | ||
578 | static int msi; /* Use PCI msi; either zero (off, default) or non-zero */ | ||
579 | |||
580 | |||
581 | /* | ||
582 | * Functions | ||
583 | */ | ||
584 | |||
585 | static inline void writelfl(unsigned long data, void __iomem *addr) | ||
586 | { | ||
587 | writel(data, addr); | ||
588 | (void) readl(addr); /* flush to avoid PCI posted write */ | ||
589 | } | ||
590 | |||
591 | static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) | ||
592 | { | ||
593 | return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); | ||
594 | } | ||
595 | |||
596 | static inline unsigned int mv_hc_from_port(unsigned int port) | ||
597 | { | ||
598 | return port >> MV_PORT_HC_SHIFT; | ||
599 | } | ||
600 | |||
601 | static inline unsigned int mv_hardport_from_port(unsigned int port) | ||
602 | { | ||
603 | return port & MV_PORT_MASK; | ||
604 | } | ||
605 | |||
606 | static inline void __iomem *mv_hc_base_from_port(void __iomem *base, | ||
607 | unsigned int port) | ||
608 | { | ||
609 | return mv_hc_base(base, mv_hc_from_port(port)); | ||
610 | } | ||
611 | |||
612 | static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) | ||
613 | { | ||
614 | return mv_hc_base_from_port(base, port) + | ||
615 | MV_SATAHC_ARBTR_REG_SZ + | ||
616 | (mv_hardport_from_port(port) * MV_PORT_REG_SZ); | ||
617 | } | ||
618 | |||
619 | static inline void __iomem *mv_ap_base(struct ata_port *ap) | ||
620 | { | ||
621 | return mv_port_base(ap->host_set->mmio_base, ap->port_no); | ||
622 | } | ||
623 | |||
624 | static inline int mv_get_hc_count(unsigned long host_flags) | ||
625 | { | ||
626 | return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1); | ||
627 | } | ||
628 | |||
629 | static void mv_irq_clear(struct ata_port *ap) | ||
630 | { | ||
631 | } | ||
632 | |||
633 | /** | ||
634 | * mv_start_dma - Enable eDMA engine | ||
635 | * @base: port base address | ||
636 | * @pp: port private data | ||
637 | * | ||
638 | * Verify the local cache of the eDMA state is accurate with a | ||
639 | * WARN_ON. | ||
640 | * | ||
641 | * LOCKING: | ||
642 | * Inherited from caller. | ||
643 | */ | ||
644 | static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp) | ||
645 | { | ||
646 | if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) { | ||
647 | writelfl(EDMA_EN, base + EDMA_CMD_OFS); | ||
648 | pp->pp_flags |= MV_PP_FLAG_EDMA_EN; | ||
649 | } | ||
650 | WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS))); | ||
651 | } | ||
652 | |||
653 | /** | ||
654 | * mv_stop_dma - Disable eDMA engine | ||
655 | * @ap: ATA channel to manipulate | ||
656 | * | ||
657 | * Verify the local cache of the eDMA state is accurate with a | ||
658 | * WARN_ON. | ||
659 | * | ||
660 | * LOCKING: | ||
661 | * Inherited from caller. | ||
662 | */ | ||
663 | static void mv_stop_dma(struct ata_port *ap) | ||
664 | { | ||
665 | void __iomem *port_mmio = mv_ap_base(ap); | ||
666 | struct mv_port_priv *pp = ap->private_data; | ||
667 | u32 reg; | ||
668 | int i; | ||
669 | |||
670 | if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) { | ||
671 | /* Disable EDMA if active. The disable bit auto clears. | ||
672 | */ | ||
673 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); | ||
674 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | ||
675 | } else { | ||
676 | WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)); | ||
677 | } | ||
678 | |||
679 | /* now properly wait for the eDMA to stop */ | ||
680 | for (i = 1000; i > 0; i--) { | ||
681 | reg = readl(port_mmio + EDMA_CMD_OFS); | ||
682 | if (!(EDMA_EN & reg)) { | ||
683 | break; | ||
684 | } | ||
685 | udelay(100); | ||
686 | } | ||
687 | |||
688 | if (EDMA_EN & reg) { | ||
689 | ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); | ||
690 | /* FIXME: Consider doing a reset here to recover */ | ||
691 | } | ||
692 | } | ||
693 | |||
694 | #ifdef ATA_DEBUG | ||
695 | static void mv_dump_mem(void __iomem *start, unsigned bytes) | ||
696 | { | ||
697 | int b, w; | ||
698 | for (b = 0; b < bytes; ) { | ||
699 | DPRINTK("%p: ", start + b); | ||
700 | for (w = 0; b < bytes && w < 4; w++) { | ||
701 | printk("%08x ",readl(start + b)); | ||
702 | b += sizeof(u32); | ||
703 | } | ||
704 | printk("\n"); | ||
705 | } | ||
706 | } | ||
707 | #endif | ||
708 | |||
709 | static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) | ||
710 | { | ||
711 | #ifdef ATA_DEBUG | ||
712 | int b, w; | ||
713 | u32 dw; | ||
714 | for (b = 0; b < bytes; ) { | ||
715 | DPRINTK("%02x: ", b); | ||
716 | for (w = 0; b < bytes && w < 4; w++) { | ||
717 | (void) pci_read_config_dword(pdev,b,&dw); | ||
718 | printk("%08x ",dw); | ||
719 | b += sizeof(u32); | ||
720 | } | ||
721 | printk("\n"); | ||
722 | } | ||
723 | #endif | ||
724 | } | ||
725 | static void mv_dump_all_regs(void __iomem *mmio_base, int port, | ||
726 | struct pci_dev *pdev) | ||
727 | { | ||
728 | #ifdef ATA_DEBUG | ||
729 | void __iomem *hc_base = mv_hc_base(mmio_base, | ||
730 | port >> MV_PORT_HC_SHIFT); | ||
731 | void __iomem *port_base; | ||
732 | int start_port, num_ports, p, start_hc, num_hcs, hc; | ||
733 | |||
734 | if (0 > port) { | ||
735 | start_hc = start_port = 0; | ||
736 | num_ports = 8; /* shld be benign for 4 port devs */ | ||
737 | num_hcs = 2; | ||
738 | } else { | ||
739 | start_hc = port >> MV_PORT_HC_SHIFT; | ||
740 | start_port = port; | ||
741 | num_ports = num_hcs = 1; | ||
742 | } | ||
743 | DPRINTK("All registers for port(s) %u-%u:\n", start_port, | ||
744 | num_ports > 1 ? num_ports - 1 : start_port); | ||
745 | |||
746 | if (NULL != pdev) { | ||
747 | DPRINTK("PCI config space regs:\n"); | ||
748 | mv_dump_pci_cfg(pdev, 0x68); | ||
749 | } | ||
750 | DPRINTK("PCI regs:\n"); | ||
751 | mv_dump_mem(mmio_base+0xc00, 0x3c); | ||
752 | mv_dump_mem(mmio_base+0xd00, 0x34); | ||
753 | mv_dump_mem(mmio_base+0xf00, 0x4); | ||
754 | mv_dump_mem(mmio_base+0x1d00, 0x6c); | ||
755 | for (hc = start_hc; hc < start_hc + num_hcs; hc++) { | ||
756 | hc_base = mv_hc_base(mmio_base, hc); | ||
757 | DPRINTK("HC regs (HC %i):\n", hc); | ||
758 | mv_dump_mem(hc_base, 0x1c); | ||
759 | } | ||
760 | for (p = start_port; p < start_port + num_ports; p++) { | ||
761 | port_base = mv_port_base(mmio_base, p); | ||
762 | DPRINTK("EDMA regs (port %i):\n",p); | ||
763 | mv_dump_mem(port_base, 0x54); | ||
764 | DPRINTK("SATA regs (port %i):\n",p); | ||
765 | mv_dump_mem(port_base+0x300, 0x60); | ||
766 | } | ||
767 | #endif | ||
768 | } | ||
769 | |||
770 | static unsigned int mv_scr_offset(unsigned int sc_reg_in) | ||
771 | { | ||
772 | unsigned int ofs; | ||
773 | |||
774 | switch (sc_reg_in) { | ||
775 | case SCR_STATUS: | ||
776 | case SCR_CONTROL: | ||
777 | case SCR_ERROR: | ||
778 | ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); | ||
779 | break; | ||
780 | case SCR_ACTIVE: | ||
781 | ofs = SATA_ACTIVE_OFS; /* active is not with the others */ | ||
782 | break; | ||
783 | default: | ||
784 | ofs = 0xffffffffU; | ||
785 | break; | ||
786 | } | ||
787 | return ofs; | ||
788 | } | ||
789 | |||
790 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in) | ||
791 | { | ||
792 | unsigned int ofs = mv_scr_offset(sc_reg_in); | ||
793 | |||
794 | if (0xffffffffU != ofs) { | ||
795 | return readl(mv_ap_base(ap) + ofs); | ||
796 | } else { | ||
797 | return (u32) ofs; | ||
798 | } | ||
799 | } | ||
800 | |||
801 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) | ||
802 | { | ||
803 | unsigned int ofs = mv_scr_offset(sc_reg_in); | ||
804 | |||
805 | if (0xffffffffU != ofs) { | ||
806 | writelfl(val, mv_ap_base(ap) + ofs); | ||
807 | } | ||
808 | } | ||
809 | |||
810 | /** | ||
811 | * mv_host_stop - Host specific cleanup/stop routine. | ||
812 | * @host_set: host data structure | ||
813 | * | ||
814 | * Disable ints, cleanup host memory, call general purpose | ||
815 | * host_stop. | ||
816 | * | ||
817 | * LOCKING: | ||
818 | * Inherited from caller. | ||
819 | */ | ||
820 | static void mv_host_stop(struct ata_host_set *host_set) | ||
821 | { | ||
822 | struct mv_host_priv *hpriv = host_set->private_data; | ||
823 | struct pci_dev *pdev = to_pci_dev(host_set->dev); | ||
824 | |||
825 | if (hpriv->hp_flags & MV_HP_FLAG_MSI) { | ||
826 | pci_disable_msi(pdev); | ||
827 | } else { | ||
828 | pci_intx(pdev, 0); | ||
829 | } | ||
830 | kfree(hpriv); | ||
831 | ata_host_stop(host_set); | ||
832 | } | ||
833 | |||
834 | static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev) | ||
835 | { | ||
836 | dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma); | ||
837 | } | ||
838 | |||
839 | static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio) | ||
840 | { | ||
841 | u32 cfg = readl(port_mmio + EDMA_CFG_OFS); | ||
842 | |||
843 | /* set up non-NCQ EDMA configuration */ | ||
844 | cfg &= ~0x1f; /* clear queue depth */ | ||
845 | cfg &= ~EDMA_CFG_NCQ; /* clear NCQ mode */ | ||
846 | cfg &= ~(1 << 9); /* disable equeue */ | ||
847 | |||
848 | if (IS_GEN_I(hpriv)) | ||
849 | cfg |= (1 << 8); /* enab config burst size mask */ | ||
850 | |||
851 | else if (IS_GEN_II(hpriv)) | ||
852 | cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; | ||
853 | |||
854 | else if (IS_GEN_IIE(hpriv)) { | ||
855 | cfg |= (1 << 23); /* dis RX PM port mask */ | ||
856 | cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */ | ||
857 | cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */ | ||
858 | cfg |= (1 << 18); /* enab early completion */ | ||
859 | cfg |= (1 << 17); /* enab host q cache */ | ||
860 | cfg |= (1 << 22); /* enab cutthrough */ | ||
861 | } | ||
862 | |||
863 | writelfl(cfg, port_mmio + EDMA_CFG_OFS); | ||
864 | } | ||
865 | |||
866 | /** | ||
867 | * mv_port_start - Port specific init/start routine. | ||
868 | * @ap: ATA channel to manipulate | ||
869 | * | ||
870 | * Allocate and point to DMA memory, init port private memory, | ||
871 | * zero indices. | ||
872 | * | ||
873 | * LOCKING: | ||
874 | * Inherited from caller. | ||
875 | */ | ||
876 | static int mv_port_start(struct ata_port *ap) | ||
877 | { | ||
878 | struct device *dev = ap->host_set->dev; | ||
879 | struct mv_host_priv *hpriv = ap->host_set->private_data; | ||
880 | struct mv_port_priv *pp; | ||
881 | void __iomem *port_mmio = mv_ap_base(ap); | ||
882 | void *mem; | ||
883 | dma_addr_t mem_dma; | ||
884 | int rc = -ENOMEM; | ||
885 | |||
886 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); | ||
887 | if (!pp) | ||
888 | goto err_out; | ||
889 | memset(pp, 0, sizeof(*pp)); | ||
890 | |||
891 | mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma, | ||
892 | GFP_KERNEL); | ||
893 | if (!mem) | ||
894 | goto err_out_pp; | ||
895 | memset(mem, 0, MV_PORT_PRIV_DMA_SZ); | ||
896 | |||
897 | rc = ata_pad_alloc(ap, dev); | ||
898 | if (rc) | ||
899 | goto err_out_priv; | ||
900 | |||
901 | /* First item in chunk of DMA memory: | ||
902 | * 32-slot command request table (CRQB), 32 bytes each in size | ||
903 | */ | ||
904 | pp->crqb = mem; | ||
905 | pp->crqb_dma = mem_dma; | ||
906 | mem += MV_CRQB_Q_SZ; | ||
907 | mem_dma += MV_CRQB_Q_SZ; | ||
908 | |||
909 | /* Second item: | ||
910 | * 32-slot command response table (CRPB), 8 bytes each in size | ||
911 | */ | ||
912 | pp->crpb = mem; | ||
913 | pp->crpb_dma = mem_dma; | ||
914 | mem += MV_CRPB_Q_SZ; | ||
915 | mem_dma += MV_CRPB_Q_SZ; | ||
916 | |||
917 | /* Third item: | ||
918 | * Table of scatter-gather descriptors (ePRD), 16 bytes each | ||
919 | */ | ||
920 | pp->sg_tbl = mem; | ||
921 | pp->sg_tbl_dma = mem_dma; | ||
922 | |||
923 | mv_edma_cfg(hpriv, port_mmio); | ||
924 | |||
925 | writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); | ||
926 | writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK, | ||
927 | port_mmio + EDMA_REQ_Q_IN_PTR_OFS); | ||
928 | |||
929 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) | ||
930 | writelfl(pp->crqb_dma & 0xffffffff, | ||
931 | port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); | ||
932 | else | ||
933 | writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); | ||
934 | |||
935 | writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); | ||
936 | |||
937 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) | ||
938 | writelfl(pp->crpb_dma & 0xffffffff, | ||
939 | port_mmio + EDMA_RSP_Q_IN_PTR_OFS); | ||
940 | else | ||
941 | writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); | ||
942 | |||
943 | writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK, | ||
944 | port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); | ||
945 | |||
946 | /* Don't turn on EDMA here...do it before DMA commands only. Else | ||
947 | * we'll be unable to send non-data, PIO, etc due to restricted access | ||
948 | * to shadow regs. | ||
949 | */ | ||
950 | ap->private_data = pp; | ||
951 | return 0; | ||
952 | |||
953 | err_out_priv: | ||
954 | mv_priv_free(pp, dev); | ||
955 | err_out_pp: | ||
956 | kfree(pp); | ||
957 | err_out: | ||
958 | return rc; | ||
959 | } | ||
960 | |||
961 | /** | ||
962 | * mv_port_stop - Port specific cleanup/stop routine. | ||
963 | * @ap: ATA channel to manipulate | ||
964 | * | ||
965 | * Stop DMA, cleanup port memory. | ||
966 | * | ||
967 | * LOCKING: | ||
968 | * This routine uses the host_set lock to protect the DMA stop. | ||
969 | */ | ||
970 | static void mv_port_stop(struct ata_port *ap) | ||
971 | { | ||
972 | struct device *dev = ap->host_set->dev; | ||
973 | struct mv_port_priv *pp = ap->private_data; | ||
974 | unsigned long flags; | ||
975 | |||
976 | spin_lock_irqsave(&ap->host_set->lock, flags); | ||
977 | mv_stop_dma(ap); | ||
978 | spin_unlock_irqrestore(&ap->host_set->lock, flags); | ||
979 | |||
980 | ap->private_data = NULL; | ||
981 | ata_pad_free(ap, dev); | ||
982 | mv_priv_free(pp, dev); | ||
983 | kfree(pp); | ||
984 | } | ||
985 | |||
986 | /** | ||
987 | * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries | ||
988 | * @qc: queued command whose SG list to source from | ||
989 | * | ||
990 | * Populate the SG list and mark the last entry. | ||
991 | * | ||
992 | * LOCKING: | ||
993 | * Inherited from caller. | ||
994 | */ | ||
995 | static void mv_fill_sg(struct ata_queued_cmd *qc) | ||
996 | { | ||
997 | struct mv_port_priv *pp = qc->ap->private_data; | ||
998 | unsigned int i = 0; | ||
999 | struct scatterlist *sg; | ||
1000 | |||
1001 | ata_for_each_sg(sg, qc) { | ||
1002 | dma_addr_t addr; | ||
1003 | u32 sg_len, len, offset; | ||
1004 | |||
1005 | addr = sg_dma_address(sg); | ||
1006 | sg_len = sg_dma_len(sg); | ||
1007 | |||
1008 | while (sg_len) { | ||
1009 | offset = addr & MV_DMA_BOUNDARY; | ||
1010 | len = sg_len; | ||
1011 | if ((offset + sg_len) > 0x10000) | ||
1012 | len = 0x10000 - offset; | ||
1013 | |||
1014 | pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff); | ||
1015 | pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16); | ||
1016 | pp->sg_tbl[i].flags_size = cpu_to_le32(len & 0xffff); | ||
1017 | |||
1018 | sg_len -= len; | ||
1019 | addr += len; | ||
1020 | |||
1021 | if (!sg_len && ata_sg_is_last(sg, qc)) | ||
1022 | pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); | ||
1023 | |||
1024 | i++; | ||
1025 | } | ||
1026 | } | ||
1027 | } | ||
1028 | |||
1029 | static inline unsigned mv_inc_q_index(unsigned index) | ||
1030 | { | ||
1031 | return (index + 1) & MV_MAX_Q_DEPTH_MASK; | ||
1032 | } | ||
1033 | |||
1034 | static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) | ||
1035 | { | ||
1036 | u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | | ||
1037 | (last ? CRQB_CMD_LAST : 0); | ||
1038 | *cmdw = cpu_to_le16(tmp); | ||
1039 | } | ||
1040 | |||
1041 | /** | ||
1042 | * mv_qc_prep - Host specific command preparation. | ||
1043 | * @qc: queued command to prepare | ||
1044 | * | ||
1045 | * This routine simply redirects to the general purpose routine | ||
1046 | * if command is not DMA. Else, it handles prep of the CRQB | ||
1047 | * (command request block), does some sanity checking, and calls | ||
1048 | * the SG load routine. | ||
1049 | * | ||
1050 | * LOCKING: | ||
1051 | * Inherited from caller. | ||
1052 | */ | ||
1053 | static void mv_qc_prep(struct ata_queued_cmd *qc) | ||
1054 | { | ||
1055 | struct ata_port *ap = qc->ap; | ||
1056 | struct mv_port_priv *pp = ap->private_data; | ||
1057 | __le16 *cw; | ||
1058 | struct ata_taskfile *tf; | ||
1059 | u16 flags = 0; | ||
1060 | unsigned in_index; | ||
1061 | |||
1062 | if (ATA_PROT_DMA != qc->tf.protocol) | ||
1063 | return; | ||
1064 | |||
1065 | /* Fill in command request block | ||
1066 | */ | ||
1067 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) | ||
1068 | flags |= CRQB_FLAG_READ; | ||
1069 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); | ||
1070 | flags |= qc->tag << CRQB_TAG_SHIFT; | ||
1071 | |||
1072 | /* get current queue index from hardware */ | ||
1073 | in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS) | ||
1074 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; | ||
1075 | |||
1076 | pp->crqb[in_index].sg_addr = | ||
1077 | cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); | ||
1078 | pp->crqb[in_index].sg_addr_hi = | ||
1079 | cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); | ||
1080 | pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); | ||
1081 | |||
1082 | cw = &pp->crqb[in_index].ata_cmd[0]; | ||
1083 | tf = &qc->tf; | ||
1084 | |||
1085 | /* Sadly, the CRQB cannot accomodate all registers--there are | ||
1086 | * only 11 bytes...so we must pick and choose required | ||
1087 | * registers based on the command. So, we drop feature and | ||
1088 | * hob_feature for [RW] DMA commands, but they are needed for | ||
1089 | * NCQ. NCQ will drop hob_nsect. | ||
1090 | */ | ||
1091 | switch (tf->command) { | ||
1092 | case ATA_CMD_READ: | ||
1093 | case ATA_CMD_READ_EXT: | ||
1094 | case ATA_CMD_WRITE: | ||
1095 | case ATA_CMD_WRITE_EXT: | ||
1096 | case ATA_CMD_WRITE_FUA_EXT: | ||
1097 | mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); | ||
1098 | break; | ||
1099 | #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */ | ||
1100 | case ATA_CMD_FPDMA_READ: | ||
1101 | case ATA_CMD_FPDMA_WRITE: | ||
1102 | mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); | ||
1103 | mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); | ||
1104 | break; | ||
1105 | #endif /* FIXME: remove this line when NCQ added */ | ||
1106 | default: | ||
1107 | /* The only other commands EDMA supports in non-queued and | ||
1108 | * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none | ||
1109 | * of which are defined/used by Linux. If we get here, this | ||
1110 | * driver needs work. | ||
1111 | * | ||
1112 | * FIXME: modify libata to give qc_prep a return value and | ||
1113 | * return error here. | ||
1114 | */ | ||
1115 | BUG_ON(tf->command); | ||
1116 | break; | ||
1117 | } | ||
1118 | mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); | ||
1119 | mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); | ||
1120 | mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); | ||
1121 | mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); | ||
1122 | mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); | ||
1123 | mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); | ||
1124 | mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); | ||
1125 | mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); | ||
1126 | mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ | ||
1127 | |||
1128 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | ||
1129 | return; | ||
1130 | mv_fill_sg(qc); | ||
1131 | } | ||
1132 | |||
1133 | /** | ||
1134 | * mv_qc_prep_iie - Host specific command preparation. | ||
1135 | * @qc: queued command to prepare | ||
1136 | * | ||
1137 | * This routine simply redirects to the general purpose routine | ||
1138 | * if command is not DMA. Else, it handles prep of the CRQB | ||
1139 | * (command request block), does some sanity checking, and calls | ||
1140 | * the SG load routine. | ||
1141 | * | ||
1142 | * LOCKING: | ||
1143 | * Inherited from caller. | ||
1144 | */ | ||
1145 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc) | ||
1146 | { | ||
1147 | struct ata_port *ap = qc->ap; | ||
1148 | struct mv_port_priv *pp = ap->private_data; | ||
1149 | struct mv_crqb_iie *crqb; | ||
1150 | struct ata_taskfile *tf; | ||
1151 | unsigned in_index; | ||
1152 | u32 flags = 0; | ||
1153 | |||
1154 | if (ATA_PROT_DMA != qc->tf.protocol) | ||
1155 | return; | ||
1156 | |||
1157 | /* Fill in Gen IIE command request block | ||
1158 | */ | ||
1159 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) | ||
1160 | flags |= CRQB_FLAG_READ; | ||
1161 | |||
1162 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); | ||
1163 | flags |= qc->tag << CRQB_TAG_SHIFT; | ||
1164 | |||
1165 | /* get current queue index from hardware */ | ||
1166 | in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS) | ||
1167 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; | ||
1168 | |||
1169 | crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; | ||
1170 | crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); | ||
1171 | crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); | ||
1172 | crqb->flags = cpu_to_le32(flags); | ||
1173 | |||
1174 | tf = &qc->tf; | ||
1175 | crqb->ata_cmd[0] = cpu_to_le32( | ||
1176 | (tf->command << 16) | | ||
1177 | (tf->feature << 24) | ||
1178 | ); | ||
1179 | crqb->ata_cmd[1] = cpu_to_le32( | ||
1180 | (tf->lbal << 0) | | ||
1181 | (tf->lbam << 8) | | ||
1182 | (tf->lbah << 16) | | ||
1183 | (tf->device << 24) | ||
1184 | ); | ||
1185 | crqb->ata_cmd[2] = cpu_to_le32( | ||
1186 | (tf->hob_lbal << 0) | | ||
1187 | (tf->hob_lbam << 8) | | ||
1188 | (tf->hob_lbah << 16) | | ||
1189 | (tf->hob_feature << 24) | ||
1190 | ); | ||
1191 | crqb->ata_cmd[3] = cpu_to_le32( | ||
1192 | (tf->nsect << 0) | | ||
1193 | (tf->hob_nsect << 8) | ||
1194 | ); | ||
1195 | |||
1196 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | ||
1197 | return; | ||
1198 | mv_fill_sg(qc); | ||
1199 | } | ||
1200 | |||
1201 | /** | ||
1202 | * mv_qc_issue - Initiate a command to the host | ||
1203 | * @qc: queued command to start | ||
1204 | * | ||
1205 | * This routine simply redirects to the general purpose routine | ||
1206 | * if command is not DMA. Else, it sanity checks our local | ||
1207 | * caches of the request producer/consumer indices then enables | ||
1208 | * DMA and bumps the request producer index. | ||
1209 | * | ||
1210 | * LOCKING: | ||
1211 | * Inherited from caller. | ||
1212 | */ | ||
1213 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) | ||
1214 | { | ||
1215 | void __iomem *port_mmio = mv_ap_base(qc->ap); | ||
1216 | struct mv_port_priv *pp = qc->ap->private_data; | ||
1217 | unsigned in_index; | ||
1218 | u32 in_ptr; | ||
1219 | |||
1220 | if (ATA_PROT_DMA != qc->tf.protocol) { | ||
1221 | /* We're about to send a non-EDMA capable command to the | ||
1222 | * port. Turn off EDMA so there won't be problems accessing | ||
1223 | * shadow block, etc registers. | ||
1224 | */ | ||
1225 | mv_stop_dma(qc->ap); | ||
1226 | return ata_qc_issue_prot(qc); | ||
1227 | } | ||
1228 | |||
1229 | in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS); | ||
1230 | in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; | ||
1231 | |||
1232 | /* until we do queuing, the queue should be empty at this point */ | ||
1233 | WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) | ||
1234 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK)); | ||
1235 | |||
1236 | in_index = mv_inc_q_index(in_index); /* now incr producer index */ | ||
1237 | |||
1238 | mv_start_dma(port_mmio, pp); | ||
1239 | |||
1240 | /* and write the request in pointer to kick the EDMA to life */ | ||
1241 | in_ptr &= EDMA_REQ_Q_BASE_LO_MASK; | ||
1242 | in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT; | ||
1243 | writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS); | ||
1244 | |||
1245 | return 0; | ||
1246 | } | ||
1247 | |||
1248 | /** | ||
1249 | * mv_get_crpb_status - get status from most recently completed cmd | ||
1250 | * @ap: ATA channel to manipulate | ||
1251 | * | ||
1252 | * This routine is for use when the port is in DMA mode, when it | ||
1253 | * will be using the CRPB (command response block) method of | ||
1254 | * returning command completion information. We check indices | ||
1255 | * are good, grab status, and bump the response consumer index to | ||
1256 | * prove that we're up to date. | ||
1257 | * | ||
1258 | * LOCKING: | ||
1259 | * Inherited from caller. | ||
1260 | */ | ||
1261 | static u8 mv_get_crpb_status(struct ata_port *ap) | ||
1262 | { | ||
1263 | void __iomem *port_mmio = mv_ap_base(ap); | ||
1264 | struct mv_port_priv *pp = ap->private_data; | ||
1265 | unsigned out_index; | ||
1266 | u32 out_ptr; | ||
1267 | u8 ata_status; | ||
1268 | |||
1269 | out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); | ||
1270 | out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; | ||
1271 | |||
1272 | ata_status = le16_to_cpu(pp->crpb[out_index].flags) | ||
1273 | >> CRPB_FLAG_STATUS_SHIFT; | ||
1274 | |||
1275 | /* increment our consumer index... */ | ||
1276 | out_index = mv_inc_q_index(out_index); | ||
1277 | |||
1278 | /* and, until we do NCQ, there should only be 1 CRPB waiting */ | ||
1279 | WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) | ||
1280 | >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK)); | ||
1281 | |||
1282 | /* write out our inc'd consumer index so EDMA knows we're caught up */ | ||
1283 | out_ptr &= EDMA_RSP_Q_BASE_LO_MASK; | ||
1284 | out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT; | ||
1285 | writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); | ||
1286 | |||
1287 | /* Return ATA status register for completed CRPB */ | ||
1288 | return ata_status; | ||
1289 | } | ||
1290 | |||
1291 | /** | ||
1292 | * mv_err_intr - Handle error interrupts on the port | ||
1293 | * @ap: ATA channel to manipulate | ||
1294 | * @reset_allowed: bool: 0 == don't trigger from reset here | ||
1295 | * | ||
1296 | * In most cases, just clear the interrupt and move on. However, | ||
1297 | * some cases require an eDMA reset, which is done right before | ||
1298 | * the COMRESET in mv_phy_reset(). The SERR case requires a | ||
1299 | * clear of pending errors in the SATA SERROR register. Finally, | ||
1300 | * if the port disabled DMA, update our cached copy to match. | ||
1301 | * | ||
1302 | * LOCKING: | ||
1303 | * Inherited from caller. | ||
1304 | */ | ||
1305 | static void mv_err_intr(struct ata_port *ap, int reset_allowed) | ||
1306 | { | ||
1307 | void __iomem *port_mmio = mv_ap_base(ap); | ||
1308 | u32 edma_err_cause, serr = 0; | ||
1309 | |||
1310 | edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | ||
1311 | |||
1312 | if (EDMA_ERR_SERR & edma_err_cause) { | ||
1313 | sata_scr_read(ap, SCR_ERROR, &serr); | ||
1314 | sata_scr_write_flush(ap, SCR_ERROR, serr); | ||
1315 | } | ||
1316 | if (EDMA_ERR_SELF_DIS & edma_err_cause) { | ||
1317 | struct mv_port_priv *pp = ap->private_data; | ||
1318 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | ||
1319 | } | ||
1320 | DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x " | ||
1321 | "SERR: 0x%08x\n", ap->id, edma_err_cause, serr); | ||
1322 | |||
1323 | /* Clear EDMA now that SERR cleanup done */ | ||
1324 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | ||
1325 | |||
1326 | /* check for fatal here and recover if needed */ | ||
1327 | if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause)) | ||
1328 | mv_stop_and_reset(ap); | ||
1329 | } | ||
1330 | |||
1331 | /** | ||
1332 | * mv_host_intr - Handle all interrupts on the given host controller | ||
1333 | * @host_set: host specific structure | ||
1334 | * @relevant: port error bits relevant to this host controller | ||
1335 | * @hc: which host controller we're to look at | ||
1336 | * | ||
1337 | * Read then write clear the HC interrupt status then walk each | ||
1338 | * port connected to the HC and see if it needs servicing. Port | ||
1339 | * success ints are reported in the HC interrupt status reg, the | ||
1340 | * port error ints are reported in the higher level main | ||
1341 | * interrupt status register and thus are passed in via the | ||
1342 | * 'relevant' argument. | ||
1343 | * | ||
1344 | * LOCKING: | ||
1345 | * Inherited from caller. | ||
1346 | */ | ||
1347 | static void mv_host_intr(struct ata_host_set *host_set, u32 relevant, | ||
1348 | unsigned int hc) | ||
1349 | { | ||
1350 | void __iomem *mmio = host_set->mmio_base; | ||
1351 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); | ||
1352 | struct ata_queued_cmd *qc; | ||
1353 | u32 hc_irq_cause; | ||
1354 | int shift, port, port0, hard_port, handled; | ||
1355 | unsigned int err_mask; | ||
1356 | |||
1357 | if (hc == 0) { | ||
1358 | port0 = 0; | ||
1359 | } else { | ||
1360 | port0 = MV_PORTS_PER_HC; | ||
1361 | } | ||
1362 | |||
1363 | /* we'll need the HC success int register in most cases */ | ||
1364 | hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); | ||
1365 | if (hc_irq_cause) { | ||
1366 | writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); | ||
1367 | } | ||
1368 | |||
1369 | VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n", | ||
1370 | hc,relevant,hc_irq_cause); | ||
1371 | |||
1372 | for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) { | ||
1373 | u8 ata_status = 0; | ||
1374 | struct ata_port *ap = host_set->ports[port]; | ||
1375 | struct mv_port_priv *pp = ap->private_data; | ||
1376 | |||
1377 | hard_port = mv_hardport_from_port(port); /* range 0..3 */ | ||
1378 | handled = 0; /* ensure ata_status is set if handled++ */ | ||
1379 | |||
1380 | /* Note that DEV_IRQ might happen spuriously during EDMA, | ||
1381 | * and should be ignored in such cases. | ||
1382 | * The cause of this is still under investigation. | ||
1383 | */ | ||
1384 | if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { | ||
1385 | /* EDMA: check for response queue interrupt */ | ||
1386 | if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) { | ||
1387 | ata_status = mv_get_crpb_status(ap); | ||
1388 | handled = 1; | ||
1389 | } | ||
1390 | } else { | ||
1391 | /* PIO: check for device (drive) interrupt */ | ||
1392 | if ((DEV_IRQ << hard_port) & hc_irq_cause) { | ||
1393 | ata_status = readb((void __iomem *) | ||
1394 | ap->ioaddr.status_addr); | ||
1395 | handled = 1; | ||
1396 | /* ignore spurious intr if drive still BUSY */ | ||
1397 | if (ata_status & ATA_BUSY) { | ||
1398 | ata_status = 0; | ||
1399 | handled = 0; | ||
1400 | } | ||
1401 | } | ||
1402 | } | ||
1403 | |||
1404 | if (ap && (ap->flags & ATA_FLAG_DISABLED)) | ||
1405 | continue; | ||
1406 | |||
1407 | err_mask = ac_err_mask(ata_status); | ||
1408 | |||
1409 | shift = port << 1; /* (port * 2) */ | ||
1410 | if (port >= MV_PORTS_PER_HC) { | ||
1411 | shift++; /* skip bit 8 in the HC Main IRQ reg */ | ||
1412 | } | ||
1413 | if ((PORT0_ERR << shift) & relevant) { | ||
1414 | mv_err_intr(ap, 1); | ||
1415 | err_mask |= AC_ERR_OTHER; | ||
1416 | handled = 1; | ||
1417 | } | ||
1418 | |||
1419 | if (handled) { | ||
1420 | qc = ata_qc_from_tag(ap, ap->active_tag); | ||
1421 | if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) { | ||
1422 | VPRINTK("port %u IRQ found for qc, " | ||
1423 | "ata_status 0x%x\n", port,ata_status); | ||
1424 | /* mark qc status appropriately */ | ||
1425 | if (!(qc->tf.flags & ATA_TFLAG_POLLING)) { | ||
1426 | qc->err_mask |= err_mask; | ||
1427 | ata_qc_complete(qc); | ||
1428 | } | ||
1429 | } | ||
1430 | } | ||
1431 | } | ||
1432 | VPRINTK("EXIT\n"); | ||
1433 | } | ||
1434 | |||
1435 | /** | ||
1436 | * mv_interrupt - | ||
1437 | * @irq: unused | ||
1438 | * @dev_instance: private data; in this case the host structure | ||
1439 | * @regs: unused | ||
1440 | * | ||
1441 | * Read the read only register to determine if any host | ||
1442 | * controllers have pending interrupts. If so, call lower level | ||
1443 | * routine to handle. Also check for PCI errors which are only | ||
1444 | * reported here. | ||
1445 | * | ||
1446 | * LOCKING: | ||
1447 | * This routine holds the host_set lock while processing pending | ||
1448 | * interrupts. | ||
1449 | */ | ||
1450 | static irqreturn_t mv_interrupt(int irq, void *dev_instance, | ||
1451 | struct pt_regs *regs) | ||
1452 | { | ||
1453 | struct ata_host_set *host_set = dev_instance; | ||
1454 | unsigned int hc, handled = 0, n_hcs; | ||
1455 | void __iomem *mmio = host_set->mmio_base; | ||
1456 | struct mv_host_priv *hpriv; | ||
1457 | u32 irq_stat; | ||
1458 | |||
1459 | irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS); | ||
1460 | |||
1461 | /* check the cases where we either have nothing pending or have read | ||
1462 | * a bogus register value which can indicate HW removal or PCI fault | ||
1463 | */ | ||
1464 | if (!irq_stat || (0xffffffffU == irq_stat)) { | ||
1465 | return IRQ_NONE; | ||
1466 | } | ||
1467 | |||
1468 | n_hcs = mv_get_hc_count(host_set->ports[0]->flags); | ||
1469 | spin_lock(&host_set->lock); | ||
1470 | |||
1471 | for (hc = 0; hc < n_hcs; hc++) { | ||
1472 | u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT)); | ||
1473 | if (relevant) { | ||
1474 | mv_host_intr(host_set, relevant, hc); | ||
1475 | handled++; | ||
1476 | } | ||
1477 | } | ||
1478 | |||
1479 | hpriv = host_set->private_data; | ||
1480 | if (IS_60XX(hpriv)) { | ||
1481 | /* deal with the interrupt coalescing bits */ | ||
1482 | if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) { | ||
1483 | writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO); | ||
1484 | writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI); | ||
1485 | writelfl(0, mmio + MV_IRQ_COAL_CAUSE); | ||
1486 | } | ||
1487 | } | ||
1488 | |||
1489 | if (PCI_ERR & irq_stat) { | ||
1490 | printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n", | ||
1491 | readl(mmio + PCI_IRQ_CAUSE_OFS)); | ||
1492 | |||
1493 | DPRINTK("All regs @ PCI error\n"); | ||
1494 | mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev)); | ||
1495 | |||
1496 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); | ||
1497 | handled++; | ||
1498 | } | ||
1499 | spin_unlock(&host_set->lock); | ||
1500 | |||
1501 | return IRQ_RETVAL(handled); | ||
1502 | } | ||
1503 | |||
1504 | static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) | ||
1505 | { | ||
1506 | void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); | ||
1507 | unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; | ||
1508 | |||
1509 | return hc_mmio + ofs; | ||
1510 | } | ||
1511 | |||
1512 | static unsigned int mv5_scr_offset(unsigned int sc_reg_in) | ||
1513 | { | ||
1514 | unsigned int ofs; | ||
1515 | |||
1516 | switch (sc_reg_in) { | ||
1517 | case SCR_STATUS: | ||
1518 | case SCR_ERROR: | ||
1519 | case SCR_CONTROL: | ||
1520 | ofs = sc_reg_in * sizeof(u32); | ||
1521 | break; | ||
1522 | default: | ||
1523 | ofs = 0xffffffffU; | ||
1524 | break; | ||
1525 | } | ||
1526 | return ofs; | ||
1527 | } | ||
1528 | |||
1529 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in) | ||
1530 | { | ||
1531 | void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no); | ||
1532 | unsigned int ofs = mv5_scr_offset(sc_reg_in); | ||
1533 | |||
1534 | if (ofs != 0xffffffffU) | ||
1535 | return readl(mmio + ofs); | ||
1536 | else | ||
1537 | return (u32) ofs; | ||
1538 | } | ||
1539 | |||
1540 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) | ||
1541 | { | ||
1542 | void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no); | ||
1543 | unsigned int ofs = mv5_scr_offset(sc_reg_in); | ||
1544 | |||
1545 | if (ofs != 0xffffffffU) | ||
1546 | writelfl(val, mmio + ofs); | ||
1547 | } | ||
1548 | |||
1549 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio) | ||
1550 | { | ||
1551 | u8 rev_id; | ||
1552 | int early_5080; | ||
1553 | |||
1554 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); | ||
1555 | |||
1556 | early_5080 = (pdev->device == 0x5080) && (rev_id == 0); | ||
1557 | |||
1558 | if (!early_5080) { | ||
1559 | u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); | ||
1560 | tmp |= (1 << 0); | ||
1561 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); | ||
1562 | } | ||
1563 | |||
1564 | mv_reset_pci_bus(pdev, mmio); | ||
1565 | } | ||
1566 | |||
1567 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) | ||
1568 | { | ||
1569 | writel(0x0fcfffff, mmio + MV_FLASH_CTL); | ||
1570 | } | ||
1571 | |||
1572 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, | ||
1573 | void __iomem *mmio) | ||
1574 | { | ||
1575 | void __iomem *phy_mmio = mv5_phy_base(mmio, idx); | ||
1576 | u32 tmp; | ||
1577 | |||
1578 | tmp = readl(phy_mmio + MV5_PHY_MODE); | ||
1579 | |||
1580 | hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ | ||
1581 | hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ | ||
1582 | } | ||
1583 | |||
1584 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) | ||
1585 | { | ||
1586 | u32 tmp; | ||
1587 | |||
1588 | writel(0, mmio + MV_GPIO_PORT_CTL); | ||
1589 | |||
1590 | /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ | ||
1591 | |||
1592 | tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); | ||
1593 | tmp |= ~(1 << 0); | ||
1594 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); | ||
1595 | } | ||
1596 | |||
1597 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
1598 | unsigned int port) | ||
1599 | { | ||
1600 | void __iomem *phy_mmio = mv5_phy_base(mmio, port); | ||
1601 | const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); | ||
1602 | u32 tmp; | ||
1603 | int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); | ||
1604 | |||
1605 | if (fix_apm_sq) { | ||
1606 | tmp = readl(phy_mmio + MV5_LT_MODE); | ||
1607 | tmp |= (1 << 19); | ||
1608 | writel(tmp, phy_mmio + MV5_LT_MODE); | ||
1609 | |||
1610 | tmp = readl(phy_mmio + MV5_PHY_CTL); | ||
1611 | tmp &= ~0x3; | ||
1612 | tmp |= 0x1; | ||
1613 | writel(tmp, phy_mmio + MV5_PHY_CTL); | ||
1614 | } | ||
1615 | |||
1616 | tmp = readl(phy_mmio + MV5_PHY_MODE); | ||
1617 | tmp &= ~mask; | ||
1618 | tmp |= hpriv->signal[port].pre; | ||
1619 | tmp |= hpriv->signal[port].amps; | ||
1620 | writel(tmp, phy_mmio + MV5_PHY_MODE); | ||
1621 | } | ||
1622 | |||
1623 | |||
1624 | #undef ZERO | ||
1625 | #define ZERO(reg) writel(0, port_mmio + (reg)) | ||
1626 | static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
1627 | unsigned int port) | ||
1628 | { | ||
1629 | void __iomem *port_mmio = mv_port_base(mmio, port); | ||
1630 | |||
1631 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); | ||
1632 | |||
1633 | mv_channel_reset(hpriv, mmio, port); | ||
1634 | |||
1635 | ZERO(0x028); /* command */ | ||
1636 | writel(0x11f, port_mmio + EDMA_CFG_OFS); | ||
1637 | ZERO(0x004); /* timer */ | ||
1638 | ZERO(0x008); /* irq err cause */ | ||
1639 | ZERO(0x00c); /* irq err mask */ | ||
1640 | ZERO(0x010); /* rq bah */ | ||
1641 | ZERO(0x014); /* rq inp */ | ||
1642 | ZERO(0x018); /* rq outp */ | ||
1643 | ZERO(0x01c); /* respq bah */ | ||
1644 | ZERO(0x024); /* respq outp */ | ||
1645 | ZERO(0x020); /* respq inp */ | ||
1646 | ZERO(0x02c); /* test control */ | ||
1647 | writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); | ||
1648 | } | ||
1649 | #undef ZERO | ||
1650 | |||
1651 | #define ZERO(reg) writel(0, hc_mmio + (reg)) | ||
1652 | static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
1653 | unsigned int hc) | ||
1654 | { | ||
1655 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); | ||
1656 | u32 tmp; | ||
1657 | |||
1658 | ZERO(0x00c); | ||
1659 | ZERO(0x010); | ||
1660 | ZERO(0x014); | ||
1661 | ZERO(0x018); | ||
1662 | |||
1663 | tmp = readl(hc_mmio + 0x20); | ||
1664 | tmp &= 0x1c1c1c1c; | ||
1665 | tmp |= 0x03030303; | ||
1666 | writel(tmp, hc_mmio + 0x20); | ||
1667 | } | ||
1668 | #undef ZERO | ||
1669 | |||
1670 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
1671 | unsigned int n_hc) | ||
1672 | { | ||
1673 | unsigned int hc, port; | ||
1674 | |||
1675 | for (hc = 0; hc < n_hc; hc++) { | ||
1676 | for (port = 0; port < MV_PORTS_PER_HC; port++) | ||
1677 | mv5_reset_hc_port(hpriv, mmio, | ||
1678 | (hc * MV_PORTS_PER_HC) + port); | ||
1679 | |||
1680 | mv5_reset_one_hc(hpriv, mmio, hc); | ||
1681 | } | ||
1682 | |||
1683 | return 0; | ||
1684 | } | ||
1685 | |||
1686 | #undef ZERO | ||
1687 | #define ZERO(reg) writel(0, mmio + (reg)) | ||
1688 | static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio) | ||
1689 | { | ||
1690 | u32 tmp; | ||
1691 | |||
1692 | tmp = readl(mmio + MV_PCI_MODE); | ||
1693 | tmp &= 0xff00ffff; | ||
1694 | writel(tmp, mmio + MV_PCI_MODE); | ||
1695 | |||
1696 | ZERO(MV_PCI_DISC_TIMER); | ||
1697 | ZERO(MV_PCI_MSI_TRIGGER); | ||
1698 | writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); | ||
1699 | ZERO(HC_MAIN_IRQ_MASK_OFS); | ||
1700 | ZERO(MV_PCI_SERR_MASK); | ||
1701 | ZERO(PCI_IRQ_CAUSE_OFS); | ||
1702 | ZERO(PCI_IRQ_MASK_OFS); | ||
1703 | ZERO(MV_PCI_ERR_LOW_ADDRESS); | ||
1704 | ZERO(MV_PCI_ERR_HIGH_ADDRESS); | ||
1705 | ZERO(MV_PCI_ERR_ATTRIBUTE); | ||
1706 | ZERO(MV_PCI_ERR_COMMAND); | ||
1707 | } | ||
1708 | #undef ZERO | ||
1709 | |||
1710 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) | ||
1711 | { | ||
1712 | u32 tmp; | ||
1713 | |||
1714 | mv5_reset_flash(hpriv, mmio); | ||
1715 | |||
1716 | tmp = readl(mmio + MV_GPIO_PORT_CTL); | ||
1717 | tmp &= 0x3; | ||
1718 | tmp |= (1 << 5) | (1 << 6); | ||
1719 | writel(tmp, mmio + MV_GPIO_PORT_CTL); | ||
1720 | } | ||
1721 | |||
1722 | /** | ||
1723 | * mv6_reset_hc - Perform the 6xxx global soft reset | ||
1724 | * @mmio: base address of the HBA | ||
1725 | * | ||
1726 | * This routine only applies to 6xxx parts. | ||
1727 | * | ||
1728 | * LOCKING: | ||
1729 | * Inherited from caller. | ||
1730 | */ | ||
1731 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
1732 | unsigned int n_hc) | ||
1733 | { | ||
1734 | void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; | ||
1735 | int i, rc = 0; | ||
1736 | u32 t; | ||
1737 | |||
1738 | /* Following procedure defined in PCI "main command and status | ||
1739 | * register" table. | ||
1740 | */ | ||
1741 | t = readl(reg); | ||
1742 | writel(t | STOP_PCI_MASTER, reg); | ||
1743 | |||
1744 | for (i = 0; i < 1000; i++) { | ||
1745 | udelay(1); | ||
1746 | t = readl(reg); | ||
1747 | if (PCI_MASTER_EMPTY & t) { | ||
1748 | break; | ||
1749 | } | ||
1750 | } | ||
1751 | if (!(PCI_MASTER_EMPTY & t)) { | ||
1752 | printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); | ||
1753 | rc = 1; | ||
1754 | goto done; | ||
1755 | } | ||
1756 | |||
1757 | /* set reset */ | ||
1758 | i = 5; | ||
1759 | do { | ||
1760 | writel(t | GLOB_SFT_RST, reg); | ||
1761 | t = readl(reg); | ||
1762 | udelay(1); | ||
1763 | } while (!(GLOB_SFT_RST & t) && (i-- > 0)); | ||
1764 | |||
1765 | if (!(GLOB_SFT_RST & t)) { | ||
1766 | printk(KERN_ERR DRV_NAME ": can't set global reset\n"); | ||
1767 | rc = 1; | ||
1768 | goto done; | ||
1769 | } | ||
1770 | |||
1771 | /* clear reset and *reenable the PCI master* (not mentioned in spec) */ | ||
1772 | i = 5; | ||
1773 | do { | ||
1774 | writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); | ||
1775 | t = readl(reg); | ||
1776 | udelay(1); | ||
1777 | } while ((GLOB_SFT_RST & t) && (i-- > 0)); | ||
1778 | |||
1779 | if (GLOB_SFT_RST & t) { | ||
1780 | printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); | ||
1781 | rc = 1; | ||
1782 | } | ||
1783 | done: | ||
1784 | return rc; | ||
1785 | } | ||
1786 | |||
1787 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, | ||
1788 | void __iomem *mmio) | ||
1789 | { | ||
1790 | void __iomem *port_mmio; | ||
1791 | u32 tmp; | ||
1792 | |||
1793 | tmp = readl(mmio + MV_RESET_CFG); | ||
1794 | if ((tmp & (1 << 0)) == 0) { | ||
1795 | hpriv->signal[idx].amps = 0x7 << 8; | ||
1796 | hpriv->signal[idx].pre = 0x1 << 5; | ||
1797 | return; | ||
1798 | } | ||
1799 | |||
1800 | port_mmio = mv_port_base(mmio, idx); | ||
1801 | tmp = readl(port_mmio + PHY_MODE2); | ||
1802 | |||
1803 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ | ||
1804 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ | ||
1805 | } | ||
1806 | |||
1807 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) | ||
1808 | { | ||
1809 | writel(0x00000060, mmio + MV_GPIO_PORT_CTL); | ||
1810 | } | ||
1811 | |||
1812 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
1813 | unsigned int port) | ||
1814 | { | ||
1815 | void __iomem *port_mmio = mv_port_base(mmio, port); | ||
1816 | |||
1817 | u32 hp_flags = hpriv->hp_flags; | ||
1818 | int fix_phy_mode2 = | ||
1819 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); | ||
1820 | int fix_phy_mode4 = | ||
1821 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); | ||
1822 | u32 m2, tmp; | ||
1823 | |||
1824 | if (fix_phy_mode2) { | ||
1825 | m2 = readl(port_mmio + PHY_MODE2); | ||
1826 | m2 &= ~(1 << 16); | ||
1827 | m2 |= (1 << 31); | ||
1828 | writel(m2, port_mmio + PHY_MODE2); | ||
1829 | |||
1830 | udelay(200); | ||
1831 | |||
1832 | m2 = readl(port_mmio + PHY_MODE2); | ||
1833 | m2 &= ~((1 << 16) | (1 << 31)); | ||
1834 | writel(m2, port_mmio + PHY_MODE2); | ||
1835 | |||
1836 | udelay(200); | ||
1837 | } | ||
1838 | |||
1839 | /* who knows what this magic does */ | ||
1840 | tmp = readl(port_mmio + PHY_MODE3); | ||
1841 | tmp &= ~0x7F800000; | ||
1842 | tmp |= 0x2A800000; | ||
1843 | writel(tmp, port_mmio + PHY_MODE3); | ||
1844 | |||
1845 | if (fix_phy_mode4) { | ||
1846 | u32 m4; | ||
1847 | |||
1848 | m4 = readl(port_mmio + PHY_MODE4); | ||
1849 | |||
1850 | if (hp_flags & MV_HP_ERRATA_60X1B2) | ||
1851 | tmp = readl(port_mmio + 0x310); | ||
1852 | |||
1853 | m4 = (m4 & ~(1 << 1)) | (1 << 0); | ||
1854 | |||
1855 | writel(m4, port_mmio + PHY_MODE4); | ||
1856 | |||
1857 | if (hp_flags & MV_HP_ERRATA_60X1B2) | ||
1858 | writel(tmp, port_mmio + 0x310); | ||
1859 | } | ||
1860 | |||
1861 | /* Revert values of pre-emphasis and signal amps to the saved ones */ | ||
1862 | m2 = readl(port_mmio + PHY_MODE2); | ||
1863 | |||
1864 | m2 &= ~MV_M2_PREAMP_MASK; | ||
1865 | m2 |= hpriv->signal[port].amps; | ||
1866 | m2 |= hpriv->signal[port].pre; | ||
1867 | m2 &= ~(1 << 16); | ||
1868 | |||
1869 | /* according to mvSata 3.6.1, some IIE values are fixed */ | ||
1870 | if (IS_GEN_IIE(hpriv)) { | ||
1871 | m2 &= ~0xC30FF01F; | ||
1872 | m2 |= 0x0000900F; | ||
1873 | } | ||
1874 | |||
1875 | writel(m2, port_mmio + PHY_MODE2); | ||
1876 | } | ||
1877 | |||
1878 | static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, | ||
1879 | unsigned int port_no) | ||
1880 | { | ||
1881 | void __iomem *port_mmio = mv_port_base(mmio, port_no); | ||
1882 | |||
1883 | writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); | ||
1884 | |||
1885 | if (IS_60XX(hpriv)) { | ||
1886 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL); | ||
1887 | ifctl |= (1 << 7); /* enable gen2i speed */ | ||
1888 | ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */ | ||
1889 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL); | ||
1890 | } | ||
1891 | |||
1892 | udelay(25); /* allow reset propagation */ | ||
1893 | |||
1894 | /* Spec never mentions clearing the bit. Marvell's driver does | ||
1895 | * clear the bit, however. | ||
1896 | */ | ||
1897 | writelfl(0, port_mmio + EDMA_CMD_OFS); | ||
1898 | |||
1899 | hpriv->ops->phy_errata(hpriv, mmio, port_no); | ||
1900 | |||
1901 | if (IS_50XX(hpriv)) | ||
1902 | mdelay(1); | ||
1903 | } | ||
1904 | |||
1905 | static void mv_stop_and_reset(struct ata_port *ap) | ||
1906 | { | ||
1907 | struct mv_host_priv *hpriv = ap->host_set->private_data; | ||
1908 | void __iomem *mmio = ap->host_set->mmio_base; | ||
1909 | |||
1910 | mv_stop_dma(ap); | ||
1911 | |||
1912 | mv_channel_reset(hpriv, mmio, ap->port_no); | ||
1913 | |||
1914 | __mv_phy_reset(ap, 0); | ||
1915 | } | ||
1916 | |||
1917 | static inline void __msleep(unsigned int msec, int can_sleep) | ||
1918 | { | ||
1919 | if (can_sleep) | ||
1920 | msleep(msec); | ||
1921 | else | ||
1922 | mdelay(msec); | ||
1923 | } | ||
1924 | |||
1925 | /** | ||
1926 | * __mv_phy_reset - Perform eDMA reset followed by COMRESET | ||
1927 | * @ap: ATA channel to manipulate | ||
1928 | * | ||
1929 | * Part of this is taken from __sata_phy_reset and modified to | ||
1930 | * not sleep since this routine gets called from interrupt level. | ||
1931 | * | ||
1932 | * LOCKING: | ||
1933 | * Inherited from caller. This is coded to safe to call at | ||
1934 | * interrupt level, i.e. it does not sleep. | ||
1935 | */ | ||
1936 | static void __mv_phy_reset(struct ata_port *ap, int can_sleep) | ||
1937 | { | ||
1938 | struct mv_port_priv *pp = ap->private_data; | ||
1939 | struct mv_host_priv *hpriv = ap->host_set->private_data; | ||
1940 | void __iomem *port_mmio = mv_ap_base(ap); | ||
1941 | struct ata_taskfile tf; | ||
1942 | struct ata_device *dev = &ap->device[0]; | ||
1943 | unsigned long timeout; | ||
1944 | int retry = 5; | ||
1945 | u32 sstatus; | ||
1946 | |||
1947 | VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio); | ||
1948 | |||
1949 | DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " | ||
1950 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), | ||
1951 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); | ||
1952 | |||
1953 | /* Issue COMRESET via SControl */ | ||
1954 | comreset_retry: | ||
1955 | sata_scr_write_flush(ap, SCR_CONTROL, 0x301); | ||
1956 | __msleep(1, can_sleep); | ||
1957 | |||
1958 | sata_scr_write_flush(ap, SCR_CONTROL, 0x300); | ||
1959 | __msleep(20, can_sleep); | ||
1960 | |||
1961 | timeout = jiffies + msecs_to_jiffies(200); | ||
1962 | do { | ||
1963 | sata_scr_read(ap, SCR_STATUS, &sstatus); | ||
1964 | sstatus &= 0x3; | ||
1965 | if ((sstatus == 3) || (sstatus == 0)) | ||
1966 | break; | ||
1967 | |||
1968 | __msleep(1, can_sleep); | ||
1969 | } while (time_before(jiffies, timeout)); | ||
1970 | |||
1971 | /* work around errata */ | ||
1972 | if (IS_60XX(hpriv) && | ||
1973 | (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) && | ||
1974 | (retry-- > 0)) | ||
1975 | goto comreset_retry; | ||
1976 | |||
1977 | DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " | ||
1978 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), | ||
1979 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); | ||
1980 | |||
1981 | if (ata_port_online(ap)) { | ||
1982 | ata_port_probe(ap); | ||
1983 | } else { | ||
1984 | sata_scr_read(ap, SCR_STATUS, &sstatus); | ||
1985 | ata_port_printk(ap, KERN_INFO, | ||
1986 | "no device found (phy stat %08x)\n", sstatus); | ||
1987 | ata_port_disable(ap); | ||
1988 | return; | ||
1989 | } | ||
1990 | ap->cbl = ATA_CBL_SATA; | ||
1991 | |||
1992 | /* even after SStatus reflects that device is ready, | ||
1993 | * it seems to take a while for link to be fully | ||
1994 | * established (and thus Status no longer 0x80/0x7F), | ||
1995 | * so we poll a bit for that, here. | ||
1996 | */ | ||
1997 | retry = 20; | ||
1998 | while (1) { | ||
1999 | u8 drv_stat = ata_check_status(ap); | ||
2000 | if ((drv_stat != 0x80) && (drv_stat != 0x7f)) | ||
2001 | break; | ||
2002 | __msleep(500, can_sleep); | ||
2003 | if (retry-- <= 0) | ||
2004 | break; | ||
2005 | } | ||
2006 | |||
2007 | tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr); | ||
2008 | tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr); | ||
2009 | tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr); | ||
2010 | tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr); | ||
2011 | |||
2012 | dev->class = ata_dev_classify(&tf); | ||
2013 | if (!ata_dev_enabled(dev)) { | ||
2014 | VPRINTK("Port disabled post-sig: No device present.\n"); | ||
2015 | ata_port_disable(ap); | ||
2016 | } | ||
2017 | |||
2018 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | ||
2019 | |||
2020 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | ||
2021 | |||
2022 | VPRINTK("EXIT\n"); | ||
2023 | } | ||
2024 | |||
2025 | static void mv_phy_reset(struct ata_port *ap) | ||
2026 | { | ||
2027 | __mv_phy_reset(ap, 1); | ||
2028 | } | ||
2029 | |||
2030 | /** | ||
2031 | * mv_eng_timeout - Routine called by libata when SCSI times out I/O | ||
2032 | * @ap: ATA channel to manipulate | ||
2033 | * | ||
2034 | * Intent is to clear all pending error conditions, reset the | ||
2035 | * chip/bus, fail the command, and move on. | ||
2036 | * | ||
2037 | * LOCKING: | ||
2038 | * This routine holds the host_set lock while failing the command. | ||
2039 | */ | ||
2040 | static void mv_eng_timeout(struct ata_port *ap) | ||
2041 | { | ||
2042 | struct ata_queued_cmd *qc; | ||
2043 | unsigned long flags; | ||
2044 | |||
2045 | ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n"); | ||
2046 | DPRINTK("All regs @ start of eng_timeout\n"); | ||
2047 | mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no, | ||
2048 | to_pci_dev(ap->host_set->dev)); | ||
2049 | |||
2050 | qc = ata_qc_from_tag(ap, ap->active_tag); | ||
2051 | printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n", | ||
2052 | ap->host_set->mmio_base, ap, qc, qc->scsicmd, | ||
2053 | &qc->scsicmd->cmnd); | ||
2054 | |||
2055 | spin_lock_irqsave(&ap->host_set->lock, flags); | ||
2056 | mv_err_intr(ap, 0); | ||
2057 | mv_stop_and_reset(ap); | ||
2058 | spin_unlock_irqrestore(&ap->host_set->lock, flags); | ||
2059 | |||
2060 | WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE)); | ||
2061 | if (qc->flags & ATA_QCFLAG_ACTIVE) { | ||
2062 | qc->err_mask |= AC_ERR_TIMEOUT; | ||
2063 | ata_eh_qc_complete(qc); | ||
2064 | } | ||
2065 | } | ||
2066 | |||
2067 | /** | ||
2068 | * mv_port_init - Perform some early initialization on a single port. | ||
2069 | * @port: libata data structure storing shadow register addresses | ||
2070 | * @port_mmio: base address of the port | ||
2071 | * | ||
2072 | * Initialize shadow register mmio addresses, clear outstanding | ||
2073 | * interrupts on the port, and unmask interrupts for the future | ||
2074 | * start of the port. | ||
2075 | * | ||
2076 | * LOCKING: | ||
2077 | * Inherited from caller. | ||
2078 | */ | ||
2079 | static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) | ||
2080 | { | ||
2081 | unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS; | ||
2082 | unsigned serr_ofs; | ||
2083 | |||
2084 | /* PIO related setup | ||
2085 | */ | ||
2086 | port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); | ||
2087 | port->error_addr = | ||
2088 | port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); | ||
2089 | port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); | ||
2090 | port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); | ||
2091 | port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); | ||
2092 | port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); | ||
2093 | port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); | ||
2094 | port->status_addr = | ||
2095 | port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); | ||
2096 | /* special case: control/altstatus doesn't have ATA_REG_ address */ | ||
2097 | port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; | ||
2098 | |||
2099 | /* unused: */ | ||
2100 | port->cmd_addr = port->bmdma_addr = port->scr_addr = 0; | ||
2101 | |||
2102 | /* Clear any currently outstanding port interrupt conditions */ | ||
2103 | serr_ofs = mv_scr_offset(SCR_ERROR); | ||
2104 | writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); | ||
2105 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | ||
2106 | |||
2107 | /* unmask all EDMA error interrupts */ | ||
2108 | writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS); | ||
2109 | |||
2110 | VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", | ||
2111 | readl(port_mmio + EDMA_CFG_OFS), | ||
2112 | readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), | ||
2113 | readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); | ||
2114 | } | ||
2115 | |||
2116 | static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv, | ||
2117 | unsigned int board_idx) | ||
2118 | { | ||
2119 | u8 rev_id; | ||
2120 | u32 hp_flags = hpriv->hp_flags; | ||
2121 | |||
2122 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); | ||
2123 | |||
2124 | switch(board_idx) { | ||
2125 | case chip_5080: | ||
2126 | hpriv->ops = &mv5xxx_ops; | ||
2127 | hp_flags |= MV_HP_50XX; | ||
2128 | |||
2129 | switch (rev_id) { | ||
2130 | case 0x1: | ||
2131 | hp_flags |= MV_HP_ERRATA_50XXB0; | ||
2132 | break; | ||
2133 | case 0x3: | ||
2134 | hp_flags |= MV_HP_ERRATA_50XXB2; | ||
2135 | break; | ||
2136 | default: | ||
2137 | dev_printk(KERN_WARNING, &pdev->dev, | ||
2138 | "Applying 50XXB2 workarounds to unknown rev\n"); | ||
2139 | hp_flags |= MV_HP_ERRATA_50XXB2; | ||
2140 | break; | ||
2141 | } | ||
2142 | break; | ||
2143 | |||
2144 | case chip_504x: | ||
2145 | case chip_508x: | ||
2146 | hpriv->ops = &mv5xxx_ops; | ||
2147 | hp_flags |= MV_HP_50XX; | ||
2148 | |||
2149 | switch (rev_id) { | ||
2150 | case 0x0: | ||
2151 | hp_flags |= MV_HP_ERRATA_50XXB0; | ||
2152 | break; | ||
2153 | case 0x3: | ||
2154 | hp_flags |= MV_HP_ERRATA_50XXB2; | ||
2155 | break; | ||
2156 | default: | ||
2157 | dev_printk(KERN_WARNING, &pdev->dev, | ||
2158 | "Applying B2 workarounds to unknown rev\n"); | ||
2159 | hp_flags |= MV_HP_ERRATA_50XXB2; | ||
2160 | break; | ||
2161 | } | ||
2162 | break; | ||
2163 | |||
2164 | case chip_604x: | ||
2165 | case chip_608x: | ||
2166 | hpriv->ops = &mv6xxx_ops; | ||
2167 | |||
2168 | switch (rev_id) { | ||
2169 | case 0x7: | ||
2170 | hp_flags |= MV_HP_ERRATA_60X1B2; | ||
2171 | break; | ||
2172 | case 0x9: | ||
2173 | hp_flags |= MV_HP_ERRATA_60X1C0; | ||
2174 | break; | ||
2175 | default: | ||
2176 | dev_printk(KERN_WARNING, &pdev->dev, | ||
2177 | "Applying B2 workarounds to unknown rev\n"); | ||
2178 | hp_flags |= MV_HP_ERRATA_60X1B2; | ||
2179 | break; | ||
2180 | } | ||
2181 | break; | ||
2182 | |||
2183 | case chip_7042: | ||
2184 | case chip_6042: | ||
2185 | hpriv->ops = &mv6xxx_ops; | ||
2186 | |||
2187 | hp_flags |= MV_HP_GEN_IIE; | ||
2188 | |||
2189 | switch (rev_id) { | ||
2190 | case 0x0: | ||
2191 | hp_flags |= MV_HP_ERRATA_XX42A0; | ||
2192 | break; | ||
2193 | case 0x1: | ||
2194 | hp_flags |= MV_HP_ERRATA_60X1C0; | ||
2195 | break; | ||
2196 | default: | ||
2197 | dev_printk(KERN_WARNING, &pdev->dev, | ||
2198 | "Applying 60X1C0 workarounds to unknown rev\n"); | ||
2199 | hp_flags |= MV_HP_ERRATA_60X1C0; | ||
2200 | break; | ||
2201 | } | ||
2202 | break; | ||
2203 | |||
2204 | default: | ||
2205 | printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx); | ||
2206 | return 1; | ||
2207 | } | ||
2208 | |||
2209 | hpriv->hp_flags = hp_flags; | ||
2210 | |||
2211 | return 0; | ||
2212 | } | ||
2213 | |||
2214 | /** | ||
2215 | * mv_init_host - Perform some early initialization of the host. | ||
2216 | * @pdev: host PCI device | ||
2217 | * @probe_ent: early data struct representing the host | ||
2218 | * | ||
2219 | * If possible, do an early global reset of the host. Then do | ||
2220 | * our port init and clear/unmask all/relevant host interrupts. | ||
2221 | * | ||
2222 | * LOCKING: | ||
2223 | * Inherited from caller. | ||
2224 | */ | ||
2225 | static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent, | ||
2226 | unsigned int board_idx) | ||
2227 | { | ||
2228 | int rc = 0, n_hc, port, hc; | ||
2229 | void __iomem *mmio = probe_ent->mmio_base; | ||
2230 | struct mv_host_priv *hpriv = probe_ent->private_data; | ||
2231 | |||
2232 | /* global interrupt mask */ | ||
2233 | writel(0, mmio + HC_MAIN_IRQ_MASK_OFS); | ||
2234 | |||
2235 | rc = mv_chip_id(pdev, hpriv, board_idx); | ||
2236 | if (rc) | ||
2237 | goto done; | ||
2238 | |||
2239 | n_hc = mv_get_hc_count(probe_ent->host_flags); | ||
2240 | probe_ent->n_ports = MV_PORTS_PER_HC * n_hc; | ||
2241 | |||
2242 | for (port = 0; port < probe_ent->n_ports; port++) | ||
2243 | hpriv->ops->read_preamp(hpriv, port, mmio); | ||
2244 | |||
2245 | rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); | ||
2246 | if (rc) | ||
2247 | goto done; | ||
2248 | |||
2249 | hpriv->ops->reset_flash(hpriv, mmio); | ||
2250 | hpriv->ops->reset_bus(pdev, mmio); | ||
2251 | hpriv->ops->enable_leds(hpriv, mmio); | ||
2252 | |||
2253 | for (port = 0; port < probe_ent->n_ports; port++) { | ||
2254 | if (IS_60XX(hpriv)) { | ||
2255 | void __iomem *port_mmio = mv_port_base(mmio, port); | ||
2256 | |||
2257 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL); | ||
2258 | ifctl |= (1 << 7); /* enable gen2i speed */ | ||
2259 | ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */ | ||
2260 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL); | ||
2261 | } | ||
2262 | |||
2263 | hpriv->ops->phy_errata(hpriv, mmio, port); | ||
2264 | } | ||
2265 | |||
2266 | for (port = 0; port < probe_ent->n_ports; port++) { | ||
2267 | void __iomem *port_mmio = mv_port_base(mmio, port); | ||
2268 | mv_port_init(&probe_ent->port[port], port_mmio); | ||
2269 | } | ||
2270 | |||
2271 | for (hc = 0; hc < n_hc; hc++) { | ||
2272 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); | ||
2273 | |||
2274 | VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " | ||
2275 | "(before clear)=0x%08x\n", hc, | ||
2276 | readl(hc_mmio + HC_CFG_OFS), | ||
2277 | readl(hc_mmio + HC_IRQ_CAUSE_OFS)); | ||
2278 | |||
2279 | /* Clear any currently outstanding hc interrupt conditions */ | ||
2280 | writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); | ||
2281 | } | ||
2282 | |||
2283 | /* Clear any currently outstanding host interrupt conditions */ | ||
2284 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); | ||
2285 | |||
2286 | /* and unmask interrupt generation for host regs */ | ||
2287 | writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS); | ||
2288 | writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS); | ||
2289 | |||
2290 | VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " | ||
2291 | "PCI int cause/mask=0x%08x/0x%08x\n", | ||
2292 | readl(mmio + HC_MAIN_IRQ_CAUSE_OFS), | ||
2293 | readl(mmio + HC_MAIN_IRQ_MASK_OFS), | ||
2294 | readl(mmio + PCI_IRQ_CAUSE_OFS), | ||
2295 | readl(mmio + PCI_IRQ_MASK_OFS)); | ||
2296 | |||
2297 | done: | ||
2298 | return rc; | ||
2299 | } | ||
2300 | |||
2301 | /** | ||
2302 | * mv_print_info - Dump key info to kernel log for perusal. | ||
2303 | * @probe_ent: early data struct representing the host | ||
2304 | * | ||
2305 | * FIXME: complete this. | ||
2306 | * | ||
2307 | * LOCKING: | ||
2308 | * Inherited from caller. | ||
2309 | */ | ||
2310 | static void mv_print_info(struct ata_probe_ent *probe_ent) | ||
2311 | { | ||
2312 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | ||
2313 | struct mv_host_priv *hpriv = probe_ent->private_data; | ||
2314 | u8 rev_id, scc; | ||
2315 | const char *scc_s; | ||
2316 | |||
2317 | /* Use this to determine the HW stepping of the chip so we know | ||
2318 | * what errata to workaround | ||
2319 | */ | ||
2320 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); | ||
2321 | |||
2322 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); | ||
2323 | if (scc == 0) | ||
2324 | scc_s = "SCSI"; | ||
2325 | else if (scc == 0x01) | ||
2326 | scc_s = "RAID"; | ||
2327 | else | ||
2328 | scc_s = "unknown"; | ||
2329 | |||
2330 | dev_printk(KERN_INFO, &pdev->dev, | ||
2331 | "%u slots %u ports %s mode IRQ via %s\n", | ||
2332 | (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports, | ||
2333 | scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); | ||
2334 | } | ||
2335 | |||
2336 | /** | ||
2337 | * mv_init_one - handle a positive probe of a Marvell host | ||
2338 | * @pdev: PCI device found | ||
2339 | * @ent: PCI device ID entry for the matched host | ||
2340 | * | ||
2341 | * LOCKING: | ||
2342 | * Inherited from caller. | ||
2343 | */ | ||
2344 | static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | ||
2345 | { | ||
2346 | static int printed_version = 0; | ||
2347 | struct ata_probe_ent *probe_ent = NULL; | ||
2348 | struct mv_host_priv *hpriv; | ||
2349 | unsigned int board_idx = (unsigned int)ent->driver_data; | ||
2350 | void __iomem *mmio_base; | ||
2351 | int pci_dev_busy = 0, rc; | ||
2352 | |||
2353 | if (!printed_version++) | ||
2354 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | ||
2355 | |||
2356 | rc = pci_enable_device(pdev); | ||
2357 | if (rc) { | ||
2358 | return rc; | ||
2359 | } | ||
2360 | pci_set_master(pdev); | ||
2361 | |||
2362 | rc = pci_request_regions(pdev, DRV_NAME); | ||
2363 | if (rc) { | ||
2364 | pci_dev_busy = 1; | ||
2365 | goto err_out; | ||
2366 | } | ||
2367 | |||
2368 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | ||
2369 | if (probe_ent == NULL) { | ||
2370 | rc = -ENOMEM; | ||
2371 | goto err_out_regions; | ||
2372 | } | ||
2373 | |||
2374 | memset(probe_ent, 0, sizeof(*probe_ent)); | ||
2375 | probe_ent->dev = pci_dev_to_dev(pdev); | ||
2376 | INIT_LIST_HEAD(&probe_ent->node); | ||
2377 | |||
2378 | mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0); | ||
2379 | if (mmio_base == NULL) { | ||
2380 | rc = -ENOMEM; | ||
2381 | goto err_out_free_ent; | ||
2382 | } | ||
2383 | |||
2384 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); | ||
2385 | if (!hpriv) { | ||
2386 | rc = -ENOMEM; | ||
2387 | goto err_out_iounmap; | ||
2388 | } | ||
2389 | memset(hpriv, 0, sizeof(*hpriv)); | ||
2390 | |||
2391 | probe_ent->sht = mv_port_info[board_idx].sht; | ||
2392 | probe_ent->host_flags = mv_port_info[board_idx].host_flags; | ||
2393 | probe_ent->pio_mask = mv_port_info[board_idx].pio_mask; | ||
2394 | probe_ent->udma_mask = mv_port_info[board_idx].udma_mask; | ||
2395 | probe_ent->port_ops = mv_port_info[board_idx].port_ops; | ||
2396 | |||
2397 | probe_ent->irq = pdev->irq; | ||
2398 | probe_ent->irq_flags = IRQF_SHARED; | ||
2399 | probe_ent->mmio_base = mmio_base; | ||
2400 | probe_ent->private_data = hpriv; | ||
2401 | |||
2402 | /* initialize adapter */ | ||
2403 | rc = mv_init_host(pdev, probe_ent, board_idx); | ||
2404 | if (rc) { | ||
2405 | goto err_out_hpriv; | ||
2406 | } | ||
2407 | |||
2408 | /* Enable interrupts */ | ||
2409 | if (msi && pci_enable_msi(pdev) == 0) { | ||
2410 | hpriv->hp_flags |= MV_HP_FLAG_MSI; | ||
2411 | } else { | ||
2412 | pci_intx(pdev, 1); | ||
2413 | } | ||
2414 | |||
2415 | mv_dump_pci_cfg(pdev, 0x68); | ||
2416 | mv_print_info(probe_ent); | ||
2417 | |||
2418 | if (ata_device_add(probe_ent) == 0) { | ||
2419 | rc = -ENODEV; /* No devices discovered */ | ||
2420 | goto err_out_dev_add; | ||
2421 | } | ||
2422 | |||
2423 | kfree(probe_ent); | ||
2424 | return 0; | ||
2425 | |||
2426 | err_out_dev_add: | ||
2427 | if (MV_HP_FLAG_MSI & hpriv->hp_flags) { | ||
2428 | pci_disable_msi(pdev); | ||
2429 | } else { | ||
2430 | pci_intx(pdev, 0); | ||
2431 | } | ||
2432 | err_out_hpriv: | ||
2433 | kfree(hpriv); | ||
2434 | err_out_iounmap: | ||
2435 | pci_iounmap(pdev, mmio_base); | ||
2436 | err_out_free_ent: | ||
2437 | kfree(probe_ent); | ||
2438 | err_out_regions: | ||
2439 | pci_release_regions(pdev); | ||
2440 | err_out: | ||
2441 | if (!pci_dev_busy) { | ||
2442 | pci_disable_device(pdev); | ||
2443 | } | ||
2444 | |||
2445 | return rc; | ||
2446 | } | ||
2447 | |||
2448 | static int __init mv_init(void) | ||
2449 | { | ||
2450 | return pci_register_driver(&mv_pci_driver); | ||
2451 | } | ||
2452 | |||
2453 | static void __exit mv_exit(void) | ||
2454 | { | ||
2455 | pci_unregister_driver(&mv_pci_driver); | ||
2456 | } | ||
2457 | |||
2458 | MODULE_AUTHOR("Brett Russ"); | ||
2459 | MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); | ||
2460 | MODULE_LICENSE("GPL"); | ||
2461 | MODULE_DEVICE_TABLE(pci, mv_pci_tbl); | ||
2462 | MODULE_VERSION(DRV_VERSION); | ||
2463 | |||
2464 | module_param(msi, int, 0444); | ||
2465 | MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); | ||
2466 | |||
2467 | module_init(mv_init); | ||
2468 | module_exit(mv_exit); | ||