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path: root/drivers/ata/sata_mv.c
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Diffstat (limited to 'drivers/ata/sata_mv.c')
-rw-r--r--drivers/ata/sata_mv.c366
1 files changed, 321 insertions, 45 deletions
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 3c1b5c9027db..080b8362f8d6 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -69,8 +69,11 @@
69#include <linux/blkdev.h> 69#include <linux/blkdev.h>
70#include <linux/delay.h> 70#include <linux/delay.h>
71#include <linux/interrupt.h> 71#include <linux/interrupt.h>
72#include <linux/dmapool.h>
72#include <linux/dma-mapping.h> 73#include <linux/dma-mapping.h>
73#include <linux/device.h> 74#include <linux/device.h>
75#include <linux/platform_device.h>
76#include <linux/ata_platform.h>
74#include <scsi/scsi_host.h> 77#include <scsi/scsi_host.h>
75#include <scsi/scsi_cmnd.h> 78#include <scsi/scsi_cmnd.h>
76#include <scsi/scsi_device.h> 79#include <scsi/scsi_device.h>
@@ -179,6 +182,8 @@ enum {
179 182
180 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 183 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
181 HC_MAIN_IRQ_MASK_OFS = 0x1d64, 184 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
185 HC_SOC_MAIN_IRQ_CAUSE_OFS = 0x20020,
186 HC_SOC_MAIN_IRQ_MASK_OFS = 0x20024,
182 PORT0_ERR = (1 << 0), /* shift by port # */ 187 PORT0_ERR = (1 << 0), /* shift by port # */
183 PORT0_DONE = (1 << 1), /* shift by port # */ 188 PORT0_DONE = (1 << 1), /* shift by port # */
184 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 189 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
@@ -194,11 +199,13 @@ enum {
194 TWSI_INT = (1 << 24), 199 TWSI_INT = (1 << 24),
195 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 200 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
196 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 201 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
202 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
197 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | 203 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
198 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | 204 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
199 HC_MAIN_RSVD), 205 HC_MAIN_RSVD),
200 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 206 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
201 HC_MAIN_RSVD_5), 207 HC_MAIN_RSVD_5),
208 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
202 209
203 /* SATAHC registers */ 210 /* SATAHC registers */
204 HC_CFG_OFS = 0, 211 HC_CFG_OFS = 0,
@@ -368,6 +375,7 @@ enum chip_type {
368 chip_608x, 375 chip_608x,
369 chip_6042, 376 chip_6042,
370 chip_7042, 377 chip_7042,
378 chip_soc,
371}; 379};
372 380
373/* Command ReQuest Block: 32B */ 381/* Command ReQuest Block: 32B */
@@ -424,6 +432,10 @@ struct mv_host_priv {
424 u32 hp_flags; 432 u32 hp_flags;
425 struct mv_port_signal signal[8]; 433 struct mv_port_signal signal[8];
426 const struct mv_hw_ops *ops; 434 const struct mv_hw_ops *ops;
435 int n_ports;
436 void __iomem *base;
437 void __iomem *main_cause_reg_addr;
438 void __iomem *main_mask_reg_addr;
427 u32 irq_cause_ofs; 439 u32 irq_cause_ofs;
428 u32 irq_mask_ofs; 440 u32 irq_mask_ofs;
429 u32 unmask_all_irqs; 441 u32 unmask_all_irqs;
@@ -482,6 +494,15 @@ static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
482static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 494static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
483 unsigned int n_hc); 495 unsigned int n_hc);
484static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 496static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
497static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
498 void __iomem *mmio);
499static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
500 void __iomem *mmio);
501static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
502 void __iomem *mmio, unsigned int n_hc);
503static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
504 void __iomem *mmio);
505static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
485static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 506static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
486static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, 507static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
487 unsigned int port_no); 508 unsigned int port_no);
@@ -661,6 +682,12 @@ static const struct ata_port_info mv_port_info[] = {
661 .udma_mask = ATA_UDMA6, 682 .udma_mask = ATA_UDMA6,
662 .port_ops = &mv_iie_ops, 683 .port_ops = &mv_iie_ops,
663 }, 684 },
685 { /* chip_soc */
686 .flags = MV_COMMON_FLAGS | MV_FLAG_SOC,
687 .pio_mask = 0x1f, /* pio0-4 */
688 .udma_mask = ATA_UDMA6,
689 .port_ops = &mv_iie_ops,
690 },
664}; 691};
665 692
666static const struct pci_device_id mv_pci_tbl[] = { 693static const struct pci_device_id mv_pci_tbl[] = {
@@ -711,6 +738,15 @@ static const struct mv_hw_ops mv6xxx_ops = {
711 .reset_bus = mv_reset_pci_bus, 738 .reset_bus = mv_reset_pci_bus,
712}; 739};
713 740
741static const struct mv_hw_ops mv_soc_ops = {
742 .phy_errata = mv6_phy_errata,
743 .enable_leds = mv_soc_enable_leds,
744 .read_preamp = mv_soc_read_preamp,
745 .reset_hc = mv_soc_reset_hc,
746 .reset_flash = mv_soc_reset_flash,
747 .reset_bus = mv_soc_reset_bus,
748};
749
714/* 750/*
715 * Functions 751 * Functions
716 */ 752 */
@@ -749,9 +785,15 @@ static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
749 (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 785 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
750} 786}
751 787
788static inline void __iomem *mv_host_base(struct ata_host *host)
789{
790 struct mv_host_priv *hpriv = host->private_data;
791 return hpriv->base;
792}
793
752static inline void __iomem *mv_ap_base(struct ata_port *ap) 794static inline void __iomem *mv_ap_base(struct ata_port *ap)
753{ 795{
754 return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no); 796 return mv_port_base(mv_host_base(ap->host), ap->port_no);
755} 797}
756 798
757static inline int mv_get_hc_count(unsigned long port_flags) 799static inline int mv_get_hc_count(unsigned long port_flags)
@@ -1649,16 +1691,21 @@ static void mv_intr_edma(struct ata_port *ap)
1649 */ 1691 */
1650static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc) 1692static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
1651{ 1693{
1652 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR]; 1694 struct mv_host_priv *hpriv = host->private_data;
1695 void __iomem *mmio = hpriv->base;
1653 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 1696 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1654 u32 hc_irq_cause; 1697 u32 hc_irq_cause;
1655 int port, port0; 1698 int port, port0, last_port;
1656 1699
1657 if (hc == 0) 1700 if (hc == 0)
1658 port0 = 0; 1701 port0 = 0;
1659 else 1702 else
1660 port0 = MV_PORTS_PER_HC; 1703 port0 = MV_PORTS_PER_HC;
1661 1704
1705 if (HAS_PCI(host))
1706 last_port = port0 + MV_PORTS_PER_HC;
1707 else
1708 last_port = port0 + hpriv->n_ports;
1662 /* we'll need the HC success int register in most cases */ 1709 /* we'll need the HC success int register in most cases */
1663 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 1710 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1664 if (!hc_irq_cause) 1711 if (!hc_irq_cause)
@@ -1669,7 +1716,7 @@ static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
1669 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n", 1716 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1670 hc, relevant, hc_irq_cause); 1717 hc, relevant, hc_irq_cause);
1671 1718
1672 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) { 1719 for (port = port0; port < port0 + last_port; port++) {
1673 struct ata_port *ap = host->ports[port]; 1720 struct ata_port *ap = host->ports[port];
1674 struct mv_port_priv *pp = ap->private_data; 1721 struct mv_port_priv *pp = ap->private_data;
1675 int have_err_bits, hard_port, shift; 1722 int have_err_bits, hard_port, shift;
@@ -1764,13 +1811,15 @@ static void mv_pci_error(struct ata_host *host, void __iomem *mmio)
1764static irqreturn_t mv_interrupt(int irq, void *dev_instance) 1811static irqreturn_t mv_interrupt(int irq, void *dev_instance)
1765{ 1812{
1766 struct ata_host *host = dev_instance; 1813 struct ata_host *host = dev_instance;
1814 struct mv_host_priv *hpriv = host->private_data;
1767 unsigned int hc, handled = 0, n_hcs; 1815 unsigned int hc, handled = 0, n_hcs;
1768 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR]; 1816 void __iomem *mmio = hpriv->base;
1769 u32 irq_stat, irq_mask; 1817 u32 irq_stat, irq_mask;
1770 1818
1771 spin_lock(&host->lock); 1819 spin_lock(&host->lock);
1772 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS); 1820
1773 irq_mask = readl(mmio + HC_MAIN_IRQ_MASK_OFS); 1821 irq_stat = readl(hpriv->main_cause_reg_addr);
1822 irq_mask = readl(hpriv->main_mask_reg_addr);
1774 1823
1775 /* check the cases where we either have nothing pending or have read 1824 /* check the cases where we either have nothing pending or have read
1776 * a bogus register value which can indicate HW removal or PCI fault 1825 * a bogus register value which can indicate HW removal or PCI fault
@@ -1827,7 +1876,8 @@ static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1827 1876
1828static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 1877static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
1829{ 1878{
1830 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; 1879 struct mv_host_priv *hpriv = ap->host->private_data;
1880 void __iomem *mmio = hpriv->base;
1831 void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1881 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1832 unsigned int ofs = mv5_scr_offset(sc_reg_in); 1882 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1833 1883
@@ -1840,7 +1890,8 @@ static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
1840 1890
1841static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 1891static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1842{ 1892{
1843 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; 1893 struct mv_host_priv *hpriv = ap->host->private_data;
1894 void __iomem *mmio = hpriv->base;
1844 void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1895 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1845 unsigned int ofs = mv5_scr_offset(sc_reg_in); 1896 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1846 1897
@@ -2178,6 +2229,93 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2178 writel(m2, port_mmio + PHY_MODE2); 2229 writel(m2, port_mmio + PHY_MODE2);
2179} 2230}
2180 2231
2232/* TODO: use the generic LED interface to configure the SATA Presence */
2233/* & Acitivy LEDs on the board */
2234static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2235 void __iomem *mmio)
2236{
2237 return;
2238}
2239
2240static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2241 void __iomem *mmio)
2242{
2243 void __iomem *port_mmio;
2244 u32 tmp;
2245
2246 port_mmio = mv_port_base(mmio, idx);
2247 tmp = readl(port_mmio + PHY_MODE2);
2248
2249 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2250 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2251}
2252
2253#undef ZERO
2254#define ZERO(reg) writel(0, port_mmio + (reg))
2255static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2256 void __iomem *mmio, unsigned int port)
2257{
2258 void __iomem *port_mmio = mv_port_base(mmio, port);
2259
2260 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
2261
2262 mv_channel_reset(hpriv, mmio, port);
2263
2264 ZERO(0x028); /* command */
2265 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2266 ZERO(0x004); /* timer */
2267 ZERO(0x008); /* irq err cause */
2268 ZERO(0x00c); /* irq err mask */
2269 ZERO(0x010); /* rq bah */
2270 ZERO(0x014); /* rq inp */
2271 ZERO(0x018); /* rq outp */
2272 ZERO(0x01c); /* respq bah */
2273 ZERO(0x024); /* respq outp */
2274 ZERO(0x020); /* respq inp */
2275 ZERO(0x02c); /* test control */
2276 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
2277}
2278
2279#undef ZERO
2280
2281#define ZERO(reg) writel(0, hc_mmio + (reg))
2282static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2283 void __iomem *mmio)
2284{
2285 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2286
2287 ZERO(0x00c);
2288 ZERO(0x010);
2289 ZERO(0x014);
2290
2291}
2292
2293#undef ZERO
2294
2295static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2296 void __iomem *mmio, unsigned int n_hc)
2297{
2298 unsigned int port;
2299
2300 for (port = 0; port < hpriv->n_ports; port++)
2301 mv_soc_reset_hc_port(hpriv, mmio, port);
2302
2303 mv_soc_reset_one_hc(hpriv, mmio);
2304
2305 return 0;
2306}
2307
2308static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2309 void __iomem *mmio)
2310{
2311 return;
2312}
2313
2314static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2315{
2316 return;
2317}
2318
2181static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, 2319static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
2182 unsigned int port_no) 2320 unsigned int port_no)
2183{ 2321{
@@ -2342,7 +2480,7 @@ static int mv_hardreset(struct ata_link *link, unsigned int *class,
2342{ 2480{
2343 struct ata_port *ap = link->ap; 2481 struct ata_port *ap = link->ap;
2344 struct mv_host_priv *hpriv = ap->host->private_data; 2482 struct mv_host_priv *hpriv = ap->host->private_data;
2345 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; 2483 void __iomem *mmio = hpriv->base;
2346 2484
2347 mv_stop_dma(ap); 2485 mv_stop_dma(ap);
2348 2486
@@ -2383,7 +2521,7 @@ static void mv_error_handler(struct ata_port *ap)
2383 2521
2384static void mv_eh_freeze(struct ata_port *ap) 2522static void mv_eh_freeze(struct ata_port *ap)
2385{ 2523{
2386 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; 2524 struct mv_host_priv *hpriv = ap->host->private_data;
2387 unsigned int hc = (ap->port_no > 3) ? 1 : 0; 2525 unsigned int hc = (ap->port_no > 3) ? 1 : 0;
2388 u32 tmp, mask; 2526 u32 tmp, mask;
2389 unsigned int shift; 2527 unsigned int shift;
@@ -2397,13 +2535,14 @@ static void mv_eh_freeze(struct ata_port *ap)
2397 mask = 0x3 << shift; 2535 mask = 0x3 << shift;
2398 2536
2399 /* disable assertion of portN err, done events */ 2537 /* disable assertion of portN err, done events */
2400 tmp = readl(mmio + HC_MAIN_IRQ_MASK_OFS); 2538 tmp = readl(hpriv->main_mask_reg_addr);
2401 writelfl(tmp & ~mask, mmio + HC_MAIN_IRQ_MASK_OFS); 2539 writelfl(tmp & ~mask, hpriv->main_mask_reg_addr);
2402} 2540}
2403 2541
2404static void mv_eh_thaw(struct ata_port *ap) 2542static void mv_eh_thaw(struct ata_port *ap)
2405{ 2543{
2406 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; 2544 struct mv_host_priv *hpriv = ap->host->private_data;
2545 void __iomem *mmio = hpriv->base;
2407 unsigned int hc = (ap->port_no > 3) ? 1 : 0; 2546 unsigned int hc = (ap->port_no > 3) ? 1 : 0;
2408 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2547 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2409 void __iomem *port_mmio = mv_ap_base(ap); 2548 void __iomem *port_mmio = mv_ap_base(ap);
@@ -2430,8 +2569,8 @@ static void mv_eh_thaw(struct ata_port *ap)
2430 writel(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2569 writel(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
2431 2570
2432 /* enable assertion of portN err, done events */ 2571 /* enable assertion of portN err, done events */
2433 tmp = readl(mmio + HC_MAIN_IRQ_MASK_OFS); 2572 tmp = readl(hpriv->main_mask_reg_addr);
2434 writelfl(tmp | mask, mmio + HC_MAIN_IRQ_MASK_OFS); 2573 writelfl(tmp | mask, hpriv->main_mask_reg_addr);
2435} 2574}
2436 2575
2437/** 2576/**
@@ -2598,9 +2737,13 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2598 break; 2737 break;
2599 } 2738 }
2600 break; 2739 break;
2740 case chip_soc:
2741 hpriv->ops = &mv_soc_ops;
2742 hp_flags |= MV_HP_ERRATA_60X1C0;
2743 break;
2601 2744
2602 default: 2745 default:
2603 dev_printk(KERN_ERR, &pdev->dev, 2746 dev_printk(KERN_ERR, host->dev,
2604 "BUG: invalid board index %u\n", board_idx); 2747 "BUG: invalid board index %u\n", board_idx);
2605 return 1; 2748 return 1;
2606 } 2749 }
@@ -2633,15 +2776,25 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2633static int mv_init_host(struct ata_host *host, unsigned int board_idx) 2776static int mv_init_host(struct ata_host *host, unsigned int board_idx)
2634{ 2777{
2635 int rc = 0, n_hc, port, hc; 2778 int rc = 0, n_hc, port, hc;
2636 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
2637 struct mv_host_priv *hpriv = host->private_data; 2779 struct mv_host_priv *hpriv = host->private_data;
2638 2780 void __iomem *mmio = hpriv->base;
2639 /* global interrupt mask */
2640 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2641 2781
2642 rc = mv_chip_id(host, board_idx); 2782 rc = mv_chip_id(host, board_idx);
2643 if (rc) 2783 if (rc)
2644 goto done; 2784 goto done;
2785
2786 if (HAS_PCI(host)) {
2787 hpriv->main_cause_reg_addr = hpriv->base +
2788 HC_MAIN_IRQ_CAUSE_OFS;
2789 hpriv->main_mask_reg_addr = hpriv->base + HC_MAIN_IRQ_MASK_OFS;
2790 } else {
2791 hpriv->main_cause_reg_addr = hpriv->base +
2792 HC_SOC_MAIN_IRQ_CAUSE_OFS;
2793 hpriv->main_mask_reg_addr = hpriv->base +
2794 HC_SOC_MAIN_IRQ_MASK_OFS;
2795 }
2796 /* global interrupt mask */
2797 writel(0, hpriv->main_mask_reg_addr);
2645 2798
2646 n_hc = mv_get_hc_count(host->ports[0]->flags); 2799 n_hc = mv_get_hc_count(host->ports[0]->flags);
2647 2800
@@ -2672,13 +2825,15 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
2672 for (port = 0; port < host->n_ports; port++) { 2825 for (port = 0; port < host->n_ports; port++) {
2673 struct ata_port *ap = host->ports[port]; 2826 struct ata_port *ap = host->ports[port];
2674 void __iomem *port_mmio = mv_port_base(mmio, port); 2827 void __iomem *port_mmio = mv_port_base(mmio, port);
2675 unsigned int offset = port_mmio - mmio;
2676 2828
2677 mv_port_init(&ap->ioaddr, port_mmio); 2829 mv_port_init(&ap->ioaddr, port_mmio);
2678 2830
2679#ifdef CONFIG_PCI 2831#ifdef CONFIG_PCI
2680 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 2832 if (HAS_PCI(host)) {
2681 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 2833 unsigned int offset = port_mmio - mmio;
2834 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
2835 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
2836 }
2682#endif 2837#endif
2683 } 2838 }
2684 2839
@@ -2694,35 +2849,141 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
2694 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 2849 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2695 } 2850 }
2696 2851
2697 /* Clear any currently outstanding host interrupt conditions */ 2852 if (HAS_PCI(host)) {
2698 writelfl(0, mmio + hpriv->irq_cause_ofs); 2853 /* Clear any currently outstanding host interrupt conditions */
2854 writelfl(0, mmio + hpriv->irq_cause_ofs);
2699 2855
2700 /* and unmask interrupt generation for host regs */ 2856 /* and unmask interrupt generation for host regs */
2701 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 2857 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
2858 if (IS_GEN_I(hpriv))
2859 writelfl(~HC_MAIN_MASKED_IRQS_5,
2860 hpriv->main_mask_reg_addr);
2861 else
2862 writelfl(~HC_MAIN_MASKED_IRQS,
2863 hpriv->main_mask_reg_addr);
2864
2865 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2866 "PCI int cause/mask=0x%08x/0x%08x\n",
2867 readl(hpriv->main_cause_reg_addr),
2868 readl(hpriv->main_mask_reg_addr),
2869 readl(mmio + hpriv->irq_cause_ofs),
2870 readl(mmio + hpriv->irq_mask_ofs));
2871 } else {
2872 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
2873 hpriv->main_mask_reg_addr);
2874 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
2875 readl(hpriv->main_cause_reg_addr),
2876 readl(hpriv->main_mask_reg_addr));
2877 }
2878done:
2879 return rc;
2880}
2702 2881
2703 if (IS_GEN_I(hpriv)) 2882/**
2704 writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS); 2883 * mv_platform_probe - handle a positive probe of an soc Marvell
2705 else 2884 * host
2706 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS); 2885 * @pdev: platform device found
2886 *
2887 * LOCKING:
2888 * Inherited from caller.
2889 */
2890static int mv_platform_probe(struct platform_device *pdev)
2891{
2892 static int printed_version;
2893 const struct mv_sata_platform_data *mv_platform_data;
2894 const struct ata_port_info *ppi[] =
2895 { &mv_port_info[chip_soc], NULL };
2896 struct ata_host *host;
2897 struct mv_host_priv *hpriv;
2898 struct resource *res;
2899 int n_ports, rc;
2707 2900
2708 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " 2901 if (!printed_version++)
2709 "PCI int cause/mask=0x%08x/0x%08x\n", 2902 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2710 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2711 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2712 readl(mmio + hpriv->irq_cause_ofs),
2713 readl(mmio + hpriv->irq_mask_ofs));
2714 2903
2715done: 2904 /*
2716 return rc; 2905 * Simple resource validation ..
2906 */
2907 if (unlikely(pdev->num_resources != 2)) {
2908 dev_err(&pdev->dev, "invalid number of resources\n");
2909 return -EINVAL;
2910 }
2911
2912 /*
2913 * Get the register base first
2914 */
2915 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2916 if (res == NULL)
2917 return -EINVAL;
2918
2919 /* allocate host */
2920 mv_platform_data = pdev->dev.platform_data;
2921 n_ports = mv_platform_data->n_ports;
2922
2923 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2924 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
2925
2926 if (!host || !hpriv)
2927 return -ENOMEM;
2928 host->private_data = hpriv;
2929 hpriv->n_ports = n_ports;
2930
2931 host->iomap = NULL;
2932 hpriv->base = ioremap(res->start, res->end - res->start + 1);
2933 hpriv->base -= MV_SATAHC0_REG_BASE;
2934
2935 /* initialize adapter */
2936 rc = mv_init_host(host, chip_soc);
2937 if (rc)
2938 return rc;
2939
2940 dev_printk(KERN_INFO, &pdev->dev,
2941 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
2942 host->n_ports);
2943
2944 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
2945 IRQF_SHARED, &mv6_sht);
2946}
2947
2948/*
2949 *
2950 * mv_platform_remove - unplug a platform interface
2951 * @pdev: platform device
2952 *
2953 * A platform bus SATA device has been unplugged. Perform the needed
2954 * cleanup. Also called on module unload for any active devices.
2955 */
2956static int __devexit mv_platform_remove(struct platform_device *pdev)
2957{
2958 struct device *dev = &pdev->dev;
2959 struct ata_host *host = dev_get_drvdata(dev);
2960 struct mv_host_priv *hpriv = host->private_data;
2961 void __iomem *base = hpriv->base;
2962
2963 ata_host_detach(host);
2964 iounmap(base);
2965 return 0;
2717} 2966}
2718 2967
2968static struct platform_driver mv_platform_driver = {
2969 .probe = mv_platform_probe,
2970 .remove = __devexit_p(mv_platform_remove),
2971 .driver = {
2972 .name = DRV_NAME,
2973 .owner = THIS_MODULE,
2974 },
2975};
2976
2977
2719#ifdef CONFIG_PCI 2978#ifdef CONFIG_PCI
2720static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 2979static int mv_pci_init_one(struct pci_dev *pdev,
2980 const struct pci_device_id *ent);
2981
2721 2982
2722static struct pci_driver mv_pci_driver = { 2983static struct pci_driver mv_pci_driver = {
2723 .name = DRV_NAME, 2984 .name = DRV_NAME,
2724 .id_table = mv_pci_tbl, 2985 .id_table = mv_pci_tbl,
2725 .probe = mv_init_one, 2986 .probe = mv_pci_init_one,
2726 .remove = ata_pci_remove_one, 2987 .remove = ata_pci_remove_one,
2727}; 2988};
2728 2989
@@ -2828,14 +3089,15 @@ static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
2828} 3089}
2829 3090
2830/** 3091/**
2831 * mv_init_one - handle a positive probe of a Marvell host 3092 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
2832 * @pdev: PCI device found 3093 * @pdev: PCI device found
2833 * @ent: PCI device ID entry for the matched host 3094 * @ent: PCI device ID entry for the matched host
2834 * 3095 *
2835 * LOCKING: 3096 * LOCKING:
2836 * Inherited from caller. 3097 * Inherited from caller.
2837 */ 3098 */
2838static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 3099static int mv_pci_init_one(struct pci_dev *pdev,
3100 const struct pci_device_id *ent)
2839{ 3101{
2840 static int printed_version; 3102 static int printed_version;
2841 unsigned int board_idx = (unsigned int)ent->driver_data; 3103 unsigned int board_idx = (unsigned int)ent->driver_data;
@@ -2855,6 +3117,7 @@ static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2855 if (!host || !hpriv) 3117 if (!host || !hpriv)
2856 return -ENOMEM; 3118 return -ENOMEM;
2857 host->private_data = hpriv; 3119 host->private_data = hpriv;
3120 hpriv->n_ports = n_ports;
2858 3121
2859 /* acquire resources */ 3122 /* acquire resources */
2860 rc = pcim_enable_device(pdev); 3123 rc = pcim_enable_device(pdev);
@@ -2867,6 +3130,7 @@ static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2867 if (rc) 3130 if (rc)
2868 return rc; 3131 return rc;
2869 host->iomap = pcim_iomap_table(pdev); 3132 host->iomap = pcim_iomap_table(pdev);
3133 hpriv->base = host->iomap[MV_PRIMARY_BAR];
2870 3134
2871 rc = pci_go_64(pdev); 3135 rc = pci_go_64(pdev);
2872 if (rc) 3136 if (rc)
@@ -2895,11 +3159,22 @@ static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2895} 3159}
2896#endif 3160#endif
2897 3161
3162static int mv_platform_probe(struct platform_device *pdev);
3163static int __devexit mv_platform_remove(struct platform_device *pdev);
3164
2898static int __init mv_init(void) 3165static int __init mv_init(void)
2899{ 3166{
2900 int rc = -ENODEV; 3167 int rc = -ENODEV;
2901#ifdef CONFIG_PCI 3168#ifdef CONFIG_PCI
2902 rc = pci_register_driver(&mv_pci_driver); 3169 rc = pci_register_driver(&mv_pci_driver);
3170 if (rc < 0)
3171 return rc;
3172#endif
3173 rc = platform_driver_register(&mv_platform_driver);
3174
3175#ifdef CONFIG_PCI
3176 if (rc < 0)
3177 pci_unregister_driver(&mv_pci_driver);
2903#endif 3178#endif
2904 return rc; 3179 return rc;
2905} 3180}
@@ -2909,6 +3184,7 @@ static void __exit mv_exit(void)
2909#ifdef CONFIG_PCI 3184#ifdef CONFIG_PCI
2910 pci_unregister_driver(&mv_pci_driver); 3185 pci_unregister_driver(&mv_pci_driver);
2911#endif 3186#endif
3187 platform_driver_unregister(&mv_platform_driver);
2912} 3188}
2913 3189
2914MODULE_AUTHOR("Brett Russ"); 3190MODULE_AUTHOR("Brett Russ");