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path: root/drivers/ata/pata_via.c
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-rw-r--r--drivers/ata/pata_via.c568
1 files changed, 568 insertions, 0 deletions
diff --git a/drivers/ata/pata_via.c b/drivers/ata/pata_via.c
new file mode 100644
index 000000000000..2580e1606d9e
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+++ b/drivers/ata/pata_via.c
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1/*
2 * pata_via.c - VIA PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Documentation
7 * Most chipset documentation available under NDA only
8 *
9 * VIA version guide
10 * VIA VT82C561 - early design, uses ata_generic currently
11 * VIA VT82C576 - MWDMA, 33Mhz
12 * VIA VT82C586 - MWDMA, 33Mhz
13 * VIA VT82C586a - Added UDMA to 33Mhz
14 * VIA VT82C586b - UDMA33
15 * VIA VT82C596a - Nonfunctional UDMA66
16 * VIA VT82C596b - Working UDMA66
17 * VIA VT82C686 - Nonfunctional UDMA66
18 * VIA VT82C686a - Working UDMA66
19 * VIA VT82C686b - Updated to UDMA100
20 * VIA VT8231 - UDMA100
21 * VIA VT8233 - UDMA100
22 * VIA VT8233a - UDMA133
23 * VIA VT8233c - UDMA100
24 * VIA VT8235 - UDMA133
25 * VIA VT8237 - UDMA133
26 *
27 * Most registers remain compatible across chips. Others start reserved
28 * and acquire sensible semantics if set to 1 (eg cable detect). A few
29 * exceptions exist, notably around the FIFO settings.
30 *
31 * One additional quirk of the VIA design is that like ALi they use few
32 * PCI IDs for a lot of chips.
33 *
34 * Based heavily on:
35 *
36 * Version 3.38
37 *
38 * VIA IDE driver for Linux. Supported southbridges:
39 *
40 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
41 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
42 * vt8235, vt8237
43 *
44 * Copyright (c) 2000-2002 Vojtech Pavlik
45 *
46 * Based on the work of:
47 * Michel Aubry
48 * Jeff Garzik
49 * Andre Hedrick
50
51 */
52
53#include <linux/kernel.h>
54#include <linux/module.h>
55#include <linux/pci.h>
56#include <linux/init.h>
57#include <linux/blkdev.h>
58#include <linux/delay.h>
59#include <scsi/scsi_host.h>
60#include <linux/libata.h>
61
62#define DRV_NAME "pata_via"
63#define DRV_VERSION "0.1.13"
64
65/*
66 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
67 * driver.
68 */
69
70enum {
71 VIA_UDMA = 0x007,
72 VIA_UDMA_NONE = 0x000,
73 VIA_UDMA_33 = 0x001,
74 VIA_UDMA_66 = 0x002,
75 VIA_UDMA_100 = 0x003,
76 VIA_UDMA_133 = 0x004,
77 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */
78 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */
79 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */
80 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */
81 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */
82 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */
83 VIA_NO_ENABLES = 0x400, /* Has no enablebits */
84};
85
86/*
87 * VIA SouthBridge chips.
88 */
89
90static const struct via_isa_bridge {
91 const char *name;
92 u16 id;
93 u8 rev_min;
94 u8 rev_max;
95 u16 flags;
96} via_isa_bridges[] = {
97 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
98 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES},
99 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
100 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
101 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
102 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
103 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
104 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
105 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
106 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
107 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
108 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
109 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
110 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
111 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
112 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
113 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
114 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
115 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
116 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
117 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
118 { NULL }
119};
120
121/**
122 * via_cable_detect - cable detection
123 * @ap: ATA port
124 *
125 * Perform cable detection. Actually for the VIA case the BIOS
126 * already did this for us. We read the values provided by the
127 * BIOS. If you are using an 8235 in a non-PC configuration you
128 * may need to update this code.
129 *
130 * Hotplug also impacts on this.
131 */
132
133static int via_cable_detect(struct ata_port *ap) {
134 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
135 u32 ata66;
136
137 pci_read_config_dword(pdev, 0x50, &ata66);
138 /* Check both the drive cable reporting bits, we might not have
139 two drives */
140 if (ata66 & (0x10100000 >> (16 * ap->port_no)))
141 return ATA_CBL_PATA80;
142 else
143 return ATA_CBL_PATA40;
144}
145
146static int via_pre_reset(struct ata_port *ap)
147{
148 const struct via_isa_bridge *config = ap->host->private_data;
149
150 if (!(config->flags & VIA_NO_ENABLES)) {
151 static const struct pci_bits via_enable_bits[] = {
152 { 0x40, 1, 0x02, 0x02 },
153 { 0x40, 1, 0x01, 0x01 }
154 };
155
156 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
157
158 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no])) {
159 ata_port_disable(ap);
160 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
161 return 0;
162 }
163 }
164
165 if ((config->flags & VIA_UDMA) >= VIA_UDMA_66)
166 ap->cbl = via_cable_detect(ap);
167 else
168 ap->cbl = ATA_CBL_PATA40;
169 return ata_std_prereset(ap);
170}
171
172
173/**
174 * via_error_handler - reset for VIA chips
175 * @ap: ATA port
176 *
177 * Handle the reset callback for the later chips with cable detect
178 */
179
180static void via_error_handler(struct ata_port *ap)
181{
182 ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
183}
184
185/**
186 * via_do_set_mode - set initial PIO mode data
187 * @ap: ATA interface
188 * @adev: ATA device
189 * @mode: ATA mode being programmed
190 * @tdiv: Clocks per PCI clock
191 * @set_ast: Set to program address setup
192 * @udma_type: UDMA mode/format of registers
193 *
194 * Program the VIA registers for DMA and PIO modes. Uses the ata timing
195 * support in order to compute modes.
196 *
197 * FIXME: Hotplug will require we serialize multiple mode changes
198 * on the two channels.
199 */
200
201static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type)
202{
203 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
204 struct ata_device *peer = ata_dev_pair(adev);
205 struct ata_timing t, p;
206 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */
207 unsigned long T = 1000000000 / via_clock;
208 unsigned long UT = T/tdiv;
209 int ut;
210 int offset = 3 - (2*ap->port_no) - adev->devno;
211
212
213 /* Calculate the timing values we require */
214 ata_timing_compute(adev, mode, &t, T, UT);
215
216 /* We share 8bit timing so we must merge the constraints */
217 if (peer) {
218 if (peer->pio_mode) {
219 ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
220 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
221 }
222 }
223
224 /* Address setup is programmable but breaks on UDMA133 setups */
225 if (set_ast) {
226 u8 setup; /* 2 bits per drive */
227 int shift = 2 * offset;
228
229 pci_read_config_byte(pdev, 0x4C, &setup);
230 setup &= ~(3 << shift);
231 setup |= FIT(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */
232 pci_write_config_byte(pdev, 0x4C, setup);
233 }
234
235 /* Load the PIO mode bits */
236 pci_write_config_byte(pdev, 0x4F - ap->port_no,
237 ((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1));
238 pci_write_config_byte(pdev, 0x48 + offset,
239 ((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1));
240
241 /* Load the UDMA bits according to type */
242 switch(udma_type) {
243 default:
244 /* BUG() ? */
245 /* fall through */
246 case 33:
247 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03;
248 break;
249 case 66:
250 ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f;
251 break;
252 case 100:
253 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
254 break;
255 case 133:
256 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
257 break;
258 }
259 /* Set UDMA unless device is not UDMA capable */
260 if (udma_type)
261 pci_write_config_byte(pdev, 0x50 + offset, ut);
262}
263
264static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
265{
266 const struct via_isa_bridge *config = ap->host->private_data;
267 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
268 int mode = config->flags & VIA_UDMA;
269 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
270 static u8 udma[5] = { 0, 33, 66, 100, 133 };
271
272 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
273}
274
275static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
276{
277 const struct via_isa_bridge *config = ap->host->private_data;
278 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
279 int mode = config->flags & VIA_UDMA;
280 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
281 static u8 udma[5] = { 0, 33, 66, 100, 133 };
282
283 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
284}
285
286static struct scsi_host_template via_sht = {
287 .module = THIS_MODULE,
288 .name = DRV_NAME,
289 .ioctl = ata_scsi_ioctl,
290 .queuecommand = ata_scsi_queuecmd,
291 .can_queue = ATA_DEF_QUEUE,
292 .this_id = ATA_SHT_THIS_ID,
293 .sg_tablesize = LIBATA_MAX_PRD,
294 .max_sectors = ATA_MAX_SECTORS,
295 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
296 .emulated = ATA_SHT_EMULATED,
297 .use_clustering = ATA_SHT_USE_CLUSTERING,
298 .proc_name = DRV_NAME,
299 .dma_boundary = ATA_DMA_BOUNDARY,
300 .slave_configure = ata_scsi_slave_config,
301 .bios_param = ata_std_bios_param,
302};
303
304static struct ata_port_operations via_port_ops = {
305 .port_disable = ata_port_disable,
306 .set_piomode = via_set_piomode,
307 .set_dmamode = via_set_dmamode,
308 .mode_filter = ata_pci_default_filter,
309
310 .tf_load = ata_tf_load,
311 .tf_read = ata_tf_read,
312 .check_status = ata_check_status,
313 .exec_command = ata_exec_command,
314 .dev_select = ata_std_dev_select,
315
316 .freeze = ata_bmdma_freeze,
317 .thaw = ata_bmdma_thaw,
318 .error_handler = via_error_handler,
319 .post_internal_cmd = ata_bmdma_post_internal_cmd,
320
321 .bmdma_setup = ata_bmdma_setup,
322 .bmdma_start = ata_bmdma_start,
323 .bmdma_stop = ata_bmdma_stop,
324 .bmdma_status = ata_bmdma_status,
325
326 .qc_prep = ata_qc_prep,
327 .qc_issue = ata_qc_issue_prot,
328 .eng_timeout = ata_eng_timeout,
329 .data_xfer = ata_pio_data_xfer,
330
331 .irq_handler = ata_interrupt,
332 .irq_clear = ata_bmdma_irq_clear,
333
334 .port_start = ata_port_start,
335 .port_stop = ata_port_stop,
336 .host_stop = ata_host_stop
337};
338
339static struct ata_port_operations via_port_ops_noirq = {
340 .port_disable = ata_port_disable,
341 .set_piomode = via_set_piomode,
342 .set_dmamode = via_set_dmamode,
343 .mode_filter = ata_pci_default_filter,
344
345 .tf_load = ata_tf_load,
346 .tf_read = ata_tf_read,
347 .check_status = ata_check_status,
348 .exec_command = ata_exec_command,
349 .dev_select = ata_std_dev_select,
350
351 .freeze = ata_bmdma_freeze,
352 .thaw = ata_bmdma_thaw,
353 .error_handler = via_error_handler,
354 .post_internal_cmd = ata_bmdma_post_internal_cmd,
355
356 .bmdma_setup = ata_bmdma_setup,
357 .bmdma_start = ata_bmdma_start,
358 .bmdma_stop = ata_bmdma_stop,
359 .bmdma_status = ata_bmdma_status,
360
361 .qc_prep = ata_qc_prep,
362 .qc_issue = ata_qc_issue_prot,
363 .eng_timeout = ata_eng_timeout,
364 .data_xfer = ata_pio_data_xfer_noirq,
365
366 .irq_handler = ata_interrupt,
367 .irq_clear = ata_bmdma_irq_clear,
368
369 .port_start = ata_port_start,
370 .port_stop = ata_port_stop,
371 .host_stop = ata_host_stop
372};
373
374/**
375 * via_init_one - discovery callback
376 * @pdev: PCI device ID
377 * @id: PCI table info
378 *
379 * A VIA IDE interface has been discovered. Figure out what revision
380 * and perform configuration work before handing it to the ATA layer
381 */
382
383static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
384{
385 /* Early VIA without UDMA support */
386 static struct ata_port_info via_mwdma_info = {
387 .sht = &via_sht,
388 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
389 .pio_mask = 0x1f,
390 .mwdma_mask = 0x07,
391 .port_ops = &via_port_ops
392 };
393 /* Ditto with IRQ masking required */
394 static struct ata_port_info via_mwdma_info_borked = {
395 .sht = &via_sht,
396 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
397 .pio_mask = 0x1f,
398 .mwdma_mask = 0x07,
399 .port_ops = &via_port_ops_noirq,
400 };
401 /* VIA UDMA 33 devices (and borked 66) */
402 static struct ata_port_info via_udma33_info = {
403 .sht = &via_sht,
404 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
405 .pio_mask = 0x1f,
406 .mwdma_mask = 0x07,
407 .udma_mask = 0x7,
408 .port_ops = &via_port_ops
409 };
410 /* VIA UDMA 66 devices */
411 static struct ata_port_info via_udma66_info = {
412 .sht = &via_sht,
413 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
414 .pio_mask = 0x1f,
415 .mwdma_mask = 0x07,
416 .udma_mask = 0x1f,
417 .port_ops = &via_port_ops
418 };
419 /* VIA UDMA 100 devices */
420 static struct ata_port_info via_udma100_info = {
421 .sht = &via_sht,
422 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
423 .pio_mask = 0x1f,
424 .mwdma_mask = 0x07,
425 .udma_mask = 0x3f,
426 .port_ops = &via_port_ops
427 };
428 /* UDMA133 with bad AST (All current 133) */
429 static struct ata_port_info via_udma133_info = {
430 .sht = &via_sht,
431 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
432 .pio_mask = 0x1f,
433 .mwdma_mask = 0x07,
434 .udma_mask = 0x7f, /* FIXME: should check north bridge */
435 .port_ops = &via_port_ops
436 };
437 struct ata_port_info *port_info[2], *type;
438 struct pci_dev *isa = NULL;
439 const struct via_isa_bridge *config;
440 static int printed_version;
441 u8 t;
442 u8 enable;
443 u32 timing;
444
445 if (!printed_version++)
446 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
447
448 /* To find out how the IDE will behave and what features we
449 actually have to look at the bridge not the IDE controller */
450 for (config = via_isa_bridges; config->id; config++)
451 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
452 !!(config->flags & VIA_BAD_ID),
453 config->id, NULL))) {
454
455 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
456 if (t >= config->rev_min &&
457 t <= config->rev_max)
458 break;
459 pci_dev_put(isa);
460 }
461
462 if (!config->id) {
463 printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
464 return -ENODEV;
465 }
466 pci_dev_put(isa);
467
468 /* 0x40 low bits indicate enabled channels */
469 pci_read_config_byte(pdev, 0x40 , &enable);
470 enable &= 3;
471 if (enable == 0) {
472 return -ENODEV;
473 }
474
475 /* Initialise the FIFO for the enabled channels. */
476 if (config->flags & VIA_SET_FIFO) {
477 u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
478 u8 fifo;
479
480 pci_read_config_byte(pdev, 0x43, &fifo);
481
482 /* Clear PREQ# until DDACK# for errata */
483 if (config->flags & VIA_BAD_PREQ)
484 fifo &= 0x7F;
485 else
486 fifo &= 0x9f;
487 /* Turn on FIFO for enabled channels */
488 fifo |= fifo_setting[enable];
489 pci_write_config_byte(pdev, 0x43, fifo);
490 }
491 /* Clock set up */
492 switch(config->flags & VIA_UDMA) {
493 case VIA_UDMA_NONE:
494 if (config->flags & VIA_NO_UNMASK)
495 type = &via_mwdma_info_borked;
496 else
497 type = &via_mwdma_info;
498 break;
499 case VIA_UDMA_33:
500 type = &via_udma33_info;
501 break;
502 case VIA_UDMA_66:
503 type = &via_udma66_info;
504 /* The 66 MHz devices require we enable the clock */
505 pci_read_config_dword(pdev, 0x50, &timing);
506 timing |= 0x80008;
507 pci_write_config_dword(pdev, 0x50, timing);
508 break;
509 case VIA_UDMA_100:
510 type = &via_udma100_info;
511 break;
512 case VIA_UDMA_133:
513 type = &via_udma133_info;
514 break;
515 default:
516 WARN_ON(1);
517 return -ENODEV;
518 }
519
520 if (config->flags & VIA_BAD_CLK66) {
521 /* Disable the 66MHz clock on problem devices */
522 pci_read_config_dword(pdev, 0x50, &timing);
523 timing &= ~0x80008;
524 pci_write_config_dword(pdev, 0x50, timing);
525 }
526
527 /* We have established the device type, now fire it up */
528 type->private_data = (void *)config;
529
530 port_info[0] = port_info[1] = type;
531 return ata_pci_init_one(pdev, port_info, 2);
532}
533
534static const struct pci_device_id via[] = {
535 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1), },
536 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1), },
537 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410), },
538 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), },
539 { 0, },
540};
541
542static struct pci_driver via_pci_driver = {
543 .name = DRV_NAME,
544 .id_table = via,
545 .probe = via_init_one,
546 .remove = ata_pci_remove_one
547};
548
549static int __init via_init(void)
550{
551 return pci_register_driver(&via_pci_driver);
552}
553
554
555static void __exit via_exit(void)
556{
557 pci_unregister_driver(&via_pci_driver);
558}
559
560
561MODULE_AUTHOR("Alan Cox");
562MODULE_DESCRIPTION("low-level driver for VIA PATA");
563MODULE_LICENSE("GPL");
564MODULE_DEVICE_TABLE(pci, via);
565MODULE_VERSION(DRV_VERSION);
566
567module_init(via_init);
568module_exit(via_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 22:02:50 -0500